智也 大野 / Mbed 2 deprecated HeptaBattery

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Dependencies:   mbed PowerControl SDFileSystem

Fork of HeptaBattery by 智也 大野

hepta_sat/HeptaCamera.h@1:166ddf929155, 2016-12-13 (annotated)

Committer:
tomoya123
Date:
Tue Dec 13 06:37:27 2016 +0000
Revision:
1:166ddf929155
Parent:
0:d53e9c6fc771 
HeptaBattery

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tomoya123 0:d53e9c6fc771 1 #define BITMAPFILE
tomoya123 0:d53e9c6fc771 2 #undef BAYERBITMAPFILE
tomoya123 0:d53e9c6fc771 3 #undef HEXFILE
tomoya123 0:d53e9c6fc771 4 #undef COLORBAR
tomoya123 0:d53e9c6fc771 5 #include <algorithm>
tomoya123 0:d53e9c6fc771 6
tomoya123 0:d53e9c6fc771 7 #ifndef MBED_HEPTACAMERA_H
tomoya123 0:d53e9c6fc771 8 #define MBED_HEPTACAMERA_H
tomoya123 0:d53e9c6fc771 9 #include "mbed.h"
tomoya123 0:d53e9c6fc771 10
tomoya123 0:d53e9c6fc771 11 // size register
tomoya123 0:d53e9c6fc771 12 #define REG_COM7 0x12 /* Control 7 */
tomoya123 0:d53e9c6fc771 13 #define REG_HSTART 0x17 /* Horiz start high bits */
tomoya123 0:d53e9c6fc771 14 #define REG_HSTOP 0x18 /* Horiz stop high bits */
tomoya123 0:d53e9c6fc771 15 #define REG_HREF 0x32 /* HREF pieces */
tomoya123 0:d53e9c6fc771 16 #define REG_VSTART 0x19 /* Vert start high bits */
tomoya123 0:d53e9c6fc771 17 #define REG_VSTOP 0x1a /* Vert stop high bits */
tomoya123 0:d53e9c6fc771 18 #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
tomoya123 0:d53e9c6fc771 19 #define REG_COM3 0x0c /* Control 3 */
tomoya123 0:d53e9c6fc771 20 #define REG_COM14 0x3e /* Control 14 */
tomoya123 0:d53e9c6fc771 21 #define REG_SCALING_XSC 0x70
tomoya123 0:d53e9c6fc771 22 #define REG_SCALING_YSC 0x71
tomoya123 0:d53e9c6fc771 23 #define REG_SCALING_DCWCTR 0x72
tomoya123 0:d53e9c6fc771 24 #define REG_SCALING_PCLK_DIV 0x73
tomoya123 0:d53e9c6fc771 25 #define REG_SCALING_PCLK_DELAY 0xa2
tomoya123 0:d53e9c6fc771 26
tomoya123 0:d53e9c6fc771 27 // VGA setting
tomoya123 0:d53e9c6fc771 28 #define COM7_VGA 0x00
tomoya123 0:d53e9c6fc771 29 #define HSTART_VGA 0x13
tomoya123 0:d53e9c6fc771 30 #define HSTOP_VGA 0x01
tomoya123 0:d53e9c6fc771 31 #define HREF_VGA 0x36 //0xb6 0x36
tomoya123 0:d53e9c6fc771 32 #define VSTART_VGA 0x02
tomoya123 0:d53e9c6fc771 33 #define VSTOP_VGA 0x7a
tomoya123 0:d53e9c6fc771 34 #define VREF_VGA 0x0a
tomoya123 0:d53e9c6fc771 35 #define COM3_VGA 0x00
tomoya123 0:d53e9c6fc771 36 #define COM14_VGA 0x00
tomoya123 0:d53e9c6fc771 37 #define SCALING_XSC_VGA 0x3a
tomoya123 0:d53e9c6fc771 38 #define SCALING_YSC_VGA 0x35
tomoya123 0:d53e9c6fc771 39 #define SCALING_DCWCTR_VGA 0x11
tomoya123 0:d53e9c6fc771 40 #define SCALING_PCLK_DIV_VGA 0xf0
tomoya123 0:d53e9c6fc771 41 #define SCALING_PCLK_DELAY_VGA 0x02
tomoya123 0:d53e9c6fc771 42
tomoya123 0:d53e9c6fc771 43 // QVGA setting
tomoya123 0:d53e9c6fc771 44 #define COM7_QVGA 0x00
tomoya123 0:d53e9c6fc771 45 #define HSTART_QVGA 0x16
tomoya123 0:d53e9c6fc771 46 #define HSTOP_QVGA 0x04
tomoya123 0:d53e9c6fc771 47 #define HREF_QVGA 0x00
tomoya123 0:d53e9c6fc771 48 #define VSTART_QVGA 0x02
tomoya123 0:d53e9c6fc771 49 #define VSTOP_QVGA 0x7a
tomoya123 0:d53e9c6fc771 50 #define VREF_QVGA 0x0a
tomoya123 0:d53e9c6fc771 51 #define COM3_QVGA 0x04
tomoya123 0:d53e9c6fc771 52 #define COM14_QVGA 0x19
tomoya123 0:d53e9c6fc771 53 #define SCALING_XSC_QVGA 0x3a
tomoya123 0:d53e9c6fc771 54 #define SCALING_YSC_QVGA 0x35
tomoya123 0:d53e9c6fc771 55 #define SCALING_DCWCTR_QVGA 0x11
tomoya123 0:d53e9c6fc771 56 #define SCALING_PCLK_DIV_QVGA 0xf1
tomoya123 0:d53e9c6fc771 57 #define SCALING_PCLK_DELAY_QVGA 0x02
tomoya123 0:d53e9c6fc771 58
tomoya123 0:d53e9c6fc771 59 // QQVGA setting
tomoya123 0:d53e9c6fc771 60 #define COM7_QQVGA 0x00
tomoya123 0:d53e9c6fc771 61 #define HSTART_QQVGA 0x16
tomoya123 0:d53e9c6fc771 62 #define HSTOP_QQVGA 0x04
tomoya123 0:d53e9c6fc771 63 #define HREF_QQVGA 0xa4 //0x24? 0xa4?
tomoya123 0:d53e9c6fc771 64 #define VSTART_QQVGA 0x02
tomoya123 0:d53e9c6fc771 65 #define VSTOP_QQVGA 0x7a
tomoya123 0:d53e9c6fc771 66 #define VREF_QQVGA 0x0a
tomoya123 0:d53e9c6fc771 67 #define COM3_QQVGA 0x04
tomoya123 0:d53e9c6fc771 68 #define COM14_QQVGA 0x1a
tomoya123 0:d53e9c6fc771 69 #define SCALING_XSC_QQVGA 0x3a
tomoya123 0:d53e9c6fc771 70 #define SCALING_YSC_QQVGA 0x35
tomoya123 0:d53e9c6fc771 71 #define SCALING_DCWCTR_QQVGA 0x22
tomoya123 0:d53e9c6fc771 72 #define SCALING_PCLK_DIV_QQVGA 0xf2
tomoya123 0:d53e9c6fc771 73 #define SCALING_PCLK_DELAY_QQVGA 0x02
tomoya123 0:d53e9c6fc771 74
tomoya123 0:d53e9c6fc771 75 // CIF setting no tested linux src 2.6.29-rc5 ov7670_soc.c
tomoya123 0:d53e9c6fc771 76 #define COM7_CIF 0x00
tomoya123 0:d53e9c6fc771 77 #define HSTART_CIF 0x15
tomoya123 0:d53e9c6fc771 78 #define HSTOP_CIF 0x0b
tomoya123 0:d53e9c6fc771 79 #define HREF_CIF 0xb6
tomoya123 0:d53e9c6fc771 80 #define VSTART_CIF 0x03
tomoya123 0:d53e9c6fc771 81 #define VSTOP_CIF 0x7b
tomoya123 0:d53e9c6fc771 82 #define VREF_CIF 0x02
tomoya123 0:d53e9c6fc771 83 #define COM3_CIF 0x08
tomoya123 0:d53e9c6fc771 84 #define COM14_CIF 0x11
tomoya123 0:d53e9c6fc771 85 #define SCALING_XSC_CIF 0x3a
tomoya123 0:d53e9c6fc771 86 #define SCALING_YSC_CIF 0x35
tomoya123 0:d53e9c6fc771 87 #define SCALING_DCWCTR_CIF 0x11
tomoya123 0:d53e9c6fc771 88 #define SCALING_PCLK_DIV_CIF 0xf1
tomoya123 0:d53e9c6fc771 89 #define SCALING_PCLK_DELAY_CIF 0x02
tomoya123 0:d53e9c6fc771 90
tomoya123 0:d53e9c6fc771 91 // QCIF setting no tested no tested linux src 2.6.29-rc5 ov7670_soc.c
tomoya123 0:d53e9c6fc771 92 #define COM7_QCIF 0x00
tomoya123 0:d53e9c6fc771 93 #define HSTART_QCIF 0x39
tomoya123 0:d53e9c6fc771 94 #define HSTOP_QCIF 0x03
tomoya123 0:d53e9c6fc771 95 #define HREF_QCIF 0x80
tomoya123 0:d53e9c6fc771 96 #define VSTART_QCIF 0x03
tomoya123 0:d53e9c6fc771 97 #define VSTOP_QCIF 0x7b
tomoya123 0:d53e9c6fc771 98 #define VREF_QCIF 0x02
tomoya123 0:d53e9c6fc771 99 #define COM3_QCIF 0x0c
tomoya123 0:d53e9c6fc771 100 #define COM14_QCIF 0x11
tomoya123 0:d53e9c6fc771 101 #define SCALING_XSC_QCIF 0x3a
tomoya123 0:d53e9c6fc771 102 #define SCALING_YSC_QCIF 0x35
tomoya123 0:d53e9c6fc771 103 #define SCALING_DCWCTR_QCIF 0x11
tomoya123 0:d53e9c6fc771 104 #define SCALING_PCLK_DIV_QCIF 0xf1
tomoya123 0:d53e9c6fc771 105 #define SCALING_PCLK_DELAY_QCIF 0x52
tomoya123 0:d53e9c6fc771 106
tomoya123 0:d53e9c6fc771 107 // YUV
tomoya123 0:d53e9c6fc771 108 #define REG_COM13 0x3d /* Control 13 */
tomoya123 0:d53e9c6fc771 109 #define REG_TSLB 0x3a /* lots of stuff */
tomoya123 0:d53e9c6fc771 110
tomoya123 0:d53e9c6fc771 111 #define COM7_YUV 0x00 /* YUV */
tomoya123 0:d53e9c6fc771 112 #define COM13_UV 0x00 /* U before V - w/TSLB */
tomoya123 0:d53e9c6fc771 113 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
tomoya123 0:d53e9c6fc771 114 #define TSLB_VLAST 0x00 /* YUYV - see com13 */
tomoya123 0:d53e9c6fc771 115 #define TSLB_ULAST 0x00 /* YVYU - see com13 */
tomoya123 0:d53e9c6fc771 116 #define TSLB_YLAST 0x08 /* UYVY or VYUY - see com13 */
tomoya123 0:d53e9c6fc771 117
tomoya123 0:d53e9c6fc771 118 // RGB
tomoya123 0:d53e9c6fc771 119 #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
tomoya123 0:d53e9c6fc771 120
tomoya123 0:d53e9c6fc771 121 // RGB444
tomoya123 0:d53e9c6fc771 122 #define REG_RGB444 0x8c /* RGB 444 control */
tomoya123 0:d53e9c6fc771 123 #define REG_COM15 0x40 /* Control 15 */
tomoya123 0:d53e9c6fc771 124
tomoya123 0:d53e9c6fc771 125 #define RGB444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
tomoya123 0:d53e9c6fc771 126 #define RGB444_XBGR 0x00
tomoya123 0:d53e9c6fc771 127 #define RGB444_BGRX 0x01 /* Empty nibble at end */
tomoya123 0:d53e9c6fc771 128 #define COM15_RGB444 0x10 /* RGB444 output */
tomoya123 0:d53e9c6fc771 129
tomoya123 0:d53e9c6fc771 130 // RGB555
tomoya123 0:d53e9c6fc771 131 #define RGB444_DISABLE 0x00 /* Turn off RGB444, overrides 5x5 */
tomoya123 0:d53e9c6fc771 132 #define COM15_RGB555 0x30 /* RGB555 output */
tomoya123 0:d53e9c6fc771 133
tomoya123 0:d53e9c6fc771 134 // RGB565
tomoya123 0:d53e9c6fc771 135 #define COM15_RGB565 0x10 /* RGB565 output */
tomoya123 0:d53e9c6fc771 136
tomoya123 0:d53e9c6fc771 137 // Bayer RGB
tomoya123 0:d53e9c6fc771 138 #define COM7_BAYER 0x01 /* Bayer format */
tomoya123 0:d53e9c6fc771 139 #define COM7_PBAYER 0x05 /* "Processed bayer" */
tomoya123 0:d53e9c6fc771 140
tomoya123 0:d53e9c6fc771 141
tomoya123 0:d53e9c6fc771 142 // data format
tomoya123 0:d53e9c6fc771 143 #define COM15_R10F0 0x00 /* Data range 10 to F0 */
tomoya123 0:d53e9c6fc771 144 #define COM15_R01FE 0x80 /* 01 to FE */
tomoya123 0:d53e9c6fc771 145 #define COM15_R00FF 0xc0 /* 00 to FF */
tomoya123 0:d53e9c6fc771 146
tomoya123 0:d53e9c6fc771 147 // Night mode, flicker, banding /
tomoya123 0:d53e9c6fc771 148 #define REG_COM11 0x3b /* Control 11 */
tomoya123 0:d53e9c6fc771 149 #define COM11_NIGHT 0x80 /* NIght mode enable */
tomoya123 0:d53e9c6fc771 150 #define COM11_NIGHT_MIN_RATE_1_1 0x00 /* Normal mode same */
tomoya123 0:d53e9c6fc771 151 #define COM11_NIGHT_MIN_RATE_1_2 0x20 /* Normal mode 1/2 */
tomoya123 0:d53e9c6fc771 152 #define COM11_NIGHT_MIN_RATE_1_4 0x40 /* Normal mode 1/4 */
tomoya123 0:d53e9c6fc771 153 #define COM11_NIGHT_MIN_RATE_1_8 0x60 /* Normal mode 1/5 */
tomoya123 0:d53e9c6fc771 154 #define COM11_HZAUTO_ON 0x10 /* Auto detect 50/60 Hz on */
tomoya123 0:d53e9c6fc771 155 #define COM11_HZAUTO_OFF 0x00 /* Auto detect 50/60 Hz off */
tomoya123 0:d53e9c6fc771 156 #define COM11_60HZ 0x00 /* Manual 60Hz select */
tomoya123 0:d53e9c6fc771 157 #define COM11_50HZ 0x08 /* Manual 50Hz select */
tomoya123 0:d53e9c6fc771 158 #define COM11_EXP 0x02
tomoya123 0:d53e9c6fc771 159
tomoya123 0:d53e9c6fc771 160 #define REG_MTX1 0x4f
tomoya123 0:d53e9c6fc771 161 #define REG_MTX2 0x50
tomoya123 0:d53e9c6fc771 162 #define REG_MTX3 0x51
tomoya123 0:d53e9c6fc771 163 #define REG_MTX4 0x52
tomoya123 0:d53e9c6fc771 164 #define REG_MTX5 0x53
tomoya123 0:d53e9c6fc771 165 #define REG_MTX6 0x54
tomoya123 0:d53e9c6fc771 166 #define REG_BRIGHT 0x55 /* Brightness */
tomoya123 0:d53e9c6fc771 167 #define REG_CONTRAS 0x56 /* Contrast control */
tomoya123 0:d53e9c6fc771 168 #define REG_CONTRAS_CENTER 0x57
tomoya123 0:d53e9c6fc771 169 #define REG_MTXS 0x58
tomoya123 0:d53e9c6fc771 170 #define REG_MANU 0x67
tomoya123 0:d53e9c6fc771 171 #define REG_MANV 0x68
tomoya123 0:d53e9c6fc771 172 #define REG_GFIX 0x69 /* Fix gain control */
tomoya123 0:d53e9c6fc771 173 #define REG_GGAIN 0x6a
tomoya123 0:d53e9c6fc771 174 #define REG_DBLV 0x6b
tomoya123 0:d53e9c6fc771 175
tomoya123 0:d53e9c6fc771 176 #define REG_COM9 0x14 // Control 9 - gain ceiling
tomoya123 0:d53e9c6fc771 177 #define COM9_AGC_2X 0x00
tomoya123 0:d53e9c6fc771 178 #define COM9_AGC_4X 0x10
tomoya123 0:d53e9c6fc771 179 #define COM9_AGC_8X 0x20
tomoya123 0:d53e9c6fc771 180 #define COM9_AGC_16X 0x30
tomoya123 0:d53e9c6fc771 181 #define COM9_AGC_32X 0x40
tomoya123 0:d53e9c6fc771 182 #define COM9_AGC_64X 0x50
tomoya123 0:d53e9c6fc771 183 #define COM9_AGC_128X 0x60
tomoya123 0:d53e9c6fc771 184 #define COM9_AGC_MASK 0x70
tomoya123 0:d53e9c6fc771 185 #define COM9_FREEZE 0x01
tomoya123 0:d53e9c6fc771 186 #define COM13_GAMMA 0x80 /* Gamma enable */
tomoya123 0:d53e9c6fc771 187 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
tomoya123 0:d53e9c6fc771 188 #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
tomoya123 0:d53e9c6fc771 189 #define REG_BLUE 0x01 /* blue gain */
tomoya123 0:d53e9c6fc771 190 #define REG_RED 0x02 /* red gain */
tomoya123 0:d53e9c6fc771 191 #define REG_COM1 0x04 /* Control 1 */
tomoya123 0:d53e9c6fc771 192 #define COM1_CCIR656 0x40 /* CCIR656 enable */
tomoya123 0:d53e9c6fc771 193 #define REG_BAVE 0x05 /* U/B Average level */
tomoya123 0:d53e9c6fc771 194 #define REG_GbAVE 0x06 /* Y/Gb Average level */
tomoya123 0:d53e9c6fc771 195 #define REG_AECHH 0x07 /* AEC MS 5 bits */
tomoya123 0:d53e9c6fc771 196 #define REG_RAVE 0x08 /* V/R Average level */
tomoya123 0:d53e9c6fc771 197 #define REG_COM2 0x09 /* Control 2 */
tomoya123 0:d53e9c6fc771 198 #define COM2_SSLEEP 0x10 /* Soft sleep mode */
tomoya123 0:d53e9c6fc771 199 #define REG_PID 0x0a /* Product ID MSB */
tomoya123 0:d53e9c6fc771 200 #define REG_VER 0x0b /* Product ID LSB */
tomoya123 0:d53e9c6fc771 201 #define COM3_SWAP 0x40 /* Byte swap */
tomoya123 0:d53e9c6fc771 202 #define COM3_SCALEEN 0x08 /* Enable scaling */
tomoya123 0:d53e9c6fc771 203 #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
tomoya123 0:d53e9c6fc771 204 #define REG_COM4 0x0d /* Control 4 */
tomoya123 0:d53e9c6fc771 205 #define REG_COM5 0x0e /* All "reserved" */
tomoya123 0:d53e9c6fc771 206 #define REG_COM6 0x0f /* Control 6 */
tomoya123 0:d53e9c6fc771 207 #define REG_AECH 0x10 /* More bits of AEC value */
tomoya123 0:d53e9c6fc771 208 #define REG_CLKRC 0x11 /* Clocl control */
tomoya123 0:d53e9c6fc771 209 #define CLK_EXT 0x40 /* Use external clock directly */
tomoya123 0:d53e9c6fc771 210 #define CLK_SCALE 0x3f /* Mask for internal clock scale */
tomoya123 0:d53e9c6fc771 211 #define COM7_RESET 0x80 /* Register reset */
tomoya123 0:d53e9c6fc771 212 #define COM7_FMT_MASK 0x38
tomoya123 0:d53e9c6fc771 213 #define COM7_FMT_VGA 0x00
tomoya123 0:d53e9c6fc771 214 #define COM7_FMT_CIF 0x20 /* CIF format */
tomoya123 0:d53e9c6fc771 215 #define COM7_FMT_QVGA 0x10 /* QVGA format */
tomoya123 0:d53e9c6fc771 216 #define COM7_FMT_QCIF 0x08 /* QCIF format */
tomoya123 0:d53e9c6fc771 217 #define REG_COM8 0x13 /* Control 8 */
tomoya123 0:d53e9c6fc771 218 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
tomoya123 0:d53e9c6fc771 219 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
tomoya123 0:d53e9c6fc771 220 #define COM8_BFILT 0x20 /* Band filter enable */
tomoya123 0:d53e9c6fc771 221 #define COM8_AGC 0x04 /* Auto gain enable */
tomoya123 0:d53e9c6fc771 222 #define COM8_AWB 0x02 /* White balance enable */
tomoya123 0:d53e9c6fc771 223 #define COM8_AEC 0x01 /* Auto exposure enable */
tomoya123 0:d53e9c6fc771 224 #define REG_COM9 0x14 /* Control 9 - gain ceiling */
tomoya123 0:d53e9c6fc771 225 #define REG_COM10 0x15 /* Control 10 */
tomoya123 0:d53e9c6fc771 226 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
tomoya123 0:d53e9c6fc771 227 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
tomoya123 0:d53e9c6fc771 228 #define COM10_HREF_REV 0x08 /* Reverse HREF */
tomoya123 0:d53e9c6fc771 229 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
tomoya123 0:d53e9c6fc771 230 #define COM10_VS_NEG 0x02 /* VSYNC negative */
tomoya123 0:d53e9c6fc771 231 #define COM10_HS_NEG 0x01 /* HSYNC negative */
tomoya123 0:d53e9c6fc771 232 #define REG_PSHFT 0x1b /* Pixel delay after HREF */
tomoya123 0:d53e9c6fc771 233 #define REG_MIDH 0x1c /* Manuf. ID high */
tomoya123 0:d53e9c6fc771 234 #define REG_MIDL 0x1d /* Manuf. ID low */
tomoya123 0:d53e9c6fc771 235 #define REG_MVFP 0x1e /* Mirror / vflip */
tomoya123 0:d53e9c6fc771 236 #define MVFP_MIRROR 0x20 /* Mirror image */
tomoya123 0:d53e9c6fc771 237 #define MVFP_FLIP 0x10 /* Vertical flip */
tomoya123 0:d53e9c6fc771 238 #define REG_AEW 0x24 /* AGC upper limit */
tomoya123 0:d53e9c6fc771 239 #define REG_AEB 0x25 /* AGC lower limit */
tomoya123 0:d53e9c6fc771 240 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */
tomoya123 0:d53e9c6fc771 241 #define REG_HSYST 0x30 /* HSYNC rising edge delay */
tomoya123 0:d53e9c6fc771 242 #define REG_HSYEN 0x31 /* HSYNC falling edge delay */
tomoya123 0:d53e9c6fc771 243 #define REG_COM12 0x3c /* Control 12 */
tomoya123 0:d53e9c6fc771 244 #define COM12_HREF 0x80 /* HREF always */
tomoya123 0:d53e9c6fc771 245 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
tomoya123 0:d53e9c6fc771 246 #define REG_EDGE 0x3f /* Edge enhancement factor */
tomoya123 0:d53e9c6fc771 247 #define REG_COM16 0x41 /* Control 16 */
tomoya123 0:d53e9c6fc771 248 #define COM16_AWBGAIN 0x08 /* AWB gain enable */
tomoya123 0:d53e9c6fc771 249 #define REG_COM17 0x42 /* Control 17 */
tomoya123 0:d53e9c6fc771 250 #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
tomoya123 0:d53e9c6fc771 251 #define COM17_CBAR 0x08 /* DSP Color bar */
tomoya123 0:d53e9c6fc771 252 #define REG_CMATRIX_BASE 0x4f
tomoya123 0:d53e9c6fc771 253 #define CMATRIX_LEN 6
tomoya123 0:d53e9c6fc771 254 #define REG_REG76 0x76 /* OV's name */
tomoya123 0:d53e9c6fc771 255 #define R76_BLKPCOR 0x80 /* Black pixel correction enable */
tomoya123 0:d53e9c6fc771 256 #define R76_WHTPCOR 0x40 /* White pixel correction enable */
tomoya123 0:d53e9c6fc771 257 #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
tomoya123 0:d53e9c6fc771 258 #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
tomoya123 0:d53e9c6fc771 259 #define REG_BD50MAX 0xa5 /* 50hz banding step limit */
tomoya123 0:d53e9c6fc771 260 #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
tomoya123 0:d53e9c6fc771 261 #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
tomoya123 0:d53e9c6fc771 262 #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
tomoya123 0:d53e9c6fc771 263 #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
tomoya123 0:d53e9c6fc771 264 #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
tomoya123 0:d53e9c6fc771 265 #define REG_BD60MAX 0xab /* 60hz banding step limit */
tomoya123 0:d53e9c6fc771 266
tomoya123 0:d53e9c6fc771 267 #define OV7670_WRITE (0x42)
tomoya123 0:d53e9c6fc771 268 #define OV7670_READ (0x43)
tomoya123 0:d53e9c6fc771 269 #define OV7670_WRITEWAIT (20)
tomoya123 0:d53e9c6fc771 270 #define OV7670_NOACK (0)
tomoya123 0:d53e9c6fc771 271 #define OV7670_REGMAX (201)
tomoya123 0:d53e9c6fc771 272 #define OV7670_I2CFREQ (50000)
tomoya123 0:d53e9c6fc771 273
tomoya123 0:d53e9c6fc771 274 //Camera OV7670
tomoya123 0:d53e9c6fc771 275
tomoya123 0:d53e9c6fc771 276 class HeptaCamera{
tomoya123 0:d53e9c6fc771 277 public:
tomoya123 0:d53e9c6fc771 278 I2C camera;
tomoya123 0:d53e9c6fc771 279 InterruptIn vsync,href;
tomoya123 0:d53e9c6fc771 280 DigitalOut wen;
tomoya123 0:d53e9c6fc771 281 BusIn data;
tomoya123 0:d53e9c6fc771 282 DigitalOut rrst,oe,rclk;
tomoya123 0:d53e9c6fc771 283 volatile int LineCounter;
tomoya123 0:d53e9c6fc771 284 volatile int LastLines;
tomoya123 0:d53e9c6fc771 285 volatile bool CaptureReq;
tomoya123 0:d53e9c6fc771 286 volatile bool Busy;
tomoya123 0:d53e9c6fc771 287 volatile bool Done;
tomoya123 0:d53e9c6fc771 288
tomoya123 0:d53e9c6fc771 289 HeptaCamera(
tomoya123 0:d53e9c6fc771 290 PinName sda,// Camera I2C port
tomoya123 0:d53e9c6fc771 291 PinName scl,// Camera I2C port
tomoya123 0:d53e9c6fc771 292 PinName vs, // VSYNC
tomoya123 0:d53e9c6fc771 293 PinName hr, // HREF
tomoya123 0:d53e9c6fc771 294 PinName we, // WEN
tomoya123 0:d53e9c6fc771 295 PinName d7, // D7
tomoya123 0:d53e9c6fc771 296 PinName d6, // D6
tomoya123 0:d53e9c6fc771 297 PinName d5, // D5
tomoya123 0:d53e9c6fc771 298 PinName d4, // D4
tomoya123 0:d53e9c6fc771 299 PinName d3, // D3
tomoya123 0:d53e9c6fc771 300 PinName d2, // D2
tomoya123 0:d53e9c6fc771 301 PinName d1, // D1
tomoya123 0:d53e9c6fc771 302 PinName d0, // D0
tomoya123 0:d53e9c6fc771 303 PinName rt, // /RRST
tomoya123 0:d53e9c6fc771 304 PinName o, // /OE
tomoya123 0:d53e9c6fc771 305 PinName rc // RCLK
tomoya123 0:d53e9c6fc771 306 );
tomoya123 0:d53e9c6fc771 307 void CaptureNext(void);
tomoya123 0:d53e9c6fc771 308 bool CaptureDone(void);
tomoya123 0:d53e9c6fc771 309 void WriteReg(int addr,int data);
tomoya123 0:d53e9c6fc771 310 int ReadReg(int addr);
tomoya123 0:d53e9c6fc771 311 void PrintRegister(void);
tomoya123 0:d53e9c6fc771 312 void Reset(void);
tomoya123 0:d53e9c6fc771 313 void InitForFIFOWriteReset(void);
tomoya123 0:d53e9c6fc771 314 void InitSetColorbar(void);
tomoya123 0:d53e9c6fc771 315 void InitDefaultReg(void);
tomoya123 0:d53e9c6fc771 316 void InitRGB444(void);
tomoya123 0:d53e9c6fc771 317 void InitRGB555(void);
tomoya123 0:d53e9c6fc771 318 void InitRGB565(void);
tomoya123 0:d53e9c6fc771 319 void InitYUV(void);
tomoya123 0:d53e9c6fc771 320 void InitBayerRGB(void);
tomoya123 0:d53e9c6fc771 321 void InitVGA(void);
tomoya123 0:d53e9c6fc771 322 void InitFIFO_2bytes_color_nealy_limit_size(void);
tomoya123 0:d53e9c6fc771 323 void InitVGA_3_4(void);
tomoya123 0:d53e9c6fc771 324 void InitQVGA(void);
tomoya123 0:d53e9c6fc771 325 void InitQQVGA();
tomoya123 0:d53e9c6fc771 326 void VsyncHandler(void);
tomoya123 0:d53e9c6fc771 327 void HrefHandler(void);
tomoya123 0:d53e9c6fc771 328 int ReadOneByte(void);
tomoya123 0:d53e9c6fc771 329 void ReadStart(void);
tomoya123 0:d53e9c6fc771 330 void ReadStop(void);
tomoya123 0:d53e9c6fc771 331 void shoot();
tomoya123 0:d53e9c6fc771 332 void shoot2();
tomoya123 0:d53e9c6fc771 333 private:
tomoya123 0:d53e9c6fc771 334 };
tomoya123 0:d53e9c6fc771 335 #endif