智也 大野
Accel
Dependencies: mbed PowerControl SDFileSystem
Fork of
HeptaAccel
by 
智也 大野
hepta_sat/HeptaCamera.h@1:63c3921c608c, 2016-12-13 (annotated)
- Committer:
- tomoya123
- Date:
- Tue Dec 13 07:51:40 2016 +0000
- Revision:
- 1:63c3921c608c
- Parent:
- 0:d721efd58e4e
Accel
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| tomoya123 | 0:d721efd58e4e | 1 | #define BITMAPFILE |
| tomoya123 | 0:d721efd58e4e | 2 | #undef BAYERBITMAPFILE |
| tomoya123 | 0:d721efd58e4e | 3 | #undef HEXFILE |
| tomoya123 | 0:d721efd58e4e | 4 | #undef COLORBAR |
| tomoya123 | 0:d721efd58e4e | 5 | #include <algorithm> |
| tomoya123 | 0:d721efd58e4e | 6 | |
| tomoya123 | 0:d721efd58e4e | 7 | #ifndef MBED_HEPTACAMERA_H |
| tomoya123 | 0:d721efd58e4e | 8 | #define MBED_HEPTACAMERA_H |
| tomoya123 | 0:d721efd58e4e | 9 | #include "mbed.h" |
| tomoya123 | 0:d721efd58e4e | 10 | |
| tomoya123 | 0:d721efd58e4e | 11 | // size register |
| tomoya123 | 0:d721efd58e4e | 12 | #define REG_COM7 0x12 /* Control 7 */ |
| tomoya123 | 0:d721efd58e4e | 13 | #define REG_HSTART 0x17 /* Horiz start high bits */ |
| tomoya123 | 0:d721efd58e4e | 14 | #define REG_HSTOP 0x18 /* Horiz stop high bits */ |
| tomoya123 | 0:d721efd58e4e | 15 | #define REG_HREF 0x32 /* HREF pieces */ |
| tomoya123 | 0:d721efd58e4e | 16 | #define REG_VSTART 0x19 /* Vert start high bits */ |
| tomoya123 | 0:d721efd58e4e | 17 | #define REG_VSTOP 0x1a /* Vert stop high bits */ |
| tomoya123 | 0:d721efd58e4e | 18 | #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */ |
| tomoya123 | 0:d721efd58e4e | 19 | #define REG_COM3 0x0c /* Control 3 */ |
| tomoya123 | 0:d721efd58e4e | 20 | #define REG_COM14 0x3e /* Control 14 */ |
| tomoya123 | 0:d721efd58e4e | 21 | #define REG_SCALING_XSC 0x70 |
| tomoya123 | 0:d721efd58e4e | 22 | #define REG_SCALING_YSC 0x71 |
| tomoya123 | 0:d721efd58e4e | 23 | #define REG_SCALING_DCWCTR 0x72 |
| tomoya123 | 0:d721efd58e4e | 24 | #define REG_SCALING_PCLK_DIV 0x73 |
| tomoya123 | 0:d721efd58e4e | 25 | #define REG_SCALING_PCLK_DELAY 0xa2 |
| tomoya123 | 0:d721efd58e4e | 26 | |
| tomoya123 | 0:d721efd58e4e | 27 | // VGA setting |
| tomoya123 | 0:d721efd58e4e | 28 | #define COM7_VGA 0x00 |
| tomoya123 | 0:d721efd58e4e | 29 | #define HSTART_VGA 0x13 |
| tomoya123 | 0:d721efd58e4e | 30 | #define HSTOP_VGA 0x01 |
| tomoya123 | 0:d721efd58e4e | 31 | #define HREF_VGA 0x36 //0xb6 0x36 |
| tomoya123 | 0:d721efd58e4e | 32 | #define VSTART_VGA 0x02 |
| tomoya123 | 0:d721efd58e4e | 33 | #define VSTOP_VGA 0x7a |
| tomoya123 | 0:d721efd58e4e | 34 | #define VREF_VGA 0x0a |
| tomoya123 | 0:d721efd58e4e | 35 | #define COM3_VGA 0x00 |
| tomoya123 | 0:d721efd58e4e | 36 | #define COM14_VGA 0x00 |
| tomoya123 | 0:d721efd58e4e | 37 | #define SCALING_XSC_VGA 0x3a |
| tomoya123 | 0:d721efd58e4e | 38 | #define SCALING_YSC_VGA 0x35 |
| tomoya123 | 0:d721efd58e4e | 39 | #define SCALING_DCWCTR_VGA 0x11 |
| tomoya123 | 0:d721efd58e4e | 40 | #define SCALING_PCLK_DIV_VGA 0xf0 |
| tomoya123 | 0:d721efd58e4e | 41 | #define SCALING_PCLK_DELAY_VGA 0x02 |
| tomoya123 | 0:d721efd58e4e | 42 | |
| tomoya123 | 0:d721efd58e4e | 43 | // QVGA setting |
| tomoya123 | 0:d721efd58e4e | 44 | #define COM7_QVGA 0x00 |
| tomoya123 | 0:d721efd58e4e | 45 | #define HSTART_QVGA 0x16 |
| tomoya123 | 0:d721efd58e4e | 46 | #define HSTOP_QVGA 0x04 |
| tomoya123 | 0:d721efd58e4e | 47 | #define HREF_QVGA 0x00 |
| tomoya123 | 0:d721efd58e4e | 48 | #define VSTART_QVGA 0x02 |
| tomoya123 | 0:d721efd58e4e | 49 | #define VSTOP_QVGA 0x7a |
| tomoya123 | 0:d721efd58e4e | 50 | #define VREF_QVGA 0x0a |
| tomoya123 | 0:d721efd58e4e | 51 | #define COM3_QVGA 0x04 |
| tomoya123 | 0:d721efd58e4e | 52 | #define COM14_QVGA 0x19 |
| tomoya123 | 0:d721efd58e4e | 53 | #define SCALING_XSC_QVGA 0x3a |
| tomoya123 | 0:d721efd58e4e | 54 | #define SCALING_YSC_QVGA 0x35 |
| tomoya123 | 0:d721efd58e4e | 55 | #define SCALING_DCWCTR_QVGA 0x11 |
| tomoya123 | 0:d721efd58e4e | 56 | #define SCALING_PCLK_DIV_QVGA 0xf1 |
| tomoya123 | 0:d721efd58e4e | 57 | #define SCALING_PCLK_DELAY_QVGA 0x02 |
| tomoya123 | 0:d721efd58e4e | 58 | |
| tomoya123 | 0:d721efd58e4e | 59 | // QQVGA setting |
| tomoya123 | 0:d721efd58e4e | 60 | #define COM7_QQVGA 0x00 |
| tomoya123 | 0:d721efd58e4e | 61 | #define HSTART_QQVGA 0x16 |
| tomoya123 | 0:d721efd58e4e | 62 | #define HSTOP_QQVGA 0x04 |
| tomoya123 | 0:d721efd58e4e | 63 | #define HREF_QQVGA 0xa4 //0x24? 0xa4? |
| tomoya123 | 0:d721efd58e4e | 64 | #define VSTART_QQVGA 0x02 |
| tomoya123 | 0:d721efd58e4e | 65 | #define VSTOP_QQVGA 0x7a |
| tomoya123 | 0:d721efd58e4e | 66 | #define VREF_QQVGA 0x0a |
| tomoya123 | 0:d721efd58e4e | 67 | #define COM3_QQVGA 0x04 |
| tomoya123 | 0:d721efd58e4e | 68 | #define COM14_QQVGA 0x1a |
| tomoya123 | 0:d721efd58e4e | 69 | #define SCALING_XSC_QQVGA 0x3a |
| tomoya123 | 0:d721efd58e4e | 70 | #define SCALING_YSC_QQVGA 0x35 |
| tomoya123 | 0:d721efd58e4e | 71 | #define SCALING_DCWCTR_QQVGA 0x22 |
| tomoya123 | 0:d721efd58e4e | 72 | #define SCALING_PCLK_DIV_QQVGA 0xf2 |
| tomoya123 | 0:d721efd58e4e | 73 | #define SCALING_PCLK_DELAY_QQVGA 0x02 |
| tomoya123 | 0:d721efd58e4e | 74 | |
| tomoya123 | 0:d721efd58e4e | 75 | // CIF setting no tested linux src 2.6.29-rc5 ov7670_soc.c |
| tomoya123 | 0:d721efd58e4e | 76 | #define COM7_CIF 0x00 |
| tomoya123 | 0:d721efd58e4e | 77 | #define HSTART_CIF 0x15 |
| tomoya123 | 0:d721efd58e4e | 78 | #define HSTOP_CIF 0x0b |
| tomoya123 | 0:d721efd58e4e | 79 | #define HREF_CIF 0xb6 |
| tomoya123 | 0:d721efd58e4e | 80 | #define VSTART_CIF 0x03 |
| tomoya123 | 0:d721efd58e4e | 81 | #define VSTOP_CIF 0x7b |
| tomoya123 | 0:d721efd58e4e | 82 | #define VREF_CIF 0x02 |
| tomoya123 | 0:d721efd58e4e | 83 | #define COM3_CIF 0x08 |
| tomoya123 | 0:d721efd58e4e | 84 | #define COM14_CIF 0x11 |
| tomoya123 | 0:d721efd58e4e | 85 | #define SCALING_XSC_CIF 0x3a |
| tomoya123 | 0:d721efd58e4e | 86 | #define SCALING_YSC_CIF 0x35 |
| tomoya123 | 0:d721efd58e4e | 87 | #define SCALING_DCWCTR_CIF 0x11 |
| tomoya123 | 0:d721efd58e4e | 88 | #define SCALING_PCLK_DIV_CIF 0xf1 |
| tomoya123 | 0:d721efd58e4e | 89 | #define SCALING_PCLK_DELAY_CIF 0x02 |
| tomoya123 | 0:d721efd58e4e | 90 | |
| tomoya123 | 0:d721efd58e4e | 91 | // QCIF setting no tested no tested linux src 2.6.29-rc5 ov7670_soc.c |
| tomoya123 | 0:d721efd58e4e | 92 | #define COM7_QCIF 0x00 |
| tomoya123 | 0:d721efd58e4e | 93 | #define HSTART_QCIF 0x39 |
| tomoya123 | 0:d721efd58e4e | 94 | #define HSTOP_QCIF 0x03 |
| tomoya123 | 0:d721efd58e4e | 95 | #define HREF_QCIF 0x80 |
| tomoya123 | 0:d721efd58e4e | 96 | #define VSTART_QCIF 0x03 |
| tomoya123 | 0:d721efd58e4e | 97 | #define VSTOP_QCIF 0x7b |
| tomoya123 | 0:d721efd58e4e | 98 | #define VREF_QCIF 0x02 |
| tomoya123 | 0:d721efd58e4e | 99 | #define COM3_QCIF 0x0c |
| tomoya123 | 0:d721efd58e4e | 100 | #define COM14_QCIF 0x11 |
| tomoya123 | 0:d721efd58e4e | 101 | #define SCALING_XSC_QCIF 0x3a |
| tomoya123 | 0:d721efd58e4e | 102 | #define SCALING_YSC_QCIF 0x35 |
| tomoya123 | 0:d721efd58e4e | 103 | #define SCALING_DCWCTR_QCIF 0x11 |
| tomoya123 | 0:d721efd58e4e | 104 | #define SCALING_PCLK_DIV_QCIF 0xf1 |
| tomoya123 | 0:d721efd58e4e | 105 | #define SCALING_PCLK_DELAY_QCIF 0x52 |
| tomoya123 | 0:d721efd58e4e | 106 | |
| tomoya123 | 0:d721efd58e4e | 107 | // YUV |
| tomoya123 | 0:d721efd58e4e | 108 | #define REG_COM13 0x3d /* Control 13 */ |
| tomoya123 | 0:d721efd58e4e | 109 | #define REG_TSLB 0x3a /* lots of stuff */ |
| tomoya123 | 0:d721efd58e4e | 110 | |
| tomoya123 | 0:d721efd58e4e | 111 | #define COM7_YUV 0x00 /* YUV */ |
| tomoya123 | 0:d721efd58e4e | 112 | #define COM13_UV 0x00 /* U before V - w/TSLB */ |
| tomoya123 | 0:d721efd58e4e | 113 | #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */ |
| tomoya123 | 0:d721efd58e4e | 114 | #define TSLB_VLAST 0x00 /* YUYV - see com13 */ |
| tomoya123 | 0:d721efd58e4e | 115 | #define TSLB_ULAST 0x00 /* YVYU - see com13 */ |
| tomoya123 | 0:d721efd58e4e | 116 | #define TSLB_YLAST 0x08 /* UYVY or VYUY - see com13 */ |
| tomoya123 | 0:d721efd58e4e | 117 | |
| tomoya123 | 0:d721efd58e4e | 118 | // RGB |
| tomoya123 | 0:d721efd58e4e | 119 | #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */ |
| tomoya123 | 0:d721efd58e4e | 120 | |
| tomoya123 | 0:d721efd58e4e | 121 | // RGB444 |
| tomoya123 | 0:d721efd58e4e | 122 | #define REG_RGB444 0x8c /* RGB 444 control */ |
| tomoya123 | 0:d721efd58e4e | 123 | #define REG_COM15 0x40 /* Control 15 */ |
| tomoya123 | 0:d721efd58e4e | 124 | |
| tomoya123 | 0:d721efd58e4e | 125 | #define RGB444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */ |
| tomoya123 | 0:d721efd58e4e | 126 | #define RGB444_XBGR 0x00 |
| tomoya123 | 0:d721efd58e4e | 127 | #define RGB444_BGRX 0x01 /* Empty nibble at end */ |
| tomoya123 | 0:d721efd58e4e | 128 | #define COM15_RGB444 0x10 /* RGB444 output */ |
| tomoya123 | 0:d721efd58e4e | 129 | |
| tomoya123 | 0:d721efd58e4e | 130 | // RGB555 |
| tomoya123 | 0:d721efd58e4e | 131 | #define RGB444_DISABLE 0x00 /* Turn off RGB444, overrides 5x5 */ |
| tomoya123 | 0:d721efd58e4e | 132 | #define COM15_RGB555 0x30 /* RGB555 output */ |
| tomoya123 | 0:d721efd58e4e | 133 | |
| tomoya123 | 0:d721efd58e4e | 134 | // RGB565 |
| tomoya123 | 0:d721efd58e4e | 135 | #define COM15_RGB565 0x10 /* RGB565 output */ |
| tomoya123 | 0:d721efd58e4e | 136 | |
| tomoya123 | 0:d721efd58e4e | 137 | // Bayer RGB |
| tomoya123 | 0:d721efd58e4e | 138 | #define COM7_BAYER 0x01 /* Bayer format */ |
| tomoya123 | 0:d721efd58e4e | 139 | #define COM7_PBAYER 0x05 /* "Processed bayer" */ |
| tomoya123 | 0:d721efd58e4e | 140 | |
| tomoya123 | 0:d721efd58e4e | 141 | |
| tomoya123 | 0:d721efd58e4e | 142 | // data format |
| tomoya123 | 0:d721efd58e4e | 143 | #define COM15_R10F0 0x00 /* Data range 10 to F0 */ |
| tomoya123 | 0:d721efd58e4e | 144 | #define COM15_R01FE 0x80 /* 01 to FE */ |
| tomoya123 | 0:d721efd58e4e | 145 | #define COM15_R00FF 0xc0 /* 00 to FF */ |
| tomoya123 | 0:d721efd58e4e | 146 | |
| tomoya123 | 0:d721efd58e4e | 147 | // Night mode, flicker, banding / |
| tomoya123 | 0:d721efd58e4e | 148 | #define REG_COM11 0x3b /* Control 11 */ |
| tomoya123 | 0:d721efd58e4e | 149 | #define COM11_NIGHT 0x80 /* NIght mode enable */ |
| tomoya123 | 0:d721efd58e4e | 150 | #define COM11_NIGHT_MIN_RATE_1_1 0x00 /* Normal mode same */ |
| tomoya123 | 0:d721efd58e4e | 151 | #define COM11_NIGHT_MIN_RATE_1_2 0x20 /* Normal mode 1/2 */ |
| tomoya123 | 0:d721efd58e4e | 152 | #define COM11_NIGHT_MIN_RATE_1_4 0x40 /* Normal mode 1/4 */ |
| tomoya123 | 0:d721efd58e4e | 153 | #define COM11_NIGHT_MIN_RATE_1_8 0x60 /* Normal mode 1/5 */ |
| tomoya123 | 0:d721efd58e4e | 154 | #define COM11_HZAUTO_ON 0x10 /* Auto detect 50/60 Hz on */ |
| tomoya123 | 0:d721efd58e4e | 155 | #define COM11_HZAUTO_OFF 0x00 /* Auto detect 50/60 Hz off */ |
| tomoya123 | 0:d721efd58e4e | 156 | #define COM11_60HZ 0x00 /* Manual 60Hz select */ |
| tomoya123 | 0:d721efd58e4e | 157 | #define COM11_50HZ 0x08 /* Manual 50Hz select */ |
| tomoya123 | 0:d721efd58e4e | 158 | #define COM11_EXP 0x02 |
| tomoya123 | 0:d721efd58e4e | 159 | |
| tomoya123 | 0:d721efd58e4e | 160 | #define REG_MTX1 0x4f |
| tomoya123 | 0:d721efd58e4e | 161 | #define REG_MTX2 0x50 |
| tomoya123 | 0:d721efd58e4e | 162 | #define REG_MTX3 0x51 |
| tomoya123 | 0:d721efd58e4e | 163 | #define REG_MTX4 0x52 |
| tomoya123 | 0:d721efd58e4e | 164 | #define REG_MTX5 0x53 |
| tomoya123 | 0:d721efd58e4e | 165 | #define REG_MTX6 0x54 |
| tomoya123 | 0:d721efd58e4e | 166 | #define REG_BRIGHT 0x55 /* Brightness */ |
| tomoya123 | 0:d721efd58e4e | 167 | #define REG_CONTRAS 0x56 /* Contrast control */ |
| tomoya123 | 0:d721efd58e4e | 168 | #define REG_CONTRAS_CENTER 0x57 |
| tomoya123 | 0:d721efd58e4e | 169 | #define REG_MTXS 0x58 |
| tomoya123 | 0:d721efd58e4e | 170 | #define REG_MANU 0x67 |
| tomoya123 | 0:d721efd58e4e | 171 | #define REG_MANV 0x68 |
| tomoya123 | 0:d721efd58e4e | 172 | #define REG_GFIX 0x69 /* Fix gain control */ |
| tomoya123 | 0:d721efd58e4e | 173 | #define REG_GGAIN 0x6a |
| tomoya123 | 0:d721efd58e4e | 174 | #define REG_DBLV 0x6b |
| tomoya123 | 0:d721efd58e4e | 175 | |
| tomoya123 | 0:d721efd58e4e | 176 | #define REG_COM9 0x14 // Control 9 - gain ceiling |
| tomoya123 | 0:d721efd58e4e | 177 | #define COM9_AGC_2X 0x00 |
| tomoya123 | 0:d721efd58e4e | 178 | #define COM9_AGC_4X 0x10 |
| tomoya123 | 0:d721efd58e4e | 179 | #define COM9_AGC_8X 0x20 |
| tomoya123 | 0:d721efd58e4e | 180 | #define COM9_AGC_16X 0x30 |
| tomoya123 | 0:d721efd58e4e | 181 | #define COM9_AGC_32X 0x40 |
| tomoya123 | 0:d721efd58e4e | 182 | #define COM9_AGC_64X 0x50 |
| tomoya123 | 0:d721efd58e4e | 183 | #define COM9_AGC_128X 0x60 |
| tomoya123 | 0:d721efd58e4e | 184 | #define COM9_AGC_MASK 0x70 |
| tomoya123 | 0:d721efd58e4e | 185 | #define COM9_FREEZE 0x01 |
| tomoya123 | 0:d721efd58e4e | 186 | #define COM13_GAMMA 0x80 /* Gamma enable */ |
| tomoya123 | 0:d721efd58e4e | 187 | #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */ |
| tomoya123 | 0:d721efd58e4e | 188 | #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */ |
| tomoya123 | 0:d721efd58e4e | 189 | #define REG_BLUE 0x01 /* blue gain */ |
| tomoya123 | 0:d721efd58e4e | 190 | #define REG_RED 0x02 /* red gain */ |
| tomoya123 | 0:d721efd58e4e | 191 | #define REG_COM1 0x04 /* Control 1 */ |
| tomoya123 | 0:d721efd58e4e | 192 | #define COM1_CCIR656 0x40 /* CCIR656 enable */ |
| tomoya123 | 0:d721efd58e4e | 193 | #define REG_BAVE 0x05 /* U/B Average level */ |
| tomoya123 | 0:d721efd58e4e | 194 | #define REG_GbAVE 0x06 /* Y/Gb Average level */ |
| tomoya123 | 0:d721efd58e4e | 195 | #define REG_AECHH 0x07 /* AEC MS 5 bits */ |
| tomoya123 | 0:d721efd58e4e | 196 | #define REG_RAVE 0x08 /* V/R Average level */ |
| tomoya123 | 0:d721efd58e4e | 197 | #define REG_COM2 0x09 /* Control 2 */ |
| tomoya123 | 0:d721efd58e4e | 198 | #define COM2_SSLEEP 0x10 /* Soft sleep mode */ |
| tomoya123 | 0:d721efd58e4e | 199 | #define REG_PID 0x0a /* Product ID MSB */ |
| tomoya123 | 0:d721efd58e4e | 200 | #define REG_VER 0x0b /* Product ID LSB */ |
| tomoya123 | 0:d721efd58e4e | 201 | #define COM3_SWAP 0x40 /* Byte swap */ |
| tomoya123 | 0:d721efd58e4e | 202 | #define COM3_SCALEEN 0x08 /* Enable scaling */ |
| tomoya123 | 0:d721efd58e4e | 203 | #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */ |
| tomoya123 | 0:d721efd58e4e | 204 | #define REG_COM4 0x0d /* Control 4 */ |
| tomoya123 | 0:d721efd58e4e | 205 | #define REG_COM5 0x0e /* All "reserved" */ |
| tomoya123 | 0:d721efd58e4e | 206 | #define REG_COM6 0x0f /* Control 6 */ |
| tomoya123 | 0:d721efd58e4e | 207 | #define REG_AECH 0x10 /* More bits of AEC value */ |
| tomoya123 | 0:d721efd58e4e | 208 | #define REG_CLKRC 0x11 /* Clocl control */ |
| tomoya123 | 0:d721efd58e4e | 209 | #define CLK_EXT 0x40 /* Use external clock directly */ |
| tomoya123 | 0:d721efd58e4e | 210 | #define CLK_SCALE 0x3f /* Mask for internal clock scale */ |
| tomoya123 | 0:d721efd58e4e | 211 | #define COM7_RESET 0x80 /* Register reset */ |
| tomoya123 | 0:d721efd58e4e | 212 | #define COM7_FMT_MASK 0x38 |
| tomoya123 | 0:d721efd58e4e | 213 | #define COM7_FMT_VGA 0x00 |
| tomoya123 | 0:d721efd58e4e | 214 | #define COM7_FMT_CIF 0x20 /* CIF format */ |
| tomoya123 | 0:d721efd58e4e | 215 | #define COM7_FMT_QVGA 0x10 /* QVGA format */ |
| tomoya123 | 0:d721efd58e4e | 216 | #define COM7_FMT_QCIF 0x08 /* QCIF format */ |
| tomoya123 | 0:d721efd58e4e | 217 | #define REG_COM8 0x13 /* Control 8 */ |
| tomoya123 | 0:d721efd58e4e | 218 | #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */ |
| tomoya123 | 0:d721efd58e4e | 219 | #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */ |
| tomoya123 | 0:d721efd58e4e | 220 | #define COM8_BFILT 0x20 /* Band filter enable */ |
| tomoya123 | 0:d721efd58e4e | 221 | #define COM8_AGC 0x04 /* Auto gain enable */ |
| tomoya123 | 0:d721efd58e4e | 222 | #define COM8_AWB 0x02 /* White balance enable */ |
| tomoya123 | 0:d721efd58e4e | 223 | #define COM8_AEC 0x01 /* Auto exposure enable */ |
| tomoya123 | 0:d721efd58e4e | 224 | #define REG_COM9 0x14 /* Control 9 - gain ceiling */ |
| tomoya123 | 0:d721efd58e4e | 225 | #define REG_COM10 0x15 /* Control 10 */ |
| tomoya123 | 0:d721efd58e4e | 226 | #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */ |
| tomoya123 | 0:d721efd58e4e | 227 | #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */ |
| tomoya123 | 0:d721efd58e4e | 228 | #define COM10_HREF_REV 0x08 /* Reverse HREF */ |
| tomoya123 | 0:d721efd58e4e | 229 | #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */ |
| tomoya123 | 0:d721efd58e4e | 230 | #define COM10_VS_NEG 0x02 /* VSYNC negative */ |
| tomoya123 | 0:d721efd58e4e | 231 | #define COM10_HS_NEG 0x01 /* HSYNC negative */ |
| tomoya123 | 0:d721efd58e4e | 232 | #define REG_PSHFT 0x1b /* Pixel delay after HREF */ |
| tomoya123 | 0:d721efd58e4e | 233 | #define REG_MIDH 0x1c /* Manuf. ID high */ |
| tomoya123 | 0:d721efd58e4e | 234 | #define REG_MIDL 0x1d /* Manuf. ID low */ |
| tomoya123 | 0:d721efd58e4e | 235 | #define REG_MVFP 0x1e /* Mirror / vflip */ |
| tomoya123 | 0:d721efd58e4e | 236 | #define MVFP_MIRROR 0x20 /* Mirror image */ |
| tomoya123 | 0:d721efd58e4e | 237 | #define MVFP_FLIP 0x10 /* Vertical flip */ |
| tomoya123 | 0:d721efd58e4e | 238 | #define REG_AEW 0x24 /* AGC upper limit */ |
| tomoya123 | 0:d721efd58e4e | 239 | #define REG_AEB 0x25 /* AGC lower limit */ |
| tomoya123 | 0:d721efd58e4e | 240 | #define REG_VPT 0x26 /* AGC/AEC fast mode op region */ |
| tomoya123 | 0:d721efd58e4e | 241 | #define REG_HSYST 0x30 /* HSYNC rising edge delay */ |
| tomoya123 | 0:d721efd58e4e | 242 | #define REG_HSYEN 0x31 /* HSYNC falling edge delay */ |
| tomoya123 | 0:d721efd58e4e | 243 | #define REG_COM12 0x3c /* Control 12 */ |
| tomoya123 | 0:d721efd58e4e | 244 | #define COM12_HREF 0x80 /* HREF always */ |
| tomoya123 | 0:d721efd58e4e | 245 | #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */ |
| tomoya123 | 0:d721efd58e4e | 246 | #define REG_EDGE 0x3f /* Edge enhancement factor */ |
| tomoya123 | 0:d721efd58e4e | 247 | #define REG_COM16 0x41 /* Control 16 */ |
| tomoya123 | 0:d721efd58e4e | 248 | #define COM16_AWBGAIN 0x08 /* AWB gain enable */ |
| tomoya123 | 0:d721efd58e4e | 249 | #define REG_COM17 0x42 /* Control 17 */ |
| tomoya123 | 0:d721efd58e4e | 250 | #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */ |
| tomoya123 | 0:d721efd58e4e | 251 | #define COM17_CBAR 0x08 /* DSP Color bar */ |
| tomoya123 | 0:d721efd58e4e | 252 | #define REG_CMATRIX_BASE 0x4f |
| tomoya123 | 0:d721efd58e4e | 253 | #define CMATRIX_LEN 6 |
| tomoya123 | 0:d721efd58e4e | 254 | #define REG_REG76 0x76 /* OV's name */ |
| tomoya123 | 0:d721efd58e4e | 255 | #define R76_BLKPCOR 0x80 /* Black pixel correction enable */ |
| tomoya123 | 0:d721efd58e4e | 256 | #define R76_WHTPCOR 0x40 /* White pixel correction enable */ |
| tomoya123 | 0:d721efd58e4e | 257 | #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */ |
| tomoya123 | 0:d721efd58e4e | 258 | #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */ |
| tomoya123 | 0:d721efd58e4e | 259 | #define REG_BD50MAX 0xa5 /* 50hz banding step limit */ |
| tomoya123 | 0:d721efd58e4e | 260 | #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */ |
| tomoya123 | 0:d721efd58e4e | 261 | #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */ |
| tomoya123 | 0:d721efd58e4e | 262 | #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */ |
| tomoya123 | 0:d721efd58e4e | 263 | #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */ |
| tomoya123 | 0:d721efd58e4e | 264 | #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */ |
| tomoya123 | 0:d721efd58e4e | 265 | #define REG_BD60MAX 0xab /* 60hz banding step limit */ |
| tomoya123 | 0:d721efd58e4e | 266 | |
| tomoya123 | 0:d721efd58e4e | 267 | #define OV7670_WRITE (0x42) |
| tomoya123 | 0:d721efd58e4e | 268 | #define OV7670_READ (0x43) |
| tomoya123 | 0:d721efd58e4e | 269 | #define OV7670_WRITEWAIT (20) |
| tomoya123 | 0:d721efd58e4e | 270 | #define OV7670_NOACK (0) |
| tomoya123 | 0:d721efd58e4e | 271 | #define OV7670_REGMAX (201) |
| tomoya123 | 0:d721efd58e4e | 272 | #define OV7670_I2CFREQ (50000) |
| tomoya123 | 0:d721efd58e4e | 273 | |
| tomoya123 | 0:d721efd58e4e | 274 | //Camera OV7670 |
| tomoya123 | 0:d721efd58e4e | 275 | |
| tomoya123 | 0:d721efd58e4e | 276 | class HeptaCamera{ |
| tomoya123 | 0:d721efd58e4e | 277 | public: |
| tomoya123 | 0:d721efd58e4e | 278 | I2C camera; |
| tomoya123 | 0:d721efd58e4e | 279 | InterruptIn vsync,href; |
| tomoya123 | 0:d721efd58e4e | 280 | DigitalOut wen; |
| tomoya123 | 0:d721efd58e4e | 281 | BusIn data; |
| tomoya123 | 0:d721efd58e4e | 282 | DigitalOut rrst,oe,rclk; |
| tomoya123 | 0:d721efd58e4e | 283 | volatile int LineCounter; |
| tomoya123 | 0:d721efd58e4e | 284 | volatile int LastLines; |
| tomoya123 | 0:d721efd58e4e | 285 | volatile bool CaptureReq; |
| tomoya123 | 0:d721efd58e4e | 286 | volatile bool Busy; |
| tomoya123 | 0:d721efd58e4e | 287 | volatile bool Done; |
| tomoya123 | 0:d721efd58e4e | 288 | |
| tomoya123 | 0:d721efd58e4e | 289 | HeptaCamera( |
| tomoya123 | 0:d721efd58e4e | 290 | PinName sda,// Camera I2C port |
| tomoya123 | 0:d721efd58e4e | 291 | PinName scl,// Camera I2C port |
| tomoya123 | 0:d721efd58e4e | 292 | PinName vs, // VSYNC |
| tomoya123 | 0:d721efd58e4e | 293 | PinName hr, // HREF |
| tomoya123 | 0:d721efd58e4e | 294 | PinName we, // WEN |
| tomoya123 | 0:d721efd58e4e | 295 | PinName d7, // D7 |
| tomoya123 | 0:d721efd58e4e | 296 | PinName d6, // D6 |
| tomoya123 | 0:d721efd58e4e | 297 | PinName d5, // D5 |
| tomoya123 | 0:d721efd58e4e | 298 | PinName d4, // D4 |
| tomoya123 | 0:d721efd58e4e | 299 | PinName d3, // D3 |
| tomoya123 | 0:d721efd58e4e | 300 | PinName d2, // D2 |
| tomoya123 | 0:d721efd58e4e | 301 | PinName d1, // D1 |
| tomoya123 | 0:d721efd58e4e | 302 | PinName d0, // D0 |
| tomoya123 | 0:d721efd58e4e | 303 | PinName rt, // /RRST |
| tomoya123 | 0:d721efd58e4e | 304 | PinName o, // /OE |
| tomoya123 | 0:d721efd58e4e | 305 | PinName rc // RCLK |
| tomoya123 | 0:d721efd58e4e | 306 | ); |
| tomoya123 | 0:d721efd58e4e | 307 | void CaptureNext(void); |
| tomoya123 | 0:d721efd58e4e | 308 | bool CaptureDone(void); |
| tomoya123 | 0:d721efd58e4e | 309 | void WriteReg(int addr,int data); |
| tomoya123 | 0:d721efd58e4e | 310 | int ReadReg(int addr); |
| tomoya123 | 0:d721efd58e4e | 311 | void PrintRegister(void); |
| tomoya123 | 0:d721efd58e4e | 312 | void Reset(void); |
| tomoya123 | 0:d721efd58e4e | 313 | void InitForFIFOWriteReset(void); |
| tomoya123 | 0:d721efd58e4e | 314 | void InitSetColorbar(void); |
| tomoya123 | 0:d721efd58e4e | 315 | void InitDefaultReg(void); |
| tomoya123 | 0:d721efd58e4e | 316 | void InitRGB444(void); |
| tomoya123 | 0:d721efd58e4e | 317 | void InitRGB555(void); |
| tomoya123 | 0:d721efd58e4e | 318 | void InitRGB565(void); |
| tomoya123 | 0:d721efd58e4e | 319 | void InitYUV(void); |
| tomoya123 | 0:d721efd58e4e | 320 | void InitBayerRGB(void); |
| tomoya123 | 0:d721efd58e4e | 321 | void InitVGA(void); |
| tomoya123 | 0:d721efd58e4e | 322 | void InitFIFO_2bytes_color_nealy_limit_size(void); |
| tomoya123 | 0:d721efd58e4e | 323 | void InitVGA_3_4(void); |
| tomoya123 | 0:d721efd58e4e | 324 | void InitQVGA(void); |
| tomoya123 | 0:d721efd58e4e | 325 | void InitQQVGA(); |
| tomoya123 | 0:d721efd58e4e | 326 | void VsyncHandler(void); |
| tomoya123 | 0:d721efd58e4e | 327 | void HrefHandler(void); |
| tomoya123 | 0:d721efd58e4e | 328 | int ReadOneByte(void); |
| tomoya123 | 0:d721efd58e4e | 329 | void ReadStart(void); |
| tomoya123 | 0:d721efd58e4e | 330 | void ReadStop(void); |
| tomoya123 | 0:d721efd58e4e | 331 | void shoot(); |
| tomoya123 | 0:d721efd58e4e | 332 | void shoot2(); |
| tomoya123 | 0:d721efd58e4e | 333 | private: |
| tomoya123 | 0:d721efd58e4e | 334 | }; |
| tomoya123 | 0:d721efd58e4e | 335 | #endif |