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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/stm32f10x_tim.c@52:a51c77007319, 2013-12-02 (annotated)

Committer:: mbed_official
Date:: Mon Dec 02 11:30:05 2013 +0000
Revision:: 52:a51c77007319
Child:: 70:c1fbde68b492

Synchronized with git revision 49df530ae72ce97ccc773d1f2c13b38e868e6abd

Full URL: https://github.com/mbedmicro/mbed/commit/49df530ae72ce97ccc773d1f2c13b38e868e6abd/

Add STMicroelectronics NUCLEO_F103RB target

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	52:a51c77007319	1	/**
mbed_official	52:a51c77007319	2	******************************************************************************
mbed_official	52:a51c77007319	3	* @file stm32f10x_tim.c
mbed_official	52:a51c77007319	4	* @author MCD Application Team
mbed_official	52:a51c77007319	5	* @version V3.5.0
mbed_official	52:a51c77007319	6	* @date 11-March-2011
mbed_official	52:a51c77007319	7	* @brief This file provides all the TIM firmware functions.
mbed_official	52:a51c77007319	8	******************************************************************************
mbed_official	52:a51c77007319	9	* @attention
mbed_official	52:a51c77007319	10	*
mbed_official	52:a51c77007319	11	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
mbed_official	52:a51c77007319	12	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
mbed_official	52:a51c77007319	13	* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
mbed_official	52:a51c77007319	14	* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
mbed_official	52:a51c77007319	15	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
mbed_official	52:a51c77007319	16	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
mbed_official	52:a51c77007319	17	*
mbed_official	52:a51c77007319	18	* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
mbed_official	52:a51c77007319	19	******************************************************************************
mbed_official	52:a51c77007319	20	*/
mbed_official	52:a51c77007319	21
mbed_official	52:a51c77007319	22	/* Includes ------------------------------------------------------------------*/
mbed_official	52:a51c77007319	23	#include "stm32f10x_tim.h"
mbed_official	52:a51c77007319	24	#include "stm32f10x_rcc.h"
mbed_official	52:a51c77007319	25
mbed_official	52:a51c77007319	26	/** @addtogroup STM32F10x_StdPeriph_Driver
mbed_official	52:a51c77007319	27	* @{
mbed_official	52:a51c77007319	28	*/
mbed_official	52:a51c77007319	29
mbed_official	52:a51c77007319	30	/** @defgroup TIM
mbed_official	52:a51c77007319	31	* @brief TIM driver modules
mbed_official	52:a51c77007319	32	* @{
mbed_official	52:a51c77007319	33	*/
mbed_official	52:a51c77007319	34
mbed_official	52:a51c77007319	35	/** @defgroup TIM_Private_TypesDefinitions
mbed_official	52:a51c77007319	36	* @{
mbed_official	52:a51c77007319	37	*/
mbed_official	52:a51c77007319	38
mbed_official	52:a51c77007319	39	/**
mbed_official	52:a51c77007319	40	* @}
mbed_official	52:a51c77007319	41	*/
mbed_official	52:a51c77007319	42
mbed_official	52:a51c77007319	43	/** @defgroup TIM_Private_Defines
mbed_official	52:a51c77007319	44	* @{
mbed_official	52:a51c77007319	45	*/
mbed_official	52:a51c77007319	46
mbed_official	52:a51c77007319	47	/* ---------------------- TIM registers bit mask ------------------------ */
mbed_official	52:a51c77007319	48	#define SMCR_ETR_Mask ((uint16_t)0x00FF)
mbed_official	52:a51c77007319	49	#define CCMR_Offset ((uint16_t)0x0018)
mbed_official	52:a51c77007319	50	#define CCER_CCE_Set ((uint16_t)0x0001)
mbed_official	52:a51c77007319	51	#define CCER_CCNE_Set ((uint16_t)0x0004)
mbed_official	52:a51c77007319	52
mbed_official	52:a51c77007319	53	/**
mbed_official	52:a51c77007319	54	* @}
mbed_official	52:a51c77007319	55	*/
mbed_official	52:a51c77007319	56
mbed_official	52:a51c77007319	57	/** @defgroup TIM_Private_Macros
mbed_official	52:a51c77007319	58	* @{
mbed_official	52:a51c77007319	59	*/
mbed_official	52:a51c77007319	60
mbed_official	52:a51c77007319	61	/**
mbed_official	52:a51c77007319	62	* @}
mbed_official	52:a51c77007319	63	*/
mbed_official	52:a51c77007319	64
mbed_official	52:a51c77007319	65	/** @defgroup TIM_Private_Variables
mbed_official	52:a51c77007319	66	* @{
mbed_official	52:a51c77007319	67	*/
mbed_official	52:a51c77007319	68
mbed_official	52:a51c77007319	69	/**
mbed_official	52:a51c77007319	70	* @}
mbed_official	52:a51c77007319	71	*/
mbed_official	52:a51c77007319	72
mbed_official	52:a51c77007319	73	/** @defgroup TIM_Private_FunctionPrototypes
mbed_official	52:a51c77007319	74	* @{
mbed_official	52:a51c77007319	75	*/
mbed_official	52:a51c77007319	76
mbed_official	52:a51c77007319	77	static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
mbed_official	52:a51c77007319	78	uint16_t TIM_ICFilter);
mbed_official	52:a51c77007319	79	static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
mbed_official	52:a51c77007319	80	uint16_t TIM_ICFilter);
mbed_official	52:a51c77007319	81	static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
mbed_official	52:a51c77007319	82	uint16_t TIM_ICFilter);
mbed_official	52:a51c77007319	83	static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
mbed_official	52:a51c77007319	84	uint16_t TIM_ICFilter);
mbed_official	52:a51c77007319	85	/**
mbed_official	52:a51c77007319	86	* @}
mbed_official	52:a51c77007319	87	*/
mbed_official	52:a51c77007319	88
mbed_official	52:a51c77007319	89	/** @defgroup TIM_Private_Macros
mbed_official	52:a51c77007319	90	* @{
mbed_official	52:a51c77007319	91	*/
mbed_official	52:a51c77007319	92
mbed_official	52:a51c77007319	93	/**
mbed_official	52:a51c77007319	94	* @}
mbed_official	52:a51c77007319	95	*/
mbed_official	52:a51c77007319	96
mbed_official	52:a51c77007319	97	/** @defgroup TIM_Private_Variables
mbed_official	52:a51c77007319	98	* @{
mbed_official	52:a51c77007319	99	*/
mbed_official	52:a51c77007319	100
mbed_official	52:a51c77007319	101	/**
mbed_official	52:a51c77007319	102	* @}
mbed_official	52:a51c77007319	103	*/
mbed_official	52:a51c77007319	104
mbed_official	52:a51c77007319	105	/** @defgroup TIM_Private_FunctionPrototypes
mbed_official	52:a51c77007319	106	* @{
mbed_official	52:a51c77007319	107	*/
mbed_official	52:a51c77007319	108
mbed_official	52:a51c77007319	109	/**
mbed_official	52:a51c77007319	110	* @}
mbed_official	52:a51c77007319	111	*/
mbed_official	52:a51c77007319	112
mbed_official	52:a51c77007319	113	/** @defgroup TIM_Private_Functions
mbed_official	52:a51c77007319	114	* @{
mbed_official	52:a51c77007319	115	*/
mbed_official	52:a51c77007319	116
mbed_official	52:a51c77007319	117	/**
mbed_official	52:a51c77007319	118	* @brief Deinitializes the TIMx peripheral registers to their default reset values.
mbed_official	52:a51c77007319	119	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	120	* @retval None
mbed_official	52:a51c77007319	121	*/
mbed_official	52:a51c77007319	122	void TIM_DeInit(TIM_TypeDef* TIMx)
mbed_official	52:a51c77007319	123	{
mbed_official	52:a51c77007319	124	/* Check the parameters */
mbed_official	52:a51c77007319	125	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	126
mbed_official	52:a51c77007319	127	if (TIMx == TIM1)
mbed_official	52:a51c77007319	128	{
mbed_official	52:a51c77007319	129	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
mbed_official	52:a51c77007319	130	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
mbed_official	52:a51c77007319	131	}
mbed_official	52:a51c77007319	132	else if (TIMx == TIM2)
mbed_official	52:a51c77007319	133	{
mbed_official	52:a51c77007319	134	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
mbed_official	52:a51c77007319	135	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
mbed_official	52:a51c77007319	136	}
mbed_official	52:a51c77007319	137	else if (TIMx == TIM3)
mbed_official	52:a51c77007319	138	{
mbed_official	52:a51c77007319	139	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
mbed_official	52:a51c77007319	140	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
mbed_official	52:a51c77007319	141	}
mbed_official	52:a51c77007319	142	else if (TIMx == TIM4)
mbed_official	52:a51c77007319	143	{
mbed_official	52:a51c77007319	144	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
mbed_official	52:a51c77007319	145	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
mbed_official	52:a51c77007319	146	}
mbed_official	52:a51c77007319	147	else if (TIMx == TIM5)
mbed_official	52:a51c77007319	148	{
mbed_official	52:a51c77007319	149	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
mbed_official	52:a51c77007319	150	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
mbed_official	52:a51c77007319	151	}
mbed_official	52:a51c77007319	152	else if (TIMx == TIM6)
mbed_official	52:a51c77007319	153	{
mbed_official	52:a51c77007319	154	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
mbed_official	52:a51c77007319	155	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
mbed_official	52:a51c77007319	156	}
mbed_official	52:a51c77007319	157	else if (TIMx == TIM7)
mbed_official	52:a51c77007319	158	{
mbed_official	52:a51c77007319	159	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
mbed_official	52:a51c77007319	160	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
mbed_official	52:a51c77007319	161	}
mbed_official	52:a51c77007319	162	else if (TIMx == TIM8)
mbed_official	52:a51c77007319	163	{
mbed_official	52:a51c77007319	164	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
mbed_official	52:a51c77007319	165	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
mbed_official	52:a51c77007319	166	}
mbed_official	52:a51c77007319	167	else if (TIMx == TIM9)
mbed_official	52:a51c77007319	168	{
mbed_official	52:a51c77007319	169	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
mbed_official	52:a51c77007319	170	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);
mbed_official	52:a51c77007319	171	}
mbed_official	52:a51c77007319	172	else if (TIMx == TIM10)
mbed_official	52:a51c77007319	173	{
mbed_official	52:a51c77007319	174	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
mbed_official	52:a51c77007319	175	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);
mbed_official	52:a51c77007319	176	}
mbed_official	52:a51c77007319	177	else if (TIMx == TIM11)
mbed_official	52:a51c77007319	178	{
mbed_official	52:a51c77007319	179	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
mbed_official	52:a51c77007319	180	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);
mbed_official	52:a51c77007319	181	}
mbed_official	52:a51c77007319	182	else if (TIMx == TIM12)
mbed_official	52:a51c77007319	183	{
mbed_official	52:a51c77007319	184	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
mbed_official	52:a51c77007319	185	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);
mbed_official	52:a51c77007319	186	}
mbed_official	52:a51c77007319	187	else if (TIMx == TIM13)
mbed_official	52:a51c77007319	188	{
mbed_official	52:a51c77007319	189	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
mbed_official	52:a51c77007319	190	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);
mbed_official	52:a51c77007319	191	}
mbed_official	52:a51c77007319	192	else if (TIMx == TIM14)
mbed_official	52:a51c77007319	193	{
mbed_official	52:a51c77007319	194	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
mbed_official	52:a51c77007319	195	RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);
mbed_official	52:a51c77007319	196	}
mbed_official	52:a51c77007319	197	else if (TIMx == TIM15)
mbed_official	52:a51c77007319	198	{
mbed_official	52:a51c77007319	199	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
mbed_official	52:a51c77007319	200	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
mbed_official	52:a51c77007319	201	}
mbed_official	52:a51c77007319	202	else if (TIMx == TIM16)
mbed_official	52:a51c77007319	203	{
mbed_official	52:a51c77007319	204	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
mbed_official	52:a51c77007319	205	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
mbed_official	52:a51c77007319	206	}
mbed_official	52:a51c77007319	207	else
mbed_official	52:a51c77007319	208	{
mbed_official	52:a51c77007319	209	if (TIMx == TIM17)
mbed_official	52:a51c77007319	210	{
mbed_official	52:a51c77007319	211	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
mbed_official	52:a51c77007319	212	RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
mbed_official	52:a51c77007319	213	}
mbed_official	52:a51c77007319	214	}
mbed_official	52:a51c77007319	215	}
mbed_official	52:a51c77007319	216
mbed_official	52:a51c77007319	217	/**
mbed_official	52:a51c77007319	218	* @brief Initializes the TIMx Time Base Unit peripheral according to
mbed_official	52:a51c77007319	219	* the specified parameters in the TIM_TimeBaseInitStruct.
mbed_official	52:a51c77007319	220	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	221	* @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
mbed_official	52:a51c77007319	222	* structure that contains the configuration information for the
mbed_official	52:a51c77007319	223	* specified TIM peripheral.
mbed_official	52:a51c77007319	224	* @retval None
mbed_official	52:a51c77007319	225	*/
mbed_official	52:a51c77007319	226	void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
mbed_official	52:a51c77007319	227	{
mbed_official	52:a51c77007319	228	uint16_t tmpcr1 = 0;
mbed_official	52:a51c77007319	229
mbed_official	52:a51c77007319	230	/* Check the parameters */
mbed_official	52:a51c77007319	231	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	232	assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
mbed_official	52:a51c77007319	233	assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
mbed_official	52:a51c77007319	234
mbed_official	52:a51c77007319	235	tmpcr1 = TIMx->CR1;
mbed_official	52:a51c77007319	236
mbed_official	52:a51c77007319	237	if((TIMx == TIM1) \|\| (TIMx == TIM8)\|\| (TIMx == TIM2) \|\| (TIMx == TIM3)\|\|
mbed_official	52:a51c77007319	238	(TIMx == TIM4) \|\| (TIMx == TIM5))
mbed_official	52:a51c77007319	239	{
mbed_official	52:a51c77007319	240	/* Select the Counter Mode */
mbed_official	52:a51c77007319	241	tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR \| TIM_CR1_CMS)));
mbed_official	52:a51c77007319	242	tmpcr1 \|= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
mbed_official	52:a51c77007319	243	}
mbed_official	52:a51c77007319	244
mbed_official	52:a51c77007319	245	if((TIMx != TIM6) && (TIMx != TIM7))
mbed_official	52:a51c77007319	246	{
mbed_official	52:a51c77007319	247	/* Set the clock division */
mbed_official	52:a51c77007319	248	tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
mbed_official	52:a51c77007319	249	tmpcr1 \|= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
mbed_official	52:a51c77007319	250	}
mbed_official	52:a51c77007319	251
mbed_official	52:a51c77007319	252	TIMx->CR1 = tmpcr1;
mbed_official	52:a51c77007319	253
mbed_official	52:a51c77007319	254	/* Set the Autoreload value */
mbed_official	52:a51c77007319	255	TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
mbed_official	52:a51c77007319	256
mbed_official	52:a51c77007319	257	/* Set the Prescaler value */
mbed_official	52:a51c77007319	258	TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
mbed_official	52:a51c77007319	259
mbed_official	52:a51c77007319	260	if ((TIMx == TIM1) \|\| (TIMx == TIM8)\|\| (TIMx == TIM15)\|\| (TIMx == TIM16) \|\| (TIMx == TIM17))
mbed_official	52:a51c77007319	261	{
mbed_official	52:a51c77007319	262	/* Set the Repetition Counter value */
mbed_official	52:a51c77007319	263	TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
mbed_official	52:a51c77007319	264	}
mbed_official	52:a51c77007319	265
mbed_official	52:a51c77007319	266	/* Generate an update event to reload the Prescaler and the Repetition counter
mbed_official	52:a51c77007319	267	values immediately */
mbed_official	52:a51c77007319	268	TIMx->EGR = TIM_PSCReloadMode_Immediate;
mbed_official	52:a51c77007319	269	}
mbed_official	52:a51c77007319	270
mbed_official	52:a51c77007319	271	/**
mbed_official	52:a51c77007319	272	* @brief Initializes the TIMx Channel1 according to the specified
mbed_official	52:a51c77007319	273	* parameters in the TIM_OCInitStruct.
mbed_official	52:a51c77007319	274	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
mbed_official	52:a51c77007319	275	* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
mbed_official	52:a51c77007319	276	* that contains the configuration information for the specified TIM peripheral.
mbed_official	52:a51c77007319	277	* @retval None
mbed_official	52:a51c77007319	278	*/
mbed_official	52:a51c77007319	279	void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
mbed_official	52:a51c77007319	280	{
mbed_official	52:a51c77007319	281	uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
mbed_official	52:a51c77007319	282
mbed_official	52:a51c77007319	283	/* Check the parameters */
mbed_official	52:a51c77007319	284	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
mbed_official	52:a51c77007319	285	assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
mbed_official	52:a51c77007319	286	assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
mbed_official	52:a51c77007319	287	assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
mbed_official	52:a51c77007319	288	/* Disable the Channel 1: Reset the CC1E Bit */
mbed_official	52:a51c77007319	289	TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
mbed_official	52:a51c77007319	290	/* Get the TIMx CCER register value */
mbed_official	52:a51c77007319	291	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	292	/* Get the TIMx CR2 register value */
mbed_official	52:a51c77007319	293	tmpcr2 = TIMx->CR2;
mbed_official	52:a51c77007319	294
mbed_official	52:a51c77007319	295	/* Get the TIMx CCMR1 register value */
mbed_official	52:a51c77007319	296	tmpccmrx = TIMx->CCMR1;
mbed_official	52:a51c77007319	297
mbed_official	52:a51c77007319	298	/* Reset the Output Compare Mode Bits */
mbed_official	52:a51c77007319	299	tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
mbed_official	52:a51c77007319	300	tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
mbed_official	52:a51c77007319	301
mbed_official	52:a51c77007319	302	/* Select the Output Compare Mode */
mbed_official	52:a51c77007319	303	tmpccmrx \|= TIM_OCInitStruct->TIM_OCMode;
mbed_official	52:a51c77007319	304
mbed_official	52:a51c77007319	305	/* Reset the Output Polarity level */
mbed_official	52:a51c77007319	306	tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
mbed_official	52:a51c77007319	307	/* Set the Output Compare Polarity */
mbed_official	52:a51c77007319	308	tmpccer \|= TIM_OCInitStruct->TIM_OCPolarity;
mbed_official	52:a51c77007319	309
mbed_official	52:a51c77007319	310	/* Set the Output State */
mbed_official	52:a51c77007319	311	tmpccer \|= TIM_OCInitStruct->TIM_OutputState;
mbed_official	52:a51c77007319	312
mbed_official	52:a51c77007319	313	if((TIMx == TIM1) \|\| (TIMx == TIM8)\|\| (TIMx == TIM15)\|\|
mbed_official	52:a51c77007319	314	(TIMx == TIM16)\|\| (TIMx == TIM17))
mbed_official	52:a51c77007319	315	{
mbed_official	52:a51c77007319	316	assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
mbed_official	52:a51c77007319	317	assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
mbed_official	52:a51c77007319	318	assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
mbed_official	52:a51c77007319	319	assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
mbed_official	52:a51c77007319	320
mbed_official	52:a51c77007319	321	/* Reset the Output N Polarity level */
mbed_official	52:a51c77007319	322	tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
mbed_official	52:a51c77007319	323	/* Set the Output N Polarity */
mbed_official	52:a51c77007319	324	tmpccer \|= TIM_OCInitStruct->TIM_OCNPolarity;
mbed_official	52:a51c77007319	325
mbed_official	52:a51c77007319	326	/* Reset the Output N State */
mbed_official	52:a51c77007319	327	tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));
mbed_official	52:a51c77007319	328	/* Set the Output N State */
mbed_official	52:a51c77007319	329	tmpccer \|= TIM_OCInitStruct->TIM_OutputNState;
mbed_official	52:a51c77007319	330
mbed_official	52:a51c77007319	331	/* Reset the Output Compare and Output Compare N IDLE State */
mbed_official	52:a51c77007319	332	tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
mbed_official	52:a51c77007319	333	tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
mbed_official	52:a51c77007319	334
mbed_official	52:a51c77007319	335	/* Set the Output Idle state */
mbed_official	52:a51c77007319	336	tmpcr2 \|= TIM_OCInitStruct->TIM_OCIdleState;
mbed_official	52:a51c77007319	337	/* Set the Output N Idle state */
mbed_official	52:a51c77007319	338	tmpcr2 \|= TIM_OCInitStruct->TIM_OCNIdleState;
mbed_official	52:a51c77007319	339	}
mbed_official	52:a51c77007319	340	/* Write to TIMx CR2 */
mbed_official	52:a51c77007319	341	TIMx->CR2 = tmpcr2;
mbed_official	52:a51c77007319	342
mbed_official	52:a51c77007319	343	/* Write to TIMx CCMR1 */
mbed_official	52:a51c77007319	344	TIMx->CCMR1 = tmpccmrx;
mbed_official	52:a51c77007319	345
mbed_official	52:a51c77007319	346	/* Set the Capture Compare Register value */
mbed_official	52:a51c77007319	347	TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
mbed_official	52:a51c77007319	348
mbed_official	52:a51c77007319	349	/* Write to TIMx CCER */
mbed_official	52:a51c77007319	350	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	351	}
mbed_official	52:a51c77007319	352
mbed_official	52:a51c77007319	353	/**
mbed_official	52:a51c77007319	354	* @brief Initializes the TIMx Channel2 according to the specified
mbed_official	52:a51c77007319	355	* parameters in the TIM_OCInitStruct.
mbed_official	52:a51c77007319	356	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
mbed_official	52:a51c77007319	357	* the TIM peripheral.
mbed_official	52:a51c77007319	358	* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
mbed_official	52:a51c77007319	359	* that contains the configuration information for the specified TIM peripheral.
mbed_official	52:a51c77007319	360	* @retval None
mbed_official	52:a51c77007319	361	*/
mbed_official	52:a51c77007319	362	void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
mbed_official	52:a51c77007319	363	{
mbed_official	52:a51c77007319	364	uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
mbed_official	52:a51c77007319	365
mbed_official	52:a51c77007319	366	/* Check the parameters */
mbed_official	52:a51c77007319	367	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	368	assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
mbed_official	52:a51c77007319	369	assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
mbed_official	52:a51c77007319	370	assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
mbed_official	52:a51c77007319	371	/* Disable the Channel 2: Reset the CC2E Bit */
mbed_official	52:a51c77007319	372	TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
mbed_official	52:a51c77007319	373
mbed_official	52:a51c77007319	374	/* Get the TIMx CCER register value */
mbed_official	52:a51c77007319	375	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	376	/* Get the TIMx CR2 register value */
mbed_official	52:a51c77007319	377	tmpcr2 = TIMx->CR2;
mbed_official	52:a51c77007319	378
mbed_official	52:a51c77007319	379	/* Get the TIMx CCMR1 register value */
mbed_official	52:a51c77007319	380	tmpccmrx = TIMx->CCMR1;
mbed_official	52:a51c77007319	381
mbed_official	52:a51c77007319	382	/* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official	52:a51c77007319	383	tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
mbed_official	52:a51c77007319	384	tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));
mbed_official	52:a51c77007319	385
mbed_official	52:a51c77007319	386	/* Select the Output Compare Mode */
mbed_official	52:a51c77007319	387	tmpccmrx \|= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
mbed_official	52:a51c77007319	388
mbed_official	52:a51c77007319	389	/* Reset the Output Polarity level */
mbed_official	52:a51c77007319	390	tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
mbed_official	52:a51c77007319	391	/* Set the Output Compare Polarity */
mbed_official	52:a51c77007319	392	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
mbed_official	52:a51c77007319	393
mbed_official	52:a51c77007319	394	/* Set the Output State */
mbed_official	52:a51c77007319	395	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
mbed_official	52:a51c77007319	396
mbed_official	52:a51c77007319	397	if((TIMx == TIM1) \|\| (TIMx == TIM8))
mbed_official	52:a51c77007319	398	{
mbed_official	52:a51c77007319	399	assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
mbed_official	52:a51c77007319	400	assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
mbed_official	52:a51c77007319	401	assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
mbed_official	52:a51c77007319	402	assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
mbed_official	52:a51c77007319	403
mbed_official	52:a51c77007319	404	/* Reset the Output N Polarity level */
mbed_official	52:a51c77007319	405	tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));
mbed_official	52:a51c77007319	406	/* Set the Output N Polarity */
mbed_official	52:a51c77007319	407	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
mbed_official	52:a51c77007319	408
mbed_official	52:a51c77007319	409	/* Reset the Output N State */
mbed_official	52:a51c77007319	410	tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE));
mbed_official	52:a51c77007319	411	/* Set the Output N State */
mbed_official	52:a51c77007319	412	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
mbed_official	52:a51c77007319	413
mbed_official	52:a51c77007319	414	/* Reset the Output Compare and Output Compare N IDLE State */
mbed_official	52:a51c77007319	415	tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
mbed_official	52:a51c77007319	416	tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));
mbed_official	52:a51c77007319	417
mbed_official	52:a51c77007319	418	/* Set the Output Idle state */
mbed_official	52:a51c77007319	419	tmpcr2 \|= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
mbed_official	52:a51c77007319	420	/* Set the Output N Idle state */
mbed_official	52:a51c77007319	421	tmpcr2 \|= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
mbed_official	52:a51c77007319	422	}
mbed_official	52:a51c77007319	423	/* Write to TIMx CR2 */
mbed_official	52:a51c77007319	424	TIMx->CR2 = tmpcr2;
mbed_official	52:a51c77007319	425
mbed_official	52:a51c77007319	426	/* Write to TIMx CCMR1 */
mbed_official	52:a51c77007319	427	TIMx->CCMR1 = tmpccmrx;
mbed_official	52:a51c77007319	428
mbed_official	52:a51c77007319	429	/* Set the Capture Compare Register value */
mbed_official	52:a51c77007319	430	TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
mbed_official	52:a51c77007319	431
mbed_official	52:a51c77007319	432	/* Write to TIMx CCER */
mbed_official	52:a51c77007319	433	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	434	}
mbed_official	52:a51c77007319	435
mbed_official	52:a51c77007319	436	/**
mbed_official	52:a51c77007319	437	* @brief Initializes the TIMx Channel3 according to the specified
mbed_official	52:a51c77007319	438	* parameters in the TIM_OCInitStruct.
mbed_official	52:a51c77007319	439	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	440	* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
mbed_official	52:a51c77007319	441	* that contains the configuration information for the specified TIM peripheral.
mbed_official	52:a51c77007319	442	* @retval None
mbed_official	52:a51c77007319	443	*/
mbed_official	52:a51c77007319	444	void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
mbed_official	52:a51c77007319	445	{
mbed_official	52:a51c77007319	446	uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
mbed_official	52:a51c77007319	447
mbed_official	52:a51c77007319	448	/* Check the parameters */
mbed_official	52:a51c77007319	449	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	450	assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
mbed_official	52:a51c77007319	451	assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
mbed_official	52:a51c77007319	452	assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
mbed_official	52:a51c77007319	453	/* Disable the Channel 2: Reset the CC2E Bit */
mbed_official	52:a51c77007319	454	TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
mbed_official	52:a51c77007319	455
mbed_official	52:a51c77007319	456	/* Get the TIMx CCER register value */
mbed_official	52:a51c77007319	457	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	458	/* Get the TIMx CR2 register value */
mbed_official	52:a51c77007319	459	tmpcr2 = TIMx->CR2;
mbed_official	52:a51c77007319	460
mbed_official	52:a51c77007319	461	/* Get the TIMx CCMR2 register value */
mbed_official	52:a51c77007319	462	tmpccmrx = TIMx->CCMR2;
mbed_official	52:a51c77007319	463
mbed_official	52:a51c77007319	464	/* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official	52:a51c77007319	465	tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
mbed_official	52:a51c77007319	466	tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));
mbed_official	52:a51c77007319	467	/* Select the Output Compare Mode */
mbed_official	52:a51c77007319	468	tmpccmrx \|= TIM_OCInitStruct->TIM_OCMode;
mbed_official	52:a51c77007319	469
mbed_official	52:a51c77007319	470	/* Reset the Output Polarity level */
mbed_official	52:a51c77007319	471	tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
mbed_official	52:a51c77007319	472	/* Set the Output Compare Polarity */
mbed_official	52:a51c77007319	473	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
mbed_official	52:a51c77007319	474
mbed_official	52:a51c77007319	475	/* Set the Output State */
mbed_official	52:a51c77007319	476	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
mbed_official	52:a51c77007319	477
mbed_official	52:a51c77007319	478	if((TIMx == TIM1) \|\| (TIMx == TIM8))
mbed_official	52:a51c77007319	479	{
mbed_official	52:a51c77007319	480	assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
mbed_official	52:a51c77007319	481	assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
mbed_official	52:a51c77007319	482	assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
mbed_official	52:a51c77007319	483	assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
mbed_official	52:a51c77007319	484
mbed_official	52:a51c77007319	485	/* Reset the Output N Polarity level */
mbed_official	52:a51c77007319	486	tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
mbed_official	52:a51c77007319	487	/* Set the Output N Polarity */
mbed_official	52:a51c77007319	488	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
mbed_official	52:a51c77007319	489	/* Reset the Output N State */
mbed_official	52:a51c77007319	490	tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));
mbed_official	52:a51c77007319	491
mbed_official	52:a51c77007319	492	/* Set the Output N State */
mbed_official	52:a51c77007319	493	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
mbed_official	52:a51c77007319	494	/* Reset the Output Compare and Output Compare N IDLE State */
mbed_official	52:a51c77007319	495	tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
mbed_official	52:a51c77007319	496	tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
mbed_official	52:a51c77007319	497	/* Set the Output Idle state */
mbed_official	52:a51c77007319	498	tmpcr2 \|= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
mbed_official	52:a51c77007319	499	/* Set the Output N Idle state */
mbed_official	52:a51c77007319	500	tmpcr2 \|= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
mbed_official	52:a51c77007319	501	}
mbed_official	52:a51c77007319	502	/* Write to TIMx CR2 */
mbed_official	52:a51c77007319	503	TIMx->CR2 = tmpcr2;
mbed_official	52:a51c77007319	504
mbed_official	52:a51c77007319	505	/* Write to TIMx CCMR2 */
mbed_official	52:a51c77007319	506	TIMx->CCMR2 = tmpccmrx;
mbed_official	52:a51c77007319	507
mbed_official	52:a51c77007319	508	/* Set the Capture Compare Register value */
mbed_official	52:a51c77007319	509	TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
mbed_official	52:a51c77007319	510
mbed_official	52:a51c77007319	511	/* Write to TIMx CCER */
mbed_official	52:a51c77007319	512	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	513	}
mbed_official	52:a51c77007319	514
mbed_official	52:a51c77007319	515	/**
mbed_official	52:a51c77007319	516	* @brief Initializes the TIMx Channel4 according to the specified
mbed_official	52:a51c77007319	517	* parameters in the TIM_OCInitStruct.
mbed_official	52:a51c77007319	518	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	519	* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
mbed_official	52:a51c77007319	520	* that contains the configuration information for the specified TIM peripheral.
mbed_official	52:a51c77007319	521	* @retval None
mbed_official	52:a51c77007319	522	*/
mbed_official	52:a51c77007319	523	void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
mbed_official	52:a51c77007319	524	{
mbed_official	52:a51c77007319	525	uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
mbed_official	52:a51c77007319	526
mbed_official	52:a51c77007319	527	/* Check the parameters */
mbed_official	52:a51c77007319	528	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	529	assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
mbed_official	52:a51c77007319	530	assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
mbed_official	52:a51c77007319	531	assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
mbed_official	52:a51c77007319	532	/* Disable the Channel 2: Reset the CC4E Bit */
mbed_official	52:a51c77007319	533	TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
mbed_official	52:a51c77007319	534
mbed_official	52:a51c77007319	535	/* Get the TIMx CCER register value */
mbed_official	52:a51c77007319	536	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	537	/* Get the TIMx CR2 register value */
mbed_official	52:a51c77007319	538	tmpcr2 = TIMx->CR2;
mbed_official	52:a51c77007319	539
mbed_official	52:a51c77007319	540	/* Get the TIMx CCMR2 register value */
mbed_official	52:a51c77007319	541	tmpccmrx = TIMx->CCMR2;
mbed_official	52:a51c77007319	542
mbed_official	52:a51c77007319	543	/* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official	52:a51c77007319	544	tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
mbed_official	52:a51c77007319	545	tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));
mbed_official	52:a51c77007319	546
mbed_official	52:a51c77007319	547	/* Select the Output Compare Mode */
mbed_official	52:a51c77007319	548	tmpccmrx \|= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
mbed_official	52:a51c77007319	549
mbed_official	52:a51c77007319	550	/* Reset the Output Polarity level */
mbed_official	52:a51c77007319	551	tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
mbed_official	52:a51c77007319	552	/* Set the Output Compare Polarity */
mbed_official	52:a51c77007319	553	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
mbed_official	52:a51c77007319	554
mbed_official	52:a51c77007319	555	/* Set the Output State */
mbed_official	52:a51c77007319	556	tmpccer \|= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
mbed_official	52:a51c77007319	557
mbed_official	52:a51c77007319	558	if((TIMx == TIM1) \|\| (TIMx == TIM8))
mbed_official	52:a51c77007319	559	{
mbed_official	52:a51c77007319	560	assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
mbed_official	52:a51c77007319	561	/* Reset the Output Compare IDLE State */
mbed_official	52:a51c77007319	562	tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
mbed_official	52:a51c77007319	563	/* Set the Output Idle state */
mbed_official	52:a51c77007319	564	tmpcr2 \|= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
mbed_official	52:a51c77007319	565	}
mbed_official	52:a51c77007319	566	/* Write to TIMx CR2 */
mbed_official	52:a51c77007319	567	TIMx->CR2 = tmpcr2;
mbed_official	52:a51c77007319	568
mbed_official	52:a51c77007319	569	/* Write to TIMx CCMR2 */
mbed_official	52:a51c77007319	570	TIMx->CCMR2 = tmpccmrx;
mbed_official	52:a51c77007319	571
mbed_official	52:a51c77007319	572	/* Set the Capture Compare Register value */
mbed_official	52:a51c77007319	573	TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
mbed_official	52:a51c77007319	574
mbed_official	52:a51c77007319	575	/* Write to TIMx CCER */
mbed_official	52:a51c77007319	576	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	577	}
mbed_official	52:a51c77007319	578
mbed_official	52:a51c77007319	579	/**
mbed_official	52:a51c77007319	580	* @brief Initializes the TIM peripheral according to the specified
mbed_official	52:a51c77007319	581	* parameters in the TIM_ICInitStruct.
mbed_official	52:a51c77007319	582	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
mbed_official	52:a51c77007319	583	* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
mbed_official	52:a51c77007319	584	* that contains the configuration information for the specified TIM peripheral.
mbed_official	52:a51c77007319	585	* @retval None
mbed_official	52:a51c77007319	586	*/
mbed_official	52:a51c77007319	587	void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
mbed_official	52:a51c77007319	588	{
mbed_official	52:a51c77007319	589	/* Check the parameters */
mbed_official	52:a51c77007319	590	assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
mbed_official	52:a51c77007319	591	assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
mbed_official	52:a51c77007319	592	assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
mbed_official	52:a51c77007319	593	assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
mbed_official	52:a51c77007319	594
mbed_official	52:a51c77007319	595	if((TIMx == TIM1) \|\| (TIMx == TIM8) \|\| (TIMx == TIM2) \|\| (TIMx == TIM3) \|\|
mbed_official	52:a51c77007319	596	(TIMx == TIM4) \|\|(TIMx == TIM5))
mbed_official	52:a51c77007319	597	{
mbed_official	52:a51c77007319	598	assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
mbed_official	52:a51c77007319	599	}
mbed_official	52:a51c77007319	600	else
mbed_official	52:a51c77007319	601	{
mbed_official	52:a51c77007319	602	assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity));
mbed_official	52:a51c77007319	603	}
mbed_official	52:a51c77007319	604	if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
mbed_official	52:a51c77007319	605	{
mbed_official	52:a51c77007319	606	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
mbed_official	52:a51c77007319	607	/* TI1 Configuration */
mbed_official	52:a51c77007319	608	TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
mbed_official	52:a51c77007319	609	TIM_ICInitStruct->TIM_ICSelection,
mbed_official	52:a51c77007319	610	TIM_ICInitStruct->TIM_ICFilter);
mbed_official	52:a51c77007319	611	/* Set the Input Capture Prescaler value */
mbed_official	52:a51c77007319	612	TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
mbed_official	52:a51c77007319	613	}
mbed_official	52:a51c77007319	614	else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
mbed_official	52:a51c77007319	615	{
mbed_official	52:a51c77007319	616	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	617	/* TI2 Configuration */
mbed_official	52:a51c77007319	618	TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
mbed_official	52:a51c77007319	619	TIM_ICInitStruct->TIM_ICSelection,
mbed_official	52:a51c77007319	620	TIM_ICInitStruct->TIM_ICFilter);
mbed_official	52:a51c77007319	621	/* Set the Input Capture Prescaler value */
mbed_official	52:a51c77007319	622	TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
mbed_official	52:a51c77007319	623	}
mbed_official	52:a51c77007319	624	else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
mbed_official	52:a51c77007319	625	{
mbed_official	52:a51c77007319	626	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	627	/* TI3 Configuration */
mbed_official	52:a51c77007319	628	TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
mbed_official	52:a51c77007319	629	TIM_ICInitStruct->TIM_ICSelection,
mbed_official	52:a51c77007319	630	TIM_ICInitStruct->TIM_ICFilter);
mbed_official	52:a51c77007319	631	/* Set the Input Capture Prescaler value */
mbed_official	52:a51c77007319	632	TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
mbed_official	52:a51c77007319	633	}
mbed_official	52:a51c77007319	634	else
mbed_official	52:a51c77007319	635	{
mbed_official	52:a51c77007319	636	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	637	/* TI4 Configuration */
mbed_official	52:a51c77007319	638	TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
mbed_official	52:a51c77007319	639	TIM_ICInitStruct->TIM_ICSelection,
mbed_official	52:a51c77007319	640	TIM_ICInitStruct->TIM_ICFilter);
mbed_official	52:a51c77007319	641	/* Set the Input Capture Prescaler value */
mbed_official	52:a51c77007319	642	TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
mbed_official	52:a51c77007319	643	}
mbed_official	52:a51c77007319	644	}
mbed_official	52:a51c77007319	645
mbed_official	52:a51c77007319	646	/**
mbed_official	52:a51c77007319	647	* @brief Configures the TIM peripheral according to the specified
mbed_official	52:a51c77007319	648	* parameters in the TIM_ICInitStruct to measure an external PWM signal.
mbed_official	52:a51c77007319	649	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	650	* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
mbed_official	52:a51c77007319	651	* that contains the configuration information for the specified TIM peripheral.
mbed_official	52:a51c77007319	652	* @retval None
mbed_official	52:a51c77007319	653	*/
mbed_official	52:a51c77007319	654	void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
mbed_official	52:a51c77007319	655	{
mbed_official	52:a51c77007319	656	uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
mbed_official	52:a51c77007319	657	uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
mbed_official	52:a51c77007319	658	/* Check the parameters */
mbed_official	52:a51c77007319	659	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	660	/* Select the Opposite Input Polarity */
mbed_official	52:a51c77007319	661	if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
mbed_official	52:a51c77007319	662	{
mbed_official	52:a51c77007319	663	icoppositepolarity = TIM_ICPolarity_Falling;
mbed_official	52:a51c77007319	664	}
mbed_official	52:a51c77007319	665	else
mbed_official	52:a51c77007319	666	{
mbed_official	52:a51c77007319	667	icoppositepolarity = TIM_ICPolarity_Rising;
mbed_official	52:a51c77007319	668	}
mbed_official	52:a51c77007319	669	/* Select the Opposite Input */
mbed_official	52:a51c77007319	670	if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
mbed_official	52:a51c77007319	671	{
mbed_official	52:a51c77007319	672	icoppositeselection = TIM_ICSelection_IndirectTI;
mbed_official	52:a51c77007319	673	}
mbed_official	52:a51c77007319	674	else
mbed_official	52:a51c77007319	675	{
mbed_official	52:a51c77007319	676	icoppositeselection = TIM_ICSelection_DirectTI;
mbed_official	52:a51c77007319	677	}
mbed_official	52:a51c77007319	678	if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
mbed_official	52:a51c77007319	679	{
mbed_official	52:a51c77007319	680	/* TI1 Configuration */
mbed_official	52:a51c77007319	681	TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
mbed_official	52:a51c77007319	682	TIM_ICInitStruct->TIM_ICFilter);
mbed_official	52:a51c77007319	683	/* Set the Input Capture Prescaler value */
mbed_official	52:a51c77007319	684	TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
mbed_official	52:a51c77007319	685	/* TI2 Configuration */
mbed_official	52:a51c77007319	686	TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
mbed_official	52:a51c77007319	687	/* Set the Input Capture Prescaler value */
mbed_official	52:a51c77007319	688	TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
mbed_official	52:a51c77007319	689	}
mbed_official	52:a51c77007319	690	else
mbed_official	52:a51c77007319	691	{
mbed_official	52:a51c77007319	692	/* TI2 Configuration */
mbed_official	52:a51c77007319	693	TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
mbed_official	52:a51c77007319	694	TIM_ICInitStruct->TIM_ICFilter);
mbed_official	52:a51c77007319	695	/* Set the Input Capture Prescaler value */
mbed_official	52:a51c77007319	696	TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
mbed_official	52:a51c77007319	697	/* TI1 Configuration */
mbed_official	52:a51c77007319	698	TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
mbed_official	52:a51c77007319	699	/* Set the Input Capture Prescaler value */
mbed_official	52:a51c77007319	700	TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
mbed_official	52:a51c77007319	701	}
mbed_official	52:a51c77007319	702	}
mbed_official	52:a51c77007319	703
mbed_official	52:a51c77007319	704	/**
mbed_official	52:a51c77007319	705	* @brief Configures the: Break feature, dead time, Lock level, the OSSI,
mbed_official	52:a51c77007319	706	* the OSSR State and the AOE(automatic output enable).
mbed_official	52:a51c77007319	707	* @param TIMx: where x can be 1 or 8 to select the TIM
mbed_official	52:a51c77007319	708	* @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
mbed_official	52:a51c77007319	709	* contains the BDTR Register configuration information for the TIM peripheral.
mbed_official	52:a51c77007319	710	* @retval None
mbed_official	52:a51c77007319	711	*/
mbed_official	52:a51c77007319	712	void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
mbed_official	52:a51c77007319	713	{
mbed_official	52:a51c77007319	714	/* Check the parameters */
mbed_official	52:a51c77007319	715	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
mbed_official	52:a51c77007319	716	assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
mbed_official	52:a51c77007319	717	assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
mbed_official	52:a51c77007319	718	assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
mbed_official	52:a51c77007319	719	assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
mbed_official	52:a51c77007319	720	assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
mbed_official	52:a51c77007319	721	assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
mbed_official	52:a51c77007319	722	/* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
mbed_official	52:a51c77007319	723	the OSSI State, the dead time value and the Automatic Output Enable Bit */
mbed_official	52:a51c77007319	724	TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState \| TIM_BDTRInitStruct->TIM_OSSIState \|
mbed_official	52:a51c77007319	725	TIM_BDTRInitStruct->TIM_LOCKLevel \| TIM_BDTRInitStruct->TIM_DeadTime \|
mbed_official	52:a51c77007319	726	TIM_BDTRInitStruct->TIM_Break \| TIM_BDTRInitStruct->TIM_BreakPolarity \|
mbed_official	52:a51c77007319	727	TIM_BDTRInitStruct->TIM_AutomaticOutput;
mbed_official	52:a51c77007319	728	}
mbed_official	52:a51c77007319	729
mbed_official	52:a51c77007319	730	/**
mbed_official	52:a51c77007319	731	* @brief Fills each TIM_TimeBaseInitStruct member with its default value.
mbed_official	52:a51c77007319	732	* @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
mbed_official	52:a51c77007319	733	* structure which will be initialized.
mbed_official	52:a51c77007319	734	* @retval None
mbed_official	52:a51c77007319	735	*/
mbed_official	52:a51c77007319	736	void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
mbed_official	52:a51c77007319	737	{
mbed_official	52:a51c77007319	738	/* Set the default configuration */
mbed_official	52:a51c77007319	739	TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
mbed_official	52:a51c77007319	740	TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
mbed_official	52:a51c77007319	741	TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
mbed_official	52:a51c77007319	742	TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
mbed_official	52:a51c77007319	743	TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
mbed_official	52:a51c77007319	744	}
mbed_official	52:a51c77007319	745
mbed_official	52:a51c77007319	746	/**
mbed_official	52:a51c77007319	747	* @brief Fills each TIM_OCInitStruct member with its default value.
mbed_official	52:a51c77007319	748	* @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
mbed_official	52:a51c77007319	749	* be initialized.
mbed_official	52:a51c77007319	750	* @retval None
mbed_official	52:a51c77007319	751	*/
mbed_official	52:a51c77007319	752	void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
mbed_official	52:a51c77007319	753	{
mbed_official	52:a51c77007319	754	/* Set the default configuration */
mbed_official	52:a51c77007319	755	TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
mbed_official	52:a51c77007319	756	TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
mbed_official	52:a51c77007319	757	TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
mbed_official	52:a51c77007319	758	TIM_OCInitStruct->TIM_Pulse = 0x0000;
mbed_official	52:a51c77007319	759	TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
mbed_official	52:a51c77007319	760	TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
mbed_official	52:a51c77007319	761	TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
mbed_official	52:a51c77007319	762	TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
mbed_official	52:a51c77007319	763	}
mbed_official	52:a51c77007319	764
mbed_official	52:a51c77007319	765	/**
mbed_official	52:a51c77007319	766	* @brief Fills each TIM_ICInitStruct member with its default value.
mbed_official	52:a51c77007319	767	* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
mbed_official	52:a51c77007319	768	* be initialized.
mbed_official	52:a51c77007319	769	* @retval None
mbed_official	52:a51c77007319	770	*/
mbed_official	52:a51c77007319	771	void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
mbed_official	52:a51c77007319	772	{
mbed_official	52:a51c77007319	773	/* Set the default configuration */
mbed_official	52:a51c77007319	774	TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
mbed_official	52:a51c77007319	775	TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
mbed_official	52:a51c77007319	776	TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
mbed_official	52:a51c77007319	777	TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
mbed_official	52:a51c77007319	778	TIM_ICInitStruct->TIM_ICFilter = 0x00;
mbed_official	52:a51c77007319	779	}
mbed_official	52:a51c77007319	780
mbed_official	52:a51c77007319	781	/**
mbed_official	52:a51c77007319	782	* @brief Fills each TIM_BDTRInitStruct member with its default value.
mbed_official	52:a51c77007319	783	* @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
mbed_official	52:a51c77007319	784	* will be initialized.
mbed_official	52:a51c77007319	785	* @retval None
mbed_official	52:a51c77007319	786	*/
mbed_official	52:a51c77007319	787	void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
mbed_official	52:a51c77007319	788	{
mbed_official	52:a51c77007319	789	/* Set the default configuration */
mbed_official	52:a51c77007319	790	TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
mbed_official	52:a51c77007319	791	TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
mbed_official	52:a51c77007319	792	TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
mbed_official	52:a51c77007319	793	TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
mbed_official	52:a51c77007319	794	TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
mbed_official	52:a51c77007319	795	TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
mbed_official	52:a51c77007319	796	TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
mbed_official	52:a51c77007319	797	}
mbed_official	52:a51c77007319	798
mbed_official	52:a51c77007319	799	/**
mbed_official	52:a51c77007319	800	* @brief Enables or disables the specified TIM peripheral.
mbed_official	52:a51c77007319	801	* @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.
mbed_official	52:a51c77007319	802	* @param NewState: new state of the TIMx peripheral.
mbed_official	52:a51c77007319	803	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	804	* @retval None
mbed_official	52:a51c77007319	805	*/
mbed_official	52:a51c77007319	806	void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
mbed_official	52:a51c77007319	807	{
mbed_official	52:a51c77007319	808	/* Check the parameters */
mbed_official	52:a51c77007319	809	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	810	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	811
mbed_official	52:a51c77007319	812	if (NewState != DISABLE)
mbed_official	52:a51c77007319	813	{
mbed_official	52:a51c77007319	814	/* Enable the TIM Counter */
mbed_official	52:a51c77007319	815	TIMx->CR1 \|= TIM_CR1_CEN;
mbed_official	52:a51c77007319	816	}
mbed_official	52:a51c77007319	817	else
mbed_official	52:a51c77007319	818	{
mbed_official	52:a51c77007319	819	/* Disable the TIM Counter */
mbed_official	52:a51c77007319	820	TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
mbed_official	52:a51c77007319	821	}
mbed_official	52:a51c77007319	822	}
mbed_official	52:a51c77007319	823
mbed_official	52:a51c77007319	824	/**
mbed_official	52:a51c77007319	825	* @brief Enables or disables the TIM peripheral Main Outputs.
mbed_official	52:a51c77007319	826	* @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.
mbed_official	52:a51c77007319	827	* @param NewState: new state of the TIM peripheral Main Outputs.
mbed_official	52:a51c77007319	828	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	829	* @retval None
mbed_official	52:a51c77007319	830	*/
mbed_official	52:a51c77007319	831	void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
mbed_official	52:a51c77007319	832	{
mbed_official	52:a51c77007319	833	/* Check the parameters */
mbed_official	52:a51c77007319	834	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
mbed_official	52:a51c77007319	835	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	836	if (NewState != DISABLE)
mbed_official	52:a51c77007319	837	{
mbed_official	52:a51c77007319	838	/* Enable the TIM Main Output */
mbed_official	52:a51c77007319	839	TIMx->BDTR \|= TIM_BDTR_MOE;
mbed_official	52:a51c77007319	840	}
mbed_official	52:a51c77007319	841	else
mbed_official	52:a51c77007319	842	{
mbed_official	52:a51c77007319	843	/* Disable the TIM Main Output */
mbed_official	52:a51c77007319	844	TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));
mbed_official	52:a51c77007319	845	}
mbed_official	52:a51c77007319	846	}
mbed_official	52:a51c77007319	847
mbed_official	52:a51c77007319	848	/**
mbed_official	52:a51c77007319	849	* @brief Enables or disables the specified TIM interrupts.
mbed_official	52:a51c77007319	850	* @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.
mbed_official	52:a51c77007319	851	* @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
mbed_official	52:a51c77007319	852	* This parameter can be any combination of the following values:
mbed_official	52:a51c77007319	853	* @arg TIM_IT_Update: TIM update Interrupt source
mbed_official	52:a51c77007319	854	* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
mbed_official	52:a51c77007319	855	* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
mbed_official	52:a51c77007319	856	* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
mbed_official	52:a51c77007319	857	* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
mbed_official	52:a51c77007319	858	* @arg TIM_IT_COM: TIM Commutation Interrupt source
mbed_official	52:a51c77007319	859	* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
mbed_official	52:a51c77007319	860	* @arg TIM_IT_Break: TIM Break Interrupt source
mbed_official	52:a51c77007319	861	* @note
mbed_official	52:a51c77007319	862	* - TIM6 and TIM7 can only generate an update interrupt.
mbed_official	52:a51c77007319	863	* - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
mbed_official	52:a51c77007319	864	* TIM_IT_CC2 or TIM_IT_Trigger.
mbed_official	52:a51c77007319	865	* - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
mbed_official	52:a51c77007319	866	* - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
mbed_official	52:a51c77007319	867	* - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
mbed_official	52:a51c77007319	868	* @param NewState: new state of the TIM interrupts.
mbed_official	52:a51c77007319	869	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	870	* @retval None
mbed_official	52:a51c77007319	871	*/
mbed_official	52:a51c77007319	872	void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
mbed_official	52:a51c77007319	873	{
mbed_official	52:a51c77007319	874	/* Check the parameters */
mbed_official	52:a51c77007319	875	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	876	assert_param(IS_TIM_IT(TIM_IT));
mbed_official	52:a51c77007319	877	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	878
mbed_official	52:a51c77007319	879	if (NewState != DISABLE)
mbed_official	52:a51c77007319	880	{
mbed_official	52:a51c77007319	881	/* Enable the Interrupt sources */
mbed_official	52:a51c77007319	882	TIMx->DIER \|= TIM_IT;
mbed_official	52:a51c77007319	883	}
mbed_official	52:a51c77007319	884	else
mbed_official	52:a51c77007319	885	{
mbed_official	52:a51c77007319	886	/* Disable the Interrupt sources */
mbed_official	52:a51c77007319	887	TIMx->DIER &= (uint16_t)~TIM_IT;
mbed_official	52:a51c77007319	888	}
mbed_official	52:a51c77007319	889	}
mbed_official	52:a51c77007319	890
mbed_official	52:a51c77007319	891	/**
mbed_official	52:a51c77007319	892	* @brief Configures the TIMx event to be generate by software.
mbed_official	52:a51c77007319	893	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	894	* @param TIM_EventSource: specifies the event source.
mbed_official	52:a51c77007319	895	* This parameter can be one or more of the following values:
mbed_official	52:a51c77007319	896	* @arg TIM_EventSource_Update: Timer update Event source
mbed_official	52:a51c77007319	897	* @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
mbed_official	52:a51c77007319	898	* @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
mbed_official	52:a51c77007319	899	* @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
mbed_official	52:a51c77007319	900	* @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
mbed_official	52:a51c77007319	901	* @arg TIM_EventSource_COM: Timer COM event source
mbed_official	52:a51c77007319	902	* @arg TIM_EventSource_Trigger: Timer Trigger Event source
mbed_official	52:a51c77007319	903	* @arg TIM_EventSource_Break: Timer Break event source
mbed_official	52:a51c77007319	904	* @note
mbed_official	52:a51c77007319	905	* - TIM6 and TIM7 can only generate an update event.
mbed_official	52:a51c77007319	906	* - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
mbed_official	52:a51c77007319	907	* @retval None
mbed_official	52:a51c77007319	908	*/
mbed_official	52:a51c77007319	909	void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
mbed_official	52:a51c77007319	910	{
mbed_official	52:a51c77007319	911	/* Check the parameters */
mbed_official	52:a51c77007319	912	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	913	assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
mbed_official	52:a51c77007319	914
mbed_official	52:a51c77007319	915	/* Set the event sources */
mbed_official	52:a51c77007319	916	TIMx->EGR = TIM_EventSource;
mbed_official	52:a51c77007319	917	}
mbed_official	52:a51c77007319	918
mbed_official	52:a51c77007319	919	/**
mbed_official	52:a51c77007319	920	* @brief Configures the TIMx's DMA interface.
mbed_official	52:a51c77007319	921	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select
mbed_official	52:a51c77007319	922	* the TIM peripheral.
mbed_official	52:a51c77007319	923	* @param TIM_DMABase: DMA Base address.
mbed_official	52:a51c77007319	924	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	925	* @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
mbed_official	52:a51c77007319	926	* TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
mbed_official	52:a51c77007319	927	* TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
mbed_official	52:a51c77007319	928	* TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
mbed_official	52:a51c77007319	929	* TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
mbed_official	52:a51c77007319	930	* TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
mbed_official	52:a51c77007319	931	* TIM_DMABase_DCR.
mbed_official	52:a51c77007319	932	* @param TIM_DMABurstLength: DMA Burst length.
mbed_official	52:a51c77007319	933	* This parameter can be one value between:
mbed_official	52:a51c77007319	934	* TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
mbed_official	52:a51c77007319	935	* @retval None
mbed_official	52:a51c77007319	936	*/
mbed_official	52:a51c77007319	937	void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
mbed_official	52:a51c77007319	938	{
mbed_official	52:a51c77007319	939	/* Check the parameters */
mbed_official	52:a51c77007319	940	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
mbed_official	52:a51c77007319	941	assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
mbed_official	52:a51c77007319	942	assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
mbed_official	52:a51c77007319	943	/* Set the DMA Base and the DMA Burst Length */
mbed_official	52:a51c77007319	944	TIMx->DCR = TIM_DMABase \| TIM_DMABurstLength;
mbed_official	52:a51c77007319	945	}
mbed_official	52:a51c77007319	946
mbed_official	52:a51c77007319	947	/**
mbed_official	52:a51c77007319	948	* @brief Enables or disables the TIMx's DMA Requests.
mbed_official	52:a51c77007319	949	* @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17
mbed_official	52:a51c77007319	950	* to select the TIM peripheral.
mbed_official	52:a51c77007319	951	* @param TIM_DMASource: specifies the DMA Request sources.
mbed_official	52:a51c77007319	952	* This parameter can be any combination of the following values:
mbed_official	52:a51c77007319	953	* @arg TIM_DMA_Update: TIM update Interrupt source
mbed_official	52:a51c77007319	954	* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
mbed_official	52:a51c77007319	955	* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
mbed_official	52:a51c77007319	956	* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
mbed_official	52:a51c77007319	957	* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
mbed_official	52:a51c77007319	958	* @arg TIM_DMA_COM: TIM Commutation DMA source
mbed_official	52:a51c77007319	959	* @arg TIM_DMA_Trigger: TIM Trigger DMA source
mbed_official	52:a51c77007319	960	* @param NewState: new state of the DMA Request sources.
mbed_official	52:a51c77007319	961	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	962	* @retval None
mbed_official	52:a51c77007319	963	*/
mbed_official	52:a51c77007319	964	void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
mbed_official	52:a51c77007319	965	{
mbed_official	52:a51c77007319	966	/* Check the parameters */
mbed_official	52:a51c77007319	967	assert_param(IS_TIM_LIST9_PERIPH(TIMx));
mbed_official	52:a51c77007319	968	assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
mbed_official	52:a51c77007319	969	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	970
mbed_official	52:a51c77007319	971	if (NewState != DISABLE)
mbed_official	52:a51c77007319	972	{
mbed_official	52:a51c77007319	973	/* Enable the DMA sources */
mbed_official	52:a51c77007319	974	TIMx->DIER \|= TIM_DMASource;
mbed_official	52:a51c77007319	975	}
mbed_official	52:a51c77007319	976	else
mbed_official	52:a51c77007319	977	{
mbed_official	52:a51c77007319	978	/* Disable the DMA sources */
mbed_official	52:a51c77007319	979	TIMx->DIER &= (uint16_t)~TIM_DMASource;
mbed_official	52:a51c77007319	980	}
mbed_official	52:a51c77007319	981	}
mbed_official	52:a51c77007319	982
mbed_official	52:a51c77007319	983	/**
mbed_official	52:a51c77007319	984	* @brief Configures the TIMx internal Clock
mbed_official	52:a51c77007319	985	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15
mbed_official	52:a51c77007319	986	* to select the TIM peripheral.
mbed_official	52:a51c77007319	987	* @retval None
mbed_official	52:a51c77007319	988	*/
mbed_official	52:a51c77007319	989	void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
mbed_official	52:a51c77007319	990	{
mbed_official	52:a51c77007319	991	/* Check the parameters */
mbed_official	52:a51c77007319	992	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	993	/* Disable slave mode to clock the prescaler directly with the internal clock */
mbed_official	52:a51c77007319	994	TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
mbed_official	52:a51c77007319	995	}
mbed_official	52:a51c77007319	996
mbed_official	52:a51c77007319	997	/**
mbed_official	52:a51c77007319	998	* @brief Configures the TIMx Internal Trigger as External Clock
mbed_official	52:a51c77007319	999	* @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	1000	* @param TIM_ITRSource: Trigger source.
mbed_official	52:a51c77007319	1001	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1002	* @param TIM_TS_ITR0: Internal Trigger 0
mbed_official	52:a51c77007319	1003	* @param TIM_TS_ITR1: Internal Trigger 1
mbed_official	52:a51c77007319	1004	* @param TIM_TS_ITR2: Internal Trigger 2
mbed_official	52:a51c77007319	1005	* @param TIM_TS_ITR3: Internal Trigger 3
mbed_official	52:a51c77007319	1006	* @retval None
mbed_official	52:a51c77007319	1007	*/
mbed_official	52:a51c77007319	1008	void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
mbed_official	52:a51c77007319	1009	{
mbed_official	52:a51c77007319	1010	/* Check the parameters */
mbed_official	52:a51c77007319	1011	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	1012	assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
mbed_official	52:a51c77007319	1013	/* Select the Internal Trigger */
mbed_official	52:a51c77007319	1014	TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
mbed_official	52:a51c77007319	1015	/* Select the External clock mode1 */
mbed_official	52:a51c77007319	1016	TIMx->SMCR \|= TIM_SlaveMode_External1;
mbed_official	52:a51c77007319	1017	}
mbed_official	52:a51c77007319	1018
mbed_official	52:a51c77007319	1019	/**
mbed_official	52:a51c77007319	1020	* @brief Configures the TIMx Trigger as External Clock
mbed_official	52:a51c77007319	1021	* @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	1022	* @param TIM_TIxExternalCLKSource: Trigger source.
mbed_official	52:a51c77007319	1023	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1024	* @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
mbed_official	52:a51c77007319	1025	* @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
mbed_official	52:a51c77007319	1026	* @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
mbed_official	52:a51c77007319	1027	* @param TIM_ICPolarity: specifies the TIx Polarity.
mbed_official	52:a51c77007319	1028	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1029	* @arg TIM_ICPolarity_Rising
mbed_official	52:a51c77007319	1030	* @arg TIM_ICPolarity_Falling
mbed_official	52:a51c77007319	1031	* @param ICFilter : specifies the filter value.
mbed_official	52:a51c77007319	1032	* This parameter must be a value between 0x0 and 0xF.
mbed_official	52:a51c77007319	1033	* @retval None
mbed_official	52:a51c77007319	1034	*/
mbed_official	52:a51c77007319	1035	void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
mbed_official	52:a51c77007319	1036	uint16_t TIM_ICPolarity, uint16_t ICFilter)
mbed_official	52:a51c77007319	1037	{
mbed_official	52:a51c77007319	1038	/* Check the parameters */
mbed_official	52:a51c77007319	1039	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	1040	assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
mbed_official	52:a51c77007319	1041	assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
mbed_official	52:a51c77007319	1042	assert_param(IS_TIM_IC_FILTER(ICFilter));
mbed_official	52:a51c77007319	1043	/* Configure the Timer Input Clock Source */
mbed_official	52:a51c77007319	1044	if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
mbed_official	52:a51c77007319	1045	{
mbed_official	52:a51c77007319	1046	TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
mbed_official	52:a51c77007319	1047	}
mbed_official	52:a51c77007319	1048	else
mbed_official	52:a51c77007319	1049	{
mbed_official	52:a51c77007319	1050	TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
mbed_official	52:a51c77007319	1051	}
mbed_official	52:a51c77007319	1052	/* Select the Trigger source */
mbed_official	52:a51c77007319	1053	TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
mbed_official	52:a51c77007319	1054	/* Select the External clock mode1 */
mbed_official	52:a51c77007319	1055	TIMx->SMCR \|= TIM_SlaveMode_External1;
mbed_official	52:a51c77007319	1056	}
mbed_official	52:a51c77007319	1057
mbed_official	52:a51c77007319	1058	/**
mbed_official	52:a51c77007319	1059	* @brief Configures the External clock Mode1
mbed_official	52:a51c77007319	1060	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1061	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
mbed_official	52:a51c77007319	1062	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1063	* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
mbed_official	52:a51c77007319	1064	* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
mbed_official	52:a51c77007319	1065	* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
mbed_official	52:a51c77007319	1066	* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
mbed_official	52:a51c77007319	1067	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
mbed_official	52:a51c77007319	1068	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1069	* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
mbed_official	52:a51c77007319	1070	* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
mbed_official	52:a51c77007319	1071	* @param ExtTRGFilter: External Trigger Filter.
mbed_official	52:a51c77007319	1072	* This parameter must be a value between 0x00 and 0x0F
mbed_official	52:a51c77007319	1073	* @retval None
mbed_official	52:a51c77007319	1074	*/
mbed_official	52:a51c77007319	1075	void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
mbed_official	52:a51c77007319	1076	uint16_t ExtTRGFilter)
mbed_official	52:a51c77007319	1077	{
mbed_official	52:a51c77007319	1078	uint16_t tmpsmcr = 0;
mbed_official	52:a51c77007319	1079	/* Check the parameters */
mbed_official	52:a51c77007319	1080	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1081	assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
mbed_official	52:a51c77007319	1082	assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
mbed_official	52:a51c77007319	1083	assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
mbed_official	52:a51c77007319	1084	/* Configure the ETR Clock source */
mbed_official	52:a51c77007319	1085	TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
mbed_official	52:a51c77007319	1086
mbed_official	52:a51c77007319	1087	/* Get the TIMx SMCR register value */
mbed_official	52:a51c77007319	1088	tmpsmcr = TIMx->SMCR;
mbed_official	52:a51c77007319	1089	/* Reset the SMS Bits */
mbed_official	52:a51c77007319	1090	tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
mbed_official	52:a51c77007319	1091	/* Select the External clock mode1 */
mbed_official	52:a51c77007319	1092	tmpsmcr \|= TIM_SlaveMode_External1;
mbed_official	52:a51c77007319	1093	/* Select the Trigger selection : ETRF */
mbed_official	52:a51c77007319	1094	tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
mbed_official	52:a51c77007319	1095	tmpsmcr \|= TIM_TS_ETRF;
mbed_official	52:a51c77007319	1096	/* Write to TIMx SMCR */
mbed_official	52:a51c77007319	1097	TIMx->SMCR = tmpsmcr;
mbed_official	52:a51c77007319	1098	}
mbed_official	52:a51c77007319	1099
mbed_official	52:a51c77007319	1100	/**
mbed_official	52:a51c77007319	1101	* @brief Configures the External clock Mode2
mbed_official	52:a51c77007319	1102	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1103	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
mbed_official	52:a51c77007319	1104	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1105	* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
mbed_official	52:a51c77007319	1106	* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
mbed_official	52:a51c77007319	1107	* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
mbed_official	52:a51c77007319	1108	* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
mbed_official	52:a51c77007319	1109	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
mbed_official	52:a51c77007319	1110	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1111	* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
mbed_official	52:a51c77007319	1112	* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
mbed_official	52:a51c77007319	1113	* @param ExtTRGFilter: External Trigger Filter.
mbed_official	52:a51c77007319	1114	* This parameter must be a value between 0x00 and 0x0F
mbed_official	52:a51c77007319	1115	* @retval None
mbed_official	52:a51c77007319	1116	*/
mbed_official	52:a51c77007319	1117	void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
mbed_official	52:a51c77007319	1118	uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
mbed_official	52:a51c77007319	1119	{
mbed_official	52:a51c77007319	1120	/* Check the parameters */
mbed_official	52:a51c77007319	1121	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1122	assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
mbed_official	52:a51c77007319	1123	assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
mbed_official	52:a51c77007319	1124	assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
mbed_official	52:a51c77007319	1125	/* Configure the ETR Clock source */
mbed_official	52:a51c77007319	1126	TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
mbed_official	52:a51c77007319	1127	/* Enable the External clock mode2 */
mbed_official	52:a51c77007319	1128	TIMx->SMCR \|= TIM_SMCR_ECE;
mbed_official	52:a51c77007319	1129	}
mbed_official	52:a51c77007319	1130
mbed_official	52:a51c77007319	1131	/**
mbed_official	52:a51c77007319	1132	* @brief Configures the TIMx External Trigger (ETR).
mbed_official	52:a51c77007319	1133	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1134	* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
mbed_official	52:a51c77007319	1135	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1136	* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
mbed_official	52:a51c77007319	1137	* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
mbed_official	52:a51c77007319	1138	* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
mbed_official	52:a51c77007319	1139	* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
mbed_official	52:a51c77007319	1140	* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
mbed_official	52:a51c77007319	1141	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1142	* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
mbed_official	52:a51c77007319	1143	* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
mbed_official	52:a51c77007319	1144	* @param ExtTRGFilter: External Trigger Filter.
mbed_official	52:a51c77007319	1145	* This parameter must be a value between 0x00 and 0x0F
mbed_official	52:a51c77007319	1146	* @retval None
mbed_official	52:a51c77007319	1147	*/
mbed_official	52:a51c77007319	1148	void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
mbed_official	52:a51c77007319	1149	uint16_t ExtTRGFilter)
mbed_official	52:a51c77007319	1150	{
mbed_official	52:a51c77007319	1151	uint16_t tmpsmcr = 0;
mbed_official	52:a51c77007319	1152	/* Check the parameters */
mbed_official	52:a51c77007319	1153	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1154	assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
mbed_official	52:a51c77007319	1155	assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
mbed_official	52:a51c77007319	1156	assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
mbed_official	52:a51c77007319	1157	tmpsmcr = TIMx->SMCR;
mbed_official	52:a51c77007319	1158	/* Reset the ETR Bits */
mbed_official	52:a51c77007319	1159	tmpsmcr &= SMCR_ETR_Mask;
mbed_official	52:a51c77007319	1160	/* Set the Prescaler, the Filter value and the Polarity */
mbed_official	52:a51c77007319	1161	tmpsmcr \|= (uint16_t)(TIM_ExtTRGPrescaler \| (uint16_t)(TIM_ExtTRGPolarity \| (uint16_t)(ExtTRGFilter << (uint16_t)8)));
mbed_official	52:a51c77007319	1162	/* Write to TIMx SMCR */
mbed_official	52:a51c77007319	1163	TIMx->SMCR = tmpsmcr;
mbed_official	52:a51c77007319	1164	}
mbed_official	52:a51c77007319	1165
mbed_official	52:a51c77007319	1166	/**
mbed_official	52:a51c77007319	1167	* @brief Configures the TIMx Prescaler.
mbed_official	52:a51c77007319	1168	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	1169	* @param Prescaler: specifies the Prescaler Register value
mbed_official	52:a51c77007319	1170	* @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
mbed_official	52:a51c77007319	1171	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1172	* @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
mbed_official	52:a51c77007319	1173	* @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
mbed_official	52:a51c77007319	1174	* @retval None
mbed_official	52:a51c77007319	1175	*/
mbed_official	52:a51c77007319	1176	void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
mbed_official	52:a51c77007319	1177	{
mbed_official	52:a51c77007319	1178	/* Check the parameters */
mbed_official	52:a51c77007319	1179	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	1180	assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
mbed_official	52:a51c77007319	1181	/* Set the Prescaler value */
mbed_official	52:a51c77007319	1182	TIMx->PSC = Prescaler;
mbed_official	52:a51c77007319	1183	/* Set or reset the UG Bit */
mbed_official	52:a51c77007319	1184	TIMx->EGR = TIM_PSCReloadMode;
mbed_official	52:a51c77007319	1185	}
mbed_official	52:a51c77007319	1186
mbed_official	52:a51c77007319	1187	/**
mbed_official	52:a51c77007319	1188	* @brief Specifies the TIMx Counter Mode to be used.
mbed_official	52:a51c77007319	1189	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1190	* @param TIM_CounterMode: specifies the Counter Mode to be used
mbed_official	52:a51c77007319	1191	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1192	* @arg TIM_CounterMode_Up: TIM Up Counting Mode
mbed_official	52:a51c77007319	1193	* @arg TIM_CounterMode_Down: TIM Down Counting Mode
mbed_official	52:a51c77007319	1194	* @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
mbed_official	52:a51c77007319	1195	* @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
mbed_official	52:a51c77007319	1196	* @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
mbed_official	52:a51c77007319	1197	* @retval None
mbed_official	52:a51c77007319	1198	*/
mbed_official	52:a51c77007319	1199	void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
mbed_official	52:a51c77007319	1200	{
mbed_official	52:a51c77007319	1201	uint16_t tmpcr1 = 0;
mbed_official	52:a51c77007319	1202	/* Check the parameters */
mbed_official	52:a51c77007319	1203	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1204	assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
mbed_official	52:a51c77007319	1205	tmpcr1 = TIMx->CR1;
mbed_official	52:a51c77007319	1206	/* Reset the CMS and DIR Bits */
mbed_official	52:a51c77007319	1207	tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR \| TIM_CR1_CMS)));
mbed_official	52:a51c77007319	1208	/* Set the Counter Mode */
mbed_official	52:a51c77007319	1209	tmpcr1 \|= TIM_CounterMode;
mbed_official	52:a51c77007319	1210	/* Write to TIMx CR1 register */
mbed_official	52:a51c77007319	1211	TIMx->CR1 = tmpcr1;
mbed_official	52:a51c77007319	1212	}
mbed_official	52:a51c77007319	1213
mbed_official	52:a51c77007319	1214	/**
mbed_official	52:a51c77007319	1215	* @brief Selects the Input Trigger source
mbed_official	52:a51c77007319	1216	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	1217	* @param TIM_InputTriggerSource: The Input Trigger source.
mbed_official	52:a51c77007319	1218	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1219	* @arg TIM_TS_ITR0: Internal Trigger 0
mbed_official	52:a51c77007319	1220	* @arg TIM_TS_ITR1: Internal Trigger 1
mbed_official	52:a51c77007319	1221	* @arg TIM_TS_ITR2: Internal Trigger 2
mbed_official	52:a51c77007319	1222	* @arg TIM_TS_ITR3: Internal Trigger 3
mbed_official	52:a51c77007319	1223	* @arg TIM_TS_TI1F_ED: TI1 Edge Detector
mbed_official	52:a51c77007319	1224	* @arg TIM_TS_TI1FP1: Filtered Timer Input 1
mbed_official	52:a51c77007319	1225	* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
mbed_official	52:a51c77007319	1226	* @arg TIM_TS_ETRF: External Trigger input
mbed_official	52:a51c77007319	1227	* @retval None
mbed_official	52:a51c77007319	1228	*/
mbed_official	52:a51c77007319	1229	void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
mbed_official	52:a51c77007319	1230	{
mbed_official	52:a51c77007319	1231	uint16_t tmpsmcr = 0;
mbed_official	52:a51c77007319	1232	/* Check the parameters */
mbed_official	52:a51c77007319	1233	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	1234	assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
mbed_official	52:a51c77007319	1235	/* Get the TIMx SMCR register value */
mbed_official	52:a51c77007319	1236	tmpsmcr = TIMx->SMCR;
mbed_official	52:a51c77007319	1237	/* Reset the TS Bits */
mbed_official	52:a51c77007319	1238	tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
mbed_official	52:a51c77007319	1239	/* Set the Input Trigger source */
mbed_official	52:a51c77007319	1240	tmpsmcr \|= TIM_InputTriggerSource;
mbed_official	52:a51c77007319	1241	/* Write to TIMx SMCR */
mbed_official	52:a51c77007319	1242	TIMx->SMCR = tmpsmcr;
mbed_official	52:a51c77007319	1243	}
mbed_official	52:a51c77007319	1244
mbed_official	52:a51c77007319	1245	/**
mbed_official	52:a51c77007319	1246	* @brief Configures the TIMx Encoder Interface.
mbed_official	52:a51c77007319	1247	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1248	* @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
mbed_official	52:a51c77007319	1249	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1250	* @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
mbed_official	52:a51c77007319	1251	* @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
mbed_official	52:a51c77007319	1252	* @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
mbed_official	52:a51c77007319	1253	* on the level of the other input.
mbed_official	52:a51c77007319	1254	* @param TIM_IC1Polarity: specifies the IC1 Polarity
mbed_official	52:a51c77007319	1255	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1256	* @arg TIM_ICPolarity_Falling: IC Falling edge.
mbed_official	52:a51c77007319	1257	* @arg TIM_ICPolarity_Rising: IC Rising edge.
mbed_official	52:a51c77007319	1258	* @param TIM_IC2Polarity: specifies the IC2 Polarity
mbed_official	52:a51c77007319	1259	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1260	* @arg TIM_ICPolarity_Falling: IC Falling edge.
mbed_official	52:a51c77007319	1261	* @arg TIM_ICPolarity_Rising: IC Rising edge.
mbed_official	52:a51c77007319	1262	* @retval None
mbed_official	52:a51c77007319	1263	*/
mbed_official	52:a51c77007319	1264	void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
mbed_official	52:a51c77007319	1265	uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
mbed_official	52:a51c77007319	1266	{
mbed_official	52:a51c77007319	1267	uint16_t tmpsmcr = 0;
mbed_official	52:a51c77007319	1268	uint16_t tmpccmr1 = 0;
mbed_official	52:a51c77007319	1269	uint16_t tmpccer = 0;
mbed_official	52:a51c77007319	1270
mbed_official	52:a51c77007319	1271	/* Check the parameters */
mbed_official	52:a51c77007319	1272	assert_param(IS_TIM_LIST5_PERIPH(TIMx));
mbed_official	52:a51c77007319	1273	assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
mbed_official	52:a51c77007319	1274	assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
mbed_official	52:a51c77007319	1275	assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
mbed_official	52:a51c77007319	1276
mbed_official	52:a51c77007319	1277	/* Get the TIMx SMCR register value */
mbed_official	52:a51c77007319	1278	tmpsmcr = TIMx->SMCR;
mbed_official	52:a51c77007319	1279
mbed_official	52:a51c77007319	1280	/* Get the TIMx CCMR1 register value */
mbed_official	52:a51c77007319	1281	tmpccmr1 = TIMx->CCMR1;
mbed_official	52:a51c77007319	1282
mbed_official	52:a51c77007319	1283	/* Get the TIMx CCER register value */
mbed_official	52:a51c77007319	1284	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	1285
mbed_official	52:a51c77007319	1286	/* Set the encoder Mode */
mbed_official	52:a51c77007319	1287	tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
mbed_official	52:a51c77007319	1288	tmpsmcr \|= TIM_EncoderMode;
mbed_official	52:a51c77007319	1289
mbed_official	52:a51c77007319	1290	/* Select the Capture Compare 1 and the Capture Compare 2 as input */
mbed_official	52:a51c77007319	1291	tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
mbed_official	52:a51c77007319	1292	tmpccmr1 \|= TIM_CCMR1_CC1S_0 \| TIM_CCMR1_CC2S_0;
mbed_official	52:a51c77007319	1293
mbed_official	52:a51c77007319	1294	/* Set the TI1 and the TI2 Polarities */
mbed_official	52:a51c77007319	1295	tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
mbed_official	52:a51c77007319	1296	tmpccer \|= (uint16_t)(TIM_IC1Polarity \| (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
mbed_official	52:a51c77007319	1297
mbed_official	52:a51c77007319	1298	/* Write to TIMx SMCR */
mbed_official	52:a51c77007319	1299	TIMx->SMCR = tmpsmcr;
mbed_official	52:a51c77007319	1300	/* Write to TIMx CCMR1 */
mbed_official	52:a51c77007319	1301	TIMx->CCMR1 = tmpccmr1;
mbed_official	52:a51c77007319	1302	/* Write to TIMx CCER */
mbed_official	52:a51c77007319	1303	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	1304	}
mbed_official	52:a51c77007319	1305
mbed_official	52:a51c77007319	1306	/**
mbed_official	52:a51c77007319	1307	* @brief Forces the TIMx output 1 waveform to active or inactive level.
mbed_official	52:a51c77007319	1308	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
mbed_official	52:a51c77007319	1309	* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
mbed_official	52:a51c77007319	1310	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1311	* @arg TIM_ForcedAction_Active: Force active level on OC1REF
mbed_official	52:a51c77007319	1312	* @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
mbed_official	52:a51c77007319	1313	* @retval None
mbed_official	52:a51c77007319	1314	*/
mbed_official	52:a51c77007319	1315	void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
mbed_official	52:a51c77007319	1316	{
mbed_official	52:a51c77007319	1317	uint16_t tmpccmr1 = 0;
mbed_official	52:a51c77007319	1318	/* Check the parameters */
mbed_official	52:a51c77007319	1319	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
mbed_official	52:a51c77007319	1320	assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
mbed_official	52:a51c77007319	1321	tmpccmr1 = TIMx->CCMR1;
mbed_official	52:a51c77007319	1322	/* Reset the OC1M Bits */
mbed_official	52:a51c77007319	1323	tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
mbed_official	52:a51c77007319	1324	/* Configure The Forced output Mode */
mbed_official	52:a51c77007319	1325	tmpccmr1 \|= TIM_ForcedAction;
mbed_official	52:a51c77007319	1326	/* Write to TIMx CCMR1 register */
mbed_official	52:a51c77007319	1327	TIMx->CCMR1 = tmpccmr1;
mbed_official	52:a51c77007319	1328	}
mbed_official	52:a51c77007319	1329
mbed_official	52:a51c77007319	1330	/**
mbed_official	52:a51c77007319	1331	* @brief Forces the TIMx output 2 waveform to active or inactive level.
mbed_official	52:a51c77007319	1332	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	1333	* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
mbed_official	52:a51c77007319	1334	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1335	* @arg TIM_ForcedAction_Active: Force active level on OC2REF
mbed_official	52:a51c77007319	1336	* @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
mbed_official	52:a51c77007319	1337	* @retval None
mbed_official	52:a51c77007319	1338	*/
mbed_official	52:a51c77007319	1339	void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
mbed_official	52:a51c77007319	1340	{
mbed_official	52:a51c77007319	1341	uint16_t tmpccmr1 = 0;
mbed_official	52:a51c77007319	1342	/* Check the parameters */
mbed_official	52:a51c77007319	1343	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	1344	assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
mbed_official	52:a51c77007319	1345	tmpccmr1 = TIMx->CCMR1;
mbed_official	52:a51c77007319	1346	/* Reset the OC2M Bits */
mbed_official	52:a51c77007319	1347	tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
mbed_official	52:a51c77007319	1348	/* Configure The Forced output Mode */
mbed_official	52:a51c77007319	1349	tmpccmr1 \|= (uint16_t)(TIM_ForcedAction << 8);
mbed_official	52:a51c77007319	1350	/* Write to TIMx CCMR1 register */
mbed_official	52:a51c77007319	1351	TIMx->CCMR1 = tmpccmr1;
mbed_official	52:a51c77007319	1352	}
mbed_official	52:a51c77007319	1353
mbed_official	52:a51c77007319	1354	/**
mbed_official	52:a51c77007319	1355	* @brief Forces the TIMx output 3 waveform to active or inactive level.
mbed_official	52:a51c77007319	1356	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1357	* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
mbed_official	52:a51c77007319	1358	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1359	* @arg TIM_ForcedAction_Active: Force active level on OC3REF
mbed_official	52:a51c77007319	1360	* @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
mbed_official	52:a51c77007319	1361	* @retval None
mbed_official	52:a51c77007319	1362	*/
mbed_official	52:a51c77007319	1363	void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
mbed_official	52:a51c77007319	1364	{
mbed_official	52:a51c77007319	1365	uint16_t tmpccmr2 = 0;
mbed_official	52:a51c77007319	1366	/* Check the parameters */
mbed_official	52:a51c77007319	1367	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1368	assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
mbed_official	52:a51c77007319	1369	tmpccmr2 = TIMx->CCMR2;
mbed_official	52:a51c77007319	1370	/* Reset the OC1M Bits */
mbed_official	52:a51c77007319	1371	tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
mbed_official	52:a51c77007319	1372	/* Configure The Forced output Mode */
mbed_official	52:a51c77007319	1373	tmpccmr2 \|= TIM_ForcedAction;
mbed_official	52:a51c77007319	1374	/* Write to TIMx CCMR2 register */
mbed_official	52:a51c77007319	1375	TIMx->CCMR2 = tmpccmr2;
mbed_official	52:a51c77007319	1376	}
mbed_official	52:a51c77007319	1377
mbed_official	52:a51c77007319	1378	/**
mbed_official	52:a51c77007319	1379	* @brief Forces the TIMx output 4 waveform to active or inactive level.
mbed_official	52:a51c77007319	1380	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1381	* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
mbed_official	52:a51c77007319	1382	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1383	* @arg TIM_ForcedAction_Active: Force active level on OC4REF
mbed_official	52:a51c77007319	1384	* @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
mbed_official	52:a51c77007319	1385	* @retval None
mbed_official	52:a51c77007319	1386	*/
mbed_official	52:a51c77007319	1387	void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
mbed_official	52:a51c77007319	1388	{
mbed_official	52:a51c77007319	1389	uint16_t tmpccmr2 = 0;
mbed_official	52:a51c77007319	1390	/* Check the parameters */
mbed_official	52:a51c77007319	1391	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1392	assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
mbed_official	52:a51c77007319	1393	tmpccmr2 = TIMx->CCMR2;
mbed_official	52:a51c77007319	1394	/* Reset the OC2M Bits */
mbed_official	52:a51c77007319	1395	tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
mbed_official	52:a51c77007319	1396	/* Configure The Forced output Mode */
mbed_official	52:a51c77007319	1397	tmpccmr2 \|= (uint16_t)(TIM_ForcedAction << 8);
mbed_official	52:a51c77007319	1398	/* Write to TIMx CCMR2 register */
mbed_official	52:a51c77007319	1399	TIMx->CCMR2 = tmpccmr2;
mbed_official	52:a51c77007319	1400	}
mbed_official	52:a51c77007319	1401
mbed_official	52:a51c77007319	1402	/**
mbed_official	52:a51c77007319	1403	* @brief Enables or disables TIMx peripheral Preload register on ARR.
mbed_official	52:a51c77007319	1404	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	1405	* @param NewState: new state of the TIMx peripheral Preload register
mbed_official	52:a51c77007319	1406	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	1407	* @retval None
mbed_official	52:a51c77007319	1408	*/
mbed_official	52:a51c77007319	1409	void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
mbed_official	52:a51c77007319	1410	{
mbed_official	52:a51c77007319	1411	/* Check the parameters */
mbed_official	52:a51c77007319	1412	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	1413	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	1414	if (NewState != DISABLE)
mbed_official	52:a51c77007319	1415	{
mbed_official	52:a51c77007319	1416	/* Set the ARR Preload Bit */
mbed_official	52:a51c77007319	1417	TIMx->CR1 \|= TIM_CR1_ARPE;
mbed_official	52:a51c77007319	1418	}
mbed_official	52:a51c77007319	1419	else
mbed_official	52:a51c77007319	1420	{
mbed_official	52:a51c77007319	1421	/* Reset the ARR Preload Bit */
mbed_official	52:a51c77007319	1422	TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
mbed_official	52:a51c77007319	1423	}
mbed_official	52:a51c77007319	1424	}
mbed_official	52:a51c77007319	1425
mbed_official	52:a51c77007319	1426	/**
mbed_official	52:a51c77007319	1427	* @brief Selects the TIM peripheral Commutation event.
mbed_official	52:a51c77007319	1428	* @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral
mbed_official	52:a51c77007319	1429	* @param NewState: new state of the Commutation event.
mbed_official	52:a51c77007319	1430	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	1431	* @retval None
mbed_official	52:a51c77007319	1432	*/
mbed_official	52:a51c77007319	1433	void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
mbed_official	52:a51c77007319	1434	{
mbed_official	52:a51c77007319	1435	/* Check the parameters */
mbed_official	52:a51c77007319	1436	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
mbed_official	52:a51c77007319	1437	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	1438	if (NewState != DISABLE)
mbed_official	52:a51c77007319	1439	{
mbed_official	52:a51c77007319	1440	/* Set the COM Bit */
mbed_official	52:a51c77007319	1441	TIMx->CR2 \|= TIM_CR2_CCUS;
mbed_official	52:a51c77007319	1442	}
mbed_official	52:a51c77007319	1443	else
mbed_official	52:a51c77007319	1444	{
mbed_official	52:a51c77007319	1445	/* Reset the COM Bit */
mbed_official	52:a51c77007319	1446	TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);
mbed_official	52:a51c77007319	1447	}
mbed_official	52:a51c77007319	1448	}
mbed_official	52:a51c77007319	1449
mbed_official	52:a51c77007319	1450	/**
mbed_official	52:a51c77007319	1451	* @brief Selects the TIMx peripheral Capture Compare DMA source.
mbed_official	52:a51c77007319	1452	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select
mbed_official	52:a51c77007319	1453	* the TIM peripheral.
mbed_official	52:a51c77007319	1454	* @param NewState: new state of the Capture Compare DMA source
mbed_official	52:a51c77007319	1455	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	1456	* @retval None
mbed_official	52:a51c77007319	1457	*/
mbed_official	52:a51c77007319	1458	void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
mbed_official	52:a51c77007319	1459	{
mbed_official	52:a51c77007319	1460	/* Check the parameters */
mbed_official	52:a51c77007319	1461	assert_param(IS_TIM_LIST4_PERIPH(TIMx));
mbed_official	52:a51c77007319	1462	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	1463	if (NewState != DISABLE)
mbed_official	52:a51c77007319	1464	{
mbed_official	52:a51c77007319	1465	/* Set the CCDS Bit */
mbed_official	52:a51c77007319	1466	TIMx->CR2 \|= TIM_CR2_CCDS;
mbed_official	52:a51c77007319	1467	}
mbed_official	52:a51c77007319	1468	else
mbed_official	52:a51c77007319	1469	{
mbed_official	52:a51c77007319	1470	/* Reset the CCDS Bit */
mbed_official	52:a51c77007319	1471	TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
mbed_official	52:a51c77007319	1472	}
mbed_official	52:a51c77007319	1473	}
mbed_official	52:a51c77007319	1474
mbed_official	52:a51c77007319	1475	/**
mbed_official	52:a51c77007319	1476	* @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
mbed_official	52:a51c77007319	1477	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15
mbed_official	52:a51c77007319	1478	* to select the TIMx peripheral
mbed_official	52:a51c77007319	1479	* @param NewState: new state of the Capture Compare Preload Control bit
mbed_official	52:a51c77007319	1480	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	1481	* @retval None
mbed_official	52:a51c77007319	1482	*/
mbed_official	52:a51c77007319	1483	void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
mbed_official	52:a51c77007319	1484	{
mbed_official	52:a51c77007319	1485	/* Check the parameters */
mbed_official	52:a51c77007319	1486	assert_param(IS_TIM_LIST5_PERIPH(TIMx));
mbed_official	52:a51c77007319	1487	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	1488	if (NewState != DISABLE)
mbed_official	52:a51c77007319	1489	{
mbed_official	52:a51c77007319	1490	/* Set the CCPC Bit */
mbed_official	52:a51c77007319	1491	TIMx->CR2 \|= TIM_CR2_CCPC;
mbed_official	52:a51c77007319	1492	}
mbed_official	52:a51c77007319	1493	else
mbed_official	52:a51c77007319	1494	{
mbed_official	52:a51c77007319	1495	/* Reset the CCPC Bit */
mbed_official	52:a51c77007319	1496	TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);
mbed_official	52:a51c77007319	1497	}
mbed_official	52:a51c77007319	1498	}
mbed_official	52:a51c77007319	1499
mbed_official	52:a51c77007319	1500	/**
mbed_official	52:a51c77007319	1501	* @brief Enables or disables the TIMx peripheral Preload register on CCR1.
mbed_official	52:a51c77007319	1502	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
mbed_official	52:a51c77007319	1503	* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
mbed_official	52:a51c77007319	1504	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1505	* @arg TIM_OCPreload_Enable
mbed_official	52:a51c77007319	1506	* @arg TIM_OCPreload_Disable
mbed_official	52:a51c77007319	1507	* @retval None
mbed_official	52:a51c77007319	1508	*/
mbed_official	52:a51c77007319	1509	void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
mbed_official	52:a51c77007319	1510	{
mbed_official	52:a51c77007319	1511	uint16_t tmpccmr1 = 0;
mbed_official	52:a51c77007319	1512	/* Check the parameters */
mbed_official	52:a51c77007319	1513	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
mbed_official	52:a51c77007319	1514	assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
mbed_official	52:a51c77007319	1515	tmpccmr1 = TIMx->CCMR1;
mbed_official	52:a51c77007319	1516	/* Reset the OC1PE Bit */
mbed_official	52:a51c77007319	1517	tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
mbed_official	52:a51c77007319	1518	/* Enable or Disable the Output Compare Preload feature */
mbed_official	52:a51c77007319	1519	tmpccmr1 \|= TIM_OCPreload;
mbed_official	52:a51c77007319	1520	/* Write to TIMx CCMR1 register */
mbed_official	52:a51c77007319	1521	TIMx->CCMR1 = tmpccmr1;
mbed_official	52:a51c77007319	1522	}
mbed_official	52:a51c77007319	1523
mbed_official	52:a51c77007319	1524	/**
mbed_official	52:a51c77007319	1525	* @brief Enables or disables the TIMx peripheral Preload register on CCR2.
mbed_official	52:a51c77007319	1526	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
mbed_official	52:a51c77007319	1527	* the TIM peripheral.
mbed_official	52:a51c77007319	1528	* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
mbed_official	52:a51c77007319	1529	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1530	* @arg TIM_OCPreload_Enable
mbed_official	52:a51c77007319	1531	* @arg TIM_OCPreload_Disable
mbed_official	52:a51c77007319	1532	* @retval None
mbed_official	52:a51c77007319	1533	*/
mbed_official	52:a51c77007319	1534	void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
mbed_official	52:a51c77007319	1535	{
mbed_official	52:a51c77007319	1536	uint16_t tmpccmr1 = 0;
mbed_official	52:a51c77007319	1537	/* Check the parameters */
mbed_official	52:a51c77007319	1538	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	1539	assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
mbed_official	52:a51c77007319	1540	tmpccmr1 = TIMx->CCMR1;
mbed_official	52:a51c77007319	1541	/* Reset the OC2PE Bit */
mbed_official	52:a51c77007319	1542	tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
mbed_official	52:a51c77007319	1543	/* Enable or Disable the Output Compare Preload feature */
mbed_official	52:a51c77007319	1544	tmpccmr1 \|= (uint16_t)(TIM_OCPreload << 8);
mbed_official	52:a51c77007319	1545	/* Write to TIMx CCMR1 register */
mbed_official	52:a51c77007319	1546	TIMx->CCMR1 = tmpccmr1;
mbed_official	52:a51c77007319	1547	}
mbed_official	52:a51c77007319	1548
mbed_official	52:a51c77007319	1549	/**
mbed_official	52:a51c77007319	1550	* @brief Enables or disables the TIMx peripheral Preload register on CCR3.
mbed_official	52:a51c77007319	1551	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1552	* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
mbed_official	52:a51c77007319	1553	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1554	* @arg TIM_OCPreload_Enable
mbed_official	52:a51c77007319	1555	* @arg TIM_OCPreload_Disable
mbed_official	52:a51c77007319	1556	* @retval None
mbed_official	52:a51c77007319	1557	*/
mbed_official	52:a51c77007319	1558	void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
mbed_official	52:a51c77007319	1559	{
mbed_official	52:a51c77007319	1560	uint16_t tmpccmr2 = 0;
mbed_official	52:a51c77007319	1561	/* Check the parameters */
mbed_official	52:a51c77007319	1562	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1563	assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
mbed_official	52:a51c77007319	1564	tmpccmr2 = TIMx->CCMR2;
mbed_official	52:a51c77007319	1565	/* Reset the OC3PE Bit */
mbed_official	52:a51c77007319	1566	tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
mbed_official	52:a51c77007319	1567	/* Enable or Disable the Output Compare Preload feature */
mbed_official	52:a51c77007319	1568	tmpccmr2 \|= TIM_OCPreload;
mbed_official	52:a51c77007319	1569	/* Write to TIMx CCMR2 register */
mbed_official	52:a51c77007319	1570	TIMx->CCMR2 = tmpccmr2;
mbed_official	52:a51c77007319	1571	}
mbed_official	52:a51c77007319	1572
mbed_official	52:a51c77007319	1573	/**
mbed_official	52:a51c77007319	1574	* @brief Enables or disables the TIMx peripheral Preload register on CCR4.
mbed_official	52:a51c77007319	1575	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1576	* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
mbed_official	52:a51c77007319	1577	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1578	* @arg TIM_OCPreload_Enable
mbed_official	52:a51c77007319	1579	* @arg TIM_OCPreload_Disable
mbed_official	52:a51c77007319	1580	* @retval None
mbed_official	52:a51c77007319	1581	*/
mbed_official	52:a51c77007319	1582	void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
mbed_official	52:a51c77007319	1583	{
mbed_official	52:a51c77007319	1584	uint16_t tmpccmr2 = 0;
mbed_official	52:a51c77007319	1585	/* Check the parameters */
mbed_official	52:a51c77007319	1586	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1587	assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
mbed_official	52:a51c77007319	1588	tmpccmr2 = TIMx->CCMR2;
mbed_official	52:a51c77007319	1589	/* Reset the OC4PE Bit */
mbed_official	52:a51c77007319	1590	tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
mbed_official	52:a51c77007319	1591	/* Enable or Disable the Output Compare Preload feature */
mbed_official	52:a51c77007319	1592	tmpccmr2 \|= (uint16_t)(TIM_OCPreload << 8);
mbed_official	52:a51c77007319	1593	/* Write to TIMx CCMR2 register */
mbed_official	52:a51c77007319	1594	TIMx->CCMR2 = tmpccmr2;
mbed_official	52:a51c77007319	1595	}
mbed_official	52:a51c77007319	1596
mbed_official	52:a51c77007319	1597	/**
mbed_official	52:a51c77007319	1598	* @brief Configures the TIMx Output Compare 1 Fast feature.
mbed_official	52:a51c77007319	1599	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
mbed_official	52:a51c77007319	1600	* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
mbed_official	52:a51c77007319	1601	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1602	* @arg TIM_OCFast_Enable: TIM output compare fast enable
mbed_official	52:a51c77007319	1603	* @arg TIM_OCFast_Disable: TIM output compare fast disable
mbed_official	52:a51c77007319	1604	* @retval None
mbed_official	52:a51c77007319	1605	*/
mbed_official	52:a51c77007319	1606	void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
mbed_official	52:a51c77007319	1607	{
mbed_official	52:a51c77007319	1608	uint16_t tmpccmr1 = 0;
mbed_official	52:a51c77007319	1609	/* Check the parameters */
mbed_official	52:a51c77007319	1610	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
mbed_official	52:a51c77007319	1611	assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
mbed_official	52:a51c77007319	1612	/* Get the TIMx CCMR1 register value */
mbed_official	52:a51c77007319	1613	tmpccmr1 = TIMx->CCMR1;
mbed_official	52:a51c77007319	1614	/* Reset the OC1FE Bit */
mbed_official	52:a51c77007319	1615	tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
mbed_official	52:a51c77007319	1616	/* Enable or Disable the Output Compare Fast Bit */
mbed_official	52:a51c77007319	1617	tmpccmr1 \|= TIM_OCFast;
mbed_official	52:a51c77007319	1618	/* Write to TIMx CCMR1 */
mbed_official	52:a51c77007319	1619	TIMx->CCMR1 = tmpccmr1;
mbed_official	52:a51c77007319	1620	}
mbed_official	52:a51c77007319	1621
mbed_official	52:a51c77007319	1622	/**
mbed_official	52:a51c77007319	1623	* @brief Configures the TIMx Output Compare 2 Fast feature.
mbed_official	52:a51c77007319	1624	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
mbed_official	52:a51c77007319	1625	* the TIM peripheral.
mbed_official	52:a51c77007319	1626	* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
mbed_official	52:a51c77007319	1627	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1628	* @arg TIM_OCFast_Enable: TIM output compare fast enable
mbed_official	52:a51c77007319	1629	* @arg TIM_OCFast_Disable: TIM output compare fast disable
mbed_official	52:a51c77007319	1630	* @retval None
mbed_official	52:a51c77007319	1631	*/
mbed_official	52:a51c77007319	1632	void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
mbed_official	52:a51c77007319	1633	{
mbed_official	52:a51c77007319	1634	uint16_t tmpccmr1 = 0;
mbed_official	52:a51c77007319	1635	/* Check the parameters */
mbed_official	52:a51c77007319	1636	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	1637	assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
mbed_official	52:a51c77007319	1638	/* Get the TIMx CCMR1 register value */
mbed_official	52:a51c77007319	1639	tmpccmr1 = TIMx->CCMR1;
mbed_official	52:a51c77007319	1640	/* Reset the OC2FE Bit */
mbed_official	52:a51c77007319	1641	tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
mbed_official	52:a51c77007319	1642	/* Enable or Disable the Output Compare Fast Bit */
mbed_official	52:a51c77007319	1643	tmpccmr1 \|= (uint16_t)(TIM_OCFast << 8);
mbed_official	52:a51c77007319	1644	/* Write to TIMx CCMR1 */
mbed_official	52:a51c77007319	1645	TIMx->CCMR1 = tmpccmr1;
mbed_official	52:a51c77007319	1646	}
mbed_official	52:a51c77007319	1647
mbed_official	52:a51c77007319	1648	/**
mbed_official	52:a51c77007319	1649	* @brief Configures the TIMx Output Compare 3 Fast feature.
mbed_official	52:a51c77007319	1650	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1651	* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
mbed_official	52:a51c77007319	1652	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1653	* @arg TIM_OCFast_Enable: TIM output compare fast enable
mbed_official	52:a51c77007319	1654	* @arg TIM_OCFast_Disable: TIM output compare fast disable
mbed_official	52:a51c77007319	1655	* @retval None
mbed_official	52:a51c77007319	1656	*/
mbed_official	52:a51c77007319	1657	void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
mbed_official	52:a51c77007319	1658	{
mbed_official	52:a51c77007319	1659	uint16_t tmpccmr2 = 0;
mbed_official	52:a51c77007319	1660	/* Check the parameters */
mbed_official	52:a51c77007319	1661	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1662	assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
mbed_official	52:a51c77007319	1663	/* Get the TIMx CCMR2 register value */
mbed_official	52:a51c77007319	1664	tmpccmr2 = TIMx->CCMR2;
mbed_official	52:a51c77007319	1665	/* Reset the OC3FE Bit */
mbed_official	52:a51c77007319	1666	tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
mbed_official	52:a51c77007319	1667	/* Enable or Disable the Output Compare Fast Bit */
mbed_official	52:a51c77007319	1668	tmpccmr2 \|= TIM_OCFast;
mbed_official	52:a51c77007319	1669	/* Write to TIMx CCMR2 */
mbed_official	52:a51c77007319	1670	TIMx->CCMR2 = tmpccmr2;
mbed_official	52:a51c77007319	1671	}
mbed_official	52:a51c77007319	1672
mbed_official	52:a51c77007319	1673	/**
mbed_official	52:a51c77007319	1674	* @brief Configures the TIMx Output Compare 4 Fast feature.
mbed_official	52:a51c77007319	1675	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1676	* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
mbed_official	52:a51c77007319	1677	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1678	* @arg TIM_OCFast_Enable: TIM output compare fast enable
mbed_official	52:a51c77007319	1679	* @arg TIM_OCFast_Disable: TIM output compare fast disable
mbed_official	52:a51c77007319	1680	* @retval None
mbed_official	52:a51c77007319	1681	*/
mbed_official	52:a51c77007319	1682	void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
mbed_official	52:a51c77007319	1683	{
mbed_official	52:a51c77007319	1684	uint16_t tmpccmr2 = 0;
mbed_official	52:a51c77007319	1685	/* Check the parameters */
mbed_official	52:a51c77007319	1686	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1687	assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
mbed_official	52:a51c77007319	1688	/* Get the TIMx CCMR2 register value */
mbed_official	52:a51c77007319	1689	tmpccmr2 = TIMx->CCMR2;
mbed_official	52:a51c77007319	1690	/* Reset the OC4FE Bit */
mbed_official	52:a51c77007319	1691	tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
mbed_official	52:a51c77007319	1692	/* Enable or Disable the Output Compare Fast Bit */
mbed_official	52:a51c77007319	1693	tmpccmr2 \|= (uint16_t)(TIM_OCFast << 8);
mbed_official	52:a51c77007319	1694	/* Write to TIMx CCMR2 */
mbed_official	52:a51c77007319	1695	TIMx->CCMR2 = tmpccmr2;
mbed_official	52:a51c77007319	1696	}
mbed_official	52:a51c77007319	1697
mbed_official	52:a51c77007319	1698	/**
mbed_official	52:a51c77007319	1699	* @brief Clears or safeguards the OCREF1 signal on an external event
mbed_official	52:a51c77007319	1700	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1701	* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
mbed_official	52:a51c77007319	1702	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1703	* @arg TIM_OCClear_Enable: TIM Output clear enable
mbed_official	52:a51c77007319	1704	* @arg TIM_OCClear_Disable: TIM Output clear disable
mbed_official	52:a51c77007319	1705	* @retval None
mbed_official	52:a51c77007319	1706	*/
mbed_official	52:a51c77007319	1707	void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
mbed_official	52:a51c77007319	1708	{
mbed_official	52:a51c77007319	1709	uint16_t tmpccmr1 = 0;
mbed_official	52:a51c77007319	1710	/* Check the parameters */
mbed_official	52:a51c77007319	1711	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1712	assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
mbed_official	52:a51c77007319	1713
mbed_official	52:a51c77007319	1714	tmpccmr1 = TIMx->CCMR1;
mbed_official	52:a51c77007319	1715
mbed_official	52:a51c77007319	1716	/* Reset the OC1CE Bit */
mbed_official	52:a51c77007319	1717	tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
mbed_official	52:a51c77007319	1718	/* Enable or Disable the Output Compare Clear Bit */
mbed_official	52:a51c77007319	1719	tmpccmr1 \|= TIM_OCClear;
mbed_official	52:a51c77007319	1720	/* Write to TIMx CCMR1 register */
mbed_official	52:a51c77007319	1721	TIMx->CCMR1 = tmpccmr1;
mbed_official	52:a51c77007319	1722	}
mbed_official	52:a51c77007319	1723
mbed_official	52:a51c77007319	1724	/**
mbed_official	52:a51c77007319	1725	* @brief Clears or safeguards the OCREF2 signal on an external event
mbed_official	52:a51c77007319	1726	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1727	* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
mbed_official	52:a51c77007319	1728	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1729	* @arg TIM_OCClear_Enable: TIM Output clear enable
mbed_official	52:a51c77007319	1730	* @arg TIM_OCClear_Disable: TIM Output clear disable
mbed_official	52:a51c77007319	1731	* @retval None
mbed_official	52:a51c77007319	1732	*/
mbed_official	52:a51c77007319	1733	void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
mbed_official	52:a51c77007319	1734	{
mbed_official	52:a51c77007319	1735	uint16_t tmpccmr1 = 0;
mbed_official	52:a51c77007319	1736	/* Check the parameters */
mbed_official	52:a51c77007319	1737	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1738	assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
mbed_official	52:a51c77007319	1739	tmpccmr1 = TIMx->CCMR1;
mbed_official	52:a51c77007319	1740	/* Reset the OC2CE Bit */
mbed_official	52:a51c77007319	1741	tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
mbed_official	52:a51c77007319	1742	/* Enable or Disable the Output Compare Clear Bit */
mbed_official	52:a51c77007319	1743	tmpccmr1 \|= (uint16_t)(TIM_OCClear << 8);
mbed_official	52:a51c77007319	1744	/* Write to TIMx CCMR1 register */
mbed_official	52:a51c77007319	1745	TIMx->CCMR1 = tmpccmr1;
mbed_official	52:a51c77007319	1746	}
mbed_official	52:a51c77007319	1747
mbed_official	52:a51c77007319	1748	/**
mbed_official	52:a51c77007319	1749	* @brief Clears or safeguards the OCREF3 signal on an external event
mbed_official	52:a51c77007319	1750	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1751	* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
mbed_official	52:a51c77007319	1752	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1753	* @arg TIM_OCClear_Enable: TIM Output clear enable
mbed_official	52:a51c77007319	1754	* @arg TIM_OCClear_Disable: TIM Output clear disable
mbed_official	52:a51c77007319	1755	* @retval None
mbed_official	52:a51c77007319	1756	*/
mbed_official	52:a51c77007319	1757	void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
mbed_official	52:a51c77007319	1758	{
mbed_official	52:a51c77007319	1759	uint16_t tmpccmr2 = 0;
mbed_official	52:a51c77007319	1760	/* Check the parameters */
mbed_official	52:a51c77007319	1761	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1762	assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
mbed_official	52:a51c77007319	1763	tmpccmr2 = TIMx->CCMR2;
mbed_official	52:a51c77007319	1764	/* Reset the OC3CE Bit */
mbed_official	52:a51c77007319	1765	tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
mbed_official	52:a51c77007319	1766	/* Enable or Disable the Output Compare Clear Bit */
mbed_official	52:a51c77007319	1767	tmpccmr2 \|= TIM_OCClear;
mbed_official	52:a51c77007319	1768	/* Write to TIMx CCMR2 register */
mbed_official	52:a51c77007319	1769	TIMx->CCMR2 = tmpccmr2;
mbed_official	52:a51c77007319	1770	}
mbed_official	52:a51c77007319	1771
mbed_official	52:a51c77007319	1772	/**
mbed_official	52:a51c77007319	1773	* @brief Clears or safeguards the OCREF4 signal on an external event
mbed_official	52:a51c77007319	1774	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1775	* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
mbed_official	52:a51c77007319	1776	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1777	* @arg TIM_OCClear_Enable: TIM Output clear enable
mbed_official	52:a51c77007319	1778	* @arg TIM_OCClear_Disable: TIM Output clear disable
mbed_official	52:a51c77007319	1779	* @retval None
mbed_official	52:a51c77007319	1780	*/
mbed_official	52:a51c77007319	1781	void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
mbed_official	52:a51c77007319	1782	{
mbed_official	52:a51c77007319	1783	uint16_t tmpccmr2 = 0;
mbed_official	52:a51c77007319	1784	/* Check the parameters */
mbed_official	52:a51c77007319	1785	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1786	assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
mbed_official	52:a51c77007319	1787	tmpccmr2 = TIMx->CCMR2;
mbed_official	52:a51c77007319	1788	/* Reset the OC4CE Bit */
mbed_official	52:a51c77007319	1789	tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
mbed_official	52:a51c77007319	1790	/* Enable or Disable the Output Compare Clear Bit */
mbed_official	52:a51c77007319	1791	tmpccmr2 \|= (uint16_t)(TIM_OCClear << 8);
mbed_official	52:a51c77007319	1792	/* Write to TIMx CCMR2 register */
mbed_official	52:a51c77007319	1793	TIMx->CCMR2 = tmpccmr2;
mbed_official	52:a51c77007319	1794	}
mbed_official	52:a51c77007319	1795
mbed_official	52:a51c77007319	1796	/**
mbed_official	52:a51c77007319	1797	* @brief Configures the TIMx channel 1 polarity.
mbed_official	52:a51c77007319	1798	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
mbed_official	52:a51c77007319	1799	* @param TIM_OCPolarity: specifies the OC1 Polarity
mbed_official	52:a51c77007319	1800	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1801	* @arg TIM_OCPolarity_High: Output Compare active high
mbed_official	52:a51c77007319	1802	* @arg TIM_OCPolarity_Low: Output Compare active low
mbed_official	52:a51c77007319	1803	* @retval None
mbed_official	52:a51c77007319	1804	*/
mbed_official	52:a51c77007319	1805	void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
mbed_official	52:a51c77007319	1806	{
mbed_official	52:a51c77007319	1807	uint16_t tmpccer = 0;
mbed_official	52:a51c77007319	1808	/* Check the parameters */
mbed_official	52:a51c77007319	1809	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
mbed_official	52:a51c77007319	1810	assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
mbed_official	52:a51c77007319	1811	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	1812	/* Set or Reset the CC1P Bit */
mbed_official	52:a51c77007319	1813	tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
mbed_official	52:a51c77007319	1814	tmpccer \|= TIM_OCPolarity;
mbed_official	52:a51c77007319	1815	/* Write to TIMx CCER register */
mbed_official	52:a51c77007319	1816	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	1817	}
mbed_official	52:a51c77007319	1818
mbed_official	52:a51c77007319	1819	/**
mbed_official	52:a51c77007319	1820	* @brief Configures the TIMx Channel 1N polarity.
mbed_official	52:a51c77007319	1821	* @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	1822	* @param TIM_OCNPolarity: specifies the OC1N Polarity
mbed_official	52:a51c77007319	1823	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1824	* @arg TIM_OCNPolarity_High: Output Compare active high
mbed_official	52:a51c77007319	1825	* @arg TIM_OCNPolarity_Low: Output Compare active low
mbed_official	52:a51c77007319	1826	* @retval None
mbed_official	52:a51c77007319	1827	*/
mbed_official	52:a51c77007319	1828	void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
mbed_official	52:a51c77007319	1829	{
mbed_official	52:a51c77007319	1830	uint16_t tmpccer = 0;
mbed_official	52:a51c77007319	1831	/* Check the parameters */
mbed_official	52:a51c77007319	1832	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
mbed_official	52:a51c77007319	1833	assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
mbed_official	52:a51c77007319	1834
mbed_official	52:a51c77007319	1835	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	1836	/* Set or Reset the CC1NP Bit */
mbed_official	52:a51c77007319	1837	tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);
mbed_official	52:a51c77007319	1838	tmpccer \|= TIM_OCNPolarity;
mbed_official	52:a51c77007319	1839	/* Write to TIMx CCER register */
mbed_official	52:a51c77007319	1840	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	1841	}
mbed_official	52:a51c77007319	1842
mbed_official	52:a51c77007319	1843	/**
mbed_official	52:a51c77007319	1844	* @brief Configures the TIMx channel 2 polarity.
mbed_official	52:a51c77007319	1845	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	1846	* @param TIM_OCPolarity: specifies the OC2 Polarity
mbed_official	52:a51c77007319	1847	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1848	* @arg TIM_OCPolarity_High: Output Compare active high
mbed_official	52:a51c77007319	1849	* @arg TIM_OCPolarity_Low: Output Compare active low
mbed_official	52:a51c77007319	1850	* @retval None
mbed_official	52:a51c77007319	1851	*/
mbed_official	52:a51c77007319	1852	void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
mbed_official	52:a51c77007319	1853	{
mbed_official	52:a51c77007319	1854	uint16_t tmpccer = 0;
mbed_official	52:a51c77007319	1855	/* Check the parameters */
mbed_official	52:a51c77007319	1856	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	1857	assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
mbed_official	52:a51c77007319	1858	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	1859	/* Set or Reset the CC2P Bit */
mbed_official	52:a51c77007319	1860	tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
mbed_official	52:a51c77007319	1861	tmpccer \|= (uint16_t)(TIM_OCPolarity << 4);
mbed_official	52:a51c77007319	1862	/* Write to TIMx CCER register */
mbed_official	52:a51c77007319	1863	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	1864	}
mbed_official	52:a51c77007319	1865
mbed_official	52:a51c77007319	1866	/**
mbed_official	52:a51c77007319	1867	* @brief Configures the TIMx Channel 2N polarity.
mbed_official	52:a51c77007319	1868	* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1869	* @param TIM_OCNPolarity: specifies the OC2N Polarity
mbed_official	52:a51c77007319	1870	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1871	* @arg TIM_OCNPolarity_High: Output Compare active high
mbed_official	52:a51c77007319	1872	* @arg TIM_OCNPolarity_Low: Output Compare active low
mbed_official	52:a51c77007319	1873	* @retval None
mbed_official	52:a51c77007319	1874	*/
mbed_official	52:a51c77007319	1875	void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
mbed_official	52:a51c77007319	1876	{
mbed_official	52:a51c77007319	1877	uint16_t tmpccer = 0;
mbed_official	52:a51c77007319	1878	/* Check the parameters */
mbed_official	52:a51c77007319	1879	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
mbed_official	52:a51c77007319	1880	assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
mbed_official	52:a51c77007319	1881
mbed_official	52:a51c77007319	1882	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	1883	/* Set or Reset the CC2NP Bit */
mbed_official	52:a51c77007319	1884	tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);
mbed_official	52:a51c77007319	1885	tmpccer \|= (uint16_t)(TIM_OCNPolarity << 4);
mbed_official	52:a51c77007319	1886	/* Write to TIMx CCER register */
mbed_official	52:a51c77007319	1887	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	1888	}
mbed_official	52:a51c77007319	1889
mbed_official	52:a51c77007319	1890	/**
mbed_official	52:a51c77007319	1891	* @brief Configures the TIMx channel 3 polarity.
mbed_official	52:a51c77007319	1892	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1893	* @param TIM_OCPolarity: specifies the OC3 Polarity
mbed_official	52:a51c77007319	1894	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1895	* @arg TIM_OCPolarity_High: Output Compare active high
mbed_official	52:a51c77007319	1896	* @arg TIM_OCPolarity_Low: Output Compare active low
mbed_official	52:a51c77007319	1897	* @retval None
mbed_official	52:a51c77007319	1898	*/
mbed_official	52:a51c77007319	1899	void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
mbed_official	52:a51c77007319	1900	{
mbed_official	52:a51c77007319	1901	uint16_t tmpccer = 0;
mbed_official	52:a51c77007319	1902	/* Check the parameters */
mbed_official	52:a51c77007319	1903	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1904	assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
mbed_official	52:a51c77007319	1905	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	1906	/* Set or Reset the CC3P Bit */
mbed_official	52:a51c77007319	1907	tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
mbed_official	52:a51c77007319	1908	tmpccer \|= (uint16_t)(TIM_OCPolarity << 8);
mbed_official	52:a51c77007319	1909	/* Write to TIMx CCER register */
mbed_official	52:a51c77007319	1910	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	1911	}
mbed_official	52:a51c77007319	1912
mbed_official	52:a51c77007319	1913	/**
mbed_official	52:a51c77007319	1914	* @brief Configures the TIMx Channel 3N polarity.
mbed_official	52:a51c77007319	1915	* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1916	* @param TIM_OCNPolarity: specifies the OC3N Polarity
mbed_official	52:a51c77007319	1917	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1918	* @arg TIM_OCNPolarity_High: Output Compare active high
mbed_official	52:a51c77007319	1919	* @arg TIM_OCNPolarity_Low: Output Compare active low
mbed_official	52:a51c77007319	1920	* @retval None
mbed_official	52:a51c77007319	1921	*/
mbed_official	52:a51c77007319	1922	void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
mbed_official	52:a51c77007319	1923	{
mbed_official	52:a51c77007319	1924	uint16_t tmpccer = 0;
mbed_official	52:a51c77007319	1925
mbed_official	52:a51c77007319	1926	/* Check the parameters */
mbed_official	52:a51c77007319	1927	assert_param(IS_TIM_LIST1_PERIPH(TIMx));
mbed_official	52:a51c77007319	1928	assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
mbed_official	52:a51c77007319	1929
mbed_official	52:a51c77007319	1930	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	1931	/* Set or Reset the CC3NP Bit */
mbed_official	52:a51c77007319	1932	tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);
mbed_official	52:a51c77007319	1933	tmpccer \|= (uint16_t)(TIM_OCNPolarity << 8);
mbed_official	52:a51c77007319	1934	/* Write to TIMx CCER register */
mbed_official	52:a51c77007319	1935	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	1936	}
mbed_official	52:a51c77007319	1937
mbed_official	52:a51c77007319	1938	/**
mbed_official	52:a51c77007319	1939	* @brief Configures the TIMx channel 4 polarity.
mbed_official	52:a51c77007319	1940	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	1941	* @param TIM_OCPolarity: specifies the OC4 Polarity
mbed_official	52:a51c77007319	1942	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1943	* @arg TIM_OCPolarity_High: Output Compare active high
mbed_official	52:a51c77007319	1944	* @arg TIM_OCPolarity_Low: Output Compare active low
mbed_official	52:a51c77007319	1945	* @retval None
mbed_official	52:a51c77007319	1946	*/
mbed_official	52:a51c77007319	1947	void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
mbed_official	52:a51c77007319	1948	{
mbed_official	52:a51c77007319	1949	uint16_t tmpccer = 0;
mbed_official	52:a51c77007319	1950	/* Check the parameters */
mbed_official	52:a51c77007319	1951	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	1952	assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
mbed_official	52:a51c77007319	1953	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	1954	/* Set or Reset the CC4P Bit */
mbed_official	52:a51c77007319	1955	tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
mbed_official	52:a51c77007319	1956	tmpccer \|= (uint16_t)(TIM_OCPolarity << 12);
mbed_official	52:a51c77007319	1957	/* Write to TIMx CCER register */
mbed_official	52:a51c77007319	1958	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	1959	}
mbed_official	52:a51c77007319	1960
mbed_official	52:a51c77007319	1961	/**
mbed_official	52:a51c77007319	1962	* @brief Enables or disables the TIM Capture Compare Channel x.
mbed_official	52:a51c77007319	1963	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
mbed_official	52:a51c77007319	1964	* @param TIM_Channel: specifies the TIM Channel
mbed_official	52:a51c77007319	1965	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1966	* @arg TIM_Channel_1: TIM Channel 1
mbed_official	52:a51c77007319	1967	* @arg TIM_Channel_2: TIM Channel 2
mbed_official	52:a51c77007319	1968	* @arg TIM_Channel_3: TIM Channel 3
mbed_official	52:a51c77007319	1969	* @arg TIM_Channel_4: TIM Channel 4
mbed_official	52:a51c77007319	1970	* @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
mbed_official	52:a51c77007319	1971	* This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
mbed_official	52:a51c77007319	1972	* @retval None
mbed_official	52:a51c77007319	1973	*/
mbed_official	52:a51c77007319	1974	void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
mbed_official	52:a51c77007319	1975	{
mbed_official	52:a51c77007319	1976	uint16_t tmp = 0;
mbed_official	52:a51c77007319	1977
mbed_official	52:a51c77007319	1978	/* Check the parameters */
mbed_official	52:a51c77007319	1979	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
mbed_official	52:a51c77007319	1980	assert_param(IS_TIM_CHANNEL(TIM_Channel));
mbed_official	52:a51c77007319	1981	assert_param(IS_TIM_CCX(TIM_CCx));
mbed_official	52:a51c77007319	1982
mbed_official	52:a51c77007319	1983	tmp = CCER_CCE_Set << TIM_Channel;
mbed_official	52:a51c77007319	1984
mbed_official	52:a51c77007319	1985	/* Reset the CCxE Bit */
mbed_official	52:a51c77007319	1986	TIMx->CCER &= (uint16_t)~ tmp;
mbed_official	52:a51c77007319	1987
mbed_official	52:a51c77007319	1988	/* Set or reset the CCxE Bit */
mbed_official	52:a51c77007319	1989	TIMx->CCER \|= (uint16_t)(TIM_CCx << TIM_Channel);
mbed_official	52:a51c77007319	1990	}
mbed_official	52:a51c77007319	1991
mbed_official	52:a51c77007319	1992	/**
mbed_official	52:a51c77007319	1993	* @brief Enables or disables the TIM Capture Compare Channel xN.
mbed_official	52:a51c77007319	1994	* @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	1995	* @param TIM_Channel: specifies the TIM Channel
mbed_official	52:a51c77007319	1996	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	1997	* @arg TIM_Channel_1: TIM Channel 1
mbed_official	52:a51c77007319	1998	* @arg TIM_Channel_2: TIM Channel 2
mbed_official	52:a51c77007319	1999	* @arg TIM_Channel_3: TIM Channel 3
mbed_official	52:a51c77007319	2000	* @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
mbed_official	52:a51c77007319	2001	* This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
mbed_official	52:a51c77007319	2002	* @retval None
mbed_official	52:a51c77007319	2003	*/
mbed_official	52:a51c77007319	2004	void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
mbed_official	52:a51c77007319	2005	{
mbed_official	52:a51c77007319	2006	uint16_t tmp = 0;
mbed_official	52:a51c77007319	2007
mbed_official	52:a51c77007319	2008	/* Check the parameters */
mbed_official	52:a51c77007319	2009	assert_param(IS_TIM_LIST2_PERIPH(TIMx));
mbed_official	52:a51c77007319	2010	assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
mbed_official	52:a51c77007319	2011	assert_param(IS_TIM_CCXN(TIM_CCxN));
mbed_official	52:a51c77007319	2012
mbed_official	52:a51c77007319	2013	tmp = CCER_CCNE_Set << TIM_Channel;
mbed_official	52:a51c77007319	2014
mbed_official	52:a51c77007319	2015	/* Reset the CCxNE Bit */
mbed_official	52:a51c77007319	2016	TIMx->CCER &= (uint16_t) ~tmp;
mbed_official	52:a51c77007319	2017
mbed_official	52:a51c77007319	2018	/* Set or reset the CCxNE Bit */
mbed_official	52:a51c77007319	2019	TIMx->CCER \|= (uint16_t)(TIM_CCxN << TIM_Channel);
mbed_official	52:a51c77007319	2020	}
mbed_official	52:a51c77007319	2021
mbed_official	52:a51c77007319	2022	/**
mbed_official	52:a51c77007319	2023	* @brief Selects the TIM Output Compare Mode.
mbed_official	52:a51c77007319	2024	* @note This function disables the selected channel before changing the Output
mbed_official	52:a51c77007319	2025	* Compare Mode.
mbed_official	52:a51c77007319	2026	* User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
mbed_official	52:a51c77007319	2027	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
mbed_official	52:a51c77007319	2028	* @param TIM_Channel: specifies the TIM Channel
mbed_official	52:a51c77007319	2029	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2030	* @arg TIM_Channel_1: TIM Channel 1
mbed_official	52:a51c77007319	2031	* @arg TIM_Channel_2: TIM Channel 2
mbed_official	52:a51c77007319	2032	* @arg TIM_Channel_3: TIM Channel 3
mbed_official	52:a51c77007319	2033	* @arg TIM_Channel_4: TIM Channel 4
mbed_official	52:a51c77007319	2034	* @param TIM_OCMode: specifies the TIM Output Compare Mode.
mbed_official	52:a51c77007319	2035	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2036	* @arg TIM_OCMode_Timing
mbed_official	52:a51c77007319	2037	* @arg TIM_OCMode_Active
mbed_official	52:a51c77007319	2038	* @arg TIM_OCMode_Toggle
mbed_official	52:a51c77007319	2039	* @arg TIM_OCMode_PWM1
mbed_official	52:a51c77007319	2040	* @arg TIM_OCMode_PWM2
mbed_official	52:a51c77007319	2041	* @arg TIM_ForcedAction_Active
mbed_official	52:a51c77007319	2042	* @arg TIM_ForcedAction_InActive
mbed_official	52:a51c77007319	2043	* @retval None
mbed_official	52:a51c77007319	2044	*/
mbed_official	52:a51c77007319	2045	void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
mbed_official	52:a51c77007319	2046	{
mbed_official	52:a51c77007319	2047	uint32_t tmp = 0;
mbed_official	52:a51c77007319	2048	uint16_t tmp1 = 0;
mbed_official	52:a51c77007319	2049
mbed_official	52:a51c77007319	2050	/* Check the parameters */
mbed_official	52:a51c77007319	2051	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
mbed_official	52:a51c77007319	2052	assert_param(IS_TIM_CHANNEL(TIM_Channel));
mbed_official	52:a51c77007319	2053	assert_param(IS_TIM_OCM(TIM_OCMode));
mbed_official	52:a51c77007319	2054
mbed_official	52:a51c77007319	2055	tmp = (uint32_t) TIMx;
mbed_official	52:a51c77007319	2056	tmp += CCMR_Offset;
mbed_official	52:a51c77007319	2057
mbed_official	52:a51c77007319	2058	tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;
mbed_official	52:a51c77007319	2059
mbed_official	52:a51c77007319	2060	/* Disable the Channel: Reset the CCxE Bit */
mbed_official	52:a51c77007319	2061	TIMx->CCER &= (uint16_t) ~tmp1;
mbed_official	52:a51c77007319	2062
mbed_official	52:a51c77007319	2063	if((TIM_Channel == TIM_Channel_1) \|\|(TIM_Channel == TIM_Channel_3))
mbed_official	52:a51c77007319	2064	{
mbed_official	52:a51c77007319	2065	tmp += (TIM_Channel>>1);
mbed_official	52:a51c77007319	2066
mbed_official	52:a51c77007319	2067	/* Reset the OCxM bits in the CCMRx register */
mbed_official	52:a51c77007319	2068	(__IO uint32_t ) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
mbed_official	52:a51c77007319	2069
mbed_official	52:a51c77007319	2070	/* Configure the OCxM bits in the CCMRx register */
mbed_official	52:a51c77007319	2071	(__IO uint32_t ) tmp \|= TIM_OCMode;
mbed_official	52:a51c77007319	2072	}
mbed_official	52:a51c77007319	2073	else
mbed_official	52:a51c77007319	2074	{
mbed_official	52:a51c77007319	2075	tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
mbed_official	52:a51c77007319	2076
mbed_official	52:a51c77007319	2077	/* Reset the OCxM bits in the CCMRx register */
mbed_official	52:a51c77007319	2078	(__IO uint32_t ) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
mbed_official	52:a51c77007319	2079
mbed_official	52:a51c77007319	2080	/* Configure the OCxM bits in the CCMRx register */
mbed_official	52:a51c77007319	2081	(__IO uint32_t ) tmp \|= (uint16_t)(TIM_OCMode << 8);
mbed_official	52:a51c77007319	2082	}
mbed_official	52:a51c77007319	2083	}
mbed_official	52:a51c77007319	2084
mbed_official	52:a51c77007319	2085	/**
mbed_official	52:a51c77007319	2086	* @brief Enables or Disables the TIMx Update event.
mbed_official	52:a51c77007319	2087	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	2088	* @param NewState: new state of the TIMx UDIS bit
mbed_official	52:a51c77007319	2089	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	2090	* @retval None
mbed_official	52:a51c77007319	2091	*/
mbed_official	52:a51c77007319	2092	void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
mbed_official	52:a51c77007319	2093	{
mbed_official	52:a51c77007319	2094	/* Check the parameters */
mbed_official	52:a51c77007319	2095	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	2096	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	2097	if (NewState != DISABLE)
mbed_official	52:a51c77007319	2098	{
mbed_official	52:a51c77007319	2099	/* Set the Update Disable Bit */
mbed_official	52:a51c77007319	2100	TIMx->CR1 \|= TIM_CR1_UDIS;
mbed_official	52:a51c77007319	2101	}
mbed_official	52:a51c77007319	2102	else
mbed_official	52:a51c77007319	2103	{
mbed_official	52:a51c77007319	2104	/* Reset the Update Disable Bit */
mbed_official	52:a51c77007319	2105	TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
mbed_official	52:a51c77007319	2106	}
mbed_official	52:a51c77007319	2107	}
mbed_official	52:a51c77007319	2108
mbed_official	52:a51c77007319	2109	/**
mbed_official	52:a51c77007319	2110	* @brief Configures the TIMx Update Request Interrupt source.
mbed_official	52:a51c77007319	2111	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	2112	* @param TIM_UpdateSource: specifies the Update source.
mbed_official	52:a51c77007319	2113	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2114	* @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
mbed_official	52:a51c77007319	2115	or the setting of UG bit, or an update generation
mbed_official	52:a51c77007319	2116	through the slave mode controller.
mbed_official	52:a51c77007319	2117	* @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
mbed_official	52:a51c77007319	2118	* @retval None
mbed_official	52:a51c77007319	2119	*/
mbed_official	52:a51c77007319	2120	void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
mbed_official	52:a51c77007319	2121	{
mbed_official	52:a51c77007319	2122	/* Check the parameters */
mbed_official	52:a51c77007319	2123	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	2124	assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
mbed_official	52:a51c77007319	2125	if (TIM_UpdateSource != TIM_UpdateSource_Global)
mbed_official	52:a51c77007319	2126	{
mbed_official	52:a51c77007319	2127	/* Set the URS Bit */
mbed_official	52:a51c77007319	2128	TIMx->CR1 \|= TIM_CR1_URS;
mbed_official	52:a51c77007319	2129	}
mbed_official	52:a51c77007319	2130	else
mbed_official	52:a51c77007319	2131	{
mbed_official	52:a51c77007319	2132	/* Reset the URS Bit */
mbed_official	52:a51c77007319	2133	TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
mbed_official	52:a51c77007319	2134	}
mbed_official	52:a51c77007319	2135	}
mbed_official	52:a51c77007319	2136
mbed_official	52:a51c77007319	2137	/**
mbed_official	52:a51c77007319	2138	* @brief Enables or disables the TIMx's Hall sensor interface.
mbed_official	52:a51c77007319	2139	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	2140	* @param NewState: new state of the TIMx Hall sensor interface.
mbed_official	52:a51c77007319	2141	* This parameter can be: ENABLE or DISABLE.
mbed_official	52:a51c77007319	2142	* @retval None
mbed_official	52:a51c77007319	2143	*/
mbed_official	52:a51c77007319	2144	void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
mbed_official	52:a51c77007319	2145	{
mbed_official	52:a51c77007319	2146	/* Check the parameters */
mbed_official	52:a51c77007319	2147	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	2148	assert_param(IS_FUNCTIONAL_STATE(NewState));
mbed_official	52:a51c77007319	2149	if (NewState != DISABLE)
mbed_official	52:a51c77007319	2150	{
mbed_official	52:a51c77007319	2151	/* Set the TI1S Bit */
mbed_official	52:a51c77007319	2152	TIMx->CR2 \|= TIM_CR2_TI1S;
mbed_official	52:a51c77007319	2153	}
mbed_official	52:a51c77007319	2154	else
mbed_official	52:a51c77007319	2155	{
mbed_official	52:a51c77007319	2156	/* Reset the TI1S Bit */
mbed_official	52:a51c77007319	2157	TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
mbed_official	52:a51c77007319	2158	}
mbed_official	52:a51c77007319	2159	}
mbed_official	52:a51c77007319	2160
mbed_official	52:a51c77007319	2161	/**
mbed_official	52:a51c77007319	2162	* @brief Selects the TIMx's One Pulse Mode.
mbed_official	52:a51c77007319	2163	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	2164	* @param TIM_OPMode: specifies the OPM Mode to be used.
mbed_official	52:a51c77007319	2165	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2166	* @arg TIM_OPMode_Single
mbed_official	52:a51c77007319	2167	* @arg TIM_OPMode_Repetitive
mbed_official	52:a51c77007319	2168	* @retval None
mbed_official	52:a51c77007319	2169	*/
mbed_official	52:a51c77007319	2170	void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
mbed_official	52:a51c77007319	2171	{
mbed_official	52:a51c77007319	2172	/* Check the parameters */
mbed_official	52:a51c77007319	2173	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	2174	assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
mbed_official	52:a51c77007319	2175	/* Reset the OPM Bit */
mbed_official	52:a51c77007319	2176	TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
mbed_official	52:a51c77007319	2177	/* Configure the OPM Mode */
mbed_official	52:a51c77007319	2178	TIMx->CR1 \|= TIM_OPMode;
mbed_official	52:a51c77007319	2179	}
mbed_official	52:a51c77007319	2180
mbed_official	52:a51c77007319	2181	/**
mbed_official	52:a51c77007319	2182	* @brief Selects the TIMx Trigger Output Mode.
mbed_official	52:a51c77007319	2183	* @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	2184	* @param TIM_TRGOSource: specifies the Trigger Output source.
mbed_official	52:a51c77007319	2185	* This paramter can be one of the following values:
mbed_official	52:a51c77007319	2186	*
mbed_official	52:a51c77007319	2187	* - For all TIMx
mbed_official	52:a51c77007319	2188	* @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
mbed_official	52:a51c77007319	2189	* @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
mbed_official	52:a51c77007319	2190	* @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
mbed_official	52:a51c77007319	2191	*
mbed_official	52:a51c77007319	2192	* - For all TIMx except TIM6 and TIM7
mbed_official	52:a51c77007319	2193	* @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
mbed_official	52:a51c77007319	2194	* is to be set, as soon as a capture or compare match occurs (TRGO).
mbed_official	52:a51c77007319	2195	* @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
mbed_official	52:a51c77007319	2196	* @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
mbed_official	52:a51c77007319	2197	* @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
mbed_official	52:a51c77007319	2198	* @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
mbed_official	52:a51c77007319	2199	*
mbed_official	52:a51c77007319	2200	* @retval None
mbed_official	52:a51c77007319	2201	*/
mbed_official	52:a51c77007319	2202	void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
mbed_official	52:a51c77007319	2203	{
mbed_official	52:a51c77007319	2204	/* Check the parameters */
mbed_official	52:a51c77007319	2205	assert_param(IS_TIM_LIST7_PERIPH(TIMx));
mbed_official	52:a51c77007319	2206	assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
mbed_official	52:a51c77007319	2207	/* Reset the MMS Bits */
mbed_official	52:a51c77007319	2208	TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
mbed_official	52:a51c77007319	2209	/* Select the TRGO source */
mbed_official	52:a51c77007319	2210	TIMx->CR2 \|= TIM_TRGOSource;
mbed_official	52:a51c77007319	2211	}
mbed_official	52:a51c77007319	2212
mbed_official	52:a51c77007319	2213	/**
mbed_official	52:a51c77007319	2214	* @brief Selects the TIMx Slave Mode.
mbed_official	52:a51c77007319	2215	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	2216	* @param TIM_SlaveMode: specifies the Timer Slave Mode.
mbed_official	52:a51c77007319	2217	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2218	* @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
mbed_official	52:a51c77007319	2219	* the counter and triggers an update of the registers.
mbed_official	52:a51c77007319	2220	* @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
mbed_official	52:a51c77007319	2221	* @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
mbed_official	52:a51c77007319	2222	* @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
mbed_official	52:a51c77007319	2223	* @retval None
mbed_official	52:a51c77007319	2224	*/
mbed_official	52:a51c77007319	2225	void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
mbed_official	52:a51c77007319	2226	{
mbed_official	52:a51c77007319	2227	/* Check the parameters */
mbed_official	52:a51c77007319	2228	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	2229	assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
mbed_official	52:a51c77007319	2230	/* Reset the SMS Bits */
mbed_official	52:a51c77007319	2231	TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
mbed_official	52:a51c77007319	2232	/* Select the Slave Mode */
mbed_official	52:a51c77007319	2233	TIMx->SMCR \|= TIM_SlaveMode;
mbed_official	52:a51c77007319	2234	}
mbed_official	52:a51c77007319	2235
mbed_official	52:a51c77007319	2236	/**
mbed_official	52:a51c77007319	2237	* @brief Sets or Resets the TIMx Master/Slave Mode.
mbed_official	52:a51c77007319	2238	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	2239	* @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
mbed_official	52:a51c77007319	2240	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2241	* @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
mbed_official	52:a51c77007319	2242	* and its slaves (through TRGO).
mbed_official	52:a51c77007319	2243	* @arg TIM_MasterSlaveMode_Disable: No action
mbed_official	52:a51c77007319	2244	* @retval None
mbed_official	52:a51c77007319	2245	*/
mbed_official	52:a51c77007319	2246	void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
mbed_official	52:a51c77007319	2247	{
mbed_official	52:a51c77007319	2248	/* Check the parameters */
mbed_official	52:a51c77007319	2249	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	2250	assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
mbed_official	52:a51c77007319	2251	/* Reset the MSM Bit */
mbed_official	52:a51c77007319	2252	TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
mbed_official	52:a51c77007319	2253
mbed_official	52:a51c77007319	2254	/* Set or Reset the MSM Bit */
mbed_official	52:a51c77007319	2255	TIMx->SMCR \|= TIM_MasterSlaveMode;
mbed_official	52:a51c77007319	2256	}
mbed_official	52:a51c77007319	2257
mbed_official	52:a51c77007319	2258	/**
mbed_official	52:a51c77007319	2259	* @brief Sets the TIMx Counter Register value
mbed_official	52:a51c77007319	2260	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	2261	* @param Counter: specifies the Counter register new value.
mbed_official	52:a51c77007319	2262	* @retval None
mbed_official	52:a51c77007319	2263	*/
mbed_official	52:a51c77007319	2264	void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)
mbed_official	52:a51c77007319	2265	{
mbed_official	52:a51c77007319	2266	/* Check the parameters */
mbed_official	52:a51c77007319	2267	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	2268	/* Set the Counter Register value */
mbed_official	52:a51c77007319	2269	TIMx->CNT = Counter;
mbed_official	52:a51c77007319	2270	}
mbed_official	52:a51c77007319	2271
mbed_official	52:a51c77007319	2272	/**
mbed_official	52:a51c77007319	2273	* @brief Sets the TIMx Autoreload Register value
mbed_official	52:a51c77007319	2274	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	2275	* @param Autoreload: specifies the Autoreload register new value.
mbed_official	52:a51c77007319	2276	* @retval None
mbed_official	52:a51c77007319	2277	*/
mbed_official	52:a51c77007319	2278	void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)
mbed_official	52:a51c77007319	2279	{
mbed_official	52:a51c77007319	2280	/* Check the parameters */
mbed_official	52:a51c77007319	2281	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	2282	/* Set the Autoreload Register value */
mbed_official	52:a51c77007319	2283	TIMx->ARR = Autoreload;
mbed_official	52:a51c77007319	2284	}
mbed_official	52:a51c77007319	2285
mbed_official	52:a51c77007319	2286	/**
mbed_official	52:a51c77007319	2287	* @brief Sets the TIMx Capture Compare1 Register value
mbed_official	52:a51c77007319	2288	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
mbed_official	52:a51c77007319	2289	* @param Compare1: specifies the Capture Compare1 register new value.
mbed_official	52:a51c77007319	2290	* @retval None
mbed_official	52:a51c77007319	2291	*/
mbed_official	52:a51c77007319	2292	void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)
mbed_official	52:a51c77007319	2293	{
mbed_official	52:a51c77007319	2294	/* Check the parameters */
mbed_official	52:a51c77007319	2295	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
mbed_official	52:a51c77007319	2296	/* Set the Capture Compare1 Register value */
mbed_official	52:a51c77007319	2297	TIMx->CCR1 = Compare1;
mbed_official	52:a51c77007319	2298	}
mbed_official	52:a51c77007319	2299
mbed_official	52:a51c77007319	2300	/**
mbed_official	52:a51c77007319	2301	* @brief Sets the TIMx Capture Compare2 Register value
mbed_official	52:a51c77007319	2302	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	2303	* @param Compare2: specifies the Capture Compare2 register new value.
mbed_official	52:a51c77007319	2304	* @retval None
mbed_official	52:a51c77007319	2305	*/
mbed_official	52:a51c77007319	2306	void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)
mbed_official	52:a51c77007319	2307	{
mbed_official	52:a51c77007319	2308	/* Check the parameters */
mbed_official	52:a51c77007319	2309	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	2310	/* Set the Capture Compare2 Register value */
mbed_official	52:a51c77007319	2311	TIMx->CCR2 = Compare2;
mbed_official	52:a51c77007319	2312	}
mbed_official	52:a51c77007319	2313
mbed_official	52:a51c77007319	2314	/**
mbed_official	52:a51c77007319	2315	* @brief Sets the TIMx Capture Compare3 Register value
mbed_official	52:a51c77007319	2316	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	2317	* @param Compare3: specifies the Capture Compare3 register new value.
mbed_official	52:a51c77007319	2318	* @retval None
mbed_official	52:a51c77007319	2319	*/
mbed_official	52:a51c77007319	2320	void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)
mbed_official	52:a51c77007319	2321	{
mbed_official	52:a51c77007319	2322	/* Check the parameters */
mbed_official	52:a51c77007319	2323	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	2324	/* Set the Capture Compare3 Register value */
mbed_official	52:a51c77007319	2325	TIMx->CCR3 = Compare3;
mbed_official	52:a51c77007319	2326	}
mbed_official	52:a51c77007319	2327
mbed_official	52:a51c77007319	2328	/**
mbed_official	52:a51c77007319	2329	* @brief Sets the TIMx Capture Compare4 Register value
mbed_official	52:a51c77007319	2330	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	2331	* @param Compare4: specifies the Capture Compare4 register new value.
mbed_official	52:a51c77007319	2332	* @retval None
mbed_official	52:a51c77007319	2333	*/
mbed_official	52:a51c77007319	2334	void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)
mbed_official	52:a51c77007319	2335	{
mbed_official	52:a51c77007319	2336	/* Check the parameters */
mbed_official	52:a51c77007319	2337	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	2338	/* Set the Capture Compare4 Register value */
mbed_official	52:a51c77007319	2339	TIMx->CCR4 = Compare4;
mbed_official	52:a51c77007319	2340	}
mbed_official	52:a51c77007319	2341
mbed_official	52:a51c77007319	2342	/**
mbed_official	52:a51c77007319	2343	* @brief Sets the TIMx Input Capture 1 prescaler.
mbed_official	52:a51c77007319	2344	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
mbed_official	52:a51c77007319	2345	* @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
mbed_official	52:a51c77007319	2346	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2347	* @arg TIM_ICPSC_DIV1: no prescaler
mbed_official	52:a51c77007319	2348	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
mbed_official	52:a51c77007319	2349	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
mbed_official	52:a51c77007319	2350	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
mbed_official	52:a51c77007319	2351	* @retval None
mbed_official	52:a51c77007319	2352	*/
mbed_official	52:a51c77007319	2353	void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
mbed_official	52:a51c77007319	2354	{
mbed_official	52:a51c77007319	2355	/* Check the parameters */
mbed_official	52:a51c77007319	2356	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
mbed_official	52:a51c77007319	2357	assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
mbed_official	52:a51c77007319	2358	/* Reset the IC1PSC Bits */
mbed_official	52:a51c77007319	2359	TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
mbed_official	52:a51c77007319	2360	/* Set the IC1PSC value */
mbed_official	52:a51c77007319	2361	TIMx->CCMR1 \|= TIM_ICPSC;
mbed_official	52:a51c77007319	2362	}
mbed_official	52:a51c77007319	2363
mbed_official	52:a51c77007319	2364	/**
mbed_official	52:a51c77007319	2365	* @brief Sets the TIMx Input Capture 2 prescaler.
mbed_official	52:a51c77007319	2366	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	2367	* @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
mbed_official	52:a51c77007319	2368	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2369	* @arg TIM_ICPSC_DIV1: no prescaler
mbed_official	52:a51c77007319	2370	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
mbed_official	52:a51c77007319	2371	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
mbed_official	52:a51c77007319	2372	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
mbed_official	52:a51c77007319	2373	* @retval None
mbed_official	52:a51c77007319	2374	*/
mbed_official	52:a51c77007319	2375	void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
mbed_official	52:a51c77007319	2376	{
mbed_official	52:a51c77007319	2377	/* Check the parameters */
mbed_official	52:a51c77007319	2378	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	2379	assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
mbed_official	52:a51c77007319	2380	/* Reset the IC2PSC Bits */
mbed_official	52:a51c77007319	2381	TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
mbed_official	52:a51c77007319	2382	/* Set the IC2PSC value */
mbed_official	52:a51c77007319	2383	TIMx->CCMR1 \|= (uint16_t)(TIM_ICPSC << 8);
mbed_official	52:a51c77007319	2384	}
mbed_official	52:a51c77007319	2385
mbed_official	52:a51c77007319	2386	/**
mbed_official	52:a51c77007319	2387	* @brief Sets the TIMx Input Capture 3 prescaler.
mbed_official	52:a51c77007319	2388	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	2389	* @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
mbed_official	52:a51c77007319	2390	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2391	* @arg TIM_ICPSC_DIV1: no prescaler
mbed_official	52:a51c77007319	2392	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
mbed_official	52:a51c77007319	2393	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
mbed_official	52:a51c77007319	2394	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
mbed_official	52:a51c77007319	2395	* @retval None
mbed_official	52:a51c77007319	2396	*/
mbed_official	52:a51c77007319	2397	void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
mbed_official	52:a51c77007319	2398	{
mbed_official	52:a51c77007319	2399	/* Check the parameters */
mbed_official	52:a51c77007319	2400	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	2401	assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
mbed_official	52:a51c77007319	2402	/* Reset the IC3PSC Bits */
mbed_official	52:a51c77007319	2403	TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
mbed_official	52:a51c77007319	2404	/* Set the IC3PSC value */
mbed_official	52:a51c77007319	2405	TIMx->CCMR2 \|= TIM_ICPSC;
mbed_official	52:a51c77007319	2406	}
mbed_official	52:a51c77007319	2407
mbed_official	52:a51c77007319	2408	/**
mbed_official	52:a51c77007319	2409	* @brief Sets the TIMx Input Capture 4 prescaler.
mbed_official	52:a51c77007319	2410	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	2411	* @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
mbed_official	52:a51c77007319	2412	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2413	* @arg TIM_ICPSC_DIV1: no prescaler
mbed_official	52:a51c77007319	2414	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
mbed_official	52:a51c77007319	2415	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
mbed_official	52:a51c77007319	2416	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
mbed_official	52:a51c77007319	2417	* @retval None
mbed_official	52:a51c77007319	2418	*/
mbed_official	52:a51c77007319	2419	void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
mbed_official	52:a51c77007319	2420	{
mbed_official	52:a51c77007319	2421	/* Check the parameters */
mbed_official	52:a51c77007319	2422	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	2423	assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
mbed_official	52:a51c77007319	2424	/* Reset the IC4PSC Bits */
mbed_official	52:a51c77007319	2425	TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
mbed_official	52:a51c77007319	2426	/* Set the IC4PSC value */
mbed_official	52:a51c77007319	2427	TIMx->CCMR2 \|= (uint16_t)(TIM_ICPSC << 8);
mbed_official	52:a51c77007319	2428	}
mbed_official	52:a51c77007319	2429
mbed_official	52:a51c77007319	2430	/**
mbed_official	52:a51c77007319	2431	* @brief Sets the TIMx Clock Division value.
mbed_official	52:a51c77007319	2432	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select
mbed_official	52:a51c77007319	2433	* the TIM peripheral.
mbed_official	52:a51c77007319	2434	* @param TIM_CKD: specifies the clock division value.
mbed_official	52:a51c77007319	2435	* This parameter can be one of the following value:
mbed_official	52:a51c77007319	2436	* @arg TIM_CKD_DIV1: TDTS = Tck_tim
mbed_official	52:a51c77007319	2437	* @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
mbed_official	52:a51c77007319	2438	* @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
mbed_official	52:a51c77007319	2439	* @retval None
mbed_official	52:a51c77007319	2440	*/
mbed_official	52:a51c77007319	2441	void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
mbed_official	52:a51c77007319	2442	{
mbed_official	52:a51c77007319	2443	/* Check the parameters */
mbed_official	52:a51c77007319	2444	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
mbed_official	52:a51c77007319	2445	assert_param(IS_TIM_CKD_DIV(TIM_CKD));
mbed_official	52:a51c77007319	2446	/* Reset the CKD Bits */
mbed_official	52:a51c77007319	2447	TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
mbed_official	52:a51c77007319	2448	/* Set the CKD value */
mbed_official	52:a51c77007319	2449	TIMx->CR1 \|= TIM_CKD;
mbed_official	52:a51c77007319	2450	}
mbed_official	52:a51c77007319	2451
mbed_official	52:a51c77007319	2452	/**
mbed_official	52:a51c77007319	2453	* @brief Gets the TIMx Input Capture 1 value.
mbed_official	52:a51c77007319	2454	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
mbed_official	52:a51c77007319	2455	* @retval Capture Compare 1 Register value.
mbed_official	52:a51c77007319	2456	*/
mbed_official	52:a51c77007319	2457	uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)
mbed_official	52:a51c77007319	2458	{
mbed_official	52:a51c77007319	2459	/* Check the parameters */
mbed_official	52:a51c77007319	2460	assert_param(IS_TIM_LIST8_PERIPH(TIMx));
mbed_official	52:a51c77007319	2461	/* Get the Capture 1 Register value */
mbed_official	52:a51c77007319	2462	return TIMx->CCR1;
mbed_official	52:a51c77007319	2463	}
mbed_official	52:a51c77007319	2464
mbed_official	52:a51c77007319	2465	/**
mbed_official	52:a51c77007319	2466	* @brief Gets the TIMx Input Capture 2 value.
mbed_official	52:a51c77007319	2467	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	2468	* @retval Capture Compare 2 Register value.
mbed_official	52:a51c77007319	2469	*/
mbed_official	52:a51c77007319	2470	uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)
mbed_official	52:a51c77007319	2471	{
mbed_official	52:a51c77007319	2472	/* Check the parameters */
mbed_official	52:a51c77007319	2473	assert_param(IS_TIM_LIST6_PERIPH(TIMx));
mbed_official	52:a51c77007319	2474	/* Get the Capture 2 Register value */
mbed_official	52:a51c77007319	2475	return TIMx->CCR2;
mbed_official	52:a51c77007319	2476	}
mbed_official	52:a51c77007319	2477
mbed_official	52:a51c77007319	2478	/**
mbed_official	52:a51c77007319	2479	* @brief Gets the TIMx Input Capture 3 value.
mbed_official	52:a51c77007319	2480	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	2481	* @retval Capture Compare 3 Register value.
mbed_official	52:a51c77007319	2482	*/
mbed_official	52:a51c77007319	2483	uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)
mbed_official	52:a51c77007319	2484	{
mbed_official	52:a51c77007319	2485	/* Check the parameters */
mbed_official	52:a51c77007319	2486	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	2487	/* Get the Capture 3 Register value */
mbed_official	52:a51c77007319	2488	return TIMx->CCR3;
mbed_official	52:a51c77007319	2489	}
mbed_official	52:a51c77007319	2490
mbed_official	52:a51c77007319	2491	/**
mbed_official	52:a51c77007319	2492	* @brief Gets the TIMx Input Capture 4 value.
mbed_official	52:a51c77007319	2493	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	2494	* @retval Capture Compare 4 Register value.
mbed_official	52:a51c77007319	2495	*/
mbed_official	52:a51c77007319	2496	uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)
mbed_official	52:a51c77007319	2497	{
mbed_official	52:a51c77007319	2498	/* Check the parameters */
mbed_official	52:a51c77007319	2499	assert_param(IS_TIM_LIST3_PERIPH(TIMx));
mbed_official	52:a51c77007319	2500	/* Get the Capture 4 Register value */
mbed_official	52:a51c77007319	2501	return TIMx->CCR4;
mbed_official	52:a51c77007319	2502	}
mbed_official	52:a51c77007319	2503
mbed_official	52:a51c77007319	2504	/**
mbed_official	52:a51c77007319	2505	* @brief Gets the TIMx Counter value.
mbed_official	52:a51c77007319	2506	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	2507	* @retval Counter Register value.
mbed_official	52:a51c77007319	2508	*/
mbed_official	52:a51c77007319	2509	uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)
mbed_official	52:a51c77007319	2510	{
mbed_official	52:a51c77007319	2511	/* Check the parameters */
mbed_official	52:a51c77007319	2512	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	2513	/* Get the Counter Register value */
mbed_official	52:a51c77007319	2514	return TIMx->CNT;
mbed_official	52:a51c77007319	2515	}
mbed_official	52:a51c77007319	2516
mbed_official	52:a51c77007319	2517	/**
mbed_official	52:a51c77007319	2518	* @brief Gets the TIMx Prescaler value.
mbed_official	52:a51c77007319	2519	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	2520	* @retval Prescaler Register value.
mbed_official	52:a51c77007319	2521	*/
mbed_official	52:a51c77007319	2522	uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
mbed_official	52:a51c77007319	2523	{
mbed_official	52:a51c77007319	2524	/* Check the parameters */
mbed_official	52:a51c77007319	2525	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	2526	/* Get the Prescaler Register value */
mbed_official	52:a51c77007319	2527	return TIMx->PSC;
mbed_official	52:a51c77007319	2528	}
mbed_official	52:a51c77007319	2529
mbed_official	52:a51c77007319	2530	/**
mbed_official	52:a51c77007319	2531	* @brief Checks whether the specified TIM flag is set or not.
mbed_official	52:a51c77007319	2532	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	2533	* @param TIM_FLAG: specifies the flag to check.
mbed_official	52:a51c77007319	2534	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2535	* @arg TIM_FLAG_Update: TIM update Flag
mbed_official	52:a51c77007319	2536	* @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
mbed_official	52:a51c77007319	2537	* @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
mbed_official	52:a51c77007319	2538	* @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
mbed_official	52:a51c77007319	2539	* @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
mbed_official	52:a51c77007319	2540	* @arg TIM_FLAG_COM: TIM Commutation Flag
mbed_official	52:a51c77007319	2541	* @arg TIM_FLAG_Trigger: TIM Trigger Flag
mbed_official	52:a51c77007319	2542	* @arg TIM_FLAG_Break: TIM Break Flag
mbed_official	52:a51c77007319	2543	* @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
mbed_official	52:a51c77007319	2544	* @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
mbed_official	52:a51c77007319	2545	* @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
mbed_official	52:a51c77007319	2546	* @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
mbed_official	52:a51c77007319	2547	* @note
mbed_official	52:a51c77007319	2548	* - TIM6 and TIM7 can have only one update flag.
mbed_official	52:a51c77007319	2549	* - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
mbed_official	52:a51c77007319	2550	* TIM_FLAG_CC2 or TIM_FLAG_Trigger.
mbed_official	52:a51c77007319	2551	* - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
mbed_official	52:a51c77007319	2552	* - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15.
mbed_official	52:a51c77007319	2553	* - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
mbed_official	52:a51c77007319	2554	* @retval The new state of TIM_FLAG (SET or RESET).
mbed_official	52:a51c77007319	2555	*/
mbed_official	52:a51c77007319	2556	FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
mbed_official	52:a51c77007319	2557	{
mbed_official	52:a51c77007319	2558	ITStatus bitstatus = RESET;
mbed_official	52:a51c77007319	2559	/* Check the parameters */
mbed_official	52:a51c77007319	2560	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	2561	assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
mbed_official	52:a51c77007319	2562
mbed_official	52:a51c77007319	2563	if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
mbed_official	52:a51c77007319	2564	{
mbed_official	52:a51c77007319	2565	bitstatus = SET;
mbed_official	52:a51c77007319	2566	}
mbed_official	52:a51c77007319	2567	else
mbed_official	52:a51c77007319	2568	{
mbed_official	52:a51c77007319	2569	bitstatus = RESET;
mbed_official	52:a51c77007319	2570	}
mbed_official	52:a51c77007319	2571	return bitstatus;
mbed_official	52:a51c77007319	2572	}
mbed_official	52:a51c77007319	2573
mbed_official	52:a51c77007319	2574	/**
mbed_official	52:a51c77007319	2575	* @brief Clears the TIMx's pending flags.
mbed_official	52:a51c77007319	2576	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	2577	* @param TIM_FLAG: specifies the flag bit to clear.
mbed_official	52:a51c77007319	2578	* This parameter can be any combination of the following values:
mbed_official	52:a51c77007319	2579	* @arg TIM_FLAG_Update: TIM update Flag
mbed_official	52:a51c77007319	2580	* @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
mbed_official	52:a51c77007319	2581	* @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
mbed_official	52:a51c77007319	2582	* @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
mbed_official	52:a51c77007319	2583	* @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
mbed_official	52:a51c77007319	2584	* @arg TIM_FLAG_COM: TIM Commutation Flag
mbed_official	52:a51c77007319	2585	* @arg TIM_FLAG_Trigger: TIM Trigger Flag
mbed_official	52:a51c77007319	2586	* @arg TIM_FLAG_Break: TIM Break Flag
mbed_official	52:a51c77007319	2587	* @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
mbed_official	52:a51c77007319	2588	* @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
mbed_official	52:a51c77007319	2589	* @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
mbed_official	52:a51c77007319	2590	* @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
mbed_official	52:a51c77007319	2591	* @note
mbed_official	52:a51c77007319	2592	* - TIM6 and TIM7 can have only one update flag.
mbed_official	52:a51c77007319	2593	* - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
mbed_official	52:a51c77007319	2594	* TIM_FLAG_CC2 or TIM_FLAG_Trigger.
mbed_official	52:a51c77007319	2595	* - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
mbed_official	52:a51c77007319	2596	* - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15.
mbed_official	52:a51c77007319	2597	* - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
mbed_official	52:a51c77007319	2598	* @retval None
mbed_official	52:a51c77007319	2599	*/
mbed_official	52:a51c77007319	2600	void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
mbed_official	52:a51c77007319	2601	{
mbed_official	52:a51c77007319	2602	/* Check the parameters */
mbed_official	52:a51c77007319	2603	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	2604	assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
mbed_official	52:a51c77007319	2605
mbed_official	52:a51c77007319	2606	/* Clear the flags */
mbed_official	52:a51c77007319	2607	TIMx->SR = (uint16_t)~TIM_FLAG;
mbed_official	52:a51c77007319	2608	}
mbed_official	52:a51c77007319	2609
mbed_official	52:a51c77007319	2610	/**
mbed_official	52:a51c77007319	2611	* @brief Checks whether the TIM interrupt has occurred or not.
mbed_official	52:a51c77007319	2612	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	2613	* @param TIM_IT: specifies the TIM interrupt source to check.
mbed_official	52:a51c77007319	2614	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2615	* @arg TIM_IT_Update: TIM update Interrupt source
mbed_official	52:a51c77007319	2616	* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
mbed_official	52:a51c77007319	2617	* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
mbed_official	52:a51c77007319	2618	* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
mbed_official	52:a51c77007319	2619	* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
mbed_official	52:a51c77007319	2620	* @arg TIM_IT_COM: TIM Commutation Interrupt source
mbed_official	52:a51c77007319	2621	* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
mbed_official	52:a51c77007319	2622	* @arg TIM_IT_Break: TIM Break Interrupt source
mbed_official	52:a51c77007319	2623	* @note
mbed_official	52:a51c77007319	2624	* - TIM6 and TIM7 can generate only an update interrupt.
mbed_official	52:a51c77007319	2625	* - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
mbed_official	52:a51c77007319	2626	* TIM_IT_CC2 or TIM_IT_Trigger.
mbed_official	52:a51c77007319	2627	* - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
mbed_official	52:a51c77007319	2628	* - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
mbed_official	52:a51c77007319	2629	* - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
mbed_official	52:a51c77007319	2630	* @retval The new state of the TIM_IT(SET or RESET).
mbed_official	52:a51c77007319	2631	*/
mbed_official	52:a51c77007319	2632	ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
mbed_official	52:a51c77007319	2633	{
mbed_official	52:a51c77007319	2634	ITStatus bitstatus = RESET;
mbed_official	52:a51c77007319	2635	uint16_t itstatus = 0x0, itenable = 0x0;
mbed_official	52:a51c77007319	2636	/* Check the parameters */
mbed_official	52:a51c77007319	2637	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	2638	assert_param(IS_TIM_GET_IT(TIM_IT));
mbed_official	52:a51c77007319	2639
mbed_official	52:a51c77007319	2640	itstatus = TIMx->SR & TIM_IT;
mbed_official	52:a51c77007319	2641
mbed_official	52:a51c77007319	2642	itenable = TIMx->DIER & TIM_IT;
mbed_official	52:a51c77007319	2643	if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
mbed_official	52:a51c77007319	2644	{
mbed_official	52:a51c77007319	2645	bitstatus = SET;
mbed_official	52:a51c77007319	2646	}
mbed_official	52:a51c77007319	2647	else
mbed_official	52:a51c77007319	2648	{
mbed_official	52:a51c77007319	2649	bitstatus = RESET;
mbed_official	52:a51c77007319	2650	}
mbed_official	52:a51c77007319	2651	return bitstatus;
mbed_official	52:a51c77007319	2652	}
mbed_official	52:a51c77007319	2653
mbed_official	52:a51c77007319	2654	/**
mbed_official	52:a51c77007319	2655	* @brief Clears the TIMx's interrupt pending bits.
mbed_official	52:a51c77007319	2656	* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
mbed_official	52:a51c77007319	2657	* @param TIM_IT: specifies the pending bit to clear.
mbed_official	52:a51c77007319	2658	* This parameter can be any combination of the following values:
mbed_official	52:a51c77007319	2659	* @arg TIM_IT_Update: TIM1 update Interrupt source
mbed_official	52:a51c77007319	2660	* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
mbed_official	52:a51c77007319	2661	* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
mbed_official	52:a51c77007319	2662	* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
mbed_official	52:a51c77007319	2663	* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
mbed_official	52:a51c77007319	2664	* @arg TIM_IT_COM: TIM Commutation Interrupt source
mbed_official	52:a51c77007319	2665	* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
mbed_official	52:a51c77007319	2666	* @arg TIM_IT_Break: TIM Break Interrupt source
mbed_official	52:a51c77007319	2667	* @note
mbed_official	52:a51c77007319	2668	* - TIM6 and TIM7 can generate only an update interrupt.
mbed_official	52:a51c77007319	2669	* - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
mbed_official	52:a51c77007319	2670	* TIM_IT_CC2 or TIM_IT_Trigger.
mbed_official	52:a51c77007319	2671	* - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
mbed_official	52:a51c77007319	2672	* - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
mbed_official	52:a51c77007319	2673	* - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
mbed_official	52:a51c77007319	2674	* @retval None
mbed_official	52:a51c77007319	2675	*/
mbed_official	52:a51c77007319	2676	void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
mbed_official	52:a51c77007319	2677	{
mbed_official	52:a51c77007319	2678	/* Check the parameters */
mbed_official	52:a51c77007319	2679	assert_param(IS_TIM_ALL_PERIPH(TIMx));
mbed_official	52:a51c77007319	2680	assert_param(IS_TIM_IT(TIM_IT));
mbed_official	52:a51c77007319	2681	/* Clear the IT pending Bit */
mbed_official	52:a51c77007319	2682	TIMx->SR = (uint16_t)~TIM_IT;
mbed_official	52:a51c77007319	2683	}
mbed_official	52:a51c77007319	2684
mbed_official	52:a51c77007319	2685	/**
mbed_official	52:a51c77007319	2686	* @brief Configure the TI1 as Input.
mbed_official	52:a51c77007319	2687	* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
mbed_official	52:a51c77007319	2688	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	52:a51c77007319	2689	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2690	* @arg TIM_ICPolarity_Rising
mbed_official	52:a51c77007319	2691	* @arg TIM_ICPolarity_Falling
mbed_official	52:a51c77007319	2692	* @param TIM_ICSelection: specifies the input to be used.
mbed_official	52:a51c77007319	2693	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2694	* @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
mbed_official	52:a51c77007319	2695	* @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
mbed_official	52:a51c77007319	2696	* @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
mbed_official	52:a51c77007319	2697	* @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official	52:a51c77007319	2698	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	52:a51c77007319	2699	* @retval None
mbed_official	52:a51c77007319	2700	*/
mbed_official	52:a51c77007319	2701	static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
mbed_official	52:a51c77007319	2702	uint16_t TIM_ICFilter)
mbed_official	52:a51c77007319	2703	{
mbed_official	52:a51c77007319	2704	uint16_t tmpccmr1 = 0, tmpccer = 0;
mbed_official	52:a51c77007319	2705	/* Disable the Channel 1: Reset the CC1E Bit */
mbed_official	52:a51c77007319	2706	TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
mbed_official	52:a51c77007319	2707	tmpccmr1 = TIMx->CCMR1;
mbed_official	52:a51c77007319	2708	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	2709	/* Select the Input and set the filter */
mbed_official	52:a51c77007319	2710	tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
mbed_official	52:a51c77007319	2711	tmpccmr1 \|= (uint16_t)(TIM_ICSelection \| (uint16_t)(TIM_ICFilter << (uint16_t)4));
mbed_official	52:a51c77007319	2712
mbed_official	52:a51c77007319	2713	if((TIMx == TIM1) \|\| (TIMx == TIM8) \|\| (TIMx == TIM2) \|\| (TIMx == TIM3) \|\|
mbed_official	52:a51c77007319	2714	(TIMx == TIM4) \|\|(TIMx == TIM5))
mbed_official	52:a51c77007319	2715	{
mbed_official	52:a51c77007319	2716	/* Select the Polarity and set the CC1E Bit */
mbed_official	52:a51c77007319	2717	tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P));
mbed_official	52:a51c77007319	2718	tmpccer \|= (uint16_t)(TIM_ICPolarity \| (uint16_t)TIM_CCER_CC1E);
mbed_official	52:a51c77007319	2719	}
mbed_official	52:a51c77007319	2720	else
mbed_official	52:a51c77007319	2721	{
mbed_official	52:a51c77007319	2722	/* Select the Polarity and set the CC1E Bit */
mbed_official	52:a51c77007319	2723	tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P \| TIM_CCER_CC1NP));
mbed_official	52:a51c77007319	2724	tmpccer \|= (uint16_t)(TIM_ICPolarity \| (uint16_t)TIM_CCER_CC1E);
mbed_official	52:a51c77007319	2725	}
mbed_official	52:a51c77007319	2726
mbed_official	52:a51c77007319	2727	/* Write to TIMx CCMR1 and CCER registers */
mbed_official	52:a51c77007319	2728	TIMx->CCMR1 = tmpccmr1;
mbed_official	52:a51c77007319	2729	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	2730	}
mbed_official	52:a51c77007319	2731
mbed_official	52:a51c77007319	2732	/**
mbed_official	52:a51c77007319	2733	* @brief Configure the TI2 as Input.
mbed_official	52:a51c77007319	2734	* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
mbed_official	52:a51c77007319	2735	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	52:a51c77007319	2736	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2737	* @arg TIM_ICPolarity_Rising
mbed_official	52:a51c77007319	2738	* @arg TIM_ICPolarity_Falling
mbed_official	52:a51c77007319	2739	* @param TIM_ICSelection: specifies the input to be used.
mbed_official	52:a51c77007319	2740	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2741	* @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
mbed_official	52:a51c77007319	2742	* @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
mbed_official	52:a51c77007319	2743	* @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
mbed_official	52:a51c77007319	2744	* @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official	52:a51c77007319	2745	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	52:a51c77007319	2746	* @retval None
mbed_official	52:a51c77007319	2747	*/
mbed_official	52:a51c77007319	2748	static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
mbed_official	52:a51c77007319	2749	uint16_t TIM_ICFilter)
mbed_official	52:a51c77007319	2750	{
mbed_official	52:a51c77007319	2751	uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
mbed_official	52:a51c77007319	2752	/* Disable the Channel 2: Reset the CC2E Bit */
mbed_official	52:a51c77007319	2753	TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
mbed_official	52:a51c77007319	2754	tmpccmr1 = TIMx->CCMR1;
mbed_official	52:a51c77007319	2755	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	2756	tmp = (uint16_t)(TIM_ICPolarity << 4);
mbed_official	52:a51c77007319	2757	/* Select the Input and set the filter */
mbed_official	52:a51c77007319	2758	tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
mbed_official	52:a51c77007319	2759	tmpccmr1 \|= (uint16_t)(TIM_ICFilter << 12);
mbed_official	52:a51c77007319	2760	tmpccmr1 \|= (uint16_t)(TIM_ICSelection << 8);
mbed_official	52:a51c77007319	2761
mbed_official	52:a51c77007319	2762	if((TIMx == TIM1) \|\| (TIMx == TIM8) \|\| (TIMx == TIM2) \|\| (TIMx == TIM3) \|\|
mbed_official	52:a51c77007319	2763	(TIMx == TIM4) \|\|(TIMx == TIM5))
mbed_official	52:a51c77007319	2764	{
mbed_official	52:a51c77007319	2765	/* Select the Polarity and set the CC2E Bit */
mbed_official	52:a51c77007319	2766	tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P));
mbed_official	52:a51c77007319	2767	tmpccer \|= (uint16_t)(tmp \| (uint16_t)TIM_CCER_CC2E);
mbed_official	52:a51c77007319	2768	}
mbed_official	52:a51c77007319	2769	else
mbed_official	52:a51c77007319	2770	{
mbed_official	52:a51c77007319	2771	/* Select the Polarity and set the CC2E Bit */
mbed_official	52:a51c77007319	2772	tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P \| TIM_CCER_CC2NP));
mbed_official	52:a51c77007319	2773	tmpccer \|= (uint16_t)(TIM_ICPolarity \| (uint16_t)TIM_CCER_CC2E);
mbed_official	52:a51c77007319	2774	}
mbed_official	52:a51c77007319	2775
mbed_official	52:a51c77007319	2776	/* Write to TIMx CCMR1 and CCER registers */
mbed_official	52:a51c77007319	2777	TIMx->CCMR1 = tmpccmr1 ;
mbed_official	52:a51c77007319	2778	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	2779	}
mbed_official	52:a51c77007319	2780
mbed_official	52:a51c77007319	2781	/**
mbed_official	52:a51c77007319	2782	* @brief Configure the TI3 as Input.
mbed_official	52:a51c77007319	2783	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	2784	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	52:a51c77007319	2785	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2786	* @arg TIM_ICPolarity_Rising
mbed_official	52:a51c77007319	2787	* @arg TIM_ICPolarity_Falling
mbed_official	52:a51c77007319	2788	* @param TIM_ICSelection: specifies the input to be used.
mbed_official	52:a51c77007319	2789	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2790	* @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
mbed_official	52:a51c77007319	2791	* @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
mbed_official	52:a51c77007319	2792	* @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
mbed_official	52:a51c77007319	2793	* @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official	52:a51c77007319	2794	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	52:a51c77007319	2795	* @retval None
mbed_official	52:a51c77007319	2796	*/
mbed_official	52:a51c77007319	2797	static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
mbed_official	52:a51c77007319	2798	uint16_t TIM_ICFilter)
mbed_official	52:a51c77007319	2799	{
mbed_official	52:a51c77007319	2800	uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
mbed_official	52:a51c77007319	2801	/* Disable the Channel 3: Reset the CC3E Bit */
mbed_official	52:a51c77007319	2802	TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
mbed_official	52:a51c77007319	2803	tmpccmr2 = TIMx->CCMR2;
mbed_official	52:a51c77007319	2804	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	2805	tmp = (uint16_t)(TIM_ICPolarity << 8);
mbed_official	52:a51c77007319	2806	/* Select the Input and set the filter */
mbed_official	52:a51c77007319	2807	tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
mbed_official	52:a51c77007319	2808	tmpccmr2 \|= (uint16_t)(TIM_ICSelection \| (uint16_t)(TIM_ICFilter << (uint16_t)4));
mbed_official	52:a51c77007319	2809
mbed_official	52:a51c77007319	2810	if((TIMx == TIM1) \|\| (TIMx == TIM8) \|\| (TIMx == TIM2) \|\| (TIMx == TIM3) \|\|
mbed_official	52:a51c77007319	2811	(TIMx == TIM4) \|\|(TIMx == TIM5))
mbed_official	52:a51c77007319	2812	{
mbed_official	52:a51c77007319	2813	/* Select the Polarity and set the CC3E Bit */
mbed_official	52:a51c77007319	2814	tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P));
mbed_official	52:a51c77007319	2815	tmpccer \|= (uint16_t)(tmp \| (uint16_t)TIM_CCER_CC3E);
mbed_official	52:a51c77007319	2816	}
mbed_official	52:a51c77007319	2817	else
mbed_official	52:a51c77007319	2818	{
mbed_official	52:a51c77007319	2819	/* Select the Polarity and set the CC3E Bit */
mbed_official	52:a51c77007319	2820	tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P \| TIM_CCER_CC3NP));
mbed_official	52:a51c77007319	2821	tmpccer \|= (uint16_t)(TIM_ICPolarity \| (uint16_t)TIM_CCER_CC3E);
mbed_official	52:a51c77007319	2822	}
mbed_official	52:a51c77007319	2823
mbed_official	52:a51c77007319	2824	/* Write to TIMx CCMR2 and CCER registers */
mbed_official	52:a51c77007319	2825	TIMx->CCMR2 = tmpccmr2;
mbed_official	52:a51c77007319	2826	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	2827	}
mbed_official	52:a51c77007319	2828
mbed_official	52:a51c77007319	2829	/**
mbed_official	52:a51c77007319	2830	* @brief Configure the TI4 as Input.
mbed_official	52:a51c77007319	2831	* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
mbed_official	52:a51c77007319	2832	* @param TIM_ICPolarity : The Input Polarity.
mbed_official	52:a51c77007319	2833	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2834	* @arg TIM_ICPolarity_Rising
mbed_official	52:a51c77007319	2835	* @arg TIM_ICPolarity_Falling
mbed_official	52:a51c77007319	2836	* @param TIM_ICSelection: specifies the input to be used.
mbed_official	52:a51c77007319	2837	* This parameter can be one of the following values:
mbed_official	52:a51c77007319	2838	* @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
mbed_official	52:a51c77007319	2839	* @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
mbed_official	52:a51c77007319	2840	* @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
mbed_official	52:a51c77007319	2841	* @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official	52:a51c77007319	2842	* This parameter must be a value between 0x00 and 0x0F.
mbed_official	52:a51c77007319	2843	* @retval None
mbed_official	52:a51c77007319	2844	*/
mbed_official	52:a51c77007319	2845	static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
mbed_official	52:a51c77007319	2846	uint16_t TIM_ICFilter)
mbed_official	52:a51c77007319	2847	{
mbed_official	52:a51c77007319	2848	uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
mbed_official	52:a51c77007319	2849
mbed_official	52:a51c77007319	2850	/* Disable the Channel 4: Reset the CC4E Bit */
mbed_official	52:a51c77007319	2851	TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
mbed_official	52:a51c77007319	2852	tmpccmr2 = TIMx->CCMR2;
mbed_official	52:a51c77007319	2853	tmpccer = TIMx->CCER;
mbed_official	52:a51c77007319	2854	tmp = (uint16_t)(TIM_ICPolarity << 12);
mbed_official	52:a51c77007319	2855	/* Select the Input and set the filter */
mbed_official	52:a51c77007319	2856	tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
mbed_official	52:a51c77007319	2857	tmpccmr2 \|= (uint16_t)(TIM_ICSelection << 8);
mbed_official	52:a51c77007319	2858	tmpccmr2 \|= (uint16_t)(TIM_ICFilter << 12);
mbed_official	52:a51c77007319	2859
mbed_official	52:a51c77007319	2860	if((TIMx == TIM1) \|\| (TIMx == TIM8) \|\| (TIMx == TIM2) \|\| (TIMx == TIM3) \|\|
mbed_official	52:a51c77007319	2861	(TIMx == TIM4) \|\|(TIMx == TIM5))
mbed_official	52:a51c77007319	2862	{
mbed_official	52:a51c77007319	2863	/* Select the Polarity and set the CC4E Bit */
mbed_official	52:a51c77007319	2864	tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P));
mbed_official	52:a51c77007319	2865	tmpccer \|= (uint16_t)(tmp \| (uint16_t)TIM_CCER_CC4E);
mbed_official	52:a51c77007319	2866	}
mbed_official	52:a51c77007319	2867	else
mbed_official	52:a51c77007319	2868	{
mbed_official	52:a51c77007319	2869	/* Select the Polarity and set the CC4E Bit */
mbed_official	52:a51c77007319	2870	tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P \| TIM_CCER_CC4NP));
mbed_official	52:a51c77007319	2871	tmpccer \|= (uint16_t)(TIM_ICPolarity \| (uint16_t)TIM_CCER_CC4E);
mbed_official	52:a51c77007319	2872	}
mbed_official	52:a51c77007319	2873	/* Write to TIMx CCMR2 and CCER registers */
mbed_official	52:a51c77007319	2874	TIMx->CCMR2 = tmpccmr2;
mbed_official	52:a51c77007319	2875	TIMx->CCER = tmpccer;
mbed_official	52:a51c77007319	2876	}
mbed_official	52:a51c77007319	2877
mbed_official	52:a51c77007319	2878	/**
mbed_official	52:a51c77007319	2879	* @}
mbed_official	52:a51c77007319	2880	*/
mbed_official	52:a51c77007319	2881
mbed_official	52:a51c77007319	2882	/**
mbed_official	52:a51c77007319	2883	* @}
mbed_official	52:a51c77007319	2884	*/
mbed_official	52:a51c77007319	2885
mbed_official	52:a51c77007319	2886	/**
mbed_official	52:a51c77007319	2887	* @}
mbed_official	52:a51c77007319	2888	*/
mbed_official	52:a51c77007319	2889
mbed_official	52:a51c77007319	2890	/***************** (C) COPYRIGHT 2011 STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	05 Sep 2014
Imports:	4
Forks:	0
Commits:	309
Dependents:	0
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/stm32f10x_tim.c@52:a51c77007319, 2013-12-02 (annotated)

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