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targets/cmsis/TARGET_STM/TARGET_DISCO_F303VC/stm32f30x_tim.c@157:90e3acc479a2, 2014-04-11 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Apr 11 17:15:06 2014 +0100
- Revision:
- 157:90e3acc479a2
Synchronized with git revision 6e20ca17847dceb62132bf3d8519876411e175bf
Full URL: https://github.com/mbedmicro/mbed/commit/6e20ca17847dceb62132bf3d8519876411e175bf/
[STM32F3-Discovery][DISCO_F303VC] initial port.
Who changed what in which revision?
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mbed_official | 157:90e3acc479a2 | 1 | /** |
mbed_official | 157:90e3acc479a2 | 2 | ****************************************************************************** |
mbed_official | 157:90e3acc479a2 | 3 | * @file stm32f30x_tim.c |
mbed_official | 157:90e3acc479a2 | 4 | * @author MCD Application Team |
mbed_official | 157:90e3acc479a2 | 5 | * @version V1.1.0 |
mbed_official | 157:90e3acc479a2 | 6 | * @date 27-February-2014 |
mbed_official | 157:90e3acc479a2 | 7 | * @brief This file provides firmware functions to manage the following |
mbed_official | 157:90e3acc479a2 | 8 | * functionalities of the TIM peripheral: |
mbed_official | 157:90e3acc479a2 | 9 | * + TimeBase management |
mbed_official | 157:90e3acc479a2 | 10 | * + Output Compare management |
mbed_official | 157:90e3acc479a2 | 11 | * + Input Capture management |
mbed_official | 157:90e3acc479a2 | 12 | * + Advanced-control timers (TIM1 and TIM8) specific features |
mbed_official | 157:90e3acc479a2 | 13 | * + Interrupts, DMA and flags management |
mbed_official | 157:90e3acc479a2 | 14 | * + Clocks management |
mbed_official | 157:90e3acc479a2 | 15 | * + Synchronization management |
mbed_official | 157:90e3acc479a2 | 16 | * + Specific interface management |
mbed_official | 157:90e3acc479a2 | 17 | * + Specific remapping management |
mbed_official | 157:90e3acc479a2 | 18 | * |
mbed_official | 157:90e3acc479a2 | 19 | @verbatim |
mbed_official | 157:90e3acc479a2 | 20 | |
mbed_official | 157:90e3acc479a2 | 21 | ============================================================================== |
mbed_official | 157:90e3acc479a2 | 22 | ##### How to use this driver ##### |
mbed_official | 157:90e3acc479a2 | 23 | ============================================================================== |
mbed_official | 157:90e3acc479a2 | 24 | [..] This driver provides functions to configure and program the TIM |
mbed_official | 157:90e3acc479a2 | 25 | of all stm32f30x devices. |
mbed_official | 157:90e3acc479a2 | 26 | These functions are split in 9 groups: |
mbed_official | 157:90e3acc479a2 | 27 | |
mbed_official | 157:90e3acc479a2 | 28 | (#) TIM TimeBase management: this group includes all needed functions |
mbed_official | 157:90e3acc479a2 | 29 | to configure the TM Timebase unit: |
mbed_official | 157:90e3acc479a2 | 30 | (++) Set/Get Prescaler |
mbed_official | 157:90e3acc479a2 | 31 | (++) Set/Get Autoreload |
mbed_official | 157:90e3acc479a2 | 32 | (++) Counter modes configuration |
mbed_official | 157:90e3acc479a2 | 33 | (++) Set Clock division |
mbed_official | 157:90e3acc479a2 | 34 | (++) Select the One Pulse mode |
mbed_official | 157:90e3acc479a2 | 35 | (++) Update Request Configuration |
mbed_official | 157:90e3acc479a2 | 36 | (++) Update Disable Configuration |
mbed_official | 157:90e3acc479a2 | 37 | (++) Auto-Preload Configuration |
mbed_official | 157:90e3acc479a2 | 38 | (++) Enable/Disable the counter |
mbed_official | 157:90e3acc479a2 | 39 | |
mbed_official | 157:90e3acc479a2 | 40 | (#) TIM Output Compare management: this group includes all needed |
mbed_official | 157:90e3acc479a2 | 41 | functions to configure the Capture/Compare unit used in Output |
mbed_official | 157:90e3acc479a2 | 42 | compare mode: |
mbed_official | 157:90e3acc479a2 | 43 | (++) Configure each channel, independently, in Output Compare mode |
mbed_official | 157:90e3acc479a2 | 44 | (++) Select the output compare modes |
mbed_official | 157:90e3acc479a2 | 45 | (++) Select the Polarities of each channel |
mbed_official | 157:90e3acc479a2 | 46 | (++) Set/Get the Capture/Compare register values |
mbed_official | 157:90e3acc479a2 | 47 | (++) Select the Output Compare Fast mode |
mbed_official | 157:90e3acc479a2 | 48 | (++) Select the Output Compare Forced mode |
mbed_official | 157:90e3acc479a2 | 49 | (++) Output Compare-Preload Configuration |
mbed_official | 157:90e3acc479a2 | 50 | (++) Clear Output Compare Reference |
mbed_official | 157:90e3acc479a2 | 51 | (++) Select the OCREF Clear signal |
mbed_official | 157:90e3acc479a2 | 52 | (++) Enable/Disable the Capture/Compare Channels |
mbed_official | 157:90e3acc479a2 | 53 | |
mbed_official | 157:90e3acc479a2 | 54 | (#) TIM Input Capture management: this group includes all needed |
mbed_official | 157:90e3acc479a2 | 55 | functions to configure the Capture/Compare unit used in |
mbed_official | 157:90e3acc479a2 | 56 | Input Capture mode: |
mbed_official | 157:90e3acc479a2 | 57 | (++) Configure each channel in input capture mode |
mbed_official | 157:90e3acc479a2 | 58 | (++) Configure Channel1/2 in PWM Input mode |
mbed_official | 157:90e3acc479a2 | 59 | (++) Set the Input Capture Prescaler |
mbed_official | 157:90e3acc479a2 | 60 | (++) Get the Capture/Compare values |
mbed_official | 157:90e3acc479a2 | 61 | |
mbed_official | 157:90e3acc479a2 | 62 | (#) Advanced-control timers (TIM1 and TIM8) specific features |
mbed_official | 157:90e3acc479a2 | 63 | (++) Configures the Break input, dead time, Lock level, the OSSI, |
mbed_official | 157:90e3acc479a2 | 64 | the OSSR State and the AOE(automatic output enable) |
mbed_official | 157:90e3acc479a2 | 65 | (++) Enable/Disable the TIM peripheral Main Outputs |
mbed_official | 157:90e3acc479a2 | 66 | (++) Select the Commutation event |
mbed_official | 157:90e3acc479a2 | 67 | (++) Set/Reset the Capture Compare Preload Control bit |
mbed_official | 157:90e3acc479a2 | 68 | |
mbed_official | 157:90e3acc479a2 | 69 | (#) TIM interrupts, DMA and flags management |
mbed_official | 157:90e3acc479a2 | 70 | (++) Enable/Disable interrupt sources |
mbed_official | 157:90e3acc479a2 | 71 | (++) Get flags status |
mbed_official | 157:90e3acc479a2 | 72 | (++) Clear flags/ Pending bits |
mbed_official | 157:90e3acc479a2 | 73 | (++) Enable/Disable DMA requests |
mbed_official | 157:90e3acc479a2 | 74 | (++) Configure DMA burst mode |
mbed_official | 157:90e3acc479a2 | 75 | (++) Select CaptureCompare DMA request |
mbed_official | 157:90e3acc479a2 | 76 | |
mbed_official | 157:90e3acc479a2 | 77 | (#) TIM clocks management: this group includes all needed functions |
mbed_official | 157:90e3acc479a2 | 78 | to configure the clock controller unit: |
mbed_official | 157:90e3acc479a2 | 79 | (++) Select internal/External clock |
mbed_official | 157:90e3acc479a2 | 80 | (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx |
mbed_official | 157:90e3acc479a2 | 81 | |
mbed_official | 157:90e3acc479a2 | 82 | (#) TIM synchronization management: this group includes all needed |
mbed_official | 157:90e3acc479a2 | 83 | functions to configure the Synchronization unit: |
mbed_official | 157:90e3acc479a2 | 84 | (++) Select Input Trigger |
mbed_official | 157:90e3acc479a2 | 85 | (++) Select Output Trigger |
mbed_official | 157:90e3acc479a2 | 86 | (++) Select Master Slave Mode |
mbed_official | 157:90e3acc479a2 | 87 | (++) ETR Configuration when used as external trigger |
mbed_official | 157:90e3acc479a2 | 88 | |
mbed_official | 157:90e3acc479a2 | 89 | (#) TIM specific interface management, this group includes all |
mbed_official | 157:90e3acc479a2 | 90 | needed functions to use the specific TIM interface: |
mbed_official | 157:90e3acc479a2 | 91 | (++) Encoder Interface Configuration |
mbed_official | 157:90e3acc479a2 | 92 | (++) Select Hall Sensor |
mbed_official | 157:90e3acc479a2 | 93 | |
mbed_official | 157:90e3acc479a2 | 94 | (#) TIM specific remapping management includes the Remapping |
mbed_official | 157:90e3acc479a2 | 95 | configuration of specific timers |
mbed_official | 157:90e3acc479a2 | 96 | |
mbed_official | 157:90e3acc479a2 | 97 | @endverbatim |
mbed_official | 157:90e3acc479a2 | 98 | |
mbed_official | 157:90e3acc479a2 | 99 | ****************************************************************************** |
mbed_official | 157:90e3acc479a2 | 100 | * @attention |
mbed_official | 157:90e3acc479a2 | 101 | * |
mbed_official | 157:90e3acc479a2 | 102 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 157:90e3acc479a2 | 103 | * |
mbed_official | 157:90e3acc479a2 | 104 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 157:90e3acc479a2 | 105 | * are permitted provided that the following conditions are met: |
mbed_official | 157:90e3acc479a2 | 106 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 157:90e3acc479a2 | 107 | * this list of conditions and the following disclaimer. |
mbed_official | 157:90e3acc479a2 | 108 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 157:90e3acc479a2 | 109 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 157:90e3acc479a2 | 110 | * and/or other materials provided with the distribution. |
mbed_official | 157:90e3acc479a2 | 111 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 157:90e3acc479a2 | 112 | * may be used to endorse or promote products derived from this software |
mbed_official | 157:90e3acc479a2 | 113 | * without specific prior written permission. |
mbed_official | 157:90e3acc479a2 | 114 | * |
mbed_official | 157:90e3acc479a2 | 115 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 157:90e3acc479a2 | 116 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 157:90e3acc479a2 | 117 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 157:90e3acc479a2 | 118 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 157:90e3acc479a2 | 119 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 157:90e3acc479a2 | 120 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 157:90e3acc479a2 | 121 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 157:90e3acc479a2 | 122 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 157:90e3acc479a2 | 123 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 157:90e3acc479a2 | 124 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 157:90e3acc479a2 | 125 | * |
mbed_official | 157:90e3acc479a2 | 126 | ****************************************************************************** |
mbed_official | 157:90e3acc479a2 | 127 | */ |
mbed_official | 157:90e3acc479a2 | 128 | |
mbed_official | 157:90e3acc479a2 | 129 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 157:90e3acc479a2 | 130 | #include "stm32f30x_tim.h" |
mbed_official | 157:90e3acc479a2 | 131 | #include "stm32f30x_rcc.h" |
mbed_official | 157:90e3acc479a2 | 132 | |
mbed_official | 157:90e3acc479a2 | 133 | /** @addtogroup STM32F30x_StdPeriph_Driver |
mbed_official | 157:90e3acc479a2 | 134 | * @{ |
mbed_official | 157:90e3acc479a2 | 135 | */ |
mbed_official | 157:90e3acc479a2 | 136 | |
mbed_official | 157:90e3acc479a2 | 137 | /** @defgroup TIM |
mbed_official | 157:90e3acc479a2 | 138 | * @brief TIM driver modules |
mbed_official | 157:90e3acc479a2 | 139 | * @{ |
mbed_official | 157:90e3acc479a2 | 140 | */ |
mbed_official | 157:90e3acc479a2 | 141 | |
mbed_official | 157:90e3acc479a2 | 142 | /* Private typedef -----------------------------------------------------------*/ |
mbed_official | 157:90e3acc479a2 | 143 | /* Private define ------------------------------------------------------------*/ |
mbed_official | 157:90e3acc479a2 | 144 | |
mbed_official | 157:90e3acc479a2 | 145 | /* ---------------------- TIM registers bit mask ------------------------ */ |
mbed_official | 157:90e3acc479a2 | 146 | #define SMCR_ETR_MASK ((uint16_t)0x00FF) |
mbed_official | 157:90e3acc479a2 | 147 | #define CCMR_OFFSET ((uint16_t)0x0018) |
mbed_official | 157:90e3acc479a2 | 148 | #define CCER_CCE_SET ((uint16_t)0x0001) |
mbed_official | 157:90e3acc479a2 | 149 | #define CCER_CCNE_SET ((uint16_t)0x0004) |
mbed_official | 157:90e3acc479a2 | 150 | #define CCMR_OC13M_MASK ((uint32_t)0xFFFEFF8F) |
mbed_official | 157:90e3acc479a2 | 151 | #define CCMR_OC24M_MASK ((uint32_t)0xFEFF8FFF) |
mbed_official | 157:90e3acc479a2 | 152 | |
mbed_official | 157:90e3acc479a2 | 153 | /* Private macro -------------------------------------------------------------*/ |
mbed_official | 157:90e3acc479a2 | 154 | /* Private variables ---------------------------------------------------------*/ |
mbed_official | 157:90e3acc479a2 | 155 | /* Private function prototypes -----------------------------------------------*/ |
mbed_official | 157:90e3acc479a2 | 156 | static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, |
mbed_official | 157:90e3acc479a2 | 157 | uint16_t TIM_ICFilter); |
mbed_official | 157:90e3acc479a2 | 158 | static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, |
mbed_official | 157:90e3acc479a2 | 159 | uint16_t TIM_ICFilter); |
mbed_official | 157:90e3acc479a2 | 160 | static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, |
mbed_official | 157:90e3acc479a2 | 161 | uint16_t TIM_ICFilter); |
mbed_official | 157:90e3acc479a2 | 162 | static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, |
mbed_official | 157:90e3acc479a2 | 163 | uint16_t TIM_ICFilter); |
mbed_official | 157:90e3acc479a2 | 164 | |
mbed_official | 157:90e3acc479a2 | 165 | /* Private functions ---------------------------------------------------------*/ |
mbed_official | 157:90e3acc479a2 | 166 | |
mbed_official | 157:90e3acc479a2 | 167 | /** @defgroup TIM_Private_Functions |
mbed_official | 157:90e3acc479a2 | 168 | * @{ |
mbed_official | 157:90e3acc479a2 | 169 | */ |
mbed_official | 157:90e3acc479a2 | 170 | |
mbed_official | 157:90e3acc479a2 | 171 | /** @defgroup TIM_Group1 TimeBase management functions |
mbed_official | 157:90e3acc479a2 | 172 | * @brief TimeBase management functions |
mbed_official | 157:90e3acc479a2 | 173 | * |
mbed_official | 157:90e3acc479a2 | 174 | @verbatim |
mbed_official | 157:90e3acc479a2 | 175 | =============================================================================== |
mbed_official | 157:90e3acc479a2 | 176 | ##### TimeBase management functions ##### |
mbed_official | 157:90e3acc479a2 | 177 | =============================================================================== |
mbed_official | 157:90e3acc479a2 | 178 | |
mbed_official | 157:90e3acc479a2 | 179 | |
mbed_official | 157:90e3acc479a2 | 180 | *** TIM Driver: how to use it in Timing(Time base) Mode *** |
mbed_official | 157:90e3acc479a2 | 181 | ============================================================ |
mbed_official | 157:90e3acc479a2 | 182 | [..] |
mbed_official | 157:90e3acc479a2 | 183 | To use the Timer in Timing(Time base) mode, the following steps are mandatory: |
mbed_official | 157:90e3acc479a2 | 184 | |
mbed_official | 157:90e3acc479a2 | 185 | (#) Enable TIM clock using |
mbed_official | 157:90e3acc479a2 | 186 | RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function |
mbed_official | 157:90e3acc479a2 | 187 | (#) Fill the TIM_TimeBaseInitStruct with the desired parameters. |
mbed_official | 157:90e3acc479a2 | 188 | (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure |
mbed_official | 157:90e3acc479a2 | 189 | the Time Base unit |
mbed_official | 157:90e3acc479a2 | 190 | with the corresponding configuration |
mbed_official | 157:90e3acc479a2 | 191 | (#) Enable the NVIC if you need to generate the update interrupt. |
mbed_official | 157:90e3acc479a2 | 192 | (#) Enable the corresponding interrupt using the function |
mbed_official | 157:90e3acc479a2 | 193 | TIM_ITConfig(TIMx, TIM_IT_Update) |
mbed_official | 157:90e3acc479a2 | 194 | (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. |
mbed_official | 157:90e3acc479a2 | 195 | [..] |
mbed_official | 157:90e3acc479a2 | 196 | (@) All other functions can be used separately to modify, if needed, |
mbed_official | 157:90e3acc479a2 | 197 | a specific feature of the Timer. |
mbed_official | 157:90e3acc479a2 | 198 | |
mbed_official | 157:90e3acc479a2 | 199 | @endverbatim |
mbed_official | 157:90e3acc479a2 | 200 | * @{ |
mbed_official | 157:90e3acc479a2 | 201 | */ |
mbed_official | 157:90e3acc479a2 | 202 | |
mbed_official | 157:90e3acc479a2 | 203 | /** |
mbed_official | 157:90e3acc479a2 | 204 | * @brief Deinitializes the TIMx peripheral registers to their default reset values. |
mbed_official | 157:90e3acc479a2 | 205 | * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 206 | * @retval None |
mbed_official | 157:90e3acc479a2 | 207 | |
mbed_official | 157:90e3acc479a2 | 208 | */ |
mbed_official | 157:90e3acc479a2 | 209 | void TIM_DeInit(TIM_TypeDef* TIMx) |
mbed_official | 157:90e3acc479a2 | 210 | { |
mbed_official | 157:90e3acc479a2 | 211 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 212 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 213 | |
mbed_official | 157:90e3acc479a2 | 214 | if (TIMx == TIM1) |
mbed_official | 157:90e3acc479a2 | 215 | { |
mbed_official | 157:90e3acc479a2 | 216 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); |
mbed_official | 157:90e3acc479a2 | 217 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); |
mbed_official | 157:90e3acc479a2 | 218 | } |
mbed_official | 157:90e3acc479a2 | 219 | else if (TIMx == TIM2) |
mbed_official | 157:90e3acc479a2 | 220 | { |
mbed_official | 157:90e3acc479a2 | 221 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); |
mbed_official | 157:90e3acc479a2 | 222 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); |
mbed_official | 157:90e3acc479a2 | 223 | } |
mbed_official | 157:90e3acc479a2 | 224 | else if (TIMx == TIM3) |
mbed_official | 157:90e3acc479a2 | 225 | { |
mbed_official | 157:90e3acc479a2 | 226 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); |
mbed_official | 157:90e3acc479a2 | 227 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); |
mbed_official | 157:90e3acc479a2 | 228 | } |
mbed_official | 157:90e3acc479a2 | 229 | else if (TIMx == TIM4) |
mbed_official | 157:90e3acc479a2 | 230 | { |
mbed_official | 157:90e3acc479a2 | 231 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); |
mbed_official | 157:90e3acc479a2 | 232 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); |
mbed_official | 157:90e3acc479a2 | 233 | } |
mbed_official | 157:90e3acc479a2 | 234 | else if (TIMx == TIM6) |
mbed_official | 157:90e3acc479a2 | 235 | { |
mbed_official | 157:90e3acc479a2 | 236 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); |
mbed_official | 157:90e3acc479a2 | 237 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); |
mbed_official | 157:90e3acc479a2 | 238 | } |
mbed_official | 157:90e3acc479a2 | 239 | else if (TIMx == TIM7) |
mbed_official | 157:90e3acc479a2 | 240 | { |
mbed_official | 157:90e3acc479a2 | 241 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); |
mbed_official | 157:90e3acc479a2 | 242 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); |
mbed_official | 157:90e3acc479a2 | 243 | } |
mbed_official | 157:90e3acc479a2 | 244 | else if (TIMx == TIM8) |
mbed_official | 157:90e3acc479a2 | 245 | { |
mbed_official | 157:90e3acc479a2 | 246 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); |
mbed_official | 157:90e3acc479a2 | 247 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); |
mbed_official | 157:90e3acc479a2 | 248 | } |
mbed_official | 157:90e3acc479a2 | 249 | else if (TIMx == TIM15) |
mbed_official | 157:90e3acc479a2 | 250 | { |
mbed_official | 157:90e3acc479a2 | 251 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE); |
mbed_official | 157:90e3acc479a2 | 252 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE); |
mbed_official | 157:90e3acc479a2 | 253 | } |
mbed_official | 157:90e3acc479a2 | 254 | else if (TIMx == TIM16) |
mbed_official | 157:90e3acc479a2 | 255 | { |
mbed_official | 157:90e3acc479a2 | 256 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE); |
mbed_official | 157:90e3acc479a2 | 257 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE); |
mbed_official | 157:90e3acc479a2 | 258 | } |
mbed_official | 157:90e3acc479a2 | 259 | else |
mbed_official | 157:90e3acc479a2 | 260 | { |
mbed_official | 157:90e3acc479a2 | 261 | if (TIMx == TIM17) |
mbed_official | 157:90e3acc479a2 | 262 | { |
mbed_official | 157:90e3acc479a2 | 263 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE); |
mbed_official | 157:90e3acc479a2 | 264 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); |
mbed_official | 157:90e3acc479a2 | 265 | } |
mbed_official | 157:90e3acc479a2 | 266 | } |
mbed_official | 157:90e3acc479a2 | 267 | } |
mbed_official | 157:90e3acc479a2 | 268 | |
mbed_official | 157:90e3acc479a2 | 269 | /** |
mbed_official | 157:90e3acc479a2 | 270 | * @brief Initializes the TIMx Time Base Unit peripheral according to |
mbed_official | 157:90e3acc479a2 | 271 | * the specified parameters in the TIM_TimeBaseInitStruct. |
mbed_official | 157:90e3acc479a2 | 272 | * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 273 | * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure |
mbed_official | 157:90e3acc479a2 | 274 | * that contains the configuration information for the specified TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 275 | * @retval None |
mbed_official | 157:90e3acc479a2 | 276 | */ |
mbed_official | 157:90e3acc479a2 | 277 | void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) |
mbed_official | 157:90e3acc479a2 | 278 | { |
mbed_official | 157:90e3acc479a2 | 279 | uint16_t tmpcr1 = 0; |
mbed_official | 157:90e3acc479a2 | 280 | |
mbed_official | 157:90e3acc479a2 | 281 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 282 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 283 | assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); |
mbed_official | 157:90e3acc479a2 | 284 | assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); |
mbed_official | 157:90e3acc479a2 | 285 | |
mbed_official | 157:90e3acc479a2 | 286 | tmpcr1 = TIMx->CR1; |
mbed_official | 157:90e3acc479a2 | 287 | |
mbed_official | 157:90e3acc479a2 | 288 | if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || |
mbed_official | 157:90e3acc479a2 | 289 | (TIMx == TIM3)|| (TIMx == TIM4)) |
mbed_official | 157:90e3acc479a2 | 290 | { |
mbed_official | 157:90e3acc479a2 | 291 | /* Select the Counter Mode */ |
mbed_official | 157:90e3acc479a2 | 292 | tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS)); |
mbed_official | 157:90e3acc479a2 | 293 | tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; |
mbed_official | 157:90e3acc479a2 | 294 | } |
mbed_official | 157:90e3acc479a2 | 295 | |
mbed_official | 157:90e3acc479a2 | 296 | if((TIMx != TIM6) && (TIMx != TIM7)) |
mbed_official | 157:90e3acc479a2 | 297 | { |
mbed_official | 157:90e3acc479a2 | 298 | /* Set the clock division */ |
mbed_official | 157:90e3acc479a2 | 299 | tmpcr1 &= (uint16_t)(~TIM_CR1_CKD); |
mbed_official | 157:90e3acc479a2 | 300 | tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; |
mbed_official | 157:90e3acc479a2 | 301 | } |
mbed_official | 157:90e3acc479a2 | 302 | |
mbed_official | 157:90e3acc479a2 | 303 | TIMx->CR1 = tmpcr1; |
mbed_official | 157:90e3acc479a2 | 304 | |
mbed_official | 157:90e3acc479a2 | 305 | /* Set the Autoreload value */ |
mbed_official | 157:90e3acc479a2 | 306 | TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; |
mbed_official | 157:90e3acc479a2 | 307 | |
mbed_official | 157:90e3acc479a2 | 308 | /* Set the Prescaler value */ |
mbed_official | 157:90e3acc479a2 | 309 | TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; |
mbed_official | 157:90e3acc479a2 | 310 | |
mbed_official | 157:90e3acc479a2 | 311 | if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15) || |
mbed_official | 157:90e3acc479a2 | 312 | (TIMx == TIM16) || (TIMx == TIM17)) |
mbed_official | 157:90e3acc479a2 | 313 | { |
mbed_official | 157:90e3acc479a2 | 314 | /* Set the Repetition Counter value */ |
mbed_official | 157:90e3acc479a2 | 315 | TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; |
mbed_official | 157:90e3acc479a2 | 316 | } |
mbed_official | 157:90e3acc479a2 | 317 | |
mbed_official | 157:90e3acc479a2 | 318 | /* Generate an update event to reload the Prescaler |
mbed_official | 157:90e3acc479a2 | 319 | and the repetition counter(only for TIM1 and TIM8) value immediatly */ |
mbed_official | 157:90e3acc479a2 | 320 | TIMx->EGR = TIM_PSCReloadMode_Immediate; |
mbed_official | 157:90e3acc479a2 | 321 | } |
mbed_official | 157:90e3acc479a2 | 322 | |
mbed_official | 157:90e3acc479a2 | 323 | /** |
mbed_official | 157:90e3acc479a2 | 324 | * @brief Fills each TIM_TimeBaseInitStruct member with its default value. |
mbed_official | 157:90e3acc479a2 | 325 | * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef |
mbed_official | 157:90e3acc479a2 | 326 | * structure which will be initialized. |
mbed_official | 157:90e3acc479a2 | 327 | * @retval None |
mbed_official | 157:90e3acc479a2 | 328 | */ |
mbed_official | 157:90e3acc479a2 | 329 | void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) |
mbed_official | 157:90e3acc479a2 | 330 | { |
mbed_official | 157:90e3acc479a2 | 331 | /* Set the default configuration */ |
mbed_official | 157:90e3acc479a2 | 332 | TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF; |
mbed_official | 157:90e3acc479a2 | 333 | TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; |
mbed_official | 157:90e3acc479a2 | 334 | TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; |
mbed_official | 157:90e3acc479a2 | 335 | TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; |
mbed_official | 157:90e3acc479a2 | 336 | TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; |
mbed_official | 157:90e3acc479a2 | 337 | } |
mbed_official | 157:90e3acc479a2 | 338 | |
mbed_official | 157:90e3acc479a2 | 339 | /** |
mbed_official | 157:90e3acc479a2 | 340 | * @brief Configures the TIMx Prescaler. |
mbed_official | 157:90e3acc479a2 | 341 | * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 342 | * @param Prescaler: specifies the Prescaler Register value |
mbed_official | 157:90e3acc479a2 | 343 | * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode |
mbed_official | 157:90e3acc479a2 | 344 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 345 | * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. |
mbed_official | 157:90e3acc479a2 | 346 | * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly. |
mbed_official | 157:90e3acc479a2 | 347 | * @retval None |
mbed_official | 157:90e3acc479a2 | 348 | */ |
mbed_official | 157:90e3acc479a2 | 349 | void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) |
mbed_official | 157:90e3acc479a2 | 350 | { |
mbed_official | 157:90e3acc479a2 | 351 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 352 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 353 | assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); |
mbed_official | 157:90e3acc479a2 | 354 | /* Set the Prescaler value */ |
mbed_official | 157:90e3acc479a2 | 355 | TIMx->PSC = Prescaler; |
mbed_official | 157:90e3acc479a2 | 356 | /* Set or reset the UG Bit */ |
mbed_official | 157:90e3acc479a2 | 357 | TIMx->EGR = TIM_PSCReloadMode; |
mbed_official | 157:90e3acc479a2 | 358 | } |
mbed_official | 157:90e3acc479a2 | 359 | |
mbed_official | 157:90e3acc479a2 | 360 | /** |
mbed_official | 157:90e3acc479a2 | 361 | * @brief Specifies the TIMx Counter Mode to be used. |
mbed_official | 157:90e3acc479a2 | 362 | * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 363 | * @param TIM_CounterMode: specifies the Counter Mode to be used |
mbed_official | 157:90e3acc479a2 | 364 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 365 | * @arg TIM_CounterMode_Up: TIM Up Counting Mode |
mbed_official | 157:90e3acc479a2 | 366 | * @arg TIM_CounterMode_Down: TIM Down Counting Mode |
mbed_official | 157:90e3acc479a2 | 367 | * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 |
mbed_official | 157:90e3acc479a2 | 368 | * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 |
mbed_official | 157:90e3acc479a2 | 369 | * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 |
mbed_official | 157:90e3acc479a2 | 370 | * @retval None |
mbed_official | 157:90e3acc479a2 | 371 | */ |
mbed_official | 157:90e3acc479a2 | 372 | void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) |
mbed_official | 157:90e3acc479a2 | 373 | { |
mbed_official | 157:90e3acc479a2 | 374 | uint16_t tmpcr1 = 0; |
mbed_official | 157:90e3acc479a2 | 375 | |
mbed_official | 157:90e3acc479a2 | 376 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 377 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 378 | assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); |
mbed_official | 157:90e3acc479a2 | 379 | |
mbed_official | 157:90e3acc479a2 | 380 | tmpcr1 = TIMx->CR1; |
mbed_official | 157:90e3acc479a2 | 381 | |
mbed_official | 157:90e3acc479a2 | 382 | /* Reset the CMS and DIR Bits */ |
mbed_official | 157:90e3acc479a2 | 383 | tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS); |
mbed_official | 157:90e3acc479a2 | 384 | |
mbed_official | 157:90e3acc479a2 | 385 | /* Set the Counter Mode */ |
mbed_official | 157:90e3acc479a2 | 386 | tmpcr1 |= TIM_CounterMode; |
mbed_official | 157:90e3acc479a2 | 387 | |
mbed_official | 157:90e3acc479a2 | 388 | /* Write to TIMx CR1 register */ |
mbed_official | 157:90e3acc479a2 | 389 | TIMx->CR1 = tmpcr1; |
mbed_official | 157:90e3acc479a2 | 390 | } |
mbed_official | 157:90e3acc479a2 | 391 | |
mbed_official | 157:90e3acc479a2 | 392 | /** |
mbed_official | 157:90e3acc479a2 | 393 | * @brief Sets the TIMx Counter Register value |
mbed_official | 157:90e3acc479a2 | 394 | * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 395 | * @param Counter: specifies the Counter register new value. |
mbed_official | 157:90e3acc479a2 | 396 | * @retval None |
mbed_official | 157:90e3acc479a2 | 397 | */ |
mbed_official | 157:90e3acc479a2 | 398 | void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) |
mbed_official | 157:90e3acc479a2 | 399 | { |
mbed_official | 157:90e3acc479a2 | 400 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 401 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 402 | |
mbed_official | 157:90e3acc479a2 | 403 | /* Set the Counter Register value */ |
mbed_official | 157:90e3acc479a2 | 404 | TIMx->CNT = Counter; |
mbed_official | 157:90e3acc479a2 | 405 | } |
mbed_official | 157:90e3acc479a2 | 406 | |
mbed_official | 157:90e3acc479a2 | 407 | /** |
mbed_official | 157:90e3acc479a2 | 408 | * @brief Sets the TIMx Autoreload Register value |
mbed_official | 157:90e3acc479a2 | 409 | * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 410 | * @param Autoreload: specifies the Autoreload register new value. |
mbed_official | 157:90e3acc479a2 | 411 | * @retval None |
mbed_official | 157:90e3acc479a2 | 412 | */ |
mbed_official | 157:90e3acc479a2 | 413 | void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload) |
mbed_official | 157:90e3acc479a2 | 414 | { |
mbed_official | 157:90e3acc479a2 | 415 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 416 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 417 | |
mbed_official | 157:90e3acc479a2 | 418 | /* Set the Autoreload Register value */ |
mbed_official | 157:90e3acc479a2 | 419 | TIMx->ARR = Autoreload; |
mbed_official | 157:90e3acc479a2 | 420 | } |
mbed_official | 157:90e3acc479a2 | 421 | |
mbed_official | 157:90e3acc479a2 | 422 | /** |
mbed_official | 157:90e3acc479a2 | 423 | * @brief Gets the TIMx Counter value. |
mbed_official | 157:90e3acc479a2 | 424 | * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 425 | * @retval Counter Register value |
mbed_official | 157:90e3acc479a2 | 426 | */ |
mbed_official | 157:90e3acc479a2 | 427 | uint32_t TIM_GetCounter(TIM_TypeDef* TIMx) |
mbed_official | 157:90e3acc479a2 | 428 | { |
mbed_official | 157:90e3acc479a2 | 429 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 430 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 431 | |
mbed_official | 157:90e3acc479a2 | 432 | /* Get the Counter Register value */ |
mbed_official | 157:90e3acc479a2 | 433 | return TIMx->CNT; |
mbed_official | 157:90e3acc479a2 | 434 | } |
mbed_official | 157:90e3acc479a2 | 435 | |
mbed_official | 157:90e3acc479a2 | 436 | /** |
mbed_official | 157:90e3acc479a2 | 437 | * @brief Gets the TIMx Prescaler value. |
mbed_official | 157:90e3acc479a2 | 438 | * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 439 | * @retval Prescaler Register value. |
mbed_official | 157:90e3acc479a2 | 440 | */ |
mbed_official | 157:90e3acc479a2 | 441 | uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) |
mbed_official | 157:90e3acc479a2 | 442 | { |
mbed_official | 157:90e3acc479a2 | 443 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 444 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 445 | |
mbed_official | 157:90e3acc479a2 | 446 | /* Get the Prescaler Register value */ |
mbed_official | 157:90e3acc479a2 | 447 | return TIMx->PSC; |
mbed_official | 157:90e3acc479a2 | 448 | } |
mbed_official | 157:90e3acc479a2 | 449 | |
mbed_official | 157:90e3acc479a2 | 450 | /** |
mbed_official | 157:90e3acc479a2 | 451 | * @brief Enables or Disables the TIMx Update event. |
mbed_official | 157:90e3acc479a2 | 452 | * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 453 | * @param NewState: new state of the TIMx UDIS bit |
mbed_official | 157:90e3acc479a2 | 454 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 157:90e3acc479a2 | 455 | * @retval None |
mbed_official | 157:90e3acc479a2 | 456 | */ |
mbed_official | 157:90e3acc479a2 | 457 | void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) |
mbed_official | 157:90e3acc479a2 | 458 | { |
mbed_official | 157:90e3acc479a2 | 459 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 460 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 461 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 157:90e3acc479a2 | 462 | |
mbed_official | 157:90e3acc479a2 | 463 | if (NewState != DISABLE) |
mbed_official | 157:90e3acc479a2 | 464 | { |
mbed_official | 157:90e3acc479a2 | 465 | /* Set the Update Disable Bit */ |
mbed_official | 157:90e3acc479a2 | 466 | TIMx->CR1 |= TIM_CR1_UDIS; |
mbed_official | 157:90e3acc479a2 | 467 | } |
mbed_official | 157:90e3acc479a2 | 468 | else |
mbed_official | 157:90e3acc479a2 | 469 | { |
mbed_official | 157:90e3acc479a2 | 470 | /* Reset the Update Disable Bit */ |
mbed_official | 157:90e3acc479a2 | 471 | TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS; |
mbed_official | 157:90e3acc479a2 | 472 | } |
mbed_official | 157:90e3acc479a2 | 473 | } |
mbed_official | 157:90e3acc479a2 | 474 | |
mbed_official | 157:90e3acc479a2 | 475 | /** |
mbed_official | 157:90e3acc479a2 | 476 | * @brief Configures the TIMx Update Request Interrupt source. |
mbed_official | 157:90e3acc479a2 | 477 | * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 478 | * @param TIM_UpdateSource: specifies the Update source. |
mbed_official | 157:90e3acc479a2 | 479 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 480 | * @arg TIM_UpdateSource_Regular: Source of update is the counter |
mbed_official | 157:90e3acc479a2 | 481 | * overflow/underflow or the setting of UG bit, or an update |
mbed_official | 157:90e3acc479a2 | 482 | * generation through the slave mode controller. |
mbed_official | 157:90e3acc479a2 | 483 | * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. |
mbed_official | 157:90e3acc479a2 | 484 | * @retval None |
mbed_official | 157:90e3acc479a2 | 485 | */ |
mbed_official | 157:90e3acc479a2 | 486 | void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) |
mbed_official | 157:90e3acc479a2 | 487 | { |
mbed_official | 157:90e3acc479a2 | 488 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 489 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 490 | assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); |
mbed_official | 157:90e3acc479a2 | 491 | |
mbed_official | 157:90e3acc479a2 | 492 | if (TIM_UpdateSource != TIM_UpdateSource_Global) |
mbed_official | 157:90e3acc479a2 | 493 | { |
mbed_official | 157:90e3acc479a2 | 494 | /* Set the URS Bit */ |
mbed_official | 157:90e3acc479a2 | 495 | TIMx->CR1 |= TIM_CR1_URS; |
mbed_official | 157:90e3acc479a2 | 496 | } |
mbed_official | 157:90e3acc479a2 | 497 | else |
mbed_official | 157:90e3acc479a2 | 498 | { |
mbed_official | 157:90e3acc479a2 | 499 | /* Reset the URS Bit */ |
mbed_official | 157:90e3acc479a2 | 500 | TIMx->CR1 &= (uint16_t)~TIM_CR1_URS; |
mbed_official | 157:90e3acc479a2 | 501 | } |
mbed_official | 157:90e3acc479a2 | 502 | } |
mbed_official | 157:90e3acc479a2 | 503 | |
mbed_official | 157:90e3acc479a2 | 504 | /** |
mbed_official | 157:90e3acc479a2 | 505 | * @brief Sets or resets the update interrupt flag (UIF)status bit Remapping. |
mbed_official | 157:90e3acc479a2 | 506 | * when sets, reading TIMx_CNT register returns UIF bit instead of CNT[31] |
mbed_official | 157:90e3acc479a2 | 507 | * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 508 | * @param NewState: new state of the UIFREMAP bit. |
mbed_official | 157:90e3acc479a2 | 509 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 157:90e3acc479a2 | 510 | * @retval None |
mbed_official | 157:90e3acc479a2 | 511 | */ |
mbed_official | 157:90e3acc479a2 | 512 | void TIM_UIFRemap(TIM_TypeDef* TIMx, FunctionalState NewState) |
mbed_official | 157:90e3acc479a2 | 513 | { |
mbed_official | 157:90e3acc479a2 | 514 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 515 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 516 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 157:90e3acc479a2 | 517 | |
mbed_official | 157:90e3acc479a2 | 518 | if (NewState != DISABLE) |
mbed_official | 157:90e3acc479a2 | 519 | { |
mbed_official | 157:90e3acc479a2 | 520 | /* Enable the TIM Counter */ |
mbed_official | 157:90e3acc479a2 | 521 | TIMx->CR1 |= TIM_CR1_UIFREMAP; |
mbed_official | 157:90e3acc479a2 | 522 | } |
mbed_official | 157:90e3acc479a2 | 523 | else |
mbed_official | 157:90e3acc479a2 | 524 | { |
mbed_official | 157:90e3acc479a2 | 525 | /* Disable the TIM Counter */ |
mbed_official | 157:90e3acc479a2 | 526 | TIMx->CR1 &= (uint16_t)~TIM_CR1_UIFREMAP; |
mbed_official | 157:90e3acc479a2 | 527 | } |
mbed_official | 157:90e3acc479a2 | 528 | } |
mbed_official | 157:90e3acc479a2 | 529 | |
mbed_official | 157:90e3acc479a2 | 530 | /** |
mbed_official | 157:90e3acc479a2 | 531 | * @brief Enables or disables TIMx peripheral Preload register on ARR. |
mbed_official | 157:90e3acc479a2 | 532 | * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 533 | * @param NewState: new state of the TIMx peripheral Preload register |
mbed_official | 157:90e3acc479a2 | 534 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 157:90e3acc479a2 | 535 | * @retval None |
mbed_official | 157:90e3acc479a2 | 536 | */ |
mbed_official | 157:90e3acc479a2 | 537 | void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) |
mbed_official | 157:90e3acc479a2 | 538 | { |
mbed_official | 157:90e3acc479a2 | 539 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 540 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 541 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 157:90e3acc479a2 | 542 | |
mbed_official | 157:90e3acc479a2 | 543 | if (NewState != DISABLE) |
mbed_official | 157:90e3acc479a2 | 544 | { |
mbed_official | 157:90e3acc479a2 | 545 | /* Set the ARR Preload Bit */ |
mbed_official | 157:90e3acc479a2 | 546 | TIMx->CR1 |= TIM_CR1_ARPE; |
mbed_official | 157:90e3acc479a2 | 547 | } |
mbed_official | 157:90e3acc479a2 | 548 | else |
mbed_official | 157:90e3acc479a2 | 549 | { |
mbed_official | 157:90e3acc479a2 | 550 | /* Reset the ARR Preload Bit */ |
mbed_official | 157:90e3acc479a2 | 551 | TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE; |
mbed_official | 157:90e3acc479a2 | 552 | } |
mbed_official | 157:90e3acc479a2 | 553 | } |
mbed_official | 157:90e3acc479a2 | 554 | |
mbed_official | 157:90e3acc479a2 | 555 | /** |
mbed_official | 157:90e3acc479a2 | 556 | * @brief Selects the TIMx's One Pulse Mode. |
mbed_official | 157:90e3acc479a2 | 557 | * @param TIMx: where x can be 1, 2, 3, 4, 6 ,7 ,8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 558 | * @param TIM_OPMode: specifies the OPM Mode to be used. |
mbed_official | 157:90e3acc479a2 | 559 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 560 | * @arg TIM_OPMode_Single |
mbed_official | 157:90e3acc479a2 | 561 | * @arg TIM_OPMode_Repetitive |
mbed_official | 157:90e3acc479a2 | 562 | * @retval None |
mbed_official | 157:90e3acc479a2 | 563 | */ |
mbed_official | 157:90e3acc479a2 | 564 | void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) |
mbed_official | 157:90e3acc479a2 | 565 | { |
mbed_official | 157:90e3acc479a2 | 566 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 567 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 568 | assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); |
mbed_official | 157:90e3acc479a2 | 569 | |
mbed_official | 157:90e3acc479a2 | 570 | /* Reset the OPM Bit */ |
mbed_official | 157:90e3acc479a2 | 571 | TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM; |
mbed_official | 157:90e3acc479a2 | 572 | |
mbed_official | 157:90e3acc479a2 | 573 | /* Configure the OPM Mode */ |
mbed_official | 157:90e3acc479a2 | 574 | TIMx->CR1 |= TIM_OPMode; |
mbed_official | 157:90e3acc479a2 | 575 | } |
mbed_official | 157:90e3acc479a2 | 576 | |
mbed_official | 157:90e3acc479a2 | 577 | /** |
mbed_official | 157:90e3acc479a2 | 578 | * @brief Sets the TIMx Clock Division value. |
mbed_official | 157:90e3acc479a2 | 579 | * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17, to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 580 | * @param TIM_CKD: specifies the clock division value. |
mbed_official | 157:90e3acc479a2 | 581 | * This parameter can be one of the following value: |
mbed_official | 157:90e3acc479a2 | 582 | * @arg TIM_CKD_DIV1: TDTS = Tck_tim |
mbed_official | 157:90e3acc479a2 | 583 | * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim |
mbed_official | 157:90e3acc479a2 | 584 | * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim |
mbed_official | 157:90e3acc479a2 | 585 | * @retval None |
mbed_official | 157:90e3acc479a2 | 586 | */ |
mbed_official | 157:90e3acc479a2 | 587 | void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) |
mbed_official | 157:90e3acc479a2 | 588 | { |
mbed_official | 157:90e3acc479a2 | 589 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 590 | assert_param(IS_TIM_LIST1_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 591 | assert_param(IS_TIM_CKD_DIV(TIM_CKD)); |
mbed_official | 157:90e3acc479a2 | 592 | |
mbed_official | 157:90e3acc479a2 | 593 | /* Reset the CKD Bits */ |
mbed_official | 157:90e3acc479a2 | 594 | TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD); |
mbed_official | 157:90e3acc479a2 | 595 | |
mbed_official | 157:90e3acc479a2 | 596 | /* Set the CKD value */ |
mbed_official | 157:90e3acc479a2 | 597 | TIMx->CR1 |= TIM_CKD; |
mbed_official | 157:90e3acc479a2 | 598 | } |
mbed_official | 157:90e3acc479a2 | 599 | |
mbed_official | 157:90e3acc479a2 | 600 | /** |
mbed_official | 157:90e3acc479a2 | 601 | * @brief Enables or disables the specified TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 602 | * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select |
mbed_official | 157:90e3acc479a2 | 603 | * the TIMx peripheral. |
mbed_official | 157:90e3acc479a2 | 604 | * @param NewState: new state of the TIMx peripheral. |
mbed_official | 157:90e3acc479a2 | 605 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 157:90e3acc479a2 | 606 | * @retval None |
mbed_official | 157:90e3acc479a2 | 607 | */ |
mbed_official | 157:90e3acc479a2 | 608 | void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) |
mbed_official | 157:90e3acc479a2 | 609 | { |
mbed_official | 157:90e3acc479a2 | 610 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 611 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 612 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 157:90e3acc479a2 | 613 | |
mbed_official | 157:90e3acc479a2 | 614 | if (NewState != DISABLE) |
mbed_official | 157:90e3acc479a2 | 615 | { |
mbed_official | 157:90e3acc479a2 | 616 | /* Enable the TIM Counter */ |
mbed_official | 157:90e3acc479a2 | 617 | TIMx->CR1 |= TIM_CR1_CEN; |
mbed_official | 157:90e3acc479a2 | 618 | } |
mbed_official | 157:90e3acc479a2 | 619 | else |
mbed_official | 157:90e3acc479a2 | 620 | { |
mbed_official | 157:90e3acc479a2 | 621 | /* Disable the TIM Counter */ |
mbed_official | 157:90e3acc479a2 | 622 | TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN; |
mbed_official | 157:90e3acc479a2 | 623 | } |
mbed_official | 157:90e3acc479a2 | 624 | } |
mbed_official | 157:90e3acc479a2 | 625 | /** |
mbed_official | 157:90e3acc479a2 | 626 | * @} |
mbed_official | 157:90e3acc479a2 | 627 | */ |
mbed_official | 157:90e3acc479a2 | 628 | |
mbed_official | 157:90e3acc479a2 | 629 | /** @defgroup TIM_Group2 Output Compare management functions |
mbed_official | 157:90e3acc479a2 | 630 | * @brief Output Compare management functions |
mbed_official | 157:90e3acc479a2 | 631 | * |
mbed_official | 157:90e3acc479a2 | 632 | @verbatim |
mbed_official | 157:90e3acc479a2 | 633 | =============================================================================== |
mbed_official | 157:90e3acc479a2 | 634 | ##### Output Compare management functions ##### |
mbed_official | 157:90e3acc479a2 | 635 | =============================================================================== |
mbed_official | 157:90e3acc479a2 | 636 | |
mbed_official | 157:90e3acc479a2 | 637 | *** TIM Driver: how to use it in Output Compare Mode *** |
mbed_official | 157:90e3acc479a2 | 638 | ======================================================== |
mbed_official | 157:90e3acc479a2 | 639 | [..] |
mbed_official | 157:90e3acc479a2 | 640 | To use the Timer in Output Compare mode, the following steps are mandatory: |
mbed_official | 157:90e3acc479a2 | 641 | |
mbed_official | 157:90e3acc479a2 | 642 | (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function |
mbed_official | 157:90e3acc479a2 | 643 | |
mbed_official | 157:90e3acc479a2 | 644 | (#) Configure the TIM pins by configuring the corresponding GPIO pins |
mbed_official | 157:90e3acc479a2 | 645 | |
mbed_official | 157:90e3acc479a2 | 646 | (#) Configure the Time base unit as described in the first part of this driver, |
mbed_official | 157:90e3acc479a2 | 647 | if needed, else the Timer will run with the default configuration: |
mbed_official | 157:90e3acc479a2 | 648 | (++) Autoreload value = 0xFFFF |
mbed_official | 157:90e3acc479a2 | 649 | (++) Prescaler value = 0x0000 |
mbed_official | 157:90e3acc479a2 | 650 | (++) Counter mode = Up counting |
mbed_official | 157:90e3acc479a2 | 651 | (++) Clock Division = TIM_CKD_DIV1 |
mbed_official | 157:90e3acc479a2 | 652 | (#) Fill the TIM_OCInitStruct with the desired parameters including: |
mbed_official | 157:90e3acc479a2 | 653 | (++) The TIM Output Compare mode: TIM_OCMode |
mbed_official | 157:90e3acc479a2 | 654 | (++) TIM Output State: TIM_OutputState |
mbed_official | 157:90e3acc479a2 | 655 | (++) TIM Pulse value: TIM_Pulse |
mbed_official | 157:90e3acc479a2 | 656 | (++) TIM Output Compare Polarity : TIM_OCPolarity |
mbed_official | 157:90e3acc479a2 | 657 | |
mbed_official | 157:90e3acc479a2 | 658 | (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the |
mbed_official | 157:90e3acc479a2 | 659 | corresponding configuration |
mbed_official | 157:90e3acc479a2 | 660 | |
mbed_official | 157:90e3acc479a2 | 661 | (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. |
mbed_official | 157:90e3acc479a2 | 662 | [..] |
mbed_official | 157:90e3acc479a2 | 663 | (@) All other functions can be used separately to modify, if needed, |
mbed_official | 157:90e3acc479a2 | 664 | a specific feature of the Timer. |
mbed_official | 157:90e3acc479a2 | 665 | |
mbed_official | 157:90e3acc479a2 | 666 | (@) In case of PWM mode, this function is mandatory: |
mbed_official | 157:90e3acc479a2 | 667 | TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); |
mbed_official | 157:90e3acc479a2 | 668 | |
mbed_official | 157:90e3acc479a2 | 669 | (@) If the corresponding interrupt or DMA request are needed, the user should: |
mbed_official | 157:90e3acc479a2 | 670 | (#@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). |
mbed_official | 157:90e3acc479a2 | 671 | (#@) Enable the corresponding interrupt (or DMA request) using the function |
mbed_official | 157:90e3acc479a2 | 672 | TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) |
mbed_official | 157:90e3acc479a2 | 673 | |
mbed_official | 157:90e3acc479a2 | 674 | @endverbatim |
mbed_official | 157:90e3acc479a2 | 675 | * @{ |
mbed_official | 157:90e3acc479a2 | 676 | */ |
mbed_official | 157:90e3acc479a2 | 677 | |
mbed_official | 157:90e3acc479a2 | 678 | /** |
mbed_official | 157:90e3acc479a2 | 679 | * @brief Initializes the TIMx Channel1 according to the specified parameters in |
mbed_official | 157:90e3acc479a2 | 680 | * the TIM_OCInitStruct. |
mbed_official | 157:90e3acc479a2 | 681 | * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17, to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 682 | * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains |
mbed_official | 157:90e3acc479a2 | 683 | * the configuration information for the specified TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 684 | * @retval None |
mbed_official | 157:90e3acc479a2 | 685 | */ |
mbed_official | 157:90e3acc479a2 | 686 | void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) |
mbed_official | 157:90e3acc479a2 | 687 | { |
mbed_official | 157:90e3acc479a2 | 688 | uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; |
mbed_official | 157:90e3acc479a2 | 689 | |
mbed_official | 157:90e3acc479a2 | 690 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 691 | assert_param(IS_TIM_LIST1_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 692 | assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); |
mbed_official | 157:90e3acc479a2 | 693 | assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); |
mbed_official | 157:90e3acc479a2 | 694 | assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); |
mbed_official | 157:90e3acc479a2 | 695 | |
mbed_official | 157:90e3acc479a2 | 696 | /* Disable the Channel 1: Reset the CC1E Bit */ |
mbed_official | 157:90e3acc479a2 | 697 | TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; |
mbed_official | 157:90e3acc479a2 | 698 | |
mbed_official | 157:90e3acc479a2 | 699 | /* Get the TIMx CCER register value */ |
mbed_official | 157:90e3acc479a2 | 700 | tmpccer = TIMx->CCER; |
mbed_official | 157:90e3acc479a2 | 701 | /* Get the TIMx CR2 register value */ |
mbed_official | 157:90e3acc479a2 | 702 | tmpcr2 = TIMx->CR2; |
mbed_official | 157:90e3acc479a2 | 703 | |
mbed_official | 157:90e3acc479a2 | 704 | /* Get the TIMx CCMR1 register value */ |
mbed_official | 157:90e3acc479a2 | 705 | tmpccmrx = TIMx->CCMR1; |
mbed_official | 157:90e3acc479a2 | 706 | |
mbed_official | 157:90e3acc479a2 | 707 | /* Reset the Output Compare Mode Bits */ |
mbed_official | 157:90e3acc479a2 | 708 | tmpccmrx &= (uint32_t)~TIM_CCMR1_OC1M; |
mbed_official | 157:90e3acc479a2 | 709 | tmpccmrx &= (uint32_t)~TIM_CCMR1_CC1S; |
mbed_official | 157:90e3acc479a2 | 710 | /* Select the Output Compare Mode */ |
mbed_official | 157:90e3acc479a2 | 711 | tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; |
mbed_official | 157:90e3acc479a2 | 712 | |
mbed_official | 157:90e3acc479a2 | 713 | /* Reset the Output Polarity level */ |
mbed_official | 157:90e3acc479a2 | 714 | tmpccer &= (uint32_t)~TIM_CCER_CC1P; |
mbed_official | 157:90e3acc479a2 | 715 | /* Set the Output Compare Polarity */ |
mbed_official | 157:90e3acc479a2 | 716 | tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; |
mbed_official | 157:90e3acc479a2 | 717 | |
mbed_official | 157:90e3acc479a2 | 718 | /* Set the Output State */ |
mbed_official | 157:90e3acc479a2 | 719 | tmpccer |= TIM_OCInitStruct->TIM_OutputState; |
mbed_official | 157:90e3acc479a2 | 720 | |
mbed_official | 157:90e3acc479a2 | 721 | if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM15) || (TIMx == TIM16) || (TIMx == TIM17)) |
mbed_official | 157:90e3acc479a2 | 722 | { |
mbed_official | 157:90e3acc479a2 | 723 | assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); |
mbed_official | 157:90e3acc479a2 | 724 | assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); |
mbed_official | 157:90e3acc479a2 | 725 | assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); |
mbed_official | 157:90e3acc479a2 | 726 | assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); |
mbed_official | 157:90e3acc479a2 | 727 | |
mbed_official | 157:90e3acc479a2 | 728 | /* Reset the Output N Polarity level */ |
mbed_official | 157:90e3acc479a2 | 729 | tmpccer &= (uint32_t)~TIM_CCER_CC1NP; |
mbed_official | 157:90e3acc479a2 | 730 | /* Set the Output N Polarity */ |
mbed_official | 157:90e3acc479a2 | 731 | tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; |
mbed_official | 157:90e3acc479a2 | 732 | /* Reset the Output N State */ |
mbed_official | 157:90e3acc479a2 | 733 | tmpccer &= (uint32_t)~TIM_CCER_CC1NE; |
mbed_official | 157:90e3acc479a2 | 734 | |
mbed_official | 157:90e3acc479a2 | 735 | /* Set the Output N State */ |
mbed_official | 157:90e3acc479a2 | 736 | tmpccer |= TIM_OCInitStruct->TIM_OutputNState; |
mbed_official | 157:90e3acc479a2 | 737 | /* Reset the Output Compare and Output Compare N IDLE State */ |
mbed_official | 157:90e3acc479a2 | 738 | tmpcr2 &= (uint32_t)~TIM_CR2_OIS1; |
mbed_official | 157:90e3acc479a2 | 739 | tmpcr2 &= (uint32_t)~TIM_CR2_OIS1N; |
mbed_official | 157:90e3acc479a2 | 740 | /* Set the Output Idle state */ |
mbed_official | 157:90e3acc479a2 | 741 | tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; |
mbed_official | 157:90e3acc479a2 | 742 | /* Set the Output N Idle state */ |
mbed_official | 157:90e3acc479a2 | 743 | tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; |
mbed_official | 157:90e3acc479a2 | 744 | } |
mbed_official | 157:90e3acc479a2 | 745 | /* Write to TIMx CR2 */ |
mbed_official | 157:90e3acc479a2 | 746 | TIMx->CR2 = tmpcr2; |
mbed_official | 157:90e3acc479a2 | 747 | |
mbed_official | 157:90e3acc479a2 | 748 | /* Write to TIMx CCMR1 */ |
mbed_official | 157:90e3acc479a2 | 749 | TIMx->CCMR1 = tmpccmrx; |
mbed_official | 157:90e3acc479a2 | 750 | |
mbed_official | 157:90e3acc479a2 | 751 | /* Set the Capture Compare Register value */ |
mbed_official | 157:90e3acc479a2 | 752 | TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; |
mbed_official | 157:90e3acc479a2 | 753 | |
mbed_official | 157:90e3acc479a2 | 754 | /* Write to TIMx CCER */ |
mbed_official | 157:90e3acc479a2 | 755 | TIMx->CCER = tmpccer; |
mbed_official | 157:90e3acc479a2 | 756 | } |
mbed_official | 157:90e3acc479a2 | 757 | |
mbed_official | 157:90e3acc479a2 | 758 | /** |
mbed_official | 157:90e3acc479a2 | 759 | * @brief Initializes the TIMx Channel2 according to the specified parameters |
mbed_official | 157:90e3acc479a2 | 760 | * in the TIM_OCInitStruct. |
mbed_official | 157:90e3acc479a2 | 761 | * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 762 | * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains |
mbed_official | 157:90e3acc479a2 | 763 | * the configuration information for the specified TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 764 | * @retval None |
mbed_official | 157:90e3acc479a2 | 765 | */ |
mbed_official | 157:90e3acc479a2 | 766 | void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) |
mbed_official | 157:90e3acc479a2 | 767 | { |
mbed_official | 157:90e3acc479a2 | 768 | uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; |
mbed_official | 157:90e3acc479a2 | 769 | |
mbed_official | 157:90e3acc479a2 | 770 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 771 | assert_param(IS_TIM_LIST2_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 772 | assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); |
mbed_official | 157:90e3acc479a2 | 773 | assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); |
mbed_official | 157:90e3acc479a2 | 774 | assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); |
mbed_official | 157:90e3acc479a2 | 775 | |
mbed_official | 157:90e3acc479a2 | 776 | /* Disable the Channel 2: Reset the CC2E Bit */ |
mbed_official | 157:90e3acc479a2 | 777 | TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; |
mbed_official | 157:90e3acc479a2 | 778 | |
mbed_official | 157:90e3acc479a2 | 779 | /* Get the TIMx CCER register value */ |
mbed_official | 157:90e3acc479a2 | 780 | tmpccer = TIMx->CCER; |
mbed_official | 157:90e3acc479a2 | 781 | /* Get the TIMx CR2 register value */ |
mbed_official | 157:90e3acc479a2 | 782 | tmpcr2 = TIMx->CR2; |
mbed_official | 157:90e3acc479a2 | 783 | |
mbed_official | 157:90e3acc479a2 | 784 | /* Get the TIMx CCMR1 register value */ |
mbed_official | 157:90e3acc479a2 | 785 | tmpccmrx = TIMx->CCMR1; |
mbed_official | 157:90e3acc479a2 | 786 | |
mbed_official | 157:90e3acc479a2 | 787 | /* Reset the Output Compare mode and Capture/Compare selection Bits */ |
mbed_official | 157:90e3acc479a2 | 788 | tmpccmrx &= (uint32_t)~TIM_CCMR1_OC2M; |
mbed_official | 157:90e3acc479a2 | 789 | tmpccmrx &= (uint32_t)~TIM_CCMR1_CC2S; |
mbed_official | 157:90e3acc479a2 | 790 | |
mbed_official | 157:90e3acc479a2 | 791 | /* Select the Output Compare Mode */ |
mbed_official | 157:90e3acc479a2 | 792 | tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8); |
mbed_official | 157:90e3acc479a2 | 793 | |
mbed_official | 157:90e3acc479a2 | 794 | /* Reset the Output Polarity level */ |
mbed_official | 157:90e3acc479a2 | 795 | tmpccer &= (uint32_t)~TIM_CCER_CC2P; |
mbed_official | 157:90e3acc479a2 | 796 | /* Set the Output Compare Polarity */ |
mbed_official | 157:90e3acc479a2 | 797 | tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 4); |
mbed_official | 157:90e3acc479a2 | 798 | |
mbed_official | 157:90e3acc479a2 | 799 | /* Set the Output State */ |
mbed_official | 157:90e3acc479a2 | 800 | tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 4); |
mbed_official | 157:90e3acc479a2 | 801 | |
mbed_official | 157:90e3acc479a2 | 802 | if((TIMx == TIM1) || (TIMx == TIM8)) |
mbed_official | 157:90e3acc479a2 | 803 | { |
mbed_official | 157:90e3acc479a2 | 804 | assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); |
mbed_official | 157:90e3acc479a2 | 805 | assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); |
mbed_official | 157:90e3acc479a2 | 806 | assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); |
mbed_official | 157:90e3acc479a2 | 807 | assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); |
mbed_official | 157:90e3acc479a2 | 808 | |
mbed_official | 157:90e3acc479a2 | 809 | /* Reset the Output N Polarity level */ |
mbed_official | 157:90e3acc479a2 | 810 | tmpccer &= (uint32_t)~TIM_CCER_CC2NP; |
mbed_official | 157:90e3acc479a2 | 811 | /* Set the Output N Polarity */ |
mbed_official | 157:90e3acc479a2 | 812 | tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNPolarity << 4); |
mbed_official | 157:90e3acc479a2 | 813 | /* Reset the Output N State */ |
mbed_official | 157:90e3acc479a2 | 814 | tmpccer &= (uint32_t)~TIM_CCER_CC2NE; |
mbed_official | 157:90e3acc479a2 | 815 | |
mbed_official | 157:90e3acc479a2 | 816 | /* Set the Output N State */ |
mbed_official | 157:90e3acc479a2 | 817 | tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputNState << 4); |
mbed_official | 157:90e3acc479a2 | 818 | /* Reset the Output Compare and Output Compare N IDLE State */ |
mbed_official | 157:90e3acc479a2 | 819 | tmpcr2 &= (uint32_t)~TIM_CR2_OIS2; |
mbed_official | 157:90e3acc479a2 | 820 | tmpcr2 &= (uint32_t)~TIM_CR2_OIS2N; |
mbed_official | 157:90e3acc479a2 | 821 | /* Set the Output Idle state */ |
mbed_official | 157:90e3acc479a2 | 822 | tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 2); |
mbed_official | 157:90e3acc479a2 | 823 | /* Set the Output N Idle state */ |
mbed_official | 157:90e3acc479a2 | 824 | tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNIdleState << 2); |
mbed_official | 157:90e3acc479a2 | 825 | } |
mbed_official | 157:90e3acc479a2 | 826 | /* Write to TIMx CR2 */ |
mbed_official | 157:90e3acc479a2 | 827 | TIMx->CR2 = tmpcr2; |
mbed_official | 157:90e3acc479a2 | 828 | |
mbed_official | 157:90e3acc479a2 | 829 | /* Write to TIMx CCMR1 */ |
mbed_official | 157:90e3acc479a2 | 830 | TIMx->CCMR1 = tmpccmrx; |
mbed_official | 157:90e3acc479a2 | 831 | |
mbed_official | 157:90e3acc479a2 | 832 | /* Set the Capture Compare Register value */ |
mbed_official | 157:90e3acc479a2 | 833 | TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; |
mbed_official | 157:90e3acc479a2 | 834 | |
mbed_official | 157:90e3acc479a2 | 835 | /* Write to TIMx CCER */ |
mbed_official | 157:90e3acc479a2 | 836 | TIMx->CCER = tmpccer; |
mbed_official | 157:90e3acc479a2 | 837 | } |
mbed_official | 157:90e3acc479a2 | 838 | |
mbed_official | 157:90e3acc479a2 | 839 | /** |
mbed_official | 157:90e3acc479a2 | 840 | * @brief Initializes the TIMx Channel3 according to the specified parameters |
mbed_official | 157:90e3acc479a2 | 841 | * in the TIM_OCInitStruct. |
mbed_official | 157:90e3acc479a2 | 842 | * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 843 | * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains |
mbed_official | 157:90e3acc479a2 | 844 | * the configuration information for the specified TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 845 | * @retval None |
mbed_official | 157:90e3acc479a2 | 846 | */ |
mbed_official | 157:90e3acc479a2 | 847 | void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) |
mbed_official | 157:90e3acc479a2 | 848 | { |
mbed_official | 157:90e3acc479a2 | 849 | uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; |
mbed_official | 157:90e3acc479a2 | 850 | |
mbed_official | 157:90e3acc479a2 | 851 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 852 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 853 | assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); |
mbed_official | 157:90e3acc479a2 | 854 | assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); |
mbed_official | 157:90e3acc479a2 | 855 | assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); |
mbed_official | 157:90e3acc479a2 | 856 | |
mbed_official | 157:90e3acc479a2 | 857 | /* Disable the Channel 3: Reset the CC2E Bit */ |
mbed_official | 157:90e3acc479a2 | 858 | TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; |
mbed_official | 157:90e3acc479a2 | 859 | |
mbed_official | 157:90e3acc479a2 | 860 | /* Get the TIMx CCER register value */ |
mbed_official | 157:90e3acc479a2 | 861 | tmpccer = TIMx->CCER; |
mbed_official | 157:90e3acc479a2 | 862 | /* Get the TIMx CR2 register value */ |
mbed_official | 157:90e3acc479a2 | 863 | tmpcr2 = TIMx->CR2; |
mbed_official | 157:90e3acc479a2 | 864 | |
mbed_official | 157:90e3acc479a2 | 865 | /* Get the TIMx CCMR2 register value */ |
mbed_official | 157:90e3acc479a2 | 866 | tmpccmrx = TIMx->CCMR2; |
mbed_official | 157:90e3acc479a2 | 867 | |
mbed_official | 157:90e3acc479a2 | 868 | /* Reset the Output Compare mode and Capture/Compare selection Bits */ |
mbed_official | 157:90e3acc479a2 | 869 | tmpccmrx &= (uint32_t)~TIM_CCMR2_OC3M; |
mbed_official | 157:90e3acc479a2 | 870 | tmpccmrx &= (uint32_t)~TIM_CCMR2_CC3S; |
mbed_official | 157:90e3acc479a2 | 871 | /* Select the Output Compare Mode */ |
mbed_official | 157:90e3acc479a2 | 872 | tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; |
mbed_official | 157:90e3acc479a2 | 873 | |
mbed_official | 157:90e3acc479a2 | 874 | /* Reset the Output Polarity level */ |
mbed_official | 157:90e3acc479a2 | 875 | tmpccer &= (uint32_t)~TIM_CCER_CC3P; |
mbed_official | 157:90e3acc479a2 | 876 | /* Set the Output Compare Polarity */ |
mbed_official | 157:90e3acc479a2 | 877 | tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 8); |
mbed_official | 157:90e3acc479a2 | 878 | |
mbed_official | 157:90e3acc479a2 | 879 | /* Set the Output State */ |
mbed_official | 157:90e3acc479a2 | 880 | tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 8); |
mbed_official | 157:90e3acc479a2 | 881 | |
mbed_official | 157:90e3acc479a2 | 882 | if((TIMx == TIM1) || (TIMx == TIM8)) |
mbed_official | 157:90e3acc479a2 | 883 | { |
mbed_official | 157:90e3acc479a2 | 884 | assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); |
mbed_official | 157:90e3acc479a2 | 885 | assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); |
mbed_official | 157:90e3acc479a2 | 886 | assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); |
mbed_official | 157:90e3acc479a2 | 887 | assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); |
mbed_official | 157:90e3acc479a2 | 888 | |
mbed_official | 157:90e3acc479a2 | 889 | /* Reset the Output N Polarity level */ |
mbed_official | 157:90e3acc479a2 | 890 | tmpccer &= (uint32_t)~TIM_CCER_CC3NP; |
mbed_official | 157:90e3acc479a2 | 891 | /* Set the Output N Polarity */ |
mbed_official | 157:90e3acc479a2 | 892 | tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNPolarity << 8); |
mbed_official | 157:90e3acc479a2 | 893 | /* Reset the Output N State */ |
mbed_official | 157:90e3acc479a2 | 894 | tmpccer &= (uint32_t)~TIM_CCER_CC3NE; |
mbed_official | 157:90e3acc479a2 | 895 | |
mbed_official | 157:90e3acc479a2 | 896 | /* Set the Output N State */ |
mbed_official | 157:90e3acc479a2 | 897 | tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputNState << 8); |
mbed_official | 157:90e3acc479a2 | 898 | /* Reset the Output Compare and Output Compare N IDLE State */ |
mbed_official | 157:90e3acc479a2 | 899 | tmpcr2 &= (uint32_t)~TIM_CR2_OIS3; |
mbed_official | 157:90e3acc479a2 | 900 | tmpcr2 &= (uint32_t)~TIM_CR2_OIS3N; |
mbed_official | 157:90e3acc479a2 | 901 | /* Set the Output Idle state */ |
mbed_official | 157:90e3acc479a2 | 902 | tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 4); |
mbed_official | 157:90e3acc479a2 | 903 | /* Set the Output N Idle state */ |
mbed_official | 157:90e3acc479a2 | 904 | tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCNIdleState << 4); |
mbed_official | 157:90e3acc479a2 | 905 | } |
mbed_official | 157:90e3acc479a2 | 906 | /* Write to TIMx CR2 */ |
mbed_official | 157:90e3acc479a2 | 907 | TIMx->CR2 = tmpcr2; |
mbed_official | 157:90e3acc479a2 | 908 | |
mbed_official | 157:90e3acc479a2 | 909 | /* Write to TIMx CCMR2 */ |
mbed_official | 157:90e3acc479a2 | 910 | TIMx->CCMR2 = tmpccmrx; |
mbed_official | 157:90e3acc479a2 | 911 | |
mbed_official | 157:90e3acc479a2 | 912 | /* Set the Capture Compare Register value */ |
mbed_official | 157:90e3acc479a2 | 913 | TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; |
mbed_official | 157:90e3acc479a2 | 914 | |
mbed_official | 157:90e3acc479a2 | 915 | /* Write to TIMx CCER */ |
mbed_official | 157:90e3acc479a2 | 916 | TIMx->CCER = tmpccer; |
mbed_official | 157:90e3acc479a2 | 917 | } |
mbed_official | 157:90e3acc479a2 | 918 | |
mbed_official | 157:90e3acc479a2 | 919 | /** |
mbed_official | 157:90e3acc479a2 | 920 | * @brief Initializes the TIMx Channel4 according to the specified parameters |
mbed_official | 157:90e3acc479a2 | 921 | * in the TIM_OCInitStruct. |
mbed_official | 157:90e3acc479a2 | 922 | * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 923 | * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains |
mbed_official | 157:90e3acc479a2 | 924 | * the configuration information for the specified TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 925 | * @retval None |
mbed_official | 157:90e3acc479a2 | 926 | */ |
mbed_official | 157:90e3acc479a2 | 927 | void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) |
mbed_official | 157:90e3acc479a2 | 928 | { |
mbed_official | 157:90e3acc479a2 | 929 | uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; |
mbed_official | 157:90e3acc479a2 | 930 | |
mbed_official | 157:90e3acc479a2 | 931 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 932 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 933 | assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); |
mbed_official | 157:90e3acc479a2 | 934 | assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); |
mbed_official | 157:90e3acc479a2 | 935 | assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); |
mbed_official | 157:90e3acc479a2 | 936 | |
mbed_official | 157:90e3acc479a2 | 937 | /* Disable the Channel 4: Reset the CC4E Bit */ |
mbed_official | 157:90e3acc479a2 | 938 | TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; |
mbed_official | 157:90e3acc479a2 | 939 | |
mbed_official | 157:90e3acc479a2 | 940 | /* Get the TIMx CCER register value */ |
mbed_official | 157:90e3acc479a2 | 941 | tmpccer = TIMx->CCER; |
mbed_official | 157:90e3acc479a2 | 942 | /* Get the TIMx CR2 register value */ |
mbed_official | 157:90e3acc479a2 | 943 | tmpcr2 = TIMx->CR2; |
mbed_official | 157:90e3acc479a2 | 944 | |
mbed_official | 157:90e3acc479a2 | 945 | /* Get the TIMx CCMR2 register value */ |
mbed_official | 157:90e3acc479a2 | 946 | tmpccmrx = TIMx->CCMR2; |
mbed_official | 157:90e3acc479a2 | 947 | |
mbed_official | 157:90e3acc479a2 | 948 | /* Reset the Output Compare mode and Capture/Compare selection Bits */ |
mbed_official | 157:90e3acc479a2 | 949 | tmpccmrx &= (uint32_t)~TIM_CCMR2_OC4M; |
mbed_official | 157:90e3acc479a2 | 950 | tmpccmrx &= (uint32_t)~TIM_CCMR2_CC4S; |
mbed_official | 157:90e3acc479a2 | 951 | |
mbed_official | 157:90e3acc479a2 | 952 | /* Select the Output Compare Mode */ |
mbed_official | 157:90e3acc479a2 | 953 | tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8); |
mbed_official | 157:90e3acc479a2 | 954 | |
mbed_official | 157:90e3acc479a2 | 955 | /* Reset the Output Polarity level */ |
mbed_official | 157:90e3acc479a2 | 956 | tmpccer &= (uint32_t)~TIM_CCER_CC4P; |
mbed_official | 157:90e3acc479a2 | 957 | /* Set the Output Compare Polarity */ |
mbed_official | 157:90e3acc479a2 | 958 | tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 12); |
mbed_official | 157:90e3acc479a2 | 959 | |
mbed_official | 157:90e3acc479a2 | 960 | /* Set the Output State */ |
mbed_official | 157:90e3acc479a2 | 961 | tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 12); |
mbed_official | 157:90e3acc479a2 | 962 | |
mbed_official | 157:90e3acc479a2 | 963 | if((TIMx == TIM1) || (TIMx == TIM8)) |
mbed_official | 157:90e3acc479a2 | 964 | { |
mbed_official | 157:90e3acc479a2 | 965 | assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); |
mbed_official | 157:90e3acc479a2 | 966 | /* Reset the Output Compare IDLE State */ |
mbed_official | 157:90e3acc479a2 | 967 | tmpcr2 &=(uint32_t) ~TIM_CR2_OIS4; |
mbed_official | 157:90e3acc479a2 | 968 | /* Set the Output Idle state */ |
mbed_official | 157:90e3acc479a2 | 969 | tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 6); |
mbed_official | 157:90e3acc479a2 | 970 | } |
mbed_official | 157:90e3acc479a2 | 971 | /* Write to TIMx CR2 */ |
mbed_official | 157:90e3acc479a2 | 972 | TIMx->CR2 = tmpcr2; |
mbed_official | 157:90e3acc479a2 | 973 | |
mbed_official | 157:90e3acc479a2 | 974 | /* Write to TIMx CCMR2 */ |
mbed_official | 157:90e3acc479a2 | 975 | TIMx->CCMR2 = tmpccmrx; |
mbed_official | 157:90e3acc479a2 | 976 | |
mbed_official | 157:90e3acc479a2 | 977 | /* Set the Capture Compare Register value */ |
mbed_official | 157:90e3acc479a2 | 978 | TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; |
mbed_official | 157:90e3acc479a2 | 979 | |
mbed_official | 157:90e3acc479a2 | 980 | /* Write to TIMx CCER */ |
mbed_official | 157:90e3acc479a2 | 981 | TIMx->CCER = tmpccer; |
mbed_official | 157:90e3acc479a2 | 982 | } |
mbed_official | 157:90e3acc479a2 | 983 | |
mbed_official | 157:90e3acc479a2 | 984 | /** |
mbed_official | 157:90e3acc479a2 | 985 | * @brief Initializes the TIMx Channel5 according to the specified parameters |
mbed_official | 157:90e3acc479a2 | 986 | * in the TIM_OCInitStruct. |
mbed_official | 157:90e3acc479a2 | 987 | * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 988 | * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains |
mbed_official | 157:90e3acc479a2 | 989 | * the configuration information for the specified TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 990 | * @retval None |
mbed_official | 157:90e3acc479a2 | 991 | */ |
mbed_official | 157:90e3acc479a2 | 992 | void TIM_OC5Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) |
mbed_official | 157:90e3acc479a2 | 993 | { |
mbed_official | 157:90e3acc479a2 | 994 | uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; |
mbed_official | 157:90e3acc479a2 | 995 | |
mbed_official | 157:90e3acc479a2 | 996 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 997 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 998 | assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); |
mbed_official | 157:90e3acc479a2 | 999 | assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); |
mbed_official | 157:90e3acc479a2 | 1000 | assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); |
mbed_official | 157:90e3acc479a2 | 1001 | |
mbed_official | 157:90e3acc479a2 | 1002 | /* Disable the Channel 5: Reset the CC5E Bit */ |
mbed_official | 157:90e3acc479a2 | 1003 | TIMx->CCER &= (uint32_t)~TIM_CCER_CC5E; /* to be verified*/ |
mbed_official | 157:90e3acc479a2 | 1004 | |
mbed_official | 157:90e3acc479a2 | 1005 | /* Get the TIMx CCER register value */ |
mbed_official | 157:90e3acc479a2 | 1006 | tmpccer = TIMx->CCER; |
mbed_official | 157:90e3acc479a2 | 1007 | /* Get the TIMx CR2 register value */ |
mbed_official | 157:90e3acc479a2 | 1008 | tmpcr2 = TIMx->CR2; |
mbed_official | 157:90e3acc479a2 | 1009 | |
mbed_official | 157:90e3acc479a2 | 1010 | /* Get the TIMx CCMR3 register value */ |
mbed_official | 157:90e3acc479a2 | 1011 | tmpccmrx = TIMx->CCMR3; |
mbed_official | 157:90e3acc479a2 | 1012 | |
mbed_official | 157:90e3acc479a2 | 1013 | /* Reset the Output Compare mode and Capture/Compare selection Bits */ |
mbed_official | 157:90e3acc479a2 | 1014 | tmpccmrx &= (uint32_t)~TIM_CCMR3_OC5M; |
mbed_official | 157:90e3acc479a2 | 1015 | |
mbed_official | 157:90e3acc479a2 | 1016 | /* Select the Output Compare Mode */ |
mbed_official | 157:90e3acc479a2 | 1017 | tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode); |
mbed_official | 157:90e3acc479a2 | 1018 | |
mbed_official | 157:90e3acc479a2 | 1019 | /* Reset the Output Polarity level */ |
mbed_official | 157:90e3acc479a2 | 1020 | tmpccer &= (uint32_t)~TIM_CCER_CC5P; |
mbed_official | 157:90e3acc479a2 | 1021 | /* Set the Output Compare Polarity */ |
mbed_official | 157:90e3acc479a2 | 1022 | tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 16); |
mbed_official | 157:90e3acc479a2 | 1023 | |
mbed_official | 157:90e3acc479a2 | 1024 | /* Set the Output State */ |
mbed_official | 157:90e3acc479a2 | 1025 | tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 16); |
mbed_official | 157:90e3acc479a2 | 1026 | |
mbed_official | 157:90e3acc479a2 | 1027 | if((TIMx == TIM1) || (TIMx == TIM8)) |
mbed_official | 157:90e3acc479a2 | 1028 | { |
mbed_official | 157:90e3acc479a2 | 1029 | assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); |
mbed_official | 157:90e3acc479a2 | 1030 | /* Reset the Output Compare IDLE State */ |
mbed_official | 157:90e3acc479a2 | 1031 | tmpcr2 &=(uint32_t) ~TIM_CR2_OIS5; |
mbed_official | 157:90e3acc479a2 | 1032 | /* Set the Output Idle state */ |
mbed_official | 157:90e3acc479a2 | 1033 | tmpcr2 |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCIdleState << 16); |
mbed_official | 157:90e3acc479a2 | 1034 | } |
mbed_official | 157:90e3acc479a2 | 1035 | /* Write to TIMx CR2 */ |
mbed_official | 157:90e3acc479a2 | 1036 | TIMx->CR2 = tmpcr2; |
mbed_official | 157:90e3acc479a2 | 1037 | |
mbed_official | 157:90e3acc479a2 | 1038 | /* Write to TIMx CCMR2 */ |
mbed_official | 157:90e3acc479a2 | 1039 | TIMx->CCMR3 = tmpccmrx; |
mbed_official | 157:90e3acc479a2 | 1040 | |
mbed_official | 157:90e3acc479a2 | 1041 | /* Set the Capture Compare Register value */ |
mbed_official | 157:90e3acc479a2 | 1042 | TIMx->CCR5 = TIM_OCInitStruct->TIM_Pulse; |
mbed_official | 157:90e3acc479a2 | 1043 | |
mbed_official | 157:90e3acc479a2 | 1044 | /* Write to TIMx CCER */ |
mbed_official | 157:90e3acc479a2 | 1045 | TIMx->CCER = tmpccer; |
mbed_official | 157:90e3acc479a2 | 1046 | } |
mbed_official | 157:90e3acc479a2 | 1047 | |
mbed_official | 157:90e3acc479a2 | 1048 | /** |
mbed_official | 157:90e3acc479a2 | 1049 | * @brief Initializes the TIMx Channel6 according to the specified parameters |
mbed_official | 157:90e3acc479a2 | 1050 | * in the TIM_OCInitStruct. |
mbed_official | 157:90e3acc479a2 | 1051 | * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1052 | * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains |
mbed_official | 157:90e3acc479a2 | 1053 | * the configuration information for the specified TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1054 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1055 | */ |
mbed_official | 157:90e3acc479a2 | 1056 | void TIM_OC6Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) |
mbed_official | 157:90e3acc479a2 | 1057 | { |
mbed_official | 157:90e3acc479a2 | 1058 | uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; |
mbed_official | 157:90e3acc479a2 | 1059 | |
mbed_official | 157:90e3acc479a2 | 1060 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1061 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1062 | assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); |
mbed_official | 157:90e3acc479a2 | 1063 | assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); |
mbed_official | 157:90e3acc479a2 | 1064 | assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); |
mbed_official | 157:90e3acc479a2 | 1065 | |
mbed_official | 157:90e3acc479a2 | 1066 | /* Disable the Channel 5: Reset the CC5E Bit */ |
mbed_official | 157:90e3acc479a2 | 1067 | TIMx->CCER &= (uint32_t)~TIM_CCER_CC6E; /* to be verified*/ |
mbed_official | 157:90e3acc479a2 | 1068 | |
mbed_official | 157:90e3acc479a2 | 1069 | /* Get the TIMx CCER register value */ |
mbed_official | 157:90e3acc479a2 | 1070 | tmpccer = TIMx->CCER; |
mbed_official | 157:90e3acc479a2 | 1071 | /* Get the TIMx CR2 register value */ |
mbed_official | 157:90e3acc479a2 | 1072 | tmpcr2 = TIMx->CR2; |
mbed_official | 157:90e3acc479a2 | 1073 | |
mbed_official | 157:90e3acc479a2 | 1074 | /* Get the TIMx CCMR3 register value */ |
mbed_official | 157:90e3acc479a2 | 1075 | tmpccmrx = TIMx->CCMR3; |
mbed_official | 157:90e3acc479a2 | 1076 | |
mbed_official | 157:90e3acc479a2 | 1077 | /* Reset the Output Compare mode and Capture/Compare selection Bits */ |
mbed_official | 157:90e3acc479a2 | 1078 | tmpccmrx &= (uint32_t)~TIM_CCMR3_OC6M; |
mbed_official | 157:90e3acc479a2 | 1079 | |
mbed_official | 157:90e3acc479a2 | 1080 | /* Select the Output Compare Mode */ |
mbed_official | 157:90e3acc479a2 | 1081 | tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8); |
mbed_official | 157:90e3acc479a2 | 1082 | |
mbed_official | 157:90e3acc479a2 | 1083 | /* Reset the Output Polarity level */ |
mbed_official | 157:90e3acc479a2 | 1084 | tmpccer &= (uint32_t)~TIM_CCER_CC6P; |
mbed_official | 157:90e3acc479a2 | 1085 | /* Set the Output Compare Polarity */ |
mbed_official | 157:90e3acc479a2 | 1086 | tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OCPolarity << 20); |
mbed_official | 157:90e3acc479a2 | 1087 | |
mbed_official | 157:90e3acc479a2 | 1088 | /* Set the Output State */ |
mbed_official | 157:90e3acc479a2 | 1089 | tmpccer |= (uint32_t)((uint32_t)TIM_OCInitStruct->TIM_OutputState << 20); |
mbed_official | 157:90e3acc479a2 | 1090 | |
mbed_official | 157:90e3acc479a2 | 1091 | if((TIMx == TIM1) || (TIMx == TIM8)) |
mbed_official | 157:90e3acc479a2 | 1092 | { |
mbed_official | 157:90e3acc479a2 | 1093 | assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); |
mbed_official | 157:90e3acc479a2 | 1094 | /* Reset the Output Compare IDLE State */ |
mbed_official | 157:90e3acc479a2 | 1095 | tmpcr2 &=(uint32_t) ~TIM_CR2_OIS6; |
mbed_official | 157:90e3acc479a2 | 1096 | /* Set the Output Idle state */ |
mbed_official | 157:90e3acc479a2 | 1097 | tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 18); |
mbed_official | 157:90e3acc479a2 | 1098 | } |
mbed_official | 157:90e3acc479a2 | 1099 | /* Write to TIMx CR2 */ |
mbed_official | 157:90e3acc479a2 | 1100 | TIMx->CR2 = tmpcr2; |
mbed_official | 157:90e3acc479a2 | 1101 | |
mbed_official | 157:90e3acc479a2 | 1102 | /* Write to TIMx CCMR2 */ |
mbed_official | 157:90e3acc479a2 | 1103 | TIMx->CCMR3 = tmpccmrx; |
mbed_official | 157:90e3acc479a2 | 1104 | |
mbed_official | 157:90e3acc479a2 | 1105 | /* Set the Capture Compare Register value */ |
mbed_official | 157:90e3acc479a2 | 1106 | TIMx->CCR6 = TIM_OCInitStruct->TIM_Pulse; |
mbed_official | 157:90e3acc479a2 | 1107 | |
mbed_official | 157:90e3acc479a2 | 1108 | /* Write to TIMx CCER */ |
mbed_official | 157:90e3acc479a2 | 1109 | TIMx->CCER = tmpccer; |
mbed_official | 157:90e3acc479a2 | 1110 | } |
mbed_official | 157:90e3acc479a2 | 1111 | |
mbed_official | 157:90e3acc479a2 | 1112 | /** |
mbed_official | 157:90e3acc479a2 | 1113 | * @brief Selects the TIM Group Channel 5 and Channel 1, |
mbed_official | 157:90e3acc479a2 | 1114 | OC1REFC is the logical AND of OC1REFC and OC5REF. |
mbed_official | 157:90e3acc479a2 | 1115 | * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral |
mbed_official | 157:90e3acc479a2 | 1116 | * @param NewState: new state of the Commutation event. |
mbed_official | 157:90e3acc479a2 | 1117 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 157:90e3acc479a2 | 1118 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1119 | */ |
mbed_official | 157:90e3acc479a2 | 1120 | void TIM_SelectGC5C1(TIM_TypeDef* TIMx, FunctionalState NewState) |
mbed_official | 157:90e3acc479a2 | 1121 | { |
mbed_official | 157:90e3acc479a2 | 1122 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1123 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1124 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 157:90e3acc479a2 | 1125 | |
mbed_official | 157:90e3acc479a2 | 1126 | if (NewState != DISABLE) |
mbed_official | 157:90e3acc479a2 | 1127 | { |
mbed_official | 157:90e3acc479a2 | 1128 | /* Set the GC5C1 Bit */ |
mbed_official | 157:90e3acc479a2 | 1129 | TIMx->CCR5 |= TIM_CCR5_GC5C1; |
mbed_official | 157:90e3acc479a2 | 1130 | } |
mbed_official | 157:90e3acc479a2 | 1131 | else |
mbed_official | 157:90e3acc479a2 | 1132 | { |
mbed_official | 157:90e3acc479a2 | 1133 | /* Reset the GC5C1 Bit */ |
mbed_official | 157:90e3acc479a2 | 1134 | TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C1; |
mbed_official | 157:90e3acc479a2 | 1135 | } |
mbed_official | 157:90e3acc479a2 | 1136 | } |
mbed_official | 157:90e3acc479a2 | 1137 | |
mbed_official | 157:90e3acc479a2 | 1138 | /** |
mbed_official | 157:90e3acc479a2 | 1139 | * @brief Selects the TIM Group Channel 5 and Channel 2, |
mbed_official | 157:90e3acc479a2 | 1140 | OC2REFC is the logical AND of OC2REFC and OC5REF. |
mbed_official | 157:90e3acc479a2 | 1141 | * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral |
mbed_official | 157:90e3acc479a2 | 1142 | * @param NewState: new state of the Commutation event. |
mbed_official | 157:90e3acc479a2 | 1143 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 157:90e3acc479a2 | 1144 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1145 | */ |
mbed_official | 157:90e3acc479a2 | 1146 | void TIM_SelectGC5C2(TIM_TypeDef* TIMx, FunctionalState NewState) |
mbed_official | 157:90e3acc479a2 | 1147 | { |
mbed_official | 157:90e3acc479a2 | 1148 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1149 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1150 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 157:90e3acc479a2 | 1151 | |
mbed_official | 157:90e3acc479a2 | 1152 | if (NewState != DISABLE) |
mbed_official | 157:90e3acc479a2 | 1153 | { |
mbed_official | 157:90e3acc479a2 | 1154 | /* Set the GC5C2 Bit */ |
mbed_official | 157:90e3acc479a2 | 1155 | TIMx->CCR5 |= TIM_CCR5_GC5C2; |
mbed_official | 157:90e3acc479a2 | 1156 | } |
mbed_official | 157:90e3acc479a2 | 1157 | else |
mbed_official | 157:90e3acc479a2 | 1158 | { |
mbed_official | 157:90e3acc479a2 | 1159 | /* Reset the GC5C2 Bit */ |
mbed_official | 157:90e3acc479a2 | 1160 | TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C2; |
mbed_official | 157:90e3acc479a2 | 1161 | } |
mbed_official | 157:90e3acc479a2 | 1162 | } |
mbed_official | 157:90e3acc479a2 | 1163 | |
mbed_official | 157:90e3acc479a2 | 1164 | |
mbed_official | 157:90e3acc479a2 | 1165 | /** |
mbed_official | 157:90e3acc479a2 | 1166 | * @brief Selects the TIM Group Channel 5 and Channel 3, |
mbed_official | 157:90e3acc479a2 | 1167 | OC3REFC is the logical AND of OC3REFC and OC5REF. |
mbed_official | 157:90e3acc479a2 | 1168 | * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral |
mbed_official | 157:90e3acc479a2 | 1169 | * @param NewState: new state of the Commutation event. |
mbed_official | 157:90e3acc479a2 | 1170 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 157:90e3acc479a2 | 1171 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1172 | */ |
mbed_official | 157:90e3acc479a2 | 1173 | void TIM_SelectGC5C3(TIM_TypeDef* TIMx, FunctionalState NewState) |
mbed_official | 157:90e3acc479a2 | 1174 | { |
mbed_official | 157:90e3acc479a2 | 1175 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1176 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1177 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 157:90e3acc479a2 | 1178 | |
mbed_official | 157:90e3acc479a2 | 1179 | if (NewState != DISABLE) |
mbed_official | 157:90e3acc479a2 | 1180 | { |
mbed_official | 157:90e3acc479a2 | 1181 | /* Set the GC5C3 Bit */ |
mbed_official | 157:90e3acc479a2 | 1182 | TIMx->CCR5 |= TIM_CCR5_GC5C3; |
mbed_official | 157:90e3acc479a2 | 1183 | } |
mbed_official | 157:90e3acc479a2 | 1184 | else |
mbed_official | 157:90e3acc479a2 | 1185 | { |
mbed_official | 157:90e3acc479a2 | 1186 | /* Reset the GC5C3 Bit */ |
mbed_official | 157:90e3acc479a2 | 1187 | TIMx->CCR5 &= (uint32_t)~TIM_CCR5_GC5C3; |
mbed_official | 157:90e3acc479a2 | 1188 | } |
mbed_official | 157:90e3acc479a2 | 1189 | } |
mbed_official | 157:90e3acc479a2 | 1190 | |
mbed_official | 157:90e3acc479a2 | 1191 | /** |
mbed_official | 157:90e3acc479a2 | 1192 | * @brief Fills each TIM_OCInitStruct member with its default value. |
mbed_official | 157:90e3acc479a2 | 1193 | * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will |
mbed_official | 157:90e3acc479a2 | 1194 | * be initialized. |
mbed_official | 157:90e3acc479a2 | 1195 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1196 | */ |
mbed_official | 157:90e3acc479a2 | 1197 | void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) |
mbed_official | 157:90e3acc479a2 | 1198 | { |
mbed_official | 157:90e3acc479a2 | 1199 | /* Set the default configuration */ |
mbed_official | 157:90e3acc479a2 | 1200 | TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; |
mbed_official | 157:90e3acc479a2 | 1201 | TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; |
mbed_official | 157:90e3acc479a2 | 1202 | TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; |
mbed_official | 157:90e3acc479a2 | 1203 | TIM_OCInitStruct->TIM_Pulse = 0x00000000; |
mbed_official | 157:90e3acc479a2 | 1204 | TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; |
mbed_official | 157:90e3acc479a2 | 1205 | TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; |
mbed_official | 157:90e3acc479a2 | 1206 | TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; |
mbed_official | 157:90e3acc479a2 | 1207 | TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; |
mbed_official | 157:90e3acc479a2 | 1208 | } |
mbed_official | 157:90e3acc479a2 | 1209 | |
mbed_official | 157:90e3acc479a2 | 1210 | /** |
mbed_official | 157:90e3acc479a2 | 1211 | * @brief Selects the TIM Output Compare Mode. |
mbed_official | 157:90e3acc479a2 | 1212 | * @note This function disables the selected channel before changing the Output |
mbed_official | 157:90e3acc479a2 | 1213 | * Compare Mode. If needed, user has to enable this channel using |
mbed_official | 157:90e3acc479a2 | 1214 | * TIM_CCxCmd() and TIM_CCxNCmd() functions. |
mbed_official | 157:90e3acc479a2 | 1215 | * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1216 | * @param TIM_Channel: specifies the TIM Channel |
mbed_official | 157:90e3acc479a2 | 1217 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 1218 | * @arg TIM_Channel_1: TIM Channel 1 |
mbed_official | 157:90e3acc479a2 | 1219 | * @arg TIM_Channel_2: TIM Channel 2 |
mbed_official | 157:90e3acc479a2 | 1220 | * @arg TIM_Channel_3: TIM Channel 3 |
mbed_official | 157:90e3acc479a2 | 1221 | * @arg TIM_Channel_4: TIM Channel 4 |
mbed_official | 157:90e3acc479a2 | 1222 | * @param TIM_OCMode: specifies the TIM Output Compare Mode. |
mbed_official | 157:90e3acc479a2 | 1223 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 1224 | * @arg TIM_OCMode_Timing |
mbed_official | 157:90e3acc479a2 | 1225 | * @arg TIM_OCMode_Active |
mbed_official | 157:90e3acc479a2 | 1226 | * @arg TIM_OCMode_Toggle |
mbed_official | 157:90e3acc479a2 | 1227 | * @arg TIM_OCMode_PWM1 |
mbed_official | 157:90e3acc479a2 | 1228 | * @arg TIM_OCMode_PWM2 |
mbed_official | 157:90e3acc479a2 | 1229 | * @arg TIM_ForcedAction_Active |
mbed_official | 157:90e3acc479a2 | 1230 | * @arg TIM_ForcedAction_InActive |
mbed_official | 157:90e3acc479a2 | 1231 | * @arg TIM_OCMode_Retrigerrable_OPM1 |
mbed_official | 157:90e3acc479a2 | 1232 | * @arg TIM_OCMode_Retrigerrable_OPM2 |
mbed_official | 157:90e3acc479a2 | 1233 | * @arg TIM_OCMode_Combined_PWM1 |
mbed_official | 157:90e3acc479a2 | 1234 | * @arg TIM_OCMode_Combined_PWM2 |
mbed_official | 157:90e3acc479a2 | 1235 | * @arg TIM_OCMode_Asymmetric_PWM1 |
mbed_official | 157:90e3acc479a2 | 1236 | * @arg TIM_OCMode_Asymmetric_PWM2 |
mbed_official | 157:90e3acc479a2 | 1237 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1238 | */ |
mbed_official | 157:90e3acc479a2 | 1239 | void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint32_t TIM_OCMode) |
mbed_official | 157:90e3acc479a2 | 1240 | { |
mbed_official | 157:90e3acc479a2 | 1241 | uint32_t tmp = 0; |
mbed_official | 157:90e3acc479a2 | 1242 | uint16_t tmp1 = 0; |
mbed_official | 157:90e3acc479a2 | 1243 | |
mbed_official | 157:90e3acc479a2 | 1244 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1245 | assert_param(IS_TIM_LIST1_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1246 | assert_param(IS_TIM_CHANNEL(TIM_Channel)); |
mbed_official | 157:90e3acc479a2 | 1247 | assert_param(IS_TIM_OCM(TIM_OCMode)); |
mbed_official | 157:90e3acc479a2 | 1248 | |
mbed_official | 157:90e3acc479a2 | 1249 | tmp = (uint32_t) TIMx; |
mbed_official | 157:90e3acc479a2 | 1250 | tmp += CCMR_OFFSET; |
mbed_official | 157:90e3acc479a2 | 1251 | |
mbed_official | 157:90e3acc479a2 | 1252 | tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel; |
mbed_official | 157:90e3acc479a2 | 1253 | |
mbed_official | 157:90e3acc479a2 | 1254 | /* Disable the Channel: Reset the CCxE Bit */ |
mbed_official | 157:90e3acc479a2 | 1255 | TIMx->CCER &= (uint16_t) ~tmp1; |
mbed_official | 157:90e3acc479a2 | 1256 | |
mbed_official | 157:90e3acc479a2 | 1257 | if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) |
mbed_official | 157:90e3acc479a2 | 1258 | { |
mbed_official | 157:90e3acc479a2 | 1259 | tmp += (TIM_Channel>>1); |
mbed_official | 157:90e3acc479a2 | 1260 | |
mbed_official | 157:90e3acc479a2 | 1261 | /* Reset the OCxM bits in the CCMRx register */ |
mbed_official | 157:90e3acc479a2 | 1262 | *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK; |
mbed_official | 157:90e3acc479a2 | 1263 | |
mbed_official | 157:90e3acc479a2 | 1264 | /* Configure the OCxM bits in the CCMRx register */ |
mbed_official | 157:90e3acc479a2 | 1265 | *(__IO uint32_t *) tmp |= TIM_OCMode; |
mbed_official | 157:90e3acc479a2 | 1266 | } |
mbed_official | 157:90e3acc479a2 | 1267 | else |
mbed_official | 157:90e3acc479a2 | 1268 | { |
mbed_official | 157:90e3acc479a2 | 1269 | tmp += (uint32_t)(TIM_Channel - (uint32_t)4)>> (uint32_t)1; |
mbed_official | 157:90e3acc479a2 | 1270 | |
mbed_official | 157:90e3acc479a2 | 1271 | /* Reset the OCxM bits in the CCMRx register */ |
mbed_official | 157:90e3acc479a2 | 1272 | *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK; |
mbed_official | 157:90e3acc479a2 | 1273 | |
mbed_official | 157:90e3acc479a2 | 1274 | /* Configure the OCxM bits in the CCMRx register */ |
mbed_official | 157:90e3acc479a2 | 1275 | *(__IO uint32_t *) tmp |= (uint32_t)(TIM_OCMode << 8); |
mbed_official | 157:90e3acc479a2 | 1276 | } |
mbed_official | 157:90e3acc479a2 | 1277 | } |
mbed_official | 157:90e3acc479a2 | 1278 | |
mbed_official | 157:90e3acc479a2 | 1279 | /** |
mbed_official | 157:90e3acc479a2 | 1280 | * @brief Sets the TIMx Capture Compare1 Register value |
mbed_official | 157:90e3acc479a2 | 1281 | * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1282 | * @param Compare1: specifies the Capture Compare1 register new value. |
mbed_official | 157:90e3acc479a2 | 1283 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1284 | */ |
mbed_official | 157:90e3acc479a2 | 1285 | void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) |
mbed_official | 157:90e3acc479a2 | 1286 | { |
mbed_official | 157:90e3acc479a2 | 1287 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1288 | assert_param(IS_TIM_LIST1_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1289 | |
mbed_official | 157:90e3acc479a2 | 1290 | /* Set the Capture Compare1 Register value */ |
mbed_official | 157:90e3acc479a2 | 1291 | TIMx->CCR1 = Compare1; |
mbed_official | 157:90e3acc479a2 | 1292 | } |
mbed_official | 157:90e3acc479a2 | 1293 | |
mbed_official | 157:90e3acc479a2 | 1294 | /** |
mbed_official | 157:90e3acc479a2 | 1295 | * @brief Sets the TIMx Capture Compare2 Register value |
mbed_official | 157:90e3acc479a2 | 1296 | * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM |
mbed_official | 157:90e3acc479a2 | 1297 | * peripheral. |
mbed_official | 157:90e3acc479a2 | 1298 | * @param Compare2: specifies the Capture Compare2 register new value. |
mbed_official | 157:90e3acc479a2 | 1299 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1300 | */ |
mbed_official | 157:90e3acc479a2 | 1301 | void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2) |
mbed_official | 157:90e3acc479a2 | 1302 | { |
mbed_official | 157:90e3acc479a2 | 1303 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1304 | assert_param(IS_TIM_LIST2_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1305 | |
mbed_official | 157:90e3acc479a2 | 1306 | /* Set the Capture Compare2 Register value */ |
mbed_official | 157:90e3acc479a2 | 1307 | TIMx->CCR2 = Compare2; |
mbed_official | 157:90e3acc479a2 | 1308 | } |
mbed_official | 157:90e3acc479a2 | 1309 | |
mbed_official | 157:90e3acc479a2 | 1310 | /** |
mbed_official | 157:90e3acc479a2 | 1311 | * @brief Sets the TIMx Capture Compare3 Register value |
mbed_official | 157:90e3acc479a2 | 1312 | * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1313 | * @param Compare3: specifies the Capture Compare3 register new value. |
mbed_official | 157:90e3acc479a2 | 1314 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1315 | */ |
mbed_official | 157:90e3acc479a2 | 1316 | void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3) |
mbed_official | 157:90e3acc479a2 | 1317 | { |
mbed_official | 157:90e3acc479a2 | 1318 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1319 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1320 | |
mbed_official | 157:90e3acc479a2 | 1321 | /* Set the Capture Compare3 Register value */ |
mbed_official | 157:90e3acc479a2 | 1322 | TIMx->CCR3 = Compare3; |
mbed_official | 157:90e3acc479a2 | 1323 | } |
mbed_official | 157:90e3acc479a2 | 1324 | |
mbed_official | 157:90e3acc479a2 | 1325 | /** |
mbed_official | 157:90e3acc479a2 | 1326 | * @brief Sets the TIMx Capture Compare4 Register value |
mbed_official | 157:90e3acc479a2 | 1327 | * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1328 | * @param Compare4: specifies the Capture Compare4 register new value. |
mbed_official | 157:90e3acc479a2 | 1329 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1330 | */ |
mbed_official | 157:90e3acc479a2 | 1331 | void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4) |
mbed_official | 157:90e3acc479a2 | 1332 | { |
mbed_official | 157:90e3acc479a2 | 1333 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1334 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1335 | |
mbed_official | 157:90e3acc479a2 | 1336 | /* Set the Capture Compare4 Register value */ |
mbed_official | 157:90e3acc479a2 | 1337 | TIMx->CCR4 = Compare4; |
mbed_official | 157:90e3acc479a2 | 1338 | } |
mbed_official | 157:90e3acc479a2 | 1339 | |
mbed_official | 157:90e3acc479a2 | 1340 | /** |
mbed_official | 157:90e3acc479a2 | 1341 | * @brief Sets the TIMx Capture Compare5 Register value |
mbed_official | 157:90e3acc479a2 | 1342 | * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1343 | * @param Compare5: specifies the Capture Compare5 register new value. |
mbed_official | 157:90e3acc479a2 | 1344 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1345 | */ |
mbed_official | 157:90e3acc479a2 | 1346 | void TIM_SetCompare5(TIM_TypeDef* TIMx, uint32_t Compare5) |
mbed_official | 157:90e3acc479a2 | 1347 | { |
mbed_official | 157:90e3acc479a2 | 1348 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1349 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1350 | |
mbed_official | 157:90e3acc479a2 | 1351 | /* Set the Capture Compare5 Register value */ |
mbed_official | 157:90e3acc479a2 | 1352 | TIMx->CCR5 = Compare5; |
mbed_official | 157:90e3acc479a2 | 1353 | } |
mbed_official | 157:90e3acc479a2 | 1354 | |
mbed_official | 157:90e3acc479a2 | 1355 | /** |
mbed_official | 157:90e3acc479a2 | 1356 | * @brief Sets the TIMx Capture Compare6 Register value |
mbed_official | 157:90e3acc479a2 | 1357 | * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1358 | * @param Compare6: specifies the Capture Compare5 register new value. |
mbed_official | 157:90e3acc479a2 | 1359 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1360 | */ |
mbed_official | 157:90e3acc479a2 | 1361 | void TIM_SetCompare6(TIM_TypeDef* TIMx, uint32_t Compare6) |
mbed_official | 157:90e3acc479a2 | 1362 | { |
mbed_official | 157:90e3acc479a2 | 1363 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1364 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1365 | |
mbed_official | 157:90e3acc479a2 | 1366 | /* Set the Capture Compare6 Register value */ |
mbed_official | 157:90e3acc479a2 | 1367 | TIMx->CCR6 = Compare6; |
mbed_official | 157:90e3acc479a2 | 1368 | } |
mbed_official | 157:90e3acc479a2 | 1369 | |
mbed_official | 157:90e3acc479a2 | 1370 | /** |
mbed_official | 157:90e3acc479a2 | 1371 | * @brief Forces the TIMx output 1 waveform to active or inactive level. |
mbed_official | 157:90e3acc479a2 | 1372 | * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1373 | * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. |
mbed_official | 157:90e3acc479a2 | 1374 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 1375 | * @arg TIM_ForcedAction_Active: Force active level on OC1REF |
mbed_official | 157:90e3acc479a2 | 1376 | * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. |
mbed_official | 157:90e3acc479a2 | 1377 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1378 | */ |
mbed_official | 157:90e3acc479a2 | 1379 | void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) |
mbed_official | 157:90e3acc479a2 | 1380 | { |
mbed_official | 157:90e3acc479a2 | 1381 | uint32_t tmpccmr1 = 0; |
mbed_official | 157:90e3acc479a2 | 1382 | |
mbed_official | 157:90e3acc479a2 | 1383 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1384 | assert_param(IS_TIM_LIST1_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1385 | assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); |
mbed_official | 157:90e3acc479a2 | 1386 | tmpccmr1 = TIMx->CCMR1; |
mbed_official | 157:90e3acc479a2 | 1387 | |
mbed_official | 157:90e3acc479a2 | 1388 | /* Reset the OC1M Bits */ |
mbed_official | 157:90e3acc479a2 | 1389 | tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1M; |
mbed_official | 157:90e3acc479a2 | 1390 | |
mbed_official | 157:90e3acc479a2 | 1391 | /* Configure The Forced output Mode */ |
mbed_official | 157:90e3acc479a2 | 1392 | tmpccmr1 |= TIM_ForcedAction; |
mbed_official | 157:90e3acc479a2 | 1393 | |
mbed_official | 157:90e3acc479a2 | 1394 | /* Write to TIMx CCMR1 register */ |
mbed_official | 157:90e3acc479a2 | 1395 | TIMx->CCMR1 = tmpccmr1; |
mbed_official | 157:90e3acc479a2 | 1396 | } |
mbed_official | 157:90e3acc479a2 | 1397 | |
mbed_official | 157:90e3acc479a2 | 1398 | /** |
mbed_official | 157:90e3acc479a2 | 1399 | * @brief Forces the TIMx output 2 waveform to active or inactive level. |
mbed_official | 157:90e3acc479a2 | 1400 | * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM |
mbed_official | 157:90e3acc479a2 | 1401 | * peripheral. |
mbed_official | 157:90e3acc479a2 | 1402 | * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. |
mbed_official | 157:90e3acc479a2 | 1403 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 1404 | * @arg TIM_ForcedAction_Active: Force active level on OC2REF |
mbed_official | 157:90e3acc479a2 | 1405 | * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. |
mbed_official | 157:90e3acc479a2 | 1406 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1407 | */ |
mbed_official | 157:90e3acc479a2 | 1408 | void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) |
mbed_official | 157:90e3acc479a2 | 1409 | { |
mbed_official | 157:90e3acc479a2 | 1410 | uint32_t tmpccmr1 = 0; |
mbed_official | 157:90e3acc479a2 | 1411 | |
mbed_official | 157:90e3acc479a2 | 1412 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1413 | assert_param(IS_TIM_LIST2_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1414 | assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); |
mbed_official | 157:90e3acc479a2 | 1415 | tmpccmr1 = TIMx->CCMR1; |
mbed_official | 157:90e3acc479a2 | 1416 | |
mbed_official | 157:90e3acc479a2 | 1417 | /* Reset the OC2M Bits */ |
mbed_official | 157:90e3acc479a2 | 1418 | tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC2M; |
mbed_official | 157:90e3acc479a2 | 1419 | |
mbed_official | 157:90e3acc479a2 | 1420 | /* Configure The Forced output Mode */ |
mbed_official | 157:90e3acc479a2 | 1421 | tmpccmr1 |= ((uint32_t)TIM_ForcedAction << 8); |
mbed_official | 157:90e3acc479a2 | 1422 | |
mbed_official | 157:90e3acc479a2 | 1423 | /* Write to TIMx CCMR1 register */ |
mbed_official | 157:90e3acc479a2 | 1424 | TIMx->CCMR1 = tmpccmr1; |
mbed_official | 157:90e3acc479a2 | 1425 | } |
mbed_official | 157:90e3acc479a2 | 1426 | |
mbed_official | 157:90e3acc479a2 | 1427 | /** |
mbed_official | 157:90e3acc479a2 | 1428 | * @brief Forces the TIMx output 3 waveform to active or inactive level. |
mbed_official | 157:90e3acc479a2 | 1429 | * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1430 | * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. |
mbed_official | 157:90e3acc479a2 | 1431 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 1432 | * @arg TIM_ForcedAction_Active: Force active level on OC3REF |
mbed_official | 157:90e3acc479a2 | 1433 | * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. |
mbed_official | 157:90e3acc479a2 | 1434 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1435 | */ |
mbed_official | 157:90e3acc479a2 | 1436 | void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) |
mbed_official | 157:90e3acc479a2 | 1437 | { |
mbed_official | 157:90e3acc479a2 | 1438 | uint32_t tmpccmr2 = 0; |
mbed_official | 157:90e3acc479a2 | 1439 | |
mbed_official | 157:90e3acc479a2 | 1440 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1441 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1442 | assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); |
mbed_official | 157:90e3acc479a2 | 1443 | |
mbed_official | 157:90e3acc479a2 | 1444 | tmpccmr2 = TIMx->CCMR2; |
mbed_official | 157:90e3acc479a2 | 1445 | |
mbed_official | 157:90e3acc479a2 | 1446 | /* Reset the OC1M Bits */ |
mbed_official | 157:90e3acc479a2 | 1447 | tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3M; |
mbed_official | 157:90e3acc479a2 | 1448 | |
mbed_official | 157:90e3acc479a2 | 1449 | /* Configure The Forced output Mode */ |
mbed_official | 157:90e3acc479a2 | 1450 | tmpccmr2 |= TIM_ForcedAction; |
mbed_official | 157:90e3acc479a2 | 1451 | |
mbed_official | 157:90e3acc479a2 | 1452 | /* Write to TIMx CCMR2 register */ |
mbed_official | 157:90e3acc479a2 | 1453 | TIMx->CCMR2 = tmpccmr2; |
mbed_official | 157:90e3acc479a2 | 1454 | } |
mbed_official | 157:90e3acc479a2 | 1455 | |
mbed_official | 157:90e3acc479a2 | 1456 | /** |
mbed_official | 157:90e3acc479a2 | 1457 | * @brief Forces the TIMx output 4 waveform to active or inactive level. |
mbed_official | 157:90e3acc479a2 | 1458 | * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1459 | * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. |
mbed_official | 157:90e3acc479a2 | 1460 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 1461 | * @arg TIM_ForcedAction_Active: Force active level on OC4REF |
mbed_official | 157:90e3acc479a2 | 1462 | * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. |
mbed_official | 157:90e3acc479a2 | 1463 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1464 | */ |
mbed_official | 157:90e3acc479a2 | 1465 | void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) |
mbed_official | 157:90e3acc479a2 | 1466 | { |
mbed_official | 157:90e3acc479a2 | 1467 | uint32_t tmpccmr2 = 0; |
mbed_official | 157:90e3acc479a2 | 1468 | |
mbed_official | 157:90e3acc479a2 | 1469 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1470 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1471 | assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); |
mbed_official | 157:90e3acc479a2 | 1472 | tmpccmr2 = TIMx->CCMR2; |
mbed_official | 157:90e3acc479a2 | 1473 | |
mbed_official | 157:90e3acc479a2 | 1474 | /* Reset the OC2M Bits */ |
mbed_official | 157:90e3acc479a2 | 1475 | tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC4M; |
mbed_official | 157:90e3acc479a2 | 1476 | |
mbed_official | 157:90e3acc479a2 | 1477 | /* Configure The Forced output Mode */ |
mbed_official | 157:90e3acc479a2 | 1478 | tmpccmr2 |= ((uint32_t)TIM_ForcedAction << 8); |
mbed_official | 157:90e3acc479a2 | 1479 | |
mbed_official | 157:90e3acc479a2 | 1480 | /* Write to TIMx CCMR2 register */ |
mbed_official | 157:90e3acc479a2 | 1481 | TIMx->CCMR2 = tmpccmr2; |
mbed_official | 157:90e3acc479a2 | 1482 | } |
mbed_official | 157:90e3acc479a2 | 1483 | |
mbed_official | 157:90e3acc479a2 | 1484 | /** |
mbed_official | 157:90e3acc479a2 | 1485 | * @brief Forces the TIMx output 5 waveform to active or inactive level. |
mbed_official | 157:90e3acc479a2 | 1486 | * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1487 | * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. |
mbed_official | 157:90e3acc479a2 | 1488 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 1489 | * @arg TIM_ForcedAction_Active: Force active level on OC5REF |
mbed_official | 157:90e3acc479a2 | 1490 | * @arg TIM_ForcedAction_InActive: Force inactive level on OC5REF. |
mbed_official | 157:90e3acc479a2 | 1491 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1492 | */ |
mbed_official | 157:90e3acc479a2 | 1493 | void TIM_ForcedOC5Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) |
mbed_official | 157:90e3acc479a2 | 1494 | { |
mbed_official | 157:90e3acc479a2 | 1495 | uint32_t tmpccmr3 = 0; |
mbed_official | 157:90e3acc479a2 | 1496 | |
mbed_official | 157:90e3acc479a2 | 1497 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1498 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1499 | assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); |
mbed_official | 157:90e3acc479a2 | 1500 | tmpccmr3 = TIMx->CCMR3; |
mbed_official | 157:90e3acc479a2 | 1501 | |
mbed_official | 157:90e3acc479a2 | 1502 | /* Reset the OC5M Bits */ |
mbed_official | 157:90e3acc479a2 | 1503 | tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC5M; |
mbed_official | 157:90e3acc479a2 | 1504 | |
mbed_official | 157:90e3acc479a2 | 1505 | /* Configure The Forced output Mode */ |
mbed_official | 157:90e3acc479a2 | 1506 | tmpccmr3 |= (uint32_t)(TIM_ForcedAction); |
mbed_official | 157:90e3acc479a2 | 1507 | |
mbed_official | 157:90e3acc479a2 | 1508 | /* Write to TIMx CCMR3 register */ |
mbed_official | 157:90e3acc479a2 | 1509 | TIMx->CCMR3 = tmpccmr3; |
mbed_official | 157:90e3acc479a2 | 1510 | } |
mbed_official | 157:90e3acc479a2 | 1511 | |
mbed_official | 157:90e3acc479a2 | 1512 | /** |
mbed_official | 157:90e3acc479a2 | 1513 | * @brief Forces the TIMx output 6 waveform to active or inactive level. |
mbed_official | 157:90e3acc479a2 | 1514 | * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1515 | * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. |
mbed_official | 157:90e3acc479a2 | 1516 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 1517 | * @arg TIM_ForcedAction_Active: Force active level on OC5REF |
mbed_official | 157:90e3acc479a2 | 1518 | * @arg TIM_ForcedAction_InActive: Force inactive level on OC5REF. |
mbed_official | 157:90e3acc479a2 | 1519 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1520 | */ |
mbed_official | 157:90e3acc479a2 | 1521 | void TIM_ForcedOC6Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) |
mbed_official | 157:90e3acc479a2 | 1522 | { |
mbed_official | 157:90e3acc479a2 | 1523 | uint32_t tmpccmr3 = 0; |
mbed_official | 157:90e3acc479a2 | 1524 | |
mbed_official | 157:90e3acc479a2 | 1525 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1526 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1527 | assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); |
mbed_official | 157:90e3acc479a2 | 1528 | tmpccmr3 = TIMx->CCMR3; |
mbed_official | 157:90e3acc479a2 | 1529 | |
mbed_official | 157:90e3acc479a2 | 1530 | /* Reset the OC6M Bits */ |
mbed_official | 157:90e3acc479a2 | 1531 | tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC6M; |
mbed_official | 157:90e3acc479a2 | 1532 | |
mbed_official | 157:90e3acc479a2 | 1533 | /* Configure The Forced output Mode */ |
mbed_official | 157:90e3acc479a2 | 1534 | tmpccmr3 |= ((uint32_t)TIM_ForcedAction << 8); |
mbed_official | 157:90e3acc479a2 | 1535 | |
mbed_official | 157:90e3acc479a2 | 1536 | /* Write to TIMx CCMR3 register */ |
mbed_official | 157:90e3acc479a2 | 1537 | TIMx->CCMR3 = tmpccmr3; |
mbed_official | 157:90e3acc479a2 | 1538 | } |
mbed_official | 157:90e3acc479a2 | 1539 | |
mbed_official | 157:90e3acc479a2 | 1540 | /** |
mbed_official | 157:90e3acc479a2 | 1541 | * @brief Enables or disables the TIMx peripheral Preload register on CCR1. |
mbed_official | 157:90e3acc479a2 | 1542 | * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1543 | * @param TIM_OCPreload: new state of the TIMx peripheral Preload register |
mbed_official | 157:90e3acc479a2 | 1544 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 1545 | * @arg TIM_OCPreload_Enable |
mbed_official | 157:90e3acc479a2 | 1546 | * @arg TIM_OCPreload_Disable |
mbed_official | 157:90e3acc479a2 | 1547 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1548 | */ |
mbed_official | 157:90e3acc479a2 | 1549 | void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) |
mbed_official | 157:90e3acc479a2 | 1550 | { |
mbed_official | 157:90e3acc479a2 | 1551 | uint32_t tmpccmr1 = 0; |
mbed_official | 157:90e3acc479a2 | 1552 | |
mbed_official | 157:90e3acc479a2 | 1553 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1554 | assert_param(IS_TIM_LIST1_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1555 | assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); |
mbed_official | 157:90e3acc479a2 | 1556 | |
mbed_official | 157:90e3acc479a2 | 1557 | tmpccmr1 = TIMx->CCMR1; |
mbed_official | 157:90e3acc479a2 | 1558 | |
mbed_official | 157:90e3acc479a2 | 1559 | /* Reset the OC1PE Bit */ |
mbed_official | 157:90e3acc479a2 | 1560 | tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC1PE); |
mbed_official | 157:90e3acc479a2 | 1561 | |
mbed_official | 157:90e3acc479a2 | 1562 | /* Enable or Disable the Output Compare Preload feature */ |
mbed_official | 157:90e3acc479a2 | 1563 | tmpccmr1 |= TIM_OCPreload; |
mbed_official | 157:90e3acc479a2 | 1564 | |
mbed_official | 157:90e3acc479a2 | 1565 | /* Write to TIMx CCMR1 register */ |
mbed_official | 157:90e3acc479a2 | 1566 | TIMx->CCMR1 = tmpccmr1; |
mbed_official | 157:90e3acc479a2 | 1567 | } |
mbed_official | 157:90e3acc479a2 | 1568 | |
mbed_official | 157:90e3acc479a2 | 1569 | /** |
mbed_official | 157:90e3acc479a2 | 1570 | * @brief Enables or disables the TIMx peripheral Preload register on CCR2. |
mbed_official | 157:90e3acc479a2 | 1571 | * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM |
mbed_official | 157:90e3acc479a2 | 1572 | * peripheral. |
mbed_official | 157:90e3acc479a2 | 1573 | * @param TIM_OCPreload: new state of the TIMx peripheral Preload register |
mbed_official | 157:90e3acc479a2 | 1574 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 1575 | * @arg TIM_OCPreload_Enable |
mbed_official | 157:90e3acc479a2 | 1576 | * @arg TIM_OCPreload_Disable |
mbed_official | 157:90e3acc479a2 | 1577 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1578 | */ |
mbed_official | 157:90e3acc479a2 | 1579 | void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) |
mbed_official | 157:90e3acc479a2 | 1580 | { |
mbed_official | 157:90e3acc479a2 | 1581 | uint32_t tmpccmr1 = 0; |
mbed_official | 157:90e3acc479a2 | 1582 | |
mbed_official | 157:90e3acc479a2 | 1583 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1584 | assert_param(IS_TIM_LIST2_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1585 | assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); |
mbed_official | 157:90e3acc479a2 | 1586 | |
mbed_official | 157:90e3acc479a2 | 1587 | tmpccmr1 = TIMx->CCMR1; |
mbed_official | 157:90e3acc479a2 | 1588 | |
mbed_official | 157:90e3acc479a2 | 1589 | /* Reset the OC2PE Bit */ |
mbed_official | 157:90e3acc479a2 | 1590 | tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC2PE); |
mbed_official | 157:90e3acc479a2 | 1591 | |
mbed_official | 157:90e3acc479a2 | 1592 | /* Enable or Disable the Output Compare Preload feature */ |
mbed_official | 157:90e3acc479a2 | 1593 | tmpccmr1 |= ((uint32_t)TIM_OCPreload << 8); |
mbed_official | 157:90e3acc479a2 | 1594 | |
mbed_official | 157:90e3acc479a2 | 1595 | /* Write to TIMx CCMR1 register */ |
mbed_official | 157:90e3acc479a2 | 1596 | TIMx->CCMR1 = tmpccmr1; |
mbed_official | 157:90e3acc479a2 | 1597 | } |
mbed_official | 157:90e3acc479a2 | 1598 | |
mbed_official | 157:90e3acc479a2 | 1599 | /** |
mbed_official | 157:90e3acc479a2 | 1600 | * @brief Enables or disables the TIMx peripheral Preload register on CCR3. |
mbed_official | 157:90e3acc479a2 | 1601 | * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1602 | * @param TIM_OCPreload: new state of the TIMx peripheral Preload register |
mbed_official | 157:90e3acc479a2 | 1603 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 1604 | * @arg TIM_OCPreload_Enable |
mbed_official | 157:90e3acc479a2 | 1605 | * @arg TIM_OCPreload_Disable |
mbed_official | 157:90e3acc479a2 | 1606 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1607 | */ |
mbed_official | 157:90e3acc479a2 | 1608 | void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) |
mbed_official | 157:90e3acc479a2 | 1609 | { |
mbed_official | 157:90e3acc479a2 | 1610 | uint32_t tmpccmr2 = 0; |
mbed_official | 157:90e3acc479a2 | 1611 | |
mbed_official | 157:90e3acc479a2 | 1612 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1613 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1614 | assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); |
mbed_official | 157:90e3acc479a2 | 1615 | |
mbed_official | 157:90e3acc479a2 | 1616 | tmpccmr2 = TIMx->CCMR2; |
mbed_official | 157:90e3acc479a2 | 1617 | |
mbed_official | 157:90e3acc479a2 | 1618 | /* Reset the OC3PE Bit */ |
mbed_official | 157:90e3acc479a2 | 1619 | tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC3PE); |
mbed_official | 157:90e3acc479a2 | 1620 | |
mbed_official | 157:90e3acc479a2 | 1621 | /* Enable or Disable the Output Compare Preload feature */ |
mbed_official | 157:90e3acc479a2 | 1622 | tmpccmr2 |= TIM_OCPreload; |
mbed_official | 157:90e3acc479a2 | 1623 | |
mbed_official | 157:90e3acc479a2 | 1624 | /* Write to TIMx CCMR2 register */ |
mbed_official | 157:90e3acc479a2 | 1625 | TIMx->CCMR2 = tmpccmr2; |
mbed_official | 157:90e3acc479a2 | 1626 | } |
mbed_official | 157:90e3acc479a2 | 1627 | |
mbed_official | 157:90e3acc479a2 | 1628 | /** |
mbed_official | 157:90e3acc479a2 | 1629 | * @brief Enables or disables the TIMx peripheral Preload register on CCR4. |
mbed_official | 157:90e3acc479a2 | 1630 | * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1631 | * @param TIM_OCPreload: new state of the TIMx peripheral Preload register |
mbed_official | 157:90e3acc479a2 | 1632 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 1633 | * @arg TIM_OCPreload_Enable |
mbed_official | 157:90e3acc479a2 | 1634 | * @arg TIM_OCPreload_Disable |
mbed_official | 157:90e3acc479a2 | 1635 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1636 | */ |
mbed_official | 157:90e3acc479a2 | 1637 | void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) |
mbed_official | 157:90e3acc479a2 | 1638 | { |
mbed_official | 157:90e3acc479a2 | 1639 | uint32_t tmpccmr2 = 0; |
mbed_official | 157:90e3acc479a2 | 1640 | |
mbed_official | 157:90e3acc479a2 | 1641 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1642 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1643 | assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); |
mbed_official | 157:90e3acc479a2 | 1644 | |
mbed_official | 157:90e3acc479a2 | 1645 | tmpccmr2 = TIMx->CCMR2; |
mbed_official | 157:90e3acc479a2 | 1646 | |
mbed_official | 157:90e3acc479a2 | 1647 | /* Reset the OC4PE Bit */ |
mbed_official | 157:90e3acc479a2 | 1648 | tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC4PE); |
mbed_official | 157:90e3acc479a2 | 1649 | |
mbed_official | 157:90e3acc479a2 | 1650 | /* Enable or Disable the Output Compare Preload feature */ |
mbed_official | 157:90e3acc479a2 | 1651 | tmpccmr2 |= ((uint32_t)TIM_OCPreload << 8); |
mbed_official | 157:90e3acc479a2 | 1652 | |
mbed_official | 157:90e3acc479a2 | 1653 | /* Write to TIMx CCMR2 register */ |
mbed_official | 157:90e3acc479a2 | 1654 | TIMx->CCMR2 = tmpccmr2; |
mbed_official | 157:90e3acc479a2 | 1655 | } |
mbed_official | 157:90e3acc479a2 | 1656 | |
mbed_official | 157:90e3acc479a2 | 1657 | /** |
mbed_official | 157:90e3acc479a2 | 1658 | * @brief Enables or disables the TIMx peripheral Preload register on CCR5. |
mbed_official | 157:90e3acc479a2 | 1659 | * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1660 | * @param TIM_OCPreload: new state of the TIMx peripheral Preload register |
mbed_official | 157:90e3acc479a2 | 1661 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 1662 | * @arg TIM_OCPreload_Enable |
mbed_official | 157:90e3acc479a2 | 1663 | * @arg TIM_OCPreload_Disable |
mbed_official | 157:90e3acc479a2 | 1664 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1665 | */ |
mbed_official | 157:90e3acc479a2 | 1666 | void TIM_OC5PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) |
mbed_official | 157:90e3acc479a2 | 1667 | { |
mbed_official | 157:90e3acc479a2 | 1668 | uint32_t tmpccmr3 = 0; |
mbed_official | 157:90e3acc479a2 | 1669 | |
mbed_official | 157:90e3acc479a2 | 1670 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1671 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1672 | assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); |
mbed_official | 157:90e3acc479a2 | 1673 | |
mbed_official | 157:90e3acc479a2 | 1674 | tmpccmr3 = TIMx->CCMR3; |
mbed_official | 157:90e3acc479a2 | 1675 | |
mbed_official | 157:90e3acc479a2 | 1676 | /* Reset the OC5PE Bit */ |
mbed_official | 157:90e3acc479a2 | 1677 | tmpccmr3 &= (uint32_t)(~TIM_CCMR3_OC5PE); |
mbed_official | 157:90e3acc479a2 | 1678 | |
mbed_official | 157:90e3acc479a2 | 1679 | /* Enable or Disable the Output Compare Preload feature */ |
mbed_official | 157:90e3acc479a2 | 1680 | tmpccmr3 |= (uint32_t)(TIM_OCPreload); |
mbed_official | 157:90e3acc479a2 | 1681 | |
mbed_official | 157:90e3acc479a2 | 1682 | /* Write to TIMx CCMR3 register */ |
mbed_official | 157:90e3acc479a2 | 1683 | TIMx->CCMR3 = tmpccmr3; |
mbed_official | 157:90e3acc479a2 | 1684 | } |
mbed_official | 157:90e3acc479a2 | 1685 | |
mbed_official | 157:90e3acc479a2 | 1686 | /** |
mbed_official | 157:90e3acc479a2 | 1687 | * @brief Enables or disables the TIMx peripheral Preload register on CCR6. |
mbed_official | 157:90e3acc479a2 | 1688 | * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1689 | * @param TIM_OCPreload: new state of the TIMx peripheral Preload register |
mbed_official | 157:90e3acc479a2 | 1690 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 1691 | * @arg TIM_OCPreload_Enable |
mbed_official | 157:90e3acc479a2 | 1692 | * @arg TIM_OCPreload_Disable |
mbed_official | 157:90e3acc479a2 | 1693 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1694 | */ |
mbed_official | 157:90e3acc479a2 | 1695 | void TIM_OC6PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) |
mbed_official | 157:90e3acc479a2 | 1696 | { |
mbed_official | 157:90e3acc479a2 | 1697 | uint32_t tmpccmr3 = 0; |
mbed_official | 157:90e3acc479a2 | 1698 | |
mbed_official | 157:90e3acc479a2 | 1699 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1700 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1701 | assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); |
mbed_official | 157:90e3acc479a2 | 1702 | |
mbed_official | 157:90e3acc479a2 | 1703 | tmpccmr3 = TIMx->CCMR3; |
mbed_official | 157:90e3acc479a2 | 1704 | |
mbed_official | 157:90e3acc479a2 | 1705 | /* Reset the OC5PE Bit */ |
mbed_official | 157:90e3acc479a2 | 1706 | tmpccmr3 &= (uint32_t)(~TIM_CCMR3_OC6PE); |
mbed_official | 157:90e3acc479a2 | 1707 | |
mbed_official | 157:90e3acc479a2 | 1708 | /* Enable or Disable the Output Compare Preload feature */ |
mbed_official | 157:90e3acc479a2 | 1709 | tmpccmr3 |= ((uint32_t)TIM_OCPreload << 8); |
mbed_official | 157:90e3acc479a2 | 1710 | |
mbed_official | 157:90e3acc479a2 | 1711 | /* Write to TIMx CCMR3 register */ |
mbed_official | 157:90e3acc479a2 | 1712 | TIMx->CCMR3 = tmpccmr3; |
mbed_official | 157:90e3acc479a2 | 1713 | } |
mbed_official | 157:90e3acc479a2 | 1714 | |
mbed_official | 157:90e3acc479a2 | 1715 | /** |
mbed_official | 157:90e3acc479a2 | 1716 | * @brief Configures the TIMx Output Compare 1 Fast feature. |
mbed_official | 157:90e3acc479a2 | 1717 | * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1718 | * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. |
mbed_official | 157:90e3acc479a2 | 1719 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 1720 | * @arg TIM_OCFast_Enable: TIM output compare fast enable |
mbed_official | 157:90e3acc479a2 | 1721 | * @arg TIM_OCFast_Disable: TIM output compare fast disable |
mbed_official | 157:90e3acc479a2 | 1722 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1723 | */ |
mbed_official | 157:90e3acc479a2 | 1724 | void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) |
mbed_official | 157:90e3acc479a2 | 1725 | { |
mbed_official | 157:90e3acc479a2 | 1726 | uint32_t tmpccmr1 = 0; |
mbed_official | 157:90e3acc479a2 | 1727 | |
mbed_official | 157:90e3acc479a2 | 1728 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1729 | assert_param(IS_TIM_LIST1_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1730 | assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); |
mbed_official | 157:90e3acc479a2 | 1731 | |
mbed_official | 157:90e3acc479a2 | 1732 | /* Get the TIMx CCMR1 register value */ |
mbed_official | 157:90e3acc479a2 | 1733 | tmpccmr1 = TIMx->CCMR1; |
mbed_official | 157:90e3acc479a2 | 1734 | |
mbed_official | 157:90e3acc479a2 | 1735 | /* Reset the OC1FE Bit */ |
mbed_official | 157:90e3acc479a2 | 1736 | tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1FE; |
mbed_official | 157:90e3acc479a2 | 1737 | |
mbed_official | 157:90e3acc479a2 | 1738 | /* Enable or Disable the Output Compare Fast Bit */ |
mbed_official | 157:90e3acc479a2 | 1739 | tmpccmr1 |= TIM_OCFast; |
mbed_official | 157:90e3acc479a2 | 1740 | |
mbed_official | 157:90e3acc479a2 | 1741 | /* Write to TIMx CCMR1 */ |
mbed_official | 157:90e3acc479a2 | 1742 | TIMx->CCMR1 = tmpccmr1; |
mbed_official | 157:90e3acc479a2 | 1743 | } |
mbed_official | 157:90e3acc479a2 | 1744 | |
mbed_official | 157:90e3acc479a2 | 1745 | /** |
mbed_official | 157:90e3acc479a2 | 1746 | * @brief Configures the TIMx Output Compare 2 Fast feature. |
mbed_official | 157:90e3acc479a2 | 1747 | * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM |
mbed_official | 157:90e3acc479a2 | 1748 | * peripheral. |
mbed_official | 157:90e3acc479a2 | 1749 | * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. |
mbed_official | 157:90e3acc479a2 | 1750 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 1751 | * @arg TIM_OCFast_Enable: TIM output compare fast enable |
mbed_official | 157:90e3acc479a2 | 1752 | * @arg TIM_OCFast_Disable: TIM output compare fast disable |
mbed_official | 157:90e3acc479a2 | 1753 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1754 | */ |
mbed_official | 157:90e3acc479a2 | 1755 | void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) |
mbed_official | 157:90e3acc479a2 | 1756 | { |
mbed_official | 157:90e3acc479a2 | 1757 | uint32_t tmpccmr1 = 0; |
mbed_official | 157:90e3acc479a2 | 1758 | |
mbed_official | 157:90e3acc479a2 | 1759 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1760 | assert_param(IS_TIM_LIST2_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1761 | assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); |
mbed_official | 157:90e3acc479a2 | 1762 | |
mbed_official | 157:90e3acc479a2 | 1763 | /* Get the TIMx CCMR1 register value */ |
mbed_official | 157:90e3acc479a2 | 1764 | tmpccmr1 = TIMx->CCMR1; |
mbed_official | 157:90e3acc479a2 | 1765 | |
mbed_official | 157:90e3acc479a2 | 1766 | /* Reset the OC2FE Bit */ |
mbed_official | 157:90e3acc479a2 | 1767 | tmpccmr1 &= (uint32_t)(~TIM_CCMR1_OC2FE); |
mbed_official | 157:90e3acc479a2 | 1768 | |
mbed_official | 157:90e3acc479a2 | 1769 | /* Enable or Disable the Output Compare Fast Bit */ |
mbed_official | 157:90e3acc479a2 | 1770 | tmpccmr1 |= ((uint32_t)TIM_OCFast << 8); |
mbed_official | 157:90e3acc479a2 | 1771 | |
mbed_official | 157:90e3acc479a2 | 1772 | /* Write to TIMx CCMR1 */ |
mbed_official | 157:90e3acc479a2 | 1773 | TIMx->CCMR1 = tmpccmr1; |
mbed_official | 157:90e3acc479a2 | 1774 | } |
mbed_official | 157:90e3acc479a2 | 1775 | |
mbed_official | 157:90e3acc479a2 | 1776 | /** |
mbed_official | 157:90e3acc479a2 | 1777 | * @brief Configures the TIMx Output Compare 3 Fast feature. |
mbed_official | 157:90e3acc479a2 | 1778 | * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1779 | * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. |
mbed_official | 157:90e3acc479a2 | 1780 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 1781 | * @arg TIM_OCFast_Enable: TIM output compare fast enable |
mbed_official | 157:90e3acc479a2 | 1782 | * @arg TIM_OCFast_Disable: TIM output compare fast disable |
mbed_official | 157:90e3acc479a2 | 1783 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1784 | */ |
mbed_official | 157:90e3acc479a2 | 1785 | void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) |
mbed_official | 157:90e3acc479a2 | 1786 | { |
mbed_official | 157:90e3acc479a2 | 1787 | uint32_t tmpccmr2 = 0; |
mbed_official | 157:90e3acc479a2 | 1788 | |
mbed_official | 157:90e3acc479a2 | 1789 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1790 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1791 | assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); |
mbed_official | 157:90e3acc479a2 | 1792 | |
mbed_official | 157:90e3acc479a2 | 1793 | /* Get the TIMx CCMR2 register value */ |
mbed_official | 157:90e3acc479a2 | 1794 | tmpccmr2 = TIMx->CCMR2; |
mbed_official | 157:90e3acc479a2 | 1795 | |
mbed_official | 157:90e3acc479a2 | 1796 | /* Reset the OC3FE Bit */ |
mbed_official | 157:90e3acc479a2 | 1797 | tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3FE; |
mbed_official | 157:90e3acc479a2 | 1798 | |
mbed_official | 157:90e3acc479a2 | 1799 | /* Enable or Disable the Output Compare Fast Bit */ |
mbed_official | 157:90e3acc479a2 | 1800 | tmpccmr2 |= TIM_OCFast; |
mbed_official | 157:90e3acc479a2 | 1801 | |
mbed_official | 157:90e3acc479a2 | 1802 | /* Write to TIMx CCMR2 */ |
mbed_official | 157:90e3acc479a2 | 1803 | TIMx->CCMR2 = tmpccmr2; |
mbed_official | 157:90e3acc479a2 | 1804 | } |
mbed_official | 157:90e3acc479a2 | 1805 | |
mbed_official | 157:90e3acc479a2 | 1806 | /** |
mbed_official | 157:90e3acc479a2 | 1807 | * @brief Configures the TIMx Output Compare 4 Fast feature. |
mbed_official | 157:90e3acc479a2 | 1808 | * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1809 | * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. |
mbed_official | 157:90e3acc479a2 | 1810 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 1811 | * @arg TIM_OCFast_Enable: TIM output compare fast enable |
mbed_official | 157:90e3acc479a2 | 1812 | * @arg TIM_OCFast_Disable: TIM output compare fast disable |
mbed_official | 157:90e3acc479a2 | 1813 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1814 | */ |
mbed_official | 157:90e3acc479a2 | 1815 | void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) |
mbed_official | 157:90e3acc479a2 | 1816 | { |
mbed_official | 157:90e3acc479a2 | 1817 | uint32_t tmpccmr2 = 0; |
mbed_official | 157:90e3acc479a2 | 1818 | |
mbed_official | 157:90e3acc479a2 | 1819 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1820 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1821 | assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); |
mbed_official | 157:90e3acc479a2 | 1822 | |
mbed_official | 157:90e3acc479a2 | 1823 | /* Get the TIMx CCMR2 register value */ |
mbed_official | 157:90e3acc479a2 | 1824 | tmpccmr2 = TIMx->CCMR2; |
mbed_official | 157:90e3acc479a2 | 1825 | |
mbed_official | 157:90e3acc479a2 | 1826 | /* Reset the OC4FE Bit */ |
mbed_official | 157:90e3acc479a2 | 1827 | tmpccmr2 &= (uint32_t)(~TIM_CCMR2_OC4FE); |
mbed_official | 157:90e3acc479a2 | 1828 | |
mbed_official | 157:90e3acc479a2 | 1829 | /* Enable or Disable the Output Compare Fast Bit */ |
mbed_official | 157:90e3acc479a2 | 1830 | tmpccmr2 |= ((uint32_t)TIM_OCFast << 8); |
mbed_official | 157:90e3acc479a2 | 1831 | |
mbed_official | 157:90e3acc479a2 | 1832 | /* Write to TIMx CCMR2 */ |
mbed_official | 157:90e3acc479a2 | 1833 | TIMx->CCMR2 = tmpccmr2; |
mbed_official | 157:90e3acc479a2 | 1834 | } |
mbed_official | 157:90e3acc479a2 | 1835 | |
mbed_official | 157:90e3acc479a2 | 1836 | /** |
mbed_official | 157:90e3acc479a2 | 1837 | * @brief Clears or safeguards the OCREF1 signal on an external event |
mbed_official | 157:90e3acc479a2 | 1838 | * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1839 | * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. |
mbed_official | 157:90e3acc479a2 | 1840 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 1841 | * @arg TIM_OCClear_Enable: TIM Output clear enable |
mbed_official | 157:90e3acc479a2 | 1842 | * @arg TIM_OCClear_Disable: TIM Output clear disable |
mbed_official | 157:90e3acc479a2 | 1843 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1844 | */ |
mbed_official | 157:90e3acc479a2 | 1845 | void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) |
mbed_official | 157:90e3acc479a2 | 1846 | { |
mbed_official | 157:90e3acc479a2 | 1847 | uint32_t tmpccmr1 = 0; |
mbed_official | 157:90e3acc479a2 | 1848 | |
mbed_official | 157:90e3acc479a2 | 1849 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1850 | assert_param(IS_TIM_LIST1_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1851 | assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); |
mbed_official | 157:90e3acc479a2 | 1852 | |
mbed_official | 157:90e3acc479a2 | 1853 | tmpccmr1 = TIMx->CCMR1; |
mbed_official | 157:90e3acc479a2 | 1854 | |
mbed_official | 157:90e3acc479a2 | 1855 | /* Reset the OC1CE Bit */ |
mbed_official | 157:90e3acc479a2 | 1856 | tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC1CE; |
mbed_official | 157:90e3acc479a2 | 1857 | |
mbed_official | 157:90e3acc479a2 | 1858 | /* Enable or Disable the Output Compare Clear Bit */ |
mbed_official | 157:90e3acc479a2 | 1859 | tmpccmr1 |= TIM_OCClear; |
mbed_official | 157:90e3acc479a2 | 1860 | |
mbed_official | 157:90e3acc479a2 | 1861 | /* Write to TIMx CCMR1 register */ |
mbed_official | 157:90e3acc479a2 | 1862 | TIMx->CCMR1 = tmpccmr1; |
mbed_official | 157:90e3acc479a2 | 1863 | } |
mbed_official | 157:90e3acc479a2 | 1864 | |
mbed_official | 157:90e3acc479a2 | 1865 | /** |
mbed_official | 157:90e3acc479a2 | 1866 | * @brief Clears or safeguards the OCREF2 signal on an external event |
mbed_official | 157:90e3acc479a2 | 1867 | * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM |
mbed_official | 157:90e3acc479a2 | 1868 | * peripheral. |
mbed_official | 157:90e3acc479a2 | 1869 | * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. |
mbed_official | 157:90e3acc479a2 | 1870 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 1871 | * @arg TIM_OCClear_Enable: TIM Output clear enable |
mbed_official | 157:90e3acc479a2 | 1872 | * @arg TIM_OCClear_Disable: TIM Output clear disable |
mbed_official | 157:90e3acc479a2 | 1873 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1874 | */ |
mbed_official | 157:90e3acc479a2 | 1875 | void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) |
mbed_official | 157:90e3acc479a2 | 1876 | { |
mbed_official | 157:90e3acc479a2 | 1877 | uint32_t tmpccmr1 = 0; |
mbed_official | 157:90e3acc479a2 | 1878 | |
mbed_official | 157:90e3acc479a2 | 1879 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1880 | assert_param(IS_TIM_LIST2_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1881 | assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); |
mbed_official | 157:90e3acc479a2 | 1882 | |
mbed_official | 157:90e3acc479a2 | 1883 | tmpccmr1 = TIMx->CCMR1; |
mbed_official | 157:90e3acc479a2 | 1884 | |
mbed_official | 157:90e3acc479a2 | 1885 | /* Reset the OC2CE Bit */ |
mbed_official | 157:90e3acc479a2 | 1886 | tmpccmr1 &= (uint32_t)~TIM_CCMR1_OC2CE; |
mbed_official | 157:90e3acc479a2 | 1887 | |
mbed_official | 157:90e3acc479a2 | 1888 | /* Enable or Disable the Output Compare Clear Bit */ |
mbed_official | 157:90e3acc479a2 | 1889 | tmpccmr1 |= ((uint32_t)TIM_OCClear << 8); |
mbed_official | 157:90e3acc479a2 | 1890 | |
mbed_official | 157:90e3acc479a2 | 1891 | /* Write to TIMx CCMR1 register */ |
mbed_official | 157:90e3acc479a2 | 1892 | TIMx->CCMR1 = tmpccmr1; |
mbed_official | 157:90e3acc479a2 | 1893 | } |
mbed_official | 157:90e3acc479a2 | 1894 | |
mbed_official | 157:90e3acc479a2 | 1895 | /** |
mbed_official | 157:90e3acc479a2 | 1896 | * @brief Clears or safeguards the OCREF3 signal on an external event |
mbed_official | 157:90e3acc479a2 | 1897 | * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1898 | * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. |
mbed_official | 157:90e3acc479a2 | 1899 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 1900 | * @arg TIM_OCClear_Enable: TIM Output clear enable |
mbed_official | 157:90e3acc479a2 | 1901 | * @arg TIM_OCClear_Disable: TIM Output clear disable |
mbed_official | 157:90e3acc479a2 | 1902 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1903 | */ |
mbed_official | 157:90e3acc479a2 | 1904 | void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) |
mbed_official | 157:90e3acc479a2 | 1905 | { |
mbed_official | 157:90e3acc479a2 | 1906 | uint32_t tmpccmr2 = 0; |
mbed_official | 157:90e3acc479a2 | 1907 | |
mbed_official | 157:90e3acc479a2 | 1908 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1909 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1910 | assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); |
mbed_official | 157:90e3acc479a2 | 1911 | |
mbed_official | 157:90e3acc479a2 | 1912 | tmpccmr2 = TIMx->CCMR2; |
mbed_official | 157:90e3acc479a2 | 1913 | |
mbed_official | 157:90e3acc479a2 | 1914 | /* Reset the OC3CE Bit */ |
mbed_official | 157:90e3acc479a2 | 1915 | tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC3CE; |
mbed_official | 157:90e3acc479a2 | 1916 | |
mbed_official | 157:90e3acc479a2 | 1917 | /* Enable or Disable the Output Compare Clear Bit */ |
mbed_official | 157:90e3acc479a2 | 1918 | tmpccmr2 |= TIM_OCClear; |
mbed_official | 157:90e3acc479a2 | 1919 | |
mbed_official | 157:90e3acc479a2 | 1920 | /* Write to TIMx CCMR2 register */ |
mbed_official | 157:90e3acc479a2 | 1921 | TIMx->CCMR2 = tmpccmr2; |
mbed_official | 157:90e3acc479a2 | 1922 | } |
mbed_official | 157:90e3acc479a2 | 1923 | |
mbed_official | 157:90e3acc479a2 | 1924 | /** |
mbed_official | 157:90e3acc479a2 | 1925 | * @brief Clears or safeguards the OCREF4 signal on an external event |
mbed_official | 157:90e3acc479a2 | 1926 | * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1927 | * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. |
mbed_official | 157:90e3acc479a2 | 1928 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 1929 | * @arg TIM_OCClear_Enable: TIM Output clear enable |
mbed_official | 157:90e3acc479a2 | 1930 | * @arg TIM_OCClear_Disable: TIM Output clear disable |
mbed_official | 157:90e3acc479a2 | 1931 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1932 | */ |
mbed_official | 157:90e3acc479a2 | 1933 | void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) |
mbed_official | 157:90e3acc479a2 | 1934 | { |
mbed_official | 157:90e3acc479a2 | 1935 | uint32_t tmpccmr2 = 0; |
mbed_official | 157:90e3acc479a2 | 1936 | |
mbed_official | 157:90e3acc479a2 | 1937 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1938 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1939 | assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); |
mbed_official | 157:90e3acc479a2 | 1940 | |
mbed_official | 157:90e3acc479a2 | 1941 | tmpccmr2 = TIMx->CCMR2; |
mbed_official | 157:90e3acc479a2 | 1942 | |
mbed_official | 157:90e3acc479a2 | 1943 | /* Reset the OC4CE Bit */ |
mbed_official | 157:90e3acc479a2 | 1944 | tmpccmr2 &= (uint32_t)~TIM_CCMR2_OC4CE; |
mbed_official | 157:90e3acc479a2 | 1945 | |
mbed_official | 157:90e3acc479a2 | 1946 | /* Enable or Disable the Output Compare Clear Bit */ |
mbed_official | 157:90e3acc479a2 | 1947 | tmpccmr2 |= ((uint32_t)TIM_OCClear << 8); |
mbed_official | 157:90e3acc479a2 | 1948 | |
mbed_official | 157:90e3acc479a2 | 1949 | /* Write to TIMx CCMR2 register */ |
mbed_official | 157:90e3acc479a2 | 1950 | TIMx->CCMR2 = tmpccmr2; |
mbed_official | 157:90e3acc479a2 | 1951 | } |
mbed_official | 157:90e3acc479a2 | 1952 | |
mbed_official | 157:90e3acc479a2 | 1953 | /** |
mbed_official | 157:90e3acc479a2 | 1954 | * @brief Clears or safeguards the OCREF5 signal on an external event |
mbed_official | 157:90e3acc479a2 | 1955 | * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1956 | * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. |
mbed_official | 157:90e3acc479a2 | 1957 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 1958 | * @arg TIM_OCClear_Enable: TIM Output clear enable |
mbed_official | 157:90e3acc479a2 | 1959 | * @arg TIM_OCClear_Disable: TIM Output clear disable |
mbed_official | 157:90e3acc479a2 | 1960 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1961 | */ |
mbed_official | 157:90e3acc479a2 | 1962 | void TIM_ClearOC5Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) |
mbed_official | 157:90e3acc479a2 | 1963 | { |
mbed_official | 157:90e3acc479a2 | 1964 | uint32_t tmpccmr3 = 0; |
mbed_official | 157:90e3acc479a2 | 1965 | |
mbed_official | 157:90e3acc479a2 | 1966 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1967 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1968 | assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); |
mbed_official | 157:90e3acc479a2 | 1969 | |
mbed_official | 157:90e3acc479a2 | 1970 | tmpccmr3 = TIMx->CCMR3; |
mbed_official | 157:90e3acc479a2 | 1971 | |
mbed_official | 157:90e3acc479a2 | 1972 | /* Reset the OC5CE Bit */ |
mbed_official | 157:90e3acc479a2 | 1973 | tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC5CE; |
mbed_official | 157:90e3acc479a2 | 1974 | |
mbed_official | 157:90e3acc479a2 | 1975 | /* Enable or Disable the Output Compare Clear Bit */ |
mbed_official | 157:90e3acc479a2 | 1976 | tmpccmr3 |= (uint32_t)(TIM_OCClear); |
mbed_official | 157:90e3acc479a2 | 1977 | |
mbed_official | 157:90e3acc479a2 | 1978 | /* Write to TIMx CCMR3 register */ |
mbed_official | 157:90e3acc479a2 | 1979 | TIMx->CCMR3 = tmpccmr3; |
mbed_official | 157:90e3acc479a2 | 1980 | } |
mbed_official | 157:90e3acc479a2 | 1981 | |
mbed_official | 157:90e3acc479a2 | 1982 | /** |
mbed_official | 157:90e3acc479a2 | 1983 | * @brief Clears or safeguards the OCREF6 signal on an external event |
mbed_official | 157:90e3acc479a2 | 1984 | * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 1985 | * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. |
mbed_official | 157:90e3acc479a2 | 1986 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 1987 | * @arg TIM_OCClear_Enable: TIM Output clear enable |
mbed_official | 157:90e3acc479a2 | 1988 | * @arg TIM_OCClear_Disable: TIM Output clear disable |
mbed_official | 157:90e3acc479a2 | 1989 | * @retval None |
mbed_official | 157:90e3acc479a2 | 1990 | */ |
mbed_official | 157:90e3acc479a2 | 1991 | void TIM_ClearOC6Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) |
mbed_official | 157:90e3acc479a2 | 1992 | { |
mbed_official | 157:90e3acc479a2 | 1993 | uint32_t tmpccmr3 = 0; |
mbed_official | 157:90e3acc479a2 | 1994 | |
mbed_official | 157:90e3acc479a2 | 1995 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 1996 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 1997 | assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); |
mbed_official | 157:90e3acc479a2 | 1998 | |
mbed_official | 157:90e3acc479a2 | 1999 | tmpccmr3 = TIMx->CCMR3; |
mbed_official | 157:90e3acc479a2 | 2000 | |
mbed_official | 157:90e3acc479a2 | 2001 | /* Reset the OC5CE Bit */ |
mbed_official | 157:90e3acc479a2 | 2002 | tmpccmr3 &= (uint32_t)~TIM_CCMR3_OC6CE; |
mbed_official | 157:90e3acc479a2 | 2003 | |
mbed_official | 157:90e3acc479a2 | 2004 | /* Enable or Disable the Output Compare Clear Bit */ |
mbed_official | 157:90e3acc479a2 | 2005 | tmpccmr3 |= ((uint32_t)TIM_OCClear << 8); |
mbed_official | 157:90e3acc479a2 | 2006 | |
mbed_official | 157:90e3acc479a2 | 2007 | /* Write to TIMx CCMR3 register */ |
mbed_official | 157:90e3acc479a2 | 2008 | TIMx->CCMR3 = tmpccmr3; |
mbed_official | 157:90e3acc479a2 | 2009 | } |
mbed_official | 157:90e3acc479a2 | 2010 | |
mbed_official | 157:90e3acc479a2 | 2011 | /** |
mbed_official | 157:90e3acc479a2 | 2012 | * @brief Selects the OCReference Clear source. |
mbed_official | 157:90e3acc479a2 | 2013 | * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 2014 | * @param TIM_OCReferenceClear: specifies the OCReference Clear source. |
mbed_official | 157:90e3acc479a2 | 2015 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 2016 | * @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF. |
mbed_official | 157:90e3acc479a2 | 2017 | * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input. |
mbed_official | 157:90e3acc479a2 | 2018 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2019 | */ |
mbed_official | 157:90e3acc479a2 | 2020 | void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear) |
mbed_official | 157:90e3acc479a2 | 2021 | { |
mbed_official | 157:90e3acc479a2 | 2022 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2023 | assert_param(IS_TIM_LIST2_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2024 | assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear)); |
mbed_official | 157:90e3acc479a2 | 2025 | |
mbed_official | 157:90e3acc479a2 | 2026 | /* Set the TIM_OCReferenceClear source */ |
mbed_official | 157:90e3acc479a2 | 2027 | TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS); |
mbed_official | 157:90e3acc479a2 | 2028 | TIMx->SMCR |= TIM_OCReferenceClear; |
mbed_official | 157:90e3acc479a2 | 2029 | } |
mbed_official | 157:90e3acc479a2 | 2030 | |
mbed_official | 157:90e3acc479a2 | 2031 | /** |
mbed_official | 157:90e3acc479a2 | 2032 | * @brief Configures the TIMx channel 1 polarity. |
mbed_official | 157:90e3acc479a2 | 2033 | * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 2034 | * @param TIM_OCPolarity: specifies the OC1 Polarity |
mbed_official | 157:90e3acc479a2 | 2035 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 2036 | * @arg TIM_OCPolarity_High: Output Compare active high |
mbed_official | 157:90e3acc479a2 | 2037 | * @arg TIM_OCPolarity_Low: Output Compare active low |
mbed_official | 157:90e3acc479a2 | 2038 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2039 | */ |
mbed_official | 157:90e3acc479a2 | 2040 | void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) |
mbed_official | 157:90e3acc479a2 | 2041 | { |
mbed_official | 157:90e3acc479a2 | 2042 | uint32_t tmpccer = 0; |
mbed_official | 157:90e3acc479a2 | 2043 | |
mbed_official | 157:90e3acc479a2 | 2044 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2045 | assert_param(IS_TIM_LIST1_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2046 | assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); |
mbed_official | 157:90e3acc479a2 | 2047 | |
mbed_official | 157:90e3acc479a2 | 2048 | tmpccer = TIMx->CCER; |
mbed_official | 157:90e3acc479a2 | 2049 | |
mbed_official | 157:90e3acc479a2 | 2050 | /* Set or Reset the CC1P Bit */ |
mbed_official | 157:90e3acc479a2 | 2051 | tmpccer &= (uint32_t)(~TIM_CCER_CC1P); |
mbed_official | 157:90e3acc479a2 | 2052 | tmpccer |= TIM_OCPolarity; |
mbed_official | 157:90e3acc479a2 | 2053 | |
mbed_official | 157:90e3acc479a2 | 2054 | /* Write to TIMx CCER register */ |
mbed_official | 157:90e3acc479a2 | 2055 | TIMx->CCER = tmpccer; |
mbed_official | 157:90e3acc479a2 | 2056 | } |
mbed_official | 157:90e3acc479a2 | 2057 | |
mbed_official | 157:90e3acc479a2 | 2058 | /** |
mbed_official | 157:90e3acc479a2 | 2059 | * @brief Configures the TIMx Channel 1N polarity. |
mbed_official | 157:90e3acc479a2 | 2060 | * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 2061 | * @param TIM_OCNPolarity: specifies the OC1N Polarity |
mbed_official | 157:90e3acc479a2 | 2062 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 2063 | * @arg TIM_OCNPolarity_High: Output Compare active high |
mbed_official | 157:90e3acc479a2 | 2064 | * @arg TIM_OCNPolarity_Low: Output Compare active low |
mbed_official | 157:90e3acc479a2 | 2065 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2066 | */ |
mbed_official | 157:90e3acc479a2 | 2067 | void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) |
mbed_official | 157:90e3acc479a2 | 2068 | { |
mbed_official | 157:90e3acc479a2 | 2069 | uint32_t tmpccer = 0; |
mbed_official | 157:90e3acc479a2 | 2070 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2071 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2072 | assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); |
mbed_official | 157:90e3acc479a2 | 2073 | |
mbed_official | 157:90e3acc479a2 | 2074 | tmpccer = TIMx->CCER; |
mbed_official | 157:90e3acc479a2 | 2075 | |
mbed_official | 157:90e3acc479a2 | 2076 | /* Set or Reset the CC1NP Bit */ |
mbed_official | 157:90e3acc479a2 | 2077 | tmpccer &= (uint32_t)~TIM_CCER_CC1NP; |
mbed_official | 157:90e3acc479a2 | 2078 | tmpccer |= TIM_OCNPolarity; |
mbed_official | 157:90e3acc479a2 | 2079 | |
mbed_official | 157:90e3acc479a2 | 2080 | /* Write to TIMx CCER register */ |
mbed_official | 157:90e3acc479a2 | 2081 | TIMx->CCER = tmpccer; |
mbed_official | 157:90e3acc479a2 | 2082 | } |
mbed_official | 157:90e3acc479a2 | 2083 | |
mbed_official | 157:90e3acc479a2 | 2084 | /** |
mbed_official | 157:90e3acc479a2 | 2085 | * @brief Configures the TIMx channel 2 polarity. |
mbed_official | 157:90e3acc479a2 | 2086 | * @param TIMx: where x can be 1, 2, 3, 4 8 or 15 to select the TIM |
mbed_official | 157:90e3acc479a2 | 2087 | * peripheral. |
mbed_official | 157:90e3acc479a2 | 2088 | * @param TIM_OCPolarity: specifies the OC2 Polarity |
mbed_official | 157:90e3acc479a2 | 2089 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 2090 | * @arg TIM_OCPolarity_High: Output Compare active high |
mbed_official | 157:90e3acc479a2 | 2091 | * @arg TIM_OCPolarity_Low: Output Compare active low |
mbed_official | 157:90e3acc479a2 | 2092 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2093 | */ |
mbed_official | 157:90e3acc479a2 | 2094 | void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) |
mbed_official | 157:90e3acc479a2 | 2095 | { |
mbed_official | 157:90e3acc479a2 | 2096 | uint32_t tmpccer = 0; |
mbed_official | 157:90e3acc479a2 | 2097 | |
mbed_official | 157:90e3acc479a2 | 2098 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2099 | assert_param(IS_TIM_LIST2_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2100 | assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); |
mbed_official | 157:90e3acc479a2 | 2101 | |
mbed_official | 157:90e3acc479a2 | 2102 | tmpccer = TIMx->CCER; |
mbed_official | 157:90e3acc479a2 | 2103 | |
mbed_official | 157:90e3acc479a2 | 2104 | /* Set or Reset the CC2P Bit */ |
mbed_official | 157:90e3acc479a2 | 2105 | tmpccer &= (uint32_t)(~TIM_CCER_CC2P); |
mbed_official | 157:90e3acc479a2 | 2106 | tmpccer |= ((uint32_t)TIM_OCPolarity << 4); |
mbed_official | 157:90e3acc479a2 | 2107 | |
mbed_official | 157:90e3acc479a2 | 2108 | /* Write to TIMx CCER register */ |
mbed_official | 157:90e3acc479a2 | 2109 | TIMx->CCER = tmpccer; |
mbed_official | 157:90e3acc479a2 | 2110 | } |
mbed_official | 157:90e3acc479a2 | 2111 | |
mbed_official | 157:90e3acc479a2 | 2112 | /** |
mbed_official | 157:90e3acc479a2 | 2113 | * @brief Configures the TIMx Channel 2N polarity. |
mbed_official | 157:90e3acc479a2 | 2114 | * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 2115 | * @param TIM_OCNPolarity: specifies the OC2N Polarity |
mbed_official | 157:90e3acc479a2 | 2116 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 2117 | * @arg TIM_OCNPolarity_High: Output Compare active high |
mbed_official | 157:90e3acc479a2 | 2118 | * @arg TIM_OCNPolarity_Low: Output Compare active low |
mbed_official | 157:90e3acc479a2 | 2119 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2120 | */ |
mbed_official | 157:90e3acc479a2 | 2121 | void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) |
mbed_official | 157:90e3acc479a2 | 2122 | { |
mbed_official | 157:90e3acc479a2 | 2123 | uint32_t tmpccer = 0; |
mbed_official | 157:90e3acc479a2 | 2124 | |
mbed_official | 157:90e3acc479a2 | 2125 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2126 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2127 | assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); |
mbed_official | 157:90e3acc479a2 | 2128 | |
mbed_official | 157:90e3acc479a2 | 2129 | tmpccer = TIMx->CCER; |
mbed_official | 157:90e3acc479a2 | 2130 | |
mbed_official | 157:90e3acc479a2 | 2131 | /* Set or Reset the CC2NP Bit */ |
mbed_official | 157:90e3acc479a2 | 2132 | tmpccer &= (uint32_t)~TIM_CCER_CC2NP; |
mbed_official | 157:90e3acc479a2 | 2133 | tmpccer |= ((uint32_t)TIM_OCNPolarity << 4); |
mbed_official | 157:90e3acc479a2 | 2134 | |
mbed_official | 157:90e3acc479a2 | 2135 | /* Write to TIMx CCER register */ |
mbed_official | 157:90e3acc479a2 | 2136 | TIMx->CCER = tmpccer; |
mbed_official | 157:90e3acc479a2 | 2137 | } |
mbed_official | 157:90e3acc479a2 | 2138 | |
mbed_official | 157:90e3acc479a2 | 2139 | /** |
mbed_official | 157:90e3acc479a2 | 2140 | * @brief Configures the TIMx channel 3 polarity. |
mbed_official | 157:90e3acc479a2 | 2141 | * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 2142 | * @param TIM_OCPolarity: specifies the OC3 Polarity |
mbed_official | 157:90e3acc479a2 | 2143 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 2144 | * @arg TIM_OCPolarity_High: Output Compare active high |
mbed_official | 157:90e3acc479a2 | 2145 | * @arg TIM_OCPolarity_Low: Output Compare active low |
mbed_official | 157:90e3acc479a2 | 2146 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2147 | */ |
mbed_official | 157:90e3acc479a2 | 2148 | void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) |
mbed_official | 157:90e3acc479a2 | 2149 | { |
mbed_official | 157:90e3acc479a2 | 2150 | uint32_t tmpccer = 0; |
mbed_official | 157:90e3acc479a2 | 2151 | |
mbed_official | 157:90e3acc479a2 | 2152 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2153 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2154 | assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); |
mbed_official | 157:90e3acc479a2 | 2155 | |
mbed_official | 157:90e3acc479a2 | 2156 | tmpccer = TIMx->CCER; |
mbed_official | 157:90e3acc479a2 | 2157 | |
mbed_official | 157:90e3acc479a2 | 2158 | /* Set or Reset the CC3P Bit */ |
mbed_official | 157:90e3acc479a2 | 2159 | tmpccer &= (uint32_t)~TIM_CCER_CC3P; |
mbed_official | 157:90e3acc479a2 | 2160 | tmpccer |= ((uint32_t)TIM_OCPolarity << 8); |
mbed_official | 157:90e3acc479a2 | 2161 | |
mbed_official | 157:90e3acc479a2 | 2162 | /* Write to TIMx CCER register */ |
mbed_official | 157:90e3acc479a2 | 2163 | TIMx->CCER = tmpccer; |
mbed_official | 157:90e3acc479a2 | 2164 | } |
mbed_official | 157:90e3acc479a2 | 2165 | |
mbed_official | 157:90e3acc479a2 | 2166 | /** |
mbed_official | 157:90e3acc479a2 | 2167 | * @brief Configures the TIMx Channel 3N polarity. |
mbed_official | 157:90e3acc479a2 | 2168 | * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 2169 | * @param TIM_OCNPolarity: specifies the OC3N Polarity |
mbed_official | 157:90e3acc479a2 | 2170 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 2171 | * @arg TIM_OCNPolarity_High: Output Compare active high |
mbed_official | 157:90e3acc479a2 | 2172 | * @arg TIM_OCNPolarity_Low: Output Compare active low |
mbed_official | 157:90e3acc479a2 | 2173 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2174 | */ |
mbed_official | 157:90e3acc479a2 | 2175 | void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) |
mbed_official | 157:90e3acc479a2 | 2176 | { |
mbed_official | 157:90e3acc479a2 | 2177 | uint32_t tmpccer = 0; |
mbed_official | 157:90e3acc479a2 | 2178 | |
mbed_official | 157:90e3acc479a2 | 2179 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2180 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2181 | assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); |
mbed_official | 157:90e3acc479a2 | 2182 | |
mbed_official | 157:90e3acc479a2 | 2183 | tmpccer = TIMx->CCER; |
mbed_official | 157:90e3acc479a2 | 2184 | |
mbed_official | 157:90e3acc479a2 | 2185 | /* Set or Reset the CC3NP Bit */ |
mbed_official | 157:90e3acc479a2 | 2186 | tmpccer &= (uint32_t)~TIM_CCER_CC3NP; |
mbed_official | 157:90e3acc479a2 | 2187 | tmpccer |= ((uint32_t)TIM_OCNPolarity << 8); |
mbed_official | 157:90e3acc479a2 | 2188 | |
mbed_official | 157:90e3acc479a2 | 2189 | /* Write to TIMx CCER register */ |
mbed_official | 157:90e3acc479a2 | 2190 | TIMx->CCER = tmpccer; |
mbed_official | 157:90e3acc479a2 | 2191 | } |
mbed_official | 157:90e3acc479a2 | 2192 | |
mbed_official | 157:90e3acc479a2 | 2193 | /** |
mbed_official | 157:90e3acc479a2 | 2194 | * @brief Configures the TIMx channel 4 polarity. |
mbed_official | 157:90e3acc479a2 | 2195 | * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 2196 | * @param TIM_OCPolarity: specifies the OC4 Polarity |
mbed_official | 157:90e3acc479a2 | 2197 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 2198 | * @arg TIM_OCPolarity_High: Output Compare active high |
mbed_official | 157:90e3acc479a2 | 2199 | * @arg TIM_OCPolarity_Low: Output Compare active low |
mbed_official | 157:90e3acc479a2 | 2200 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2201 | */ |
mbed_official | 157:90e3acc479a2 | 2202 | void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) |
mbed_official | 157:90e3acc479a2 | 2203 | { |
mbed_official | 157:90e3acc479a2 | 2204 | uint32_t tmpccer = 0; |
mbed_official | 157:90e3acc479a2 | 2205 | |
mbed_official | 157:90e3acc479a2 | 2206 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2207 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2208 | assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); |
mbed_official | 157:90e3acc479a2 | 2209 | |
mbed_official | 157:90e3acc479a2 | 2210 | tmpccer = TIMx->CCER; |
mbed_official | 157:90e3acc479a2 | 2211 | |
mbed_official | 157:90e3acc479a2 | 2212 | /* Set or Reset the CC4P Bit */ |
mbed_official | 157:90e3acc479a2 | 2213 | tmpccer &= (uint32_t)~TIM_CCER_CC4P; |
mbed_official | 157:90e3acc479a2 | 2214 | tmpccer |= ((uint32_t)TIM_OCPolarity << 12); |
mbed_official | 157:90e3acc479a2 | 2215 | |
mbed_official | 157:90e3acc479a2 | 2216 | /* Write to TIMx CCER register */ |
mbed_official | 157:90e3acc479a2 | 2217 | TIMx->CCER = tmpccer; |
mbed_official | 157:90e3acc479a2 | 2218 | } |
mbed_official | 157:90e3acc479a2 | 2219 | |
mbed_official | 157:90e3acc479a2 | 2220 | /** |
mbed_official | 157:90e3acc479a2 | 2221 | * @brief Configures the TIMx channel 5 polarity. |
mbed_official | 157:90e3acc479a2 | 2222 | * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 2223 | * @param TIM_OCPolarity: specifies the OC5 Polarity |
mbed_official | 157:90e3acc479a2 | 2224 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 2225 | * @arg TIM_OCPolarity_High: Output Compare active high |
mbed_official | 157:90e3acc479a2 | 2226 | * @arg TIM_OCPolarity_Low: Output Compare active low |
mbed_official | 157:90e3acc479a2 | 2227 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2228 | */ |
mbed_official | 157:90e3acc479a2 | 2229 | void TIM_OC5PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) |
mbed_official | 157:90e3acc479a2 | 2230 | { |
mbed_official | 157:90e3acc479a2 | 2231 | uint32_t tmpccer = 0; |
mbed_official | 157:90e3acc479a2 | 2232 | |
mbed_official | 157:90e3acc479a2 | 2233 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2234 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2235 | assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); |
mbed_official | 157:90e3acc479a2 | 2236 | |
mbed_official | 157:90e3acc479a2 | 2237 | tmpccer = TIMx->CCER; |
mbed_official | 157:90e3acc479a2 | 2238 | |
mbed_official | 157:90e3acc479a2 | 2239 | /* Set or Reset the CC5P Bit */ |
mbed_official | 157:90e3acc479a2 | 2240 | tmpccer &= (uint32_t)~TIM_CCER_CC5P; |
mbed_official | 157:90e3acc479a2 | 2241 | tmpccer |= ((uint32_t)TIM_OCPolarity << 16); |
mbed_official | 157:90e3acc479a2 | 2242 | |
mbed_official | 157:90e3acc479a2 | 2243 | /* Write to TIMx CCER register */ |
mbed_official | 157:90e3acc479a2 | 2244 | TIMx->CCER = tmpccer; |
mbed_official | 157:90e3acc479a2 | 2245 | } |
mbed_official | 157:90e3acc479a2 | 2246 | |
mbed_official | 157:90e3acc479a2 | 2247 | /** |
mbed_official | 157:90e3acc479a2 | 2248 | * @brief Configures the TIMx channel 6 polarity. |
mbed_official | 157:90e3acc479a2 | 2249 | * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 2250 | * @param TIM_OCPolarity: specifies the OC6 Polarity |
mbed_official | 157:90e3acc479a2 | 2251 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 2252 | * @arg TIM_OCPolarity_High: Output Compare active high |
mbed_official | 157:90e3acc479a2 | 2253 | * @arg TIM_OCPolarity_Low: Output Compare active low |
mbed_official | 157:90e3acc479a2 | 2254 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2255 | */ |
mbed_official | 157:90e3acc479a2 | 2256 | void TIM_OC6PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) |
mbed_official | 157:90e3acc479a2 | 2257 | { |
mbed_official | 157:90e3acc479a2 | 2258 | uint32_t tmpccer = 0; |
mbed_official | 157:90e3acc479a2 | 2259 | |
mbed_official | 157:90e3acc479a2 | 2260 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2261 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2262 | assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); |
mbed_official | 157:90e3acc479a2 | 2263 | |
mbed_official | 157:90e3acc479a2 | 2264 | tmpccer = TIMx->CCER; |
mbed_official | 157:90e3acc479a2 | 2265 | |
mbed_official | 157:90e3acc479a2 | 2266 | /* Set or Reset the CC6P Bit */ |
mbed_official | 157:90e3acc479a2 | 2267 | tmpccer &= (uint32_t)~TIM_CCER_CC6P; |
mbed_official | 157:90e3acc479a2 | 2268 | tmpccer |= ((uint32_t)TIM_OCPolarity << 20); |
mbed_official | 157:90e3acc479a2 | 2269 | |
mbed_official | 157:90e3acc479a2 | 2270 | /* Write to TIMx CCER register */ |
mbed_official | 157:90e3acc479a2 | 2271 | TIMx->CCER = tmpccer; |
mbed_official | 157:90e3acc479a2 | 2272 | } |
mbed_official | 157:90e3acc479a2 | 2273 | |
mbed_official | 157:90e3acc479a2 | 2274 | /** |
mbed_official | 157:90e3acc479a2 | 2275 | * @brief Enables or disables the TIM Capture Compare Channel x. |
mbed_official | 157:90e3acc479a2 | 2276 | * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 2277 | * @param TIM_Channel: specifies the TIM Channel |
mbed_official | 157:90e3acc479a2 | 2278 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 2279 | * @arg TIM_Channel_1: TIM Channel 1 |
mbed_official | 157:90e3acc479a2 | 2280 | * @arg TIM_Channel_2: TIM Channel 2 |
mbed_official | 157:90e3acc479a2 | 2281 | * @arg TIM_Channel_3: TIM Channel 3 |
mbed_official | 157:90e3acc479a2 | 2282 | * @arg TIM_Channel_4: TIM Channel 4 |
mbed_official | 157:90e3acc479a2 | 2283 | * @arg TIM_Channel_5: TIM Channel 5 |
mbed_official | 157:90e3acc479a2 | 2284 | * @arg TIM_Channel_6: TIM Channel 6 |
mbed_official | 157:90e3acc479a2 | 2285 | * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. |
mbed_official | 157:90e3acc479a2 | 2286 | * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. |
mbed_official | 157:90e3acc479a2 | 2287 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2288 | */ |
mbed_official | 157:90e3acc479a2 | 2289 | void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) |
mbed_official | 157:90e3acc479a2 | 2290 | { |
mbed_official | 157:90e3acc479a2 | 2291 | uint32_t tmp = 0; |
mbed_official | 157:90e3acc479a2 | 2292 | |
mbed_official | 157:90e3acc479a2 | 2293 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2294 | assert_param(IS_TIM_LIST1_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2295 | assert_param(IS_TIM_CHANNEL(TIM_Channel)); |
mbed_official | 157:90e3acc479a2 | 2296 | assert_param(IS_TIM_CCX(TIM_CCx)); |
mbed_official | 157:90e3acc479a2 | 2297 | |
mbed_official | 157:90e3acc479a2 | 2298 | tmp = (uint32_t)CCER_CCE_SET << (uint32_t)TIM_Channel; |
mbed_official | 157:90e3acc479a2 | 2299 | |
mbed_official | 157:90e3acc479a2 | 2300 | /* Reset the CCxE Bit */ |
mbed_official | 157:90e3acc479a2 | 2301 | TIMx->CCER &= (uint32_t)(~tmp); |
mbed_official | 157:90e3acc479a2 | 2302 | |
mbed_official | 157:90e3acc479a2 | 2303 | /* Set or reset the CCxE Bit */ |
mbed_official | 157:90e3acc479a2 | 2304 | TIMx->CCER |= ((uint32_t)TIM_CCx << (uint32_t)TIM_Channel); |
mbed_official | 157:90e3acc479a2 | 2305 | } |
mbed_official | 157:90e3acc479a2 | 2306 | |
mbed_official | 157:90e3acc479a2 | 2307 | /** |
mbed_official | 157:90e3acc479a2 | 2308 | * @brief Enables or disables the TIM Capture Compare Channel xN. |
mbed_official | 157:90e3acc479a2 | 2309 | * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 2310 | * @param TIM_Channel: specifies the TIM Channel |
mbed_official | 157:90e3acc479a2 | 2311 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 2312 | * @arg TIM_Channel_1: TIM Channel 1 |
mbed_official | 157:90e3acc479a2 | 2313 | * @arg TIM_Channel_2: TIM Channel 2 |
mbed_official | 157:90e3acc479a2 | 2314 | * @arg TIM_Channel_3: TIM Channel 3 |
mbed_official | 157:90e3acc479a2 | 2315 | * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. |
mbed_official | 157:90e3acc479a2 | 2316 | * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. |
mbed_official | 157:90e3acc479a2 | 2317 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2318 | */ |
mbed_official | 157:90e3acc479a2 | 2319 | void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) |
mbed_official | 157:90e3acc479a2 | 2320 | { |
mbed_official | 157:90e3acc479a2 | 2321 | uint32_t tmp = 0; |
mbed_official | 157:90e3acc479a2 | 2322 | |
mbed_official | 157:90e3acc479a2 | 2323 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2324 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2325 | assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); |
mbed_official | 157:90e3acc479a2 | 2326 | assert_param(IS_TIM_CCXN(TIM_CCxN)); |
mbed_official | 157:90e3acc479a2 | 2327 | |
mbed_official | 157:90e3acc479a2 | 2328 | tmp = (uint32_t)CCER_CCNE_SET << (uint32_t)TIM_Channel; |
mbed_official | 157:90e3acc479a2 | 2329 | |
mbed_official | 157:90e3acc479a2 | 2330 | /* Reset the CCxNE Bit */ |
mbed_official | 157:90e3acc479a2 | 2331 | TIMx->CCER &= (uint32_t) ~tmp; |
mbed_official | 157:90e3acc479a2 | 2332 | |
mbed_official | 157:90e3acc479a2 | 2333 | /* Set or reset the CCxNE Bit */ |
mbed_official | 157:90e3acc479a2 | 2334 | TIMx->CCER |= ((uint32_t)TIM_CCxN << (uint32_t)TIM_Channel); |
mbed_official | 157:90e3acc479a2 | 2335 | } |
mbed_official | 157:90e3acc479a2 | 2336 | /** |
mbed_official | 157:90e3acc479a2 | 2337 | * @} |
mbed_official | 157:90e3acc479a2 | 2338 | */ |
mbed_official | 157:90e3acc479a2 | 2339 | |
mbed_official | 157:90e3acc479a2 | 2340 | /** @defgroup TIM_Group3 Input Capture management functions |
mbed_official | 157:90e3acc479a2 | 2341 | * @brief Input Capture management functions |
mbed_official | 157:90e3acc479a2 | 2342 | * |
mbed_official | 157:90e3acc479a2 | 2343 | @verbatim |
mbed_official | 157:90e3acc479a2 | 2344 | =============================================================================== |
mbed_official | 157:90e3acc479a2 | 2345 | ##### Input Capture management functions ##### |
mbed_official | 157:90e3acc479a2 | 2346 | =============================================================================== |
mbed_official | 157:90e3acc479a2 | 2347 | |
mbed_official | 157:90e3acc479a2 | 2348 | *** TIM Driver: how to use it in Input Capture Mode *** |
mbed_official | 157:90e3acc479a2 | 2349 | ======================================================= |
mbed_official | 157:90e3acc479a2 | 2350 | [..] |
mbed_official | 157:90e3acc479a2 | 2351 | To use the Timer in Input Capture mode, the following steps are mandatory: |
mbed_official | 157:90e3acc479a2 | 2352 | |
mbed_official | 157:90e3acc479a2 | 2353 | (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function |
mbed_official | 157:90e3acc479a2 | 2354 | |
mbed_official | 157:90e3acc479a2 | 2355 | (#) Configure the TIM pins by configuring the corresponding GPIO pins |
mbed_official | 157:90e3acc479a2 | 2356 | |
mbed_official | 157:90e3acc479a2 | 2357 | (#) Configure the Time base unit as described in the first part of this driver, |
mbed_official | 157:90e3acc479a2 | 2358 | if needed, else the Timer will run with the default configuration: |
mbed_official | 157:90e3acc479a2 | 2359 | (++) Autoreload value = 0xFFFF |
mbed_official | 157:90e3acc479a2 | 2360 | (++) Prescaler value = 0x0000 |
mbed_official | 157:90e3acc479a2 | 2361 | (++) Counter mode = Up counting |
mbed_official | 157:90e3acc479a2 | 2362 | (++) Clock Division = TIM_CKD_DIV1 |
mbed_official | 157:90e3acc479a2 | 2363 | |
mbed_official | 157:90e3acc479a2 | 2364 | (#) Fill the TIM_ICInitStruct with the desired parameters including: |
mbed_official | 157:90e3acc479a2 | 2365 | (++) TIM Channel: TIM_Channel |
mbed_official | 157:90e3acc479a2 | 2366 | (++) TIM Input Capture polarity: TIM_ICPolarity |
mbed_official | 157:90e3acc479a2 | 2367 | (++) TIM Input Capture selection: TIM_ICSelection |
mbed_official | 157:90e3acc479a2 | 2368 | (++) TIM Input Capture Prescaler: TIM_ICPrescaler |
mbed_official | 157:90e3acc479a2 | 2369 | (++) TIM Input CApture filter value: TIM_ICFilter |
mbed_official | 157:90e3acc479a2 | 2370 | |
mbed_official | 157:90e3acc479a2 | 2371 | (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the |
mbed_official | 157:90e3acc479a2 | 2372 | corresponding configuration and to measure only frequency or duty cycle of the input signal, |
mbed_official | 157:90e3acc479a2 | 2373 | or, |
mbed_official | 157:90e3acc479a2 | 2374 | Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the |
mbed_official | 157:90e3acc479a2 | 2375 | corresponding configuration and to measure the frequency and the duty cycle of the input signal |
mbed_official | 157:90e3acc479a2 | 2376 | |
mbed_official | 157:90e3acc479a2 | 2377 | (#) Enable the NVIC or the DMA to read the measured frequency. |
mbed_official | 157:90e3acc479a2 | 2378 | |
mbed_official | 157:90e3acc479a2 | 2379 | (#) Enable the corresponding interrupt (or DMA request) to read the Captured value, |
mbed_official | 157:90e3acc479a2 | 2380 | using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) |
mbed_official | 157:90e3acc479a2 | 2381 | |
mbed_official | 157:90e3acc479a2 | 2382 | (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. |
mbed_official | 157:90e3acc479a2 | 2383 | |
mbed_official | 157:90e3acc479a2 | 2384 | (#) Use TIM_GetCapturex(TIMx); to read the captured value. |
mbed_official | 157:90e3acc479a2 | 2385 | [..] |
mbed_official | 157:90e3acc479a2 | 2386 | (@) All other functions can be used separately to modify, if needed, |
mbed_official | 157:90e3acc479a2 | 2387 | a specific feature of the Timer. |
mbed_official | 157:90e3acc479a2 | 2388 | |
mbed_official | 157:90e3acc479a2 | 2389 | @endverbatim |
mbed_official | 157:90e3acc479a2 | 2390 | * @{ |
mbed_official | 157:90e3acc479a2 | 2391 | */ |
mbed_official | 157:90e3acc479a2 | 2392 | |
mbed_official | 157:90e3acc479a2 | 2393 | /** |
mbed_official | 157:90e3acc479a2 | 2394 | * @brief Initializes the TIM peripheral according to the specified parameters |
mbed_official | 157:90e3acc479a2 | 2395 | * in the TIM_ICInitStruct. |
mbed_official | 157:90e3acc479a2 | 2396 | * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 2397 | * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains |
mbed_official | 157:90e3acc479a2 | 2398 | * the configuration information for the specified TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 2399 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2400 | */ |
mbed_official | 157:90e3acc479a2 | 2401 | void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) |
mbed_official | 157:90e3acc479a2 | 2402 | { |
mbed_official | 157:90e3acc479a2 | 2403 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2404 | assert_param(IS_TIM_LIST1_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2405 | assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); |
mbed_official | 157:90e3acc479a2 | 2406 | assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); |
mbed_official | 157:90e3acc479a2 | 2407 | assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); |
mbed_official | 157:90e3acc479a2 | 2408 | assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); |
mbed_official | 157:90e3acc479a2 | 2409 | |
mbed_official | 157:90e3acc479a2 | 2410 | if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) |
mbed_official | 157:90e3acc479a2 | 2411 | { |
mbed_official | 157:90e3acc479a2 | 2412 | /* TI1 Configuration */ |
mbed_official | 157:90e3acc479a2 | 2413 | TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, |
mbed_official | 157:90e3acc479a2 | 2414 | TIM_ICInitStruct->TIM_ICSelection, |
mbed_official | 157:90e3acc479a2 | 2415 | TIM_ICInitStruct->TIM_ICFilter); |
mbed_official | 157:90e3acc479a2 | 2416 | /* Set the Input Capture Prescaler value */ |
mbed_official | 157:90e3acc479a2 | 2417 | TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); |
mbed_official | 157:90e3acc479a2 | 2418 | } |
mbed_official | 157:90e3acc479a2 | 2419 | else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) |
mbed_official | 157:90e3acc479a2 | 2420 | { |
mbed_official | 157:90e3acc479a2 | 2421 | /* TI2 Configuration */ |
mbed_official | 157:90e3acc479a2 | 2422 | TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, |
mbed_official | 157:90e3acc479a2 | 2423 | TIM_ICInitStruct->TIM_ICSelection, |
mbed_official | 157:90e3acc479a2 | 2424 | TIM_ICInitStruct->TIM_ICFilter); |
mbed_official | 157:90e3acc479a2 | 2425 | /* Set the Input Capture Prescaler value */ |
mbed_official | 157:90e3acc479a2 | 2426 | TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); |
mbed_official | 157:90e3acc479a2 | 2427 | } |
mbed_official | 157:90e3acc479a2 | 2428 | else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) |
mbed_official | 157:90e3acc479a2 | 2429 | { |
mbed_official | 157:90e3acc479a2 | 2430 | /* TI3 Configuration */ |
mbed_official | 157:90e3acc479a2 | 2431 | TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, |
mbed_official | 157:90e3acc479a2 | 2432 | TIM_ICInitStruct->TIM_ICSelection, |
mbed_official | 157:90e3acc479a2 | 2433 | TIM_ICInitStruct->TIM_ICFilter); |
mbed_official | 157:90e3acc479a2 | 2434 | /* Set the Input Capture Prescaler value */ |
mbed_official | 157:90e3acc479a2 | 2435 | TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); |
mbed_official | 157:90e3acc479a2 | 2436 | } |
mbed_official | 157:90e3acc479a2 | 2437 | else |
mbed_official | 157:90e3acc479a2 | 2438 | { |
mbed_official | 157:90e3acc479a2 | 2439 | /* TI4 Configuration */ |
mbed_official | 157:90e3acc479a2 | 2440 | TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, |
mbed_official | 157:90e3acc479a2 | 2441 | TIM_ICInitStruct->TIM_ICSelection, |
mbed_official | 157:90e3acc479a2 | 2442 | TIM_ICInitStruct->TIM_ICFilter); |
mbed_official | 157:90e3acc479a2 | 2443 | /* Set the Input Capture Prescaler value */ |
mbed_official | 157:90e3acc479a2 | 2444 | TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); |
mbed_official | 157:90e3acc479a2 | 2445 | } |
mbed_official | 157:90e3acc479a2 | 2446 | } |
mbed_official | 157:90e3acc479a2 | 2447 | |
mbed_official | 157:90e3acc479a2 | 2448 | /** |
mbed_official | 157:90e3acc479a2 | 2449 | * @brief Fills each TIM_ICInitStruct member with its default value. |
mbed_official | 157:90e3acc479a2 | 2450 | * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will |
mbed_official | 157:90e3acc479a2 | 2451 | * be initialized. |
mbed_official | 157:90e3acc479a2 | 2452 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2453 | */ |
mbed_official | 157:90e3acc479a2 | 2454 | void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) |
mbed_official | 157:90e3acc479a2 | 2455 | { |
mbed_official | 157:90e3acc479a2 | 2456 | /* Set the default configuration */ |
mbed_official | 157:90e3acc479a2 | 2457 | TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; |
mbed_official | 157:90e3acc479a2 | 2458 | TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; |
mbed_official | 157:90e3acc479a2 | 2459 | TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; |
mbed_official | 157:90e3acc479a2 | 2460 | TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; |
mbed_official | 157:90e3acc479a2 | 2461 | TIM_ICInitStruct->TIM_ICFilter = 0x00; |
mbed_official | 157:90e3acc479a2 | 2462 | } |
mbed_official | 157:90e3acc479a2 | 2463 | |
mbed_official | 157:90e3acc479a2 | 2464 | /** |
mbed_official | 157:90e3acc479a2 | 2465 | * @brief Configures the TIM peripheral according to the specified parameters |
mbed_official | 157:90e3acc479a2 | 2466 | * in the TIM_ICInitStruct to measure an external PWM signal. |
mbed_official | 157:90e3acc479a2 | 2467 | * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM |
mbed_official | 157:90e3acc479a2 | 2468 | * peripheral. |
mbed_official | 157:90e3acc479a2 | 2469 | * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains |
mbed_official | 157:90e3acc479a2 | 2470 | * the configuration information for the specified TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 2471 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2472 | */ |
mbed_official | 157:90e3acc479a2 | 2473 | void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) |
mbed_official | 157:90e3acc479a2 | 2474 | { |
mbed_official | 157:90e3acc479a2 | 2475 | uint16_t icoppositepolarity = TIM_ICPolarity_Rising; |
mbed_official | 157:90e3acc479a2 | 2476 | uint16_t icoppositeselection = TIM_ICSelection_DirectTI; |
mbed_official | 157:90e3acc479a2 | 2477 | |
mbed_official | 157:90e3acc479a2 | 2478 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2479 | assert_param(IS_TIM_LIST2_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2480 | |
mbed_official | 157:90e3acc479a2 | 2481 | /* Select the Opposite Input Polarity */ |
mbed_official | 157:90e3acc479a2 | 2482 | if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) |
mbed_official | 157:90e3acc479a2 | 2483 | { |
mbed_official | 157:90e3acc479a2 | 2484 | icoppositepolarity = TIM_ICPolarity_Falling; |
mbed_official | 157:90e3acc479a2 | 2485 | } |
mbed_official | 157:90e3acc479a2 | 2486 | else |
mbed_official | 157:90e3acc479a2 | 2487 | { |
mbed_official | 157:90e3acc479a2 | 2488 | icoppositepolarity = TIM_ICPolarity_Rising; |
mbed_official | 157:90e3acc479a2 | 2489 | } |
mbed_official | 157:90e3acc479a2 | 2490 | /* Select the Opposite Input */ |
mbed_official | 157:90e3acc479a2 | 2491 | if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) |
mbed_official | 157:90e3acc479a2 | 2492 | { |
mbed_official | 157:90e3acc479a2 | 2493 | icoppositeselection = TIM_ICSelection_IndirectTI; |
mbed_official | 157:90e3acc479a2 | 2494 | } |
mbed_official | 157:90e3acc479a2 | 2495 | else |
mbed_official | 157:90e3acc479a2 | 2496 | { |
mbed_official | 157:90e3acc479a2 | 2497 | icoppositeselection = TIM_ICSelection_DirectTI; |
mbed_official | 157:90e3acc479a2 | 2498 | } |
mbed_official | 157:90e3acc479a2 | 2499 | if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) |
mbed_official | 157:90e3acc479a2 | 2500 | { |
mbed_official | 157:90e3acc479a2 | 2501 | /* TI1 Configuration */ |
mbed_official | 157:90e3acc479a2 | 2502 | TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, |
mbed_official | 157:90e3acc479a2 | 2503 | TIM_ICInitStruct->TIM_ICFilter); |
mbed_official | 157:90e3acc479a2 | 2504 | /* Set the Input Capture Prescaler value */ |
mbed_official | 157:90e3acc479a2 | 2505 | TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); |
mbed_official | 157:90e3acc479a2 | 2506 | /* TI2 Configuration */ |
mbed_official | 157:90e3acc479a2 | 2507 | TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); |
mbed_official | 157:90e3acc479a2 | 2508 | /* Set the Input Capture Prescaler value */ |
mbed_official | 157:90e3acc479a2 | 2509 | TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); |
mbed_official | 157:90e3acc479a2 | 2510 | } |
mbed_official | 157:90e3acc479a2 | 2511 | else |
mbed_official | 157:90e3acc479a2 | 2512 | { |
mbed_official | 157:90e3acc479a2 | 2513 | /* TI2 Configuration */ |
mbed_official | 157:90e3acc479a2 | 2514 | TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, |
mbed_official | 157:90e3acc479a2 | 2515 | TIM_ICInitStruct->TIM_ICFilter); |
mbed_official | 157:90e3acc479a2 | 2516 | /* Set the Input Capture Prescaler value */ |
mbed_official | 157:90e3acc479a2 | 2517 | TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); |
mbed_official | 157:90e3acc479a2 | 2518 | /* TI1 Configuration */ |
mbed_official | 157:90e3acc479a2 | 2519 | TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); |
mbed_official | 157:90e3acc479a2 | 2520 | /* Set the Input Capture Prescaler value */ |
mbed_official | 157:90e3acc479a2 | 2521 | TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); |
mbed_official | 157:90e3acc479a2 | 2522 | } |
mbed_official | 157:90e3acc479a2 | 2523 | } |
mbed_official | 157:90e3acc479a2 | 2524 | |
mbed_official | 157:90e3acc479a2 | 2525 | /** |
mbed_official | 157:90e3acc479a2 | 2526 | * @brief Gets the TIMx Input Capture 1 value. |
mbed_official | 157:90e3acc479a2 | 2527 | * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 2528 | * @retval Capture Compare 1 Register value. |
mbed_official | 157:90e3acc479a2 | 2529 | */ |
mbed_official | 157:90e3acc479a2 | 2530 | uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx) |
mbed_official | 157:90e3acc479a2 | 2531 | { |
mbed_official | 157:90e3acc479a2 | 2532 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2533 | assert_param(IS_TIM_LIST1_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2534 | |
mbed_official | 157:90e3acc479a2 | 2535 | /* Get the Capture 1 Register value */ |
mbed_official | 157:90e3acc479a2 | 2536 | return TIMx->CCR1; |
mbed_official | 157:90e3acc479a2 | 2537 | } |
mbed_official | 157:90e3acc479a2 | 2538 | |
mbed_official | 157:90e3acc479a2 | 2539 | /** |
mbed_official | 157:90e3acc479a2 | 2540 | * @brief Gets the TIMx Input Capture 2 value. |
mbed_official | 157:90e3acc479a2 | 2541 | * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM |
mbed_official | 157:90e3acc479a2 | 2542 | * peripheral. |
mbed_official | 157:90e3acc479a2 | 2543 | * @retval Capture Compare 2 Register value. |
mbed_official | 157:90e3acc479a2 | 2544 | */ |
mbed_official | 157:90e3acc479a2 | 2545 | uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx) |
mbed_official | 157:90e3acc479a2 | 2546 | { |
mbed_official | 157:90e3acc479a2 | 2547 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2548 | assert_param(IS_TIM_LIST2_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2549 | |
mbed_official | 157:90e3acc479a2 | 2550 | /* Get the Capture 2 Register value */ |
mbed_official | 157:90e3acc479a2 | 2551 | return TIMx->CCR2; |
mbed_official | 157:90e3acc479a2 | 2552 | } |
mbed_official | 157:90e3acc479a2 | 2553 | |
mbed_official | 157:90e3acc479a2 | 2554 | /** |
mbed_official | 157:90e3acc479a2 | 2555 | * @brief Gets the TIMx Input Capture 3 value. |
mbed_official | 157:90e3acc479a2 | 2556 | * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 2557 | * @retval Capture Compare 3 Register value. |
mbed_official | 157:90e3acc479a2 | 2558 | */ |
mbed_official | 157:90e3acc479a2 | 2559 | uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx) |
mbed_official | 157:90e3acc479a2 | 2560 | { |
mbed_official | 157:90e3acc479a2 | 2561 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2562 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2563 | |
mbed_official | 157:90e3acc479a2 | 2564 | /* Get the Capture 3 Register value */ |
mbed_official | 157:90e3acc479a2 | 2565 | return TIMx->CCR3; |
mbed_official | 157:90e3acc479a2 | 2566 | } |
mbed_official | 157:90e3acc479a2 | 2567 | |
mbed_official | 157:90e3acc479a2 | 2568 | /** |
mbed_official | 157:90e3acc479a2 | 2569 | * @brief Gets the TIMx Input Capture 4 value. |
mbed_official | 157:90e3acc479a2 | 2570 | * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 2571 | * @retval Capture Compare 4 Register value. |
mbed_official | 157:90e3acc479a2 | 2572 | */ |
mbed_official | 157:90e3acc479a2 | 2573 | uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx) |
mbed_official | 157:90e3acc479a2 | 2574 | { |
mbed_official | 157:90e3acc479a2 | 2575 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2576 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2577 | |
mbed_official | 157:90e3acc479a2 | 2578 | /* Get the Capture 4 Register value */ |
mbed_official | 157:90e3acc479a2 | 2579 | return TIMx->CCR4; |
mbed_official | 157:90e3acc479a2 | 2580 | } |
mbed_official | 157:90e3acc479a2 | 2581 | |
mbed_official | 157:90e3acc479a2 | 2582 | /** |
mbed_official | 157:90e3acc479a2 | 2583 | * @brief Sets the TIMx Input Capture 1 prescaler. |
mbed_official | 157:90e3acc479a2 | 2584 | * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 2585 | * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. |
mbed_official | 157:90e3acc479a2 | 2586 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 2587 | * @arg TIM_ICPSC_DIV1: no prescaler |
mbed_official | 157:90e3acc479a2 | 2588 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
mbed_official | 157:90e3acc479a2 | 2589 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
mbed_official | 157:90e3acc479a2 | 2590 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
mbed_official | 157:90e3acc479a2 | 2591 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2592 | */ |
mbed_official | 157:90e3acc479a2 | 2593 | void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) |
mbed_official | 157:90e3acc479a2 | 2594 | { |
mbed_official | 157:90e3acc479a2 | 2595 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2596 | assert_param(IS_TIM_LIST1_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2597 | assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); |
mbed_official | 157:90e3acc479a2 | 2598 | |
mbed_official | 157:90e3acc479a2 | 2599 | /* Reset the IC1PSC Bits */ |
mbed_official | 157:90e3acc479a2 | 2600 | TIMx->CCMR1 &= (uint32_t)~TIM_CCMR1_IC1PSC; |
mbed_official | 157:90e3acc479a2 | 2601 | |
mbed_official | 157:90e3acc479a2 | 2602 | /* Set the IC1PSC value */ |
mbed_official | 157:90e3acc479a2 | 2603 | TIMx->CCMR1 |= TIM_ICPSC; |
mbed_official | 157:90e3acc479a2 | 2604 | } |
mbed_official | 157:90e3acc479a2 | 2605 | |
mbed_official | 157:90e3acc479a2 | 2606 | /** |
mbed_official | 157:90e3acc479a2 | 2607 | * @brief Sets the TIMx Input Capture 2 prescaler. |
mbed_official | 157:90e3acc479a2 | 2608 | * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM |
mbed_official | 157:90e3acc479a2 | 2609 | * peripheral. |
mbed_official | 157:90e3acc479a2 | 2610 | * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. |
mbed_official | 157:90e3acc479a2 | 2611 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 2612 | * @arg TIM_ICPSC_DIV1: no prescaler |
mbed_official | 157:90e3acc479a2 | 2613 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
mbed_official | 157:90e3acc479a2 | 2614 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
mbed_official | 157:90e3acc479a2 | 2615 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
mbed_official | 157:90e3acc479a2 | 2616 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2617 | */ |
mbed_official | 157:90e3acc479a2 | 2618 | void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) |
mbed_official | 157:90e3acc479a2 | 2619 | { |
mbed_official | 157:90e3acc479a2 | 2620 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2621 | assert_param(IS_TIM_LIST2_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2622 | assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); |
mbed_official | 157:90e3acc479a2 | 2623 | |
mbed_official | 157:90e3acc479a2 | 2624 | /* Reset the IC2PSC Bits */ |
mbed_official | 157:90e3acc479a2 | 2625 | TIMx->CCMR1 &= (uint32_t)~TIM_CCMR1_IC2PSC; |
mbed_official | 157:90e3acc479a2 | 2626 | |
mbed_official | 157:90e3acc479a2 | 2627 | /* Set the IC2PSC value */ |
mbed_official | 157:90e3acc479a2 | 2628 | TIMx->CCMR1 |= (uint32_t)((uint32_t)TIM_ICPSC << 8); |
mbed_official | 157:90e3acc479a2 | 2629 | } |
mbed_official | 157:90e3acc479a2 | 2630 | |
mbed_official | 157:90e3acc479a2 | 2631 | /** |
mbed_official | 157:90e3acc479a2 | 2632 | * @brief Sets the TIMx Input Capture 3 prescaler. |
mbed_official | 157:90e3acc479a2 | 2633 | * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 2634 | * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. |
mbed_official | 157:90e3acc479a2 | 2635 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 2636 | * @arg TIM_ICPSC_DIV1: no prescaler |
mbed_official | 157:90e3acc479a2 | 2637 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
mbed_official | 157:90e3acc479a2 | 2638 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
mbed_official | 157:90e3acc479a2 | 2639 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
mbed_official | 157:90e3acc479a2 | 2640 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2641 | */ |
mbed_official | 157:90e3acc479a2 | 2642 | void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) |
mbed_official | 157:90e3acc479a2 | 2643 | { |
mbed_official | 157:90e3acc479a2 | 2644 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2645 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2646 | assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); |
mbed_official | 157:90e3acc479a2 | 2647 | |
mbed_official | 157:90e3acc479a2 | 2648 | /* Reset the IC3PSC Bits */ |
mbed_official | 157:90e3acc479a2 | 2649 | TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC; |
mbed_official | 157:90e3acc479a2 | 2650 | |
mbed_official | 157:90e3acc479a2 | 2651 | /* Set the IC3PSC value */ |
mbed_official | 157:90e3acc479a2 | 2652 | TIMx->CCMR2 |= TIM_ICPSC; |
mbed_official | 157:90e3acc479a2 | 2653 | } |
mbed_official | 157:90e3acc479a2 | 2654 | |
mbed_official | 157:90e3acc479a2 | 2655 | /** |
mbed_official | 157:90e3acc479a2 | 2656 | * @brief Sets the TIMx Input Capture 4 prescaler. |
mbed_official | 157:90e3acc479a2 | 2657 | * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 2658 | * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. |
mbed_official | 157:90e3acc479a2 | 2659 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 2660 | * @arg TIM_ICPSC_DIV1: no prescaler |
mbed_official | 157:90e3acc479a2 | 2661 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
mbed_official | 157:90e3acc479a2 | 2662 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
mbed_official | 157:90e3acc479a2 | 2663 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
mbed_official | 157:90e3acc479a2 | 2664 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2665 | */ |
mbed_official | 157:90e3acc479a2 | 2666 | void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) |
mbed_official | 157:90e3acc479a2 | 2667 | { |
mbed_official | 157:90e3acc479a2 | 2668 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2669 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2670 | assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); |
mbed_official | 157:90e3acc479a2 | 2671 | |
mbed_official | 157:90e3acc479a2 | 2672 | /* Reset the IC4PSC Bits */ |
mbed_official | 157:90e3acc479a2 | 2673 | TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC; |
mbed_official | 157:90e3acc479a2 | 2674 | |
mbed_official | 157:90e3acc479a2 | 2675 | /* Set the IC4PSC value */ |
mbed_official | 157:90e3acc479a2 | 2676 | TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); |
mbed_official | 157:90e3acc479a2 | 2677 | } |
mbed_official | 157:90e3acc479a2 | 2678 | /** |
mbed_official | 157:90e3acc479a2 | 2679 | * @} |
mbed_official | 157:90e3acc479a2 | 2680 | */ |
mbed_official | 157:90e3acc479a2 | 2681 | |
mbed_official | 157:90e3acc479a2 | 2682 | /** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features |
mbed_official | 157:90e3acc479a2 | 2683 | * @brief Advanced-control timers (TIM1 and TIM8) specific features |
mbed_official | 157:90e3acc479a2 | 2684 | * |
mbed_official | 157:90e3acc479a2 | 2685 | @verbatim |
mbed_official | 157:90e3acc479a2 | 2686 | =============================================================================== |
mbed_official | 157:90e3acc479a2 | 2687 | ##### Advanced-control timers (TIM1 and TIM8) specific features ##### |
mbed_official | 157:90e3acc479a2 | 2688 | =============================================================================== |
mbed_official | 157:90e3acc479a2 | 2689 | |
mbed_official | 157:90e3acc479a2 | 2690 | *** TIM Driver: how to use the Break feature *** |
mbed_official | 157:90e3acc479a2 | 2691 | ================================================ |
mbed_official | 157:90e3acc479a2 | 2692 | [..] |
mbed_official | 157:90e3acc479a2 | 2693 | After configuring the Timer channel(s) in the appropriate Output Compare mode: |
mbed_official | 157:90e3acc479a2 | 2694 | |
mbed_official | 157:90e3acc479a2 | 2695 | (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer |
mbed_official | 157:90e3acc479a2 | 2696 | Break Polarity, dead time, Lock level, the OSSI/OSSR State and the |
mbed_official | 157:90e3acc479a2 | 2697 | AOE(automatic output enable). |
mbed_official | 157:90e3acc479a2 | 2698 | |
mbed_official | 157:90e3acc479a2 | 2699 | (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer |
mbed_official | 157:90e3acc479a2 | 2700 | |
mbed_official | 157:90e3acc479a2 | 2701 | (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) |
mbed_official | 157:90e3acc479a2 | 2702 | |
mbed_official | 157:90e3acc479a2 | 2703 | (#) Once the break even occurs, the Timer's output signals are put in reset |
mbed_official | 157:90e3acc479a2 | 2704 | state or in a known state (according to the configuration made in |
mbed_official | 157:90e3acc479a2 | 2705 | TIM_BDTRConfig() function). |
mbed_official | 157:90e3acc479a2 | 2706 | |
mbed_official | 157:90e3acc479a2 | 2707 | @endverbatim |
mbed_official | 157:90e3acc479a2 | 2708 | * @{ |
mbed_official | 157:90e3acc479a2 | 2709 | */ |
mbed_official | 157:90e3acc479a2 | 2710 | |
mbed_official | 157:90e3acc479a2 | 2711 | /** |
mbed_official | 157:90e3acc479a2 | 2712 | * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State |
mbed_official | 157:90e3acc479a2 | 2713 | * and the AOE(automatic output enable). |
mbed_official | 157:90e3acc479a2 | 2714 | * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM |
mbed_official | 157:90e3acc479a2 | 2715 | * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that |
mbed_official | 157:90e3acc479a2 | 2716 | * contains the BDTR Register configuration information for the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 2717 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2718 | */ |
mbed_official | 157:90e3acc479a2 | 2719 | void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) |
mbed_official | 157:90e3acc479a2 | 2720 | { |
mbed_official | 157:90e3acc479a2 | 2721 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2722 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2723 | assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); |
mbed_official | 157:90e3acc479a2 | 2724 | assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); |
mbed_official | 157:90e3acc479a2 | 2725 | assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); |
mbed_official | 157:90e3acc479a2 | 2726 | assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); |
mbed_official | 157:90e3acc479a2 | 2727 | assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); |
mbed_official | 157:90e3acc479a2 | 2728 | assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); |
mbed_official | 157:90e3acc479a2 | 2729 | |
mbed_official | 157:90e3acc479a2 | 2730 | /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, |
mbed_official | 157:90e3acc479a2 | 2731 | the OSSI State, the dead time value and the Automatic Output Enable Bit */ |
mbed_official | 157:90e3acc479a2 | 2732 | TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | |
mbed_official | 157:90e3acc479a2 | 2733 | TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | |
mbed_official | 157:90e3acc479a2 | 2734 | TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | |
mbed_official | 157:90e3acc479a2 | 2735 | TIM_BDTRInitStruct->TIM_AutomaticOutput; |
mbed_official | 157:90e3acc479a2 | 2736 | } |
mbed_official | 157:90e3acc479a2 | 2737 | |
mbed_official | 157:90e3acc479a2 | 2738 | /** |
mbed_official | 157:90e3acc479a2 | 2739 | * @brief Configures the Break1 feature. |
mbed_official | 157:90e3acc479a2 | 2740 | * @param TIMx: where x can be 1 or 8 to select the TIM |
mbed_official | 157:90e3acc479a2 | 2741 | * @param TIM_Break1Polarity: specifies the Break1 polarity. |
mbed_official | 157:90e3acc479a2 | 2742 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 2743 | * @arg TIM_Break1Polarity_Low: Break1 input is active low |
mbed_official | 157:90e3acc479a2 | 2744 | * @arg TIM_Break1Polarity_High: Break1 input is active high |
mbed_official | 157:90e3acc479a2 | 2745 | * @param TIM_Break1Filter: specifies the Break1 filter value. |
mbed_official | 157:90e3acc479a2 | 2746 | * This parameter must be a value between 0x00 and 0x0F |
mbed_official | 157:90e3acc479a2 | 2747 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2748 | */ |
mbed_official | 157:90e3acc479a2 | 2749 | void TIM_Break1Config(TIM_TypeDef* TIMx, uint32_t TIM_Break1Polarity, uint8_t TIM_Break1Filter) |
mbed_official | 157:90e3acc479a2 | 2750 | { /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2751 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2752 | assert_param(IS_TIM_BREAK1_FILTER(TIM_Break1Filter)); |
mbed_official | 157:90e3acc479a2 | 2753 | |
mbed_official | 157:90e3acc479a2 | 2754 | /* Reset the BKP and BKF Bits */ |
mbed_official | 157:90e3acc479a2 | 2755 | TIMx->BDTR &= (uint32_t)~ (TIM_BDTR_BKP | TIM_BDTR_BKF); |
mbed_official | 157:90e3acc479a2 | 2756 | /* Configure the Break1 polarity and filter */ |
mbed_official | 157:90e3acc479a2 | 2757 | TIMx->BDTR |= TIM_Break1Polarity |((uint32_t)TIM_Break1Filter << 16); |
mbed_official | 157:90e3acc479a2 | 2758 | } |
mbed_official | 157:90e3acc479a2 | 2759 | |
mbed_official | 157:90e3acc479a2 | 2760 | /** |
mbed_official | 157:90e3acc479a2 | 2761 | * @brief Configures the Break2 feature. |
mbed_official | 157:90e3acc479a2 | 2762 | * @param TIMx: where x can be 1 or 8 to select the TIM |
mbed_official | 157:90e3acc479a2 | 2763 | * @param TIM_Break2Polarity: specifies the Break2 polarity. |
mbed_official | 157:90e3acc479a2 | 2764 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 2765 | * @arg TIM_Break2Polarity_Low: Break2 input is active low |
mbed_official | 157:90e3acc479a2 | 2766 | * @arg TIM_Break2Polarity_High: Break2 input is active high |
mbed_official | 157:90e3acc479a2 | 2767 | * @param TIM_Break2Filter: specifies the Break2 filter value. |
mbed_official | 157:90e3acc479a2 | 2768 | * This parameter must be a value between 0x00 and 0x0F |
mbed_official | 157:90e3acc479a2 | 2769 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2770 | */ |
mbed_official | 157:90e3acc479a2 | 2771 | void TIM_Break2Config(TIM_TypeDef* TIMx, uint32_t TIM_Break2Polarity, uint8_t TIM_Break2Filter) |
mbed_official | 157:90e3acc479a2 | 2772 | { |
mbed_official | 157:90e3acc479a2 | 2773 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2774 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2775 | assert_param(IS_TIM_BREAK2_FILTER(TIM_Break2Filter)); |
mbed_official | 157:90e3acc479a2 | 2776 | |
mbed_official | 157:90e3acc479a2 | 2777 | /* Reset the BKP and BKF Bits */ |
mbed_official | 157:90e3acc479a2 | 2778 | TIMx->BDTR &= (uint32_t)~ (TIM_BDTR_BK2P | TIM_BDTR_BK2F); |
mbed_official | 157:90e3acc479a2 | 2779 | |
mbed_official | 157:90e3acc479a2 | 2780 | /* Configure the Break1 polarity and filter */ |
mbed_official | 157:90e3acc479a2 | 2781 | TIMx->BDTR |= TIM_Break2Polarity |((uint32_t)TIM_Break2Filter << 20); |
mbed_official | 157:90e3acc479a2 | 2782 | } |
mbed_official | 157:90e3acc479a2 | 2783 | |
mbed_official | 157:90e3acc479a2 | 2784 | /** |
mbed_official | 157:90e3acc479a2 | 2785 | * @brief Enables or disables the TIM Break1 input. |
mbed_official | 157:90e3acc479a2 | 2786 | * @param TIMx: where x can be 1, 8, 1, 16 or 17 to select the TIMx peripheral. |
mbed_official | 157:90e3acc479a2 | 2787 | * @param NewState: new state of the TIM Break1 input. |
mbed_official | 157:90e3acc479a2 | 2788 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 157:90e3acc479a2 | 2789 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2790 | */ |
mbed_official | 157:90e3acc479a2 | 2791 | void TIM_Break1Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) |
mbed_official | 157:90e3acc479a2 | 2792 | { |
mbed_official | 157:90e3acc479a2 | 2793 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2794 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2795 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 157:90e3acc479a2 | 2796 | |
mbed_official | 157:90e3acc479a2 | 2797 | if (NewState != DISABLE) |
mbed_official | 157:90e3acc479a2 | 2798 | { |
mbed_official | 157:90e3acc479a2 | 2799 | /* Enable the Break1 */ |
mbed_official | 157:90e3acc479a2 | 2800 | TIMx->BDTR |= TIM_BDTR_BKE; |
mbed_official | 157:90e3acc479a2 | 2801 | } |
mbed_official | 157:90e3acc479a2 | 2802 | else |
mbed_official | 157:90e3acc479a2 | 2803 | { |
mbed_official | 157:90e3acc479a2 | 2804 | /* Disable the Break1 */ |
mbed_official | 157:90e3acc479a2 | 2805 | TIMx->BDTR &= (uint32_t)~TIM_BDTR_BKE; |
mbed_official | 157:90e3acc479a2 | 2806 | } |
mbed_official | 157:90e3acc479a2 | 2807 | } |
mbed_official | 157:90e3acc479a2 | 2808 | |
mbed_official | 157:90e3acc479a2 | 2809 | /** |
mbed_official | 157:90e3acc479a2 | 2810 | * @brief Enables or disables the TIM Break2 input. |
mbed_official | 157:90e3acc479a2 | 2811 | * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral. |
mbed_official | 157:90e3acc479a2 | 2812 | * @param NewState: new state of the TIM Break2 input. |
mbed_official | 157:90e3acc479a2 | 2813 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 157:90e3acc479a2 | 2814 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2815 | */ |
mbed_official | 157:90e3acc479a2 | 2816 | void TIM_Break2Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) |
mbed_official | 157:90e3acc479a2 | 2817 | { |
mbed_official | 157:90e3acc479a2 | 2818 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2819 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2820 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 157:90e3acc479a2 | 2821 | |
mbed_official | 157:90e3acc479a2 | 2822 | if (NewState != DISABLE) |
mbed_official | 157:90e3acc479a2 | 2823 | { |
mbed_official | 157:90e3acc479a2 | 2824 | /* Enable the Break1 */ |
mbed_official | 157:90e3acc479a2 | 2825 | TIMx->BDTR |= TIM_BDTR_BK2E; |
mbed_official | 157:90e3acc479a2 | 2826 | } |
mbed_official | 157:90e3acc479a2 | 2827 | else |
mbed_official | 157:90e3acc479a2 | 2828 | { |
mbed_official | 157:90e3acc479a2 | 2829 | /* Disable the Break1 */ |
mbed_official | 157:90e3acc479a2 | 2830 | TIMx->BDTR &= (uint32_t)~TIM_BDTR_BK2E; |
mbed_official | 157:90e3acc479a2 | 2831 | } |
mbed_official | 157:90e3acc479a2 | 2832 | } |
mbed_official | 157:90e3acc479a2 | 2833 | |
mbed_official | 157:90e3acc479a2 | 2834 | /** |
mbed_official | 157:90e3acc479a2 | 2835 | * @brief Fills each TIM_BDTRInitStruct member with its default value. |
mbed_official | 157:90e3acc479a2 | 2836 | * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which |
mbed_official | 157:90e3acc479a2 | 2837 | * will be initialized. |
mbed_official | 157:90e3acc479a2 | 2838 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2839 | */ |
mbed_official | 157:90e3acc479a2 | 2840 | void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) |
mbed_official | 157:90e3acc479a2 | 2841 | { |
mbed_official | 157:90e3acc479a2 | 2842 | /* Set the default configuration */ |
mbed_official | 157:90e3acc479a2 | 2843 | TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; |
mbed_official | 157:90e3acc479a2 | 2844 | TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; |
mbed_official | 157:90e3acc479a2 | 2845 | TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; |
mbed_official | 157:90e3acc479a2 | 2846 | TIM_BDTRInitStruct->TIM_DeadTime = 0x00; |
mbed_official | 157:90e3acc479a2 | 2847 | TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; |
mbed_official | 157:90e3acc479a2 | 2848 | TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; |
mbed_official | 157:90e3acc479a2 | 2849 | TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; |
mbed_official | 157:90e3acc479a2 | 2850 | } |
mbed_official | 157:90e3acc479a2 | 2851 | |
mbed_official | 157:90e3acc479a2 | 2852 | /** |
mbed_official | 157:90e3acc479a2 | 2853 | * @brief Enables or disables the TIM peripheral Main Outputs. |
mbed_official | 157:90e3acc479a2 | 2854 | * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral. |
mbed_official | 157:90e3acc479a2 | 2855 | * @param NewState: new state of the TIM peripheral Main Outputs. |
mbed_official | 157:90e3acc479a2 | 2856 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 157:90e3acc479a2 | 2857 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2858 | */ |
mbed_official | 157:90e3acc479a2 | 2859 | void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) |
mbed_official | 157:90e3acc479a2 | 2860 | { |
mbed_official | 157:90e3acc479a2 | 2861 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2862 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2863 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 157:90e3acc479a2 | 2864 | |
mbed_official | 157:90e3acc479a2 | 2865 | if (NewState != DISABLE) |
mbed_official | 157:90e3acc479a2 | 2866 | { |
mbed_official | 157:90e3acc479a2 | 2867 | /* Enable the TIM Main Output */ |
mbed_official | 157:90e3acc479a2 | 2868 | TIMx->BDTR |= TIM_BDTR_MOE; |
mbed_official | 157:90e3acc479a2 | 2869 | } |
mbed_official | 157:90e3acc479a2 | 2870 | else |
mbed_official | 157:90e3acc479a2 | 2871 | { |
mbed_official | 157:90e3acc479a2 | 2872 | /* Disable the TIM Main Output */ |
mbed_official | 157:90e3acc479a2 | 2873 | TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE; |
mbed_official | 157:90e3acc479a2 | 2874 | } |
mbed_official | 157:90e3acc479a2 | 2875 | } |
mbed_official | 157:90e3acc479a2 | 2876 | |
mbed_official | 157:90e3acc479a2 | 2877 | /** |
mbed_official | 157:90e3acc479a2 | 2878 | * @brief Selects the TIM peripheral Commutation event. |
mbed_official | 157:90e3acc479a2 | 2879 | * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral |
mbed_official | 157:90e3acc479a2 | 2880 | * @param NewState: new state of the Commutation event. |
mbed_official | 157:90e3acc479a2 | 2881 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 157:90e3acc479a2 | 2882 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2883 | */ |
mbed_official | 157:90e3acc479a2 | 2884 | void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) |
mbed_official | 157:90e3acc479a2 | 2885 | { |
mbed_official | 157:90e3acc479a2 | 2886 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2887 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2888 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 157:90e3acc479a2 | 2889 | |
mbed_official | 157:90e3acc479a2 | 2890 | if (NewState != DISABLE) |
mbed_official | 157:90e3acc479a2 | 2891 | { |
mbed_official | 157:90e3acc479a2 | 2892 | /* Set the COM Bit */ |
mbed_official | 157:90e3acc479a2 | 2893 | TIMx->CR2 |= TIM_CR2_CCUS; |
mbed_official | 157:90e3acc479a2 | 2894 | } |
mbed_official | 157:90e3acc479a2 | 2895 | else |
mbed_official | 157:90e3acc479a2 | 2896 | { |
mbed_official | 157:90e3acc479a2 | 2897 | /* Reset the COM Bit */ |
mbed_official | 157:90e3acc479a2 | 2898 | TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS; |
mbed_official | 157:90e3acc479a2 | 2899 | } |
mbed_official | 157:90e3acc479a2 | 2900 | } |
mbed_official | 157:90e3acc479a2 | 2901 | |
mbed_official | 157:90e3acc479a2 | 2902 | /** |
mbed_official | 157:90e3acc479a2 | 2903 | * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. |
mbed_official | 157:90e3acc479a2 | 2904 | * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral |
mbed_official | 157:90e3acc479a2 | 2905 | * @param NewState: new state of the Capture Compare Preload Control bit |
mbed_official | 157:90e3acc479a2 | 2906 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 157:90e3acc479a2 | 2907 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2908 | */ |
mbed_official | 157:90e3acc479a2 | 2909 | void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) |
mbed_official | 157:90e3acc479a2 | 2910 | { |
mbed_official | 157:90e3acc479a2 | 2911 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2912 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2913 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 157:90e3acc479a2 | 2914 | if (NewState != DISABLE) |
mbed_official | 157:90e3acc479a2 | 2915 | { |
mbed_official | 157:90e3acc479a2 | 2916 | /* Set the CCPC Bit */ |
mbed_official | 157:90e3acc479a2 | 2917 | TIMx->CR2 |= TIM_CR2_CCPC; |
mbed_official | 157:90e3acc479a2 | 2918 | } |
mbed_official | 157:90e3acc479a2 | 2919 | else |
mbed_official | 157:90e3acc479a2 | 2920 | { |
mbed_official | 157:90e3acc479a2 | 2921 | /* Reset the CCPC Bit */ |
mbed_official | 157:90e3acc479a2 | 2922 | TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC; |
mbed_official | 157:90e3acc479a2 | 2923 | } |
mbed_official | 157:90e3acc479a2 | 2924 | } |
mbed_official | 157:90e3acc479a2 | 2925 | /** |
mbed_official | 157:90e3acc479a2 | 2926 | * @} |
mbed_official | 157:90e3acc479a2 | 2927 | */ |
mbed_official | 157:90e3acc479a2 | 2928 | |
mbed_official | 157:90e3acc479a2 | 2929 | /** @defgroup TIM_Group5 Interrupts DMA and flags management functions |
mbed_official | 157:90e3acc479a2 | 2930 | * @brief Interrupts, DMA and flags management functions |
mbed_official | 157:90e3acc479a2 | 2931 | * |
mbed_official | 157:90e3acc479a2 | 2932 | @verbatim |
mbed_official | 157:90e3acc479a2 | 2933 | =============================================================================== |
mbed_official | 157:90e3acc479a2 | 2934 | ##### Interrupts, DMA and flags management functions ##### |
mbed_official | 157:90e3acc479a2 | 2935 | =============================================================================== |
mbed_official | 157:90e3acc479a2 | 2936 | |
mbed_official | 157:90e3acc479a2 | 2937 | @endverbatim |
mbed_official | 157:90e3acc479a2 | 2938 | * @{ |
mbed_official | 157:90e3acc479a2 | 2939 | */ |
mbed_official | 157:90e3acc479a2 | 2940 | |
mbed_official | 157:90e3acc479a2 | 2941 | /** |
mbed_official | 157:90e3acc479a2 | 2942 | * @brief Enables or disables the specified TIM interrupts. |
mbed_official | 157:90e3acc479a2 | 2943 | * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIMx peripheral. |
mbed_official | 157:90e3acc479a2 | 2944 | * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. |
mbed_official | 157:90e3acc479a2 | 2945 | * This parameter can be any combination of the following values: |
mbed_official | 157:90e3acc479a2 | 2946 | * @arg TIM_IT_Update: TIM update Interrupt source |
mbed_official | 157:90e3acc479a2 | 2947 | * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source |
mbed_official | 157:90e3acc479a2 | 2948 | * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source |
mbed_official | 157:90e3acc479a2 | 2949 | * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source |
mbed_official | 157:90e3acc479a2 | 2950 | * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source |
mbed_official | 157:90e3acc479a2 | 2951 | * @arg TIM_IT_COM: TIM Commutation Interrupt source |
mbed_official | 157:90e3acc479a2 | 2952 | * @arg TIM_IT_Trigger: TIM Trigger Interrupt source |
mbed_official | 157:90e3acc479a2 | 2953 | * @arg TIM_IT_Break: TIM Break Interrupt source |
mbed_official | 157:90e3acc479a2 | 2954 | * |
mbed_official | 157:90e3acc479a2 | 2955 | * @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used |
mbed_official | 157:90e3acc479a2 | 2956 | * @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update, |
mbed_official | 157:90e3acc479a2 | 2957 | * TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. |
mbed_official | 157:90e3acc479a2 | 2958 | * @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can |
mbed_official | 157:90e3acc479a2 | 2959 | * be used: TIM_IT_Update or TIM_IT_CC1 |
mbed_official | 157:90e3acc479a2 | 2960 | * @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8 |
mbed_official | 157:90e3acc479a2 | 2961 | * |
mbed_official | 157:90e3acc479a2 | 2962 | * @param NewState: new state of the TIM interrupts. |
mbed_official | 157:90e3acc479a2 | 2963 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 157:90e3acc479a2 | 2964 | * @retval None |
mbed_official | 157:90e3acc479a2 | 2965 | */ |
mbed_official | 157:90e3acc479a2 | 2966 | void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) |
mbed_official | 157:90e3acc479a2 | 2967 | { |
mbed_official | 157:90e3acc479a2 | 2968 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 2969 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 2970 | assert_param(IS_TIM_IT(TIM_IT)); |
mbed_official | 157:90e3acc479a2 | 2971 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 157:90e3acc479a2 | 2972 | |
mbed_official | 157:90e3acc479a2 | 2973 | if (NewState != DISABLE) |
mbed_official | 157:90e3acc479a2 | 2974 | { |
mbed_official | 157:90e3acc479a2 | 2975 | /* Enable the Interrupt sources */ |
mbed_official | 157:90e3acc479a2 | 2976 | TIMx->DIER |= TIM_IT; |
mbed_official | 157:90e3acc479a2 | 2977 | } |
mbed_official | 157:90e3acc479a2 | 2978 | else |
mbed_official | 157:90e3acc479a2 | 2979 | { |
mbed_official | 157:90e3acc479a2 | 2980 | /* Disable the Interrupt sources */ |
mbed_official | 157:90e3acc479a2 | 2981 | TIMx->DIER &= (uint16_t)~TIM_IT; |
mbed_official | 157:90e3acc479a2 | 2982 | } |
mbed_official | 157:90e3acc479a2 | 2983 | } |
mbed_official | 157:90e3acc479a2 | 2984 | |
mbed_official | 157:90e3acc479a2 | 2985 | /** |
mbed_official | 157:90e3acc479a2 | 2986 | * @brief Configures the TIMx event to be generate by software. |
mbed_official | 157:90e3acc479a2 | 2987 | * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 2988 | * @param TIM_EventSource: specifies the event source. |
mbed_official | 157:90e3acc479a2 | 2989 | * This parameter can be one or more of the following values: |
mbed_official | 157:90e3acc479a2 | 2990 | * @arg TIM_EventSource_Update: Timer update Event source |
mbed_official | 157:90e3acc479a2 | 2991 | * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source |
mbed_official | 157:90e3acc479a2 | 2992 | * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source |
mbed_official | 157:90e3acc479a2 | 2993 | * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source |
mbed_official | 157:90e3acc479a2 | 2994 | * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source |
mbed_official | 157:90e3acc479a2 | 2995 | * @arg TIM_EventSource_COM: Timer COM event source |
mbed_official | 157:90e3acc479a2 | 2996 | * @arg TIM_EventSource_Trigger: Timer Trigger Event source |
mbed_official | 157:90e3acc479a2 | 2997 | * @arg TIM_EventSource_Break: Timer Break event source |
mbed_official | 157:90e3acc479a2 | 2998 | * |
mbed_official | 157:90e3acc479a2 | 2999 | * @note TIM6 and TIM7 can only generate an update event. |
mbed_official | 157:90e3acc479a2 | 3000 | * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. |
mbed_official | 157:90e3acc479a2 | 3001 | * |
mbed_official | 157:90e3acc479a2 | 3002 | * @retval None |
mbed_official | 157:90e3acc479a2 | 3003 | */ |
mbed_official | 157:90e3acc479a2 | 3004 | void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) |
mbed_official | 157:90e3acc479a2 | 3005 | { |
mbed_official | 157:90e3acc479a2 | 3006 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 3007 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 3008 | assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); |
mbed_official | 157:90e3acc479a2 | 3009 | |
mbed_official | 157:90e3acc479a2 | 3010 | /* Set the event sources */ |
mbed_official | 157:90e3acc479a2 | 3011 | TIMx->EGR = TIM_EventSource; |
mbed_official | 157:90e3acc479a2 | 3012 | } |
mbed_official | 157:90e3acc479a2 | 3013 | |
mbed_official | 157:90e3acc479a2 | 3014 | /** |
mbed_official | 157:90e3acc479a2 | 3015 | * @brief Checks whether the specified TIM flag is set or not. |
mbed_official | 157:90e3acc479a2 | 3016 | * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 3017 | * @param TIM_FLAG: specifies the flag to check. |
mbed_official | 157:90e3acc479a2 | 3018 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3019 | * @arg TIM_FLAG_Update: TIM update Flag |
mbed_official | 157:90e3acc479a2 | 3020 | * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag |
mbed_official | 157:90e3acc479a2 | 3021 | * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag |
mbed_official | 157:90e3acc479a2 | 3022 | * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag |
mbed_official | 157:90e3acc479a2 | 3023 | * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag |
mbed_official | 157:90e3acc479a2 | 3024 | * @arg TIM_FLAG_CC5: TIM Capture Compare 5 Flag |
mbed_official | 157:90e3acc479a2 | 3025 | * @arg TIM_FLAG_CC6: TIM Capture Compare 6 Flag |
mbed_official | 157:90e3acc479a2 | 3026 | * @arg TIM_FLAG_COM: TIM Commutation Flag |
mbed_official | 157:90e3acc479a2 | 3027 | * @arg TIM_FLAG_Trigger: TIM Trigger Flag |
mbed_official | 157:90e3acc479a2 | 3028 | * @arg TIM_FLAG_Break: TIM Break Flag |
mbed_official | 157:90e3acc479a2 | 3029 | * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag |
mbed_official | 157:90e3acc479a2 | 3030 | * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag |
mbed_official | 157:90e3acc479a2 | 3031 | * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag |
mbed_official | 157:90e3acc479a2 | 3032 | * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag |
mbed_official | 157:90e3acc479a2 | 3033 | * |
mbed_official | 157:90e3acc479a2 | 3034 | * @note TIM6 and TIM7 can have only one update flag. |
mbed_official | 157:90e3acc479a2 | 3035 | * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. |
mbed_official | 157:90e3acc479a2 | 3036 | * |
mbed_official | 157:90e3acc479a2 | 3037 | * @retval The new state of TIM_FLAG (SET or RESET). |
mbed_official | 157:90e3acc479a2 | 3038 | */ |
mbed_official | 157:90e3acc479a2 | 3039 | FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint32_t TIM_FLAG) |
mbed_official | 157:90e3acc479a2 | 3040 | { |
mbed_official | 157:90e3acc479a2 | 3041 | ITStatus bitstatus = RESET; |
mbed_official | 157:90e3acc479a2 | 3042 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 3043 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 3044 | assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); |
mbed_official | 157:90e3acc479a2 | 3045 | |
mbed_official | 157:90e3acc479a2 | 3046 | |
mbed_official | 157:90e3acc479a2 | 3047 | if ((TIMx->SR & TIM_FLAG) != RESET) |
mbed_official | 157:90e3acc479a2 | 3048 | { |
mbed_official | 157:90e3acc479a2 | 3049 | bitstatus = SET; |
mbed_official | 157:90e3acc479a2 | 3050 | } |
mbed_official | 157:90e3acc479a2 | 3051 | else |
mbed_official | 157:90e3acc479a2 | 3052 | { |
mbed_official | 157:90e3acc479a2 | 3053 | bitstatus = RESET; |
mbed_official | 157:90e3acc479a2 | 3054 | } |
mbed_official | 157:90e3acc479a2 | 3055 | return bitstatus; |
mbed_official | 157:90e3acc479a2 | 3056 | } |
mbed_official | 157:90e3acc479a2 | 3057 | |
mbed_official | 157:90e3acc479a2 | 3058 | /** |
mbed_official | 157:90e3acc479a2 | 3059 | * @brief Clears the TIMx's pending flags. |
mbed_official | 157:90e3acc479a2 | 3060 | * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 3061 | * @param TIM_FLAG: specifies the flag bit to clear. |
mbed_official | 157:90e3acc479a2 | 3062 | * This parameter can be any combination of the following values: |
mbed_official | 157:90e3acc479a2 | 3063 | * @arg TIM_FLAG_Update: TIM update Flag |
mbed_official | 157:90e3acc479a2 | 3064 | * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag |
mbed_official | 157:90e3acc479a2 | 3065 | * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag |
mbed_official | 157:90e3acc479a2 | 3066 | * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag |
mbed_official | 157:90e3acc479a2 | 3067 | * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag |
mbed_official | 157:90e3acc479a2 | 3068 | * @arg TIM_FLAG_CC5: TIM Capture Compare 5 Flag |
mbed_official | 157:90e3acc479a2 | 3069 | * @arg TIM_FLAG_CC6: TIM Capture Compare 6 Flag |
mbed_official | 157:90e3acc479a2 | 3070 | * @arg TIM_FLAG_COM: TIM Commutation Flag |
mbed_official | 157:90e3acc479a2 | 3071 | * @arg TIM_FLAG_Trigger: TIM Trigger Flag |
mbed_official | 157:90e3acc479a2 | 3072 | * @arg TIM_FLAG_Break: TIM Break Flag |
mbed_official | 157:90e3acc479a2 | 3073 | * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag |
mbed_official | 157:90e3acc479a2 | 3074 | * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag |
mbed_official | 157:90e3acc479a2 | 3075 | * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag |
mbed_official | 157:90e3acc479a2 | 3076 | * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag |
mbed_official | 157:90e3acc479a2 | 3077 | * |
mbed_official | 157:90e3acc479a2 | 3078 | * @note TIM6 and TIM7 can have only one update flag. |
mbed_official | 157:90e3acc479a2 | 3079 | * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. |
mbed_official | 157:90e3acc479a2 | 3080 | * |
mbed_official | 157:90e3acc479a2 | 3081 | * @retval None |
mbed_official | 157:90e3acc479a2 | 3082 | */ |
mbed_official | 157:90e3acc479a2 | 3083 | void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) |
mbed_official | 157:90e3acc479a2 | 3084 | { |
mbed_official | 157:90e3acc479a2 | 3085 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 3086 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 3087 | |
mbed_official | 157:90e3acc479a2 | 3088 | /* Clear the flags */ |
mbed_official | 157:90e3acc479a2 | 3089 | TIMx->SR = (uint16_t)~TIM_FLAG; |
mbed_official | 157:90e3acc479a2 | 3090 | } |
mbed_official | 157:90e3acc479a2 | 3091 | |
mbed_official | 157:90e3acc479a2 | 3092 | /** |
mbed_official | 157:90e3acc479a2 | 3093 | * @brief Checks whether the TIM interrupt has occurred or not. |
mbed_official | 157:90e3acc479a2 | 3094 | * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 3095 | * @param TIM_IT: specifies the TIM interrupt source to check. |
mbed_official | 157:90e3acc479a2 | 3096 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3097 | * @arg TIM_IT_Update: TIM update Interrupt source |
mbed_official | 157:90e3acc479a2 | 3098 | * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source |
mbed_official | 157:90e3acc479a2 | 3099 | * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source |
mbed_official | 157:90e3acc479a2 | 3100 | * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source |
mbed_official | 157:90e3acc479a2 | 3101 | * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source |
mbed_official | 157:90e3acc479a2 | 3102 | * @arg TIM_IT_COM: TIM Commutation Interrupt source |
mbed_official | 157:90e3acc479a2 | 3103 | * @arg TIM_IT_Trigger: TIM Trigger Interrupt source |
mbed_official | 157:90e3acc479a2 | 3104 | * @arg TIM_IT_Break: TIM Break Interrupt source |
mbed_official | 157:90e3acc479a2 | 3105 | * |
mbed_official | 157:90e3acc479a2 | 3106 | * @note TIM6 and TIM7 can generate only an update interrupt. |
mbed_official | 157:90e3acc479a2 | 3107 | * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. |
mbed_official | 157:90e3acc479a2 | 3108 | * |
mbed_official | 157:90e3acc479a2 | 3109 | * @retval The new state of the TIM_IT(SET or RESET). |
mbed_official | 157:90e3acc479a2 | 3110 | */ |
mbed_official | 157:90e3acc479a2 | 3111 | ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) |
mbed_official | 157:90e3acc479a2 | 3112 | { |
mbed_official | 157:90e3acc479a2 | 3113 | ITStatus bitstatus = RESET; |
mbed_official | 157:90e3acc479a2 | 3114 | uint16_t itstatus = 0x0, itenable = 0x0; |
mbed_official | 157:90e3acc479a2 | 3115 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 3116 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 3117 | assert_param(IS_TIM_GET_IT(TIM_IT)); |
mbed_official | 157:90e3acc479a2 | 3118 | |
mbed_official | 157:90e3acc479a2 | 3119 | itstatus = TIMx->SR & TIM_IT; |
mbed_official | 157:90e3acc479a2 | 3120 | |
mbed_official | 157:90e3acc479a2 | 3121 | itenable = TIMx->DIER & TIM_IT; |
mbed_official | 157:90e3acc479a2 | 3122 | if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) |
mbed_official | 157:90e3acc479a2 | 3123 | { |
mbed_official | 157:90e3acc479a2 | 3124 | bitstatus = SET; |
mbed_official | 157:90e3acc479a2 | 3125 | } |
mbed_official | 157:90e3acc479a2 | 3126 | else |
mbed_official | 157:90e3acc479a2 | 3127 | { |
mbed_official | 157:90e3acc479a2 | 3128 | bitstatus = RESET; |
mbed_official | 157:90e3acc479a2 | 3129 | } |
mbed_official | 157:90e3acc479a2 | 3130 | return bitstatus; |
mbed_official | 157:90e3acc479a2 | 3131 | } |
mbed_official | 157:90e3acc479a2 | 3132 | |
mbed_official | 157:90e3acc479a2 | 3133 | /** |
mbed_official | 157:90e3acc479a2 | 3134 | * @brief Clears the TIMx's interrupt pending bits. |
mbed_official | 157:90e3acc479a2 | 3135 | * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 3136 | * @param TIM_IT: specifies the pending bit to clear. |
mbed_official | 157:90e3acc479a2 | 3137 | * This parameter can be any combination of the following values: |
mbed_official | 157:90e3acc479a2 | 3138 | * @arg TIM_IT_Update: TIM1 update Interrupt source |
mbed_official | 157:90e3acc479a2 | 3139 | * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source |
mbed_official | 157:90e3acc479a2 | 3140 | * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source |
mbed_official | 157:90e3acc479a2 | 3141 | * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source |
mbed_official | 157:90e3acc479a2 | 3142 | * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source |
mbed_official | 157:90e3acc479a2 | 3143 | * @arg TIM_IT_COM: TIM Commutation Interrupt source |
mbed_official | 157:90e3acc479a2 | 3144 | * @arg TIM_IT_Trigger: TIM Trigger Interrupt source |
mbed_official | 157:90e3acc479a2 | 3145 | * @arg TIM_IT_Break: TIM Break Interrupt source |
mbed_official | 157:90e3acc479a2 | 3146 | * |
mbed_official | 157:90e3acc479a2 | 3147 | * @note TIM6 and TIM7 can generate only an update interrupt. |
mbed_official | 157:90e3acc479a2 | 3148 | * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. |
mbed_official | 157:90e3acc479a2 | 3149 | * |
mbed_official | 157:90e3acc479a2 | 3150 | * @retval None |
mbed_official | 157:90e3acc479a2 | 3151 | */ |
mbed_official | 157:90e3acc479a2 | 3152 | void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) |
mbed_official | 157:90e3acc479a2 | 3153 | { |
mbed_official | 157:90e3acc479a2 | 3154 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 3155 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 3156 | |
mbed_official | 157:90e3acc479a2 | 3157 | /* Clear the IT pending Bit */ |
mbed_official | 157:90e3acc479a2 | 3158 | TIMx->SR = (uint16_t)~TIM_IT; |
mbed_official | 157:90e3acc479a2 | 3159 | } |
mbed_official | 157:90e3acc479a2 | 3160 | |
mbed_official | 157:90e3acc479a2 | 3161 | /** |
mbed_official | 157:90e3acc479a2 | 3162 | * @brief Configures the TIMx's DMA interface. |
mbed_official | 157:90e3acc479a2 | 3163 | * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 3164 | * @param TIM_DMABase: DMA Base address. |
mbed_official | 157:90e3acc479a2 | 3165 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3166 | * @arg TIM_DMABase_CR1 |
mbed_official | 157:90e3acc479a2 | 3167 | * @arg TIM_DMABase_CR2 |
mbed_official | 157:90e3acc479a2 | 3168 | * @arg TIM_DMABase_SMCR |
mbed_official | 157:90e3acc479a2 | 3169 | * @arg TIM_DMABase_DIER |
mbed_official | 157:90e3acc479a2 | 3170 | * @arg TIM1_DMABase_SR |
mbed_official | 157:90e3acc479a2 | 3171 | * @arg TIM_DMABase_EGR |
mbed_official | 157:90e3acc479a2 | 3172 | * @arg TIM_DMABase_CCMR1 |
mbed_official | 157:90e3acc479a2 | 3173 | * @arg TIM_DMABase_CCMR2 |
mbed_official | 157:90e3acc479a2 | 3174 | * @arg TIM_DMABase_CCER |
mbed_official | 157:90e3acc479a2 | 3175 | * @arg TIM_DMABase_CNT |
mbed_official | 157:90e3acc479a2 | 3176 | * @arg TIM_DMABase_PSC |
mbed_official | 157:90e3acc479a2 | 3177 | * @arg TIM_DMABase_ARR |
mbed_official | 157:90e3acc479a2 | 3178 | * @arg TIM_DMABase_RCR |
mbed_official | 157:90e3acc479a2 | 3179 | * @arg TIM_DMABase_CCR1 |
mbed_official | 157:90e3acc479a2 | 3180 | * @arg TIM_DMABase_CCR2 |
mbed_official | 157:90e3acc479a2 | 3181 | * @arg TIM_DMABase_CCR3 |
mbed_official | 157:90e3acc479a2 | 3182 | * @arg TIM_DMABase_CCR4 |
mbed_official | 157:90e3acc479a2 | 3183 | * @arg TIM_DMABase_BDTR |
mbed_official | 157:90e3acc479a2 | 3184 | * @arg TIM_DMABase_DCR |
mbed_official | 157:90e3acc479a2 | 3185 | * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value |
mbed_official | 157:90e3acc479a2 | 3186 | * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. |
mbed_official | 157:90e3acc479a2 | 3187 | * @retval None |
mbed_official | 157:90e3acc479a2 | 3188 | */ |
mbed_official | 157:90e3acc479a2 | 3189 | void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) |
mbed_official | 157:90e3acc479a2 | 3190 | { |
mbed_official | 157:90e3acc479a2 | 3191 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 3192 | assert_param(IS_TIM_LIST1_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 3193 | assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); |
mbed_official | 157:90e3acc479a2 | 3194 | assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); |
mbed_official | 157:90e3acc479a2 | 3195 | |
mbed_official | 157:90e3acc479a2 | 3196 | /* Set the DMA Base and the DMA Burst Length */ |
mbed_official | 157:90e3acc479a2 | 3197 | TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; |
mbed_official | 157:90e3acc479a2 | 3198 | } |
mbed_official | 157:90e3acc479a2 | 3199 | |
mbed_official | 157:90e3acc479a2 | 3200 | /** |
mbed_official | 157:90e3acc479a2 | 3201 | * @brief Enables or disables the TIMx's DMA Requests. |
mbed_official | 157:90e3acc479a2 | 3202 | * @param TIMx: where x can be 1, 2, 3, 4, 6, 7, 8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 3203 | * @param TIM_DMASource: specifies the DMA Request sources. |
mbed_official | 157:90e3acc479a2 | 3204 | * This parameter can be any combination of the following values: |
mbed_official | 157:90e3acc479a2 | 3205 | * @arg TIM_DMA_Update: TIM update Interrupt source |
mbed_official | 157:90e3acc479a2 | 3206 | * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source |
mbed_official | 157:90e3acc479a2 | 3207 | * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source |
mbed_official | 157:90e3acc479a2 | 3208 | * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source |
mbed_official | 157:90e3acc479a2 | 3209 | * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source |
mbed_official | 157:90e3acc479a2 | 3210 | * @arg TIM_DMA_COM: TIM Commutation DMA source |
mbed_official | 157:90e3acc479a2 | 3211 | * @arg TIM_DMA_Trigger: TIM Trigger DMA source |
mbed_official | 157:90e3acc479a2 | 3212 | * @param NewState: new state of the DMA Request sources. |
mbed_official | 157:90e3acc479a2 | 3213 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 157:90e3acc479a2 | 3214 | * @retval None |
mbed_official | 157:90e3acc479a2 | 3215 | */ |
mbed_official | 157:90e3acc479a2 | 3216 | void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) |
mbed_official | 157:90e3acc479a2 | 3217 | { |
mbed_official | 157:90e3acc479a2 | 3218 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 3219 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 3220 | assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); |
mbed_official | 157:90e3acc479a2 | 3221 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 157:90e3acc479a2 | 3222 | |
mbed_official | 157:90e3acc479a2 | 3223 | if (NewState != DISABLE) |
mbed_official | 157:90e3acc479a2 | 3224 | { |
mbed_official | 157:90e3acc479a2 | 3225 | /* Enable the DMA sources */ |
mbed_official | 157:90e3acc479a2 | 3226 | TIMx->DIER |= TIM_DMASource; |
mbed_official | 157:90e3acc479a2 | 3227 | } |
mbed_official | 157:90e3acc479a2 | 3228 | else |
mbed_official | 157:90e3acc479a2 | 3229 | { |
mbed_official | 157:90e3acc479a2 | 3230 | /* Disable the DMA sources */ |
mbed_official | 157:90e3acc479a2 | 3231 | TIMx->DIER &= (uint16_t)~TIM_DMASource; |
mbed_official | 157:90e3acc479a2 | 3232 | } |
mbed_official | 157:90e3acc479a2 | 3233 | } |
mbed_official | 157:90e3acc479a2 | 3234 | |
mbed_official | 157:90e3acc479a2 | 3235 | /** |
mbed_official | 157:90e3acc479a2 | 3236 | * @brief Selects the TIMx peripheral Capture Compare DMA source. |
mbed_official | 157:90e3acc479a2 | 3237 | * @param TIMx: where x can be 1, 2, 3, 4, 8, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 3238 | * @param NewState: new state of the Capture Compare DMA source |
mbed_official | 157:90e3acc479a2 | 3239 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 157:90e3acc479a2 | 3240 | * @retval None |
mbed_official | 157:90e3acc479a2 | 3241 | */ |
mbed_official | 157:90e3acc479a2 | 3242 | void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) |
mbed_official | 157:90e3acc479a2 | 3243 | { |
mbed_official | 157:90e3acc479a2 | 3244 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 3245 | assert_param(IS_TIM_LIST1_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 3246 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 157:90e3acc479a2 | 3247 | |
mbed_official | 157:90e3acc479a2 | 3248 | if (NewState != DISABLE) |
mbed_official | 157:90e3acc479a2 | 3249 | { |
mbed_official | 157:90e3acc479a2 | 3250 | /* Set the CCDS Bit */ |
mbed_official | 157:90e3acc479a2 | 3251 | TIMx->CR2 |= TIM_CR2_CCDS; |
mbed_official | 157:90e3acc479a2 | 3252 | } |
mbed_official | 157:90e3acc479a2 | 3253 | else |
mbed_official | 157:90e3acc479a2 | 3254 | { |
mbed_official | 157:90e3acc479a2 | 3255 | /* Reset the CCDS Bit */ |
mbed_official | 157:90e3acc479a2 | 3256 | TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS; |
mbed_official | 157:90e3acc479a2 | 3257 | } |
mbed_official | 157:90e3acc479a2 | 3258 | } |
mbed_official | 157:90e3acc479a2 | 3259 | /** |
mbed_official | 157:90e3acc479a2 | 3260 | * @} |
mbed_official | 157:90e3acc479a2 | 3261 | */ |
mbed_official | 157:90e3acc479a2 | 3262 | |
mbed_official | 157:90e3acc479a2 | 3263 | /** @defgroup TIM_Group6 Clocks management functions |
mbed_official | 157:90e3acc479a2 | 3264 | * @brief Clocks management functions |
mbed_official | 157:90e3acc479a2 | 3265 | * |
mbed_official | 157:90e3acc479a2 | 3266 | @verbatim |
mbed_official | 157:90e3acc479a2 | 3267 | =============================================================================== |
mbed_official | 157:90e3acc479a2 | 3268 | ##### Clocks management functions ##### |
mbed_official | 157:90e3acc479a2 | 3269 | =============================================================================== |
mbed_official | 157:90e3acc479a2 | 3270 | |
mbed_official | 157:90e3acc479a2 | 3271 | @endverbatim |
mbed_official | 157:90e3acc479a2 | 3272 | * @{ |
mbed_official | 157:90e3acc479a2 | 3273 | */ |
mbed_official | 157:90e3acc479a2 | 3274 | |
mbed_official | 157:90e3acc479a2 | 3275 | /** |
mbed_official | 157:90e3acc479a2 | 3276 | * @brief Configures the TIMx internal Clock |
mbed_official | 157:90e3acc479a2 | 3277 | * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM |
mbed_official | 157:90e3acc479a2 | 3278 | * peripheral. |
mbed_official | 157:90e3acc479a2 | 3279 | * @retval None |
mbed_official | 157:90e3acc479a2 | 3280 | */ |
mbed_official | 157:90e3acc479a2 | 3281 | void TIM_InternalClockConfig(TIM_TypeDef* TIMx) |
mbed_official | 157:90e3acc479a2 | 3282 | { |
mbed_official | 157:90e3acc479a2 | 3283 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 3284 | assert_param(IS_TIM_LIST2_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 3285 | |
mbed_official | 157:90e3acc479a2 | 3286 | /* Disable slave mode to clock the prescaler directly with the internal clock */ |
mbed_official | 157:90e3acc479a2 | 3287 | TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; |
mbed_official | 157:90e3acc479a2 | 3288 | } |
mbed_official | 157:90e3acc479a2 | 3289 | |
mbed_official | 157:90e3acc479a2 | 3290 | /** |
mbed_official | 157:90e3acc479a2 | 3291 | * @brief Configures the TIMx Internal Trigger as External Clock |
mbed_official | 157:90e3acc479a2 | 3292 | * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM |
mbed_official | 157:90e3acc479a2 | 3293 | * peripheral. |
mbed_official | 157:90e3acc479a2 | 3294 | * @param TIM_InputTriggerSource: Trigger source. |
mbed_official | 157:90e3acc479a2 | 3295 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3296 | * @arg TIM_TS_ITR0: Internal Trigger 0 |
mbed_official | 157:90e3acc479a2 | 3297 | * @arg TIM_TS_ITR1: Internal Trigger 1 |
mbed_official | 157:90e3acc479a2 | 3298 | * @arg TIM_TS_ITR2: Internal Trigger 2 |
mbed_official | 157:90e3acc479a2 | 3299 | * @arg TIM_TS_ITR3: Internal Trigger 3 |
mbed_official | 157:90e3acc479a2 | 3300 | * @retval None |
mbed_official | 157:90e3acc479a2 | 3301 | */ |
mbed_official | 157:90e3acc479a2 | 3302 | void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) |
mbed_official | 157:90e3acc479a2 | 3303 | { |
mbed_official | 157:90e3acc479a2 | 3304 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 3305 | assert_param(IS_TIM_LIST2_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 3306 | assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); |
mbed_official | 157:90e3acc479a2 | 3307 | |
mbed_official | 157:90e3acc479a2 | 3308 | /* Select the Internal Trigger */ |
mbed_official | 157:90e3acc479a2 | 3309 | TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); |
mbed_official | 157:90e3acc479a2 | 3310 | |
mbed_official | 157:90e3acc479a2 | 3311 | /* Select the External clock mode1 */ |
mbed_official | 157:90e3acc479a2 | 3312 | TIMx->SMCR |= TIM_SlaveMode_External1; |
mbed_official | 157:90e3acc479a2 | 3313 | } |
mbed_official | 157:90e3acc479a2 | 3314 | |
mbed_official | 157:90e3acc479a2 | 3315 | /** |
mbed_official | 157:90e3acc479a2 | 3316 | * @brief Configures the TIMx Trigger as External Clock |
mbed_official | 157:90e3acc479a2 | 3317 | * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 |
mbed_official | 157:90e3acc479a2 | 3318 | * to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 3319 | * @param TIM_TIxExternalCLKSource: Trigger source. |
mbed_official | 157:90e3acc479a2 | 3320 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3321 | * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector |
mbed_official | 157:90e3acc479a2 | 3322 | * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 |
mbed_official | 157:90e3acc479a2 | 3323 | * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 |
mbed_official | 157:90e3acc479a2 | 3324 | * @param TIM_ICPolarity: specifies the TIx Polarity. |
mbed_official | 157:90e3acc479a2 | 3325 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3326 | * @arg TIM_ICPolarity_Rising |
mbed_official | 157:90e3acc479a2 | 3327 | * @arg TIM_ICPolarity_Falling |
mbed_official | 157:90e3acc479a2 | 3328 | * @param ICFilter: specifies the filter value. |
mbed_official | 157:90e3acc479a2 | 3329 | * This parameter must be a value between 0x0 and 0xF. |
mbed_official | 157:90e3acc479a2 | 3330 | * @retval None |
mbed_official | 157:90e3acc479a2 | 3331 | */ |
mbed_official | 157:90e3acc479a2 | 3332 | void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, |
mbed_official | 157:90e3acc479a2 | 3333 | uint16_t TIM_ICPolarity, uint16_t ICFilter) |
mbed_official | 157:90e3acc479a2 | 3334 | { |
mbed_official | 157:90e3acc479a2 | 3335 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 3336 | assert_param(IS_TIM_LIST2_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 3337 | assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); |
mbed_official | 157:90e3acc479a2 | 3338 | assert_param(IS_TIM_IC_FILTER(ICFilter)); |
mbed_official | 157:90e3acc479a2 | 3339 | |
mbed_official | 157:90e3acc479a2 | 3340 | /* Configure the Timer Input Clock Source */ |
mbed_official | 157:90e3acc479a2 | 3341 | if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) |
mbed_official | 157:90e3acc479a2 | 3342 | { |
mbed_official | 157:90e3acc479a2 | 3343 | TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); |
mbed_official | 157:90e3acc479a2 | 3344 | } |
mbed_official | 157:90e3acc479a2 | 3345 | else |
mbed_official | 157:90e3acc479a2 | 3346 | { |
mbed_official | 157:90e3acc479a2 | 3347 | TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); |
mbed_official | 157:90e3acc479a2 | 3348 | } |
mbed_official | 157:90e3acc479a2 | 3349 | /* Select the Trigger source */ |
mbed_official | 157:90e3acc479a2 | 3350 | TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); |
mbed_official | 157:90e3acc479a2 | 3351 | /* Select the External clock mode1 */ |
mbed_official | 157:90e3acc479a2 | 3352 | TIMx->SMCR |= TIM_SlaveMode_External1; |
mbed_official | 157:90e3acc479a2 | 3353 | } |
mbed_official | 157:90e3acc479a2 | 3354 | |
mbed_official | 157:90e3acc479a2 | 3355 | /** |
mbed_official | 157:90e3acc479a2 | 3356 | * @brief Configures the External clock Mode1 |
mbed_official | 157:90e3acc479a2 | 3357 | * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 3358 | * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. |
mbed_official | 157:90e3acc479a2 | 3359 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3360 | * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. |
mbed_official | 157:90e3acc479a2 | 3361 | * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. |
mbed_official | 157:90e3acc479a2 | 3362 | * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. |
mbed_official | 157:90e3acc479a2 | 3363 | * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. |
mbed_official | 157:90e3acc479a2 | 3364 | * @param TIM_ExtTRGPolarity: The external Trigger Polarity. |
mbed_official | 157:90e3acc479a2 | 3365 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3366 | * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. |
mbed_official | 157:90e3acc479a2 | 3367 | * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. |
mbed_official | 157:90e3acc479a2 | 3368 | * @param ExtTRGFilter: External Trigger Filter. |
mbed_official | 157:90e3acc479a2 | 3369 | * This parameter must be a value between 0x00 and 0x0F |
mbed_official | 157:90e3acc479a2 | 3370 | * @retval None |
mbed_official | 157:90e3acc479a2 | 3371 | */ |
mbed_official | 157:90e3acc479a2 | 3372 | void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, |
mbed_official | 157:90e3acc479a2 | 3373 | uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) |
mbed_official | 157:90e3acc479a2 | 3374 | { |
mbed_official | 157:90e3acc479a2 | 3375 | uint16_t tmpsmcr = 0; |
mbed_official | 157:90e3acc479a2 | 3376 | |
mbed_official | 157:90e3acc479a2 | 3377 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 3378 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 3379 | assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); |
mbed_official | 157:90e3acc479a2 | 3380 | assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); |
mbed_official | 157:90e3acc479a2 | 3381 | assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); |
mbed_official | 157:90e3acc479a2 | 3382 | /* Configure the ETR Clock source */ |
mbed_official | 157:90e3acc479a2 | 3383 | TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); |
mbed_official | 157:90e3acc479a2 | 3384 | |
mbed_official | 157:90e3acc479a2 | 3385 | /* Get the TIMx SMCR register value */ |
mbed_official | 157:90e3acc479a2 | 3386 | tmpsmcr = TIMx->SMCR; |
mbed_official | 157:90e3acc479a2 | 3387 | |
mbed_official | 157:90e3acc479a2 | 3388 | /* Reset the SMS Bits */ |
mbed_official | 157:90e3acc479a2 | 3389 | tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; |
mbed_official | 157:90e3acc479a2 | 3390 | |
mbed_official | 157:90e3acc479a2 | 3391 | /* Select the External clock mode1 */ |
mbed_official | 157:90e3acc479a2 | 3392 | tmpsmcr |= TIM_SlaveMode_External1; |
mbed_official | 157:90e3acc479a2 | 3393 | |
mbed_official | 157:90e3acc479a2 | 3394 | /* Select the Trigger selection : ETRF */ |
mbed_official | 157:90e3acc479a2 | 3395 | tmpsmcr &= (uint16_t)~TIM_SMCR_TS; |
mbed_official | 157:90e3acc479a2 | 3396 | tmpsmcr |= TIM_TS_ETRF; |
mbed_official | 157:90e3acc479a2 | 3397 | |
mbed_official | 157:90e3acc479a2 | 3398 | /* Write to TIMx SMCR */ |
mbed_official | 157:90e3acc479a2 | 3399 | TIMx->SMCR = tmpsmcr; |
mbed_official | 157:90e3acc479a2 | 3400 | } |
mbed_official | 157:90e3acc479a2 | 3401 | |
mbed_official | 157:90e3acc479a2 | 3402 | /** |
mbed_official | 157:90e3acc479a2 | 3403 | * @brief Configures the External clock Mode2 |
mbed_official | 157:90e3acc479a2 | 3404 | * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 3405 | * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. |
mbed_official | 157:90e3acc479a2 | 3406 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3407 | * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. |
mbed_official | 157:90e3acc479a2 | 3408 | * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. |
mbed_official | 157:90e3acc479a2 | 3409 | * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. |
mbed_official | 157:90e3acc479a2 | 3410 | * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. |
mbed_official | 157:90e3acc479a2 | 3411 | * @param TIM_ExtTRGPolarity: The external Trigger Polarity. |
mbed_official | 157:90e3acc479a2 | 3412 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3413 | * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. |
mbed_official | 157:90e3acc479a2 | 3414 | * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. |
mbed_official | 157:90e3acc479a2 | 3415 | * @param ExtTRGFilter: External Trigger Filter. |
mbed_official | 157:90e3acc479a2 | 3416 | * This parameter must be a value between 0x00 and 0x0F |
mbed_official | 157:90e3acc479a2 | 3417 | * @retval None |
mbed_official | 157:90e3acc479a2 | 3418 | */ |
mbed_official | 157:90e3acc479a2 | 3419 | void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, |
mbed_official | 157:90e3acc479a2 | 3420 | uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) |
mbed_official | 157:90e3acc479a2 | 3421 | { |
mbed_official | 157:90e3acc479a2 | 3422 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 3423 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 3424 | assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); |
mbed_official | 157:90e3acc479a2 | 3425 | assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); |
mbed_official | 157:90e3acc479a2 | 3426 | assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); |
mbed_official | 157:90e3acc479a2 | 3427 | |
mbed_official | 157:90e3acc479a2 | 3428 | /* Configure the ETR Clock source */ |
mbed_official | 157:90e3acc479a2 | 3429 | TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); |
mbed_official | 157:90e3acc479a2 | 3430 | |
mbed_official | 157:90e3acc479a2 | 3431 | /* Enable the External clock mode2 */ |
mbed_official | 157:90e3acc479a2 | 3432 | TIMx->SMCR |= TIM_SMCR_ECE; |
mbed_official | 157:90e3acc479a2 | 3433 | } |
mbed_official | 157:90e3acc479a2 | 3434 | /** |
mbed_official | 157:90e3acc479a2 | 3435 | * @} |
mbed_official | 157:90e3acc479a2 | 3436 | */ |
mbed_official | 157:90e3acc479a2 | 3437 | |
mbed_official | 157:90e3acc479a2 | 3438 | /** @defgroup TIM_Group7 Synchronization management functions |
mbed_official | 157:90e3acc479a2 | 3439 | * @brief Synchronization management functions |
mbed_official | 157:90e3acc479a2 | 3440 | * |
mbed_official | 157:90e3acc479a2 | 3441 | @verbatim |
mbed_official | 157:90e3acc479a2 | 3442 | =============================================================================== |
mbed_official | 157:90e3acc479a2 | 3443 | ##### Synchronization management functions ##### |
mbed_official | 157:90e3acc479a2 | 3444 | =============================================================================== |
mbed_official | 157:90e3acc479a2 | 3445 | |
mbed_official | 157:90e3acc479a2 | 3446 | *** TIM Driver: how to use it in synchronization Mode *** |
mbed_official | 157:90e3acc479a2 | 3447 | ========================================================= |
mbed_official | 157:90e3acc479a2 | 3448 | [..] Case of two/several Timers |
mbed_official | 157:90e3acc479a2 | 3449 | |
mbed_official | 157:90e3acc479a2 | 3450 | (#) Configure the Master Timers using the following functions: |
mbed_official | 157:90e3acc479a2 | 3451 | (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); |
mbed_official | 157:90e3acc479a2 | 3452 | (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); |
mbed_official | 157:90e3acc479a2 | 3453 | (#) Configure the Slave Timers using the following functions: |
mbed_official | 157:90e3acc479a2 | 3454 | (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); |
mbed_official | 157:90e3acc479a2 | 3455 | (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); |
mbed_official | 157:90e3acc479a2 | 3456 | |
mbed_official | 157:90e3acc479a2 | 3457 | [..] Case of Timers and external trigger(ETR pin) |
mbed_official | 157:90e3acc479a2 | 3458 | |
mbed_official | 157:90e3acc479a2 | 3459 | (#) Configure the External trigger using this function: |
mbed_official | 157:90e3acc479a2 | 3460 | (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, |
mbed_official | 157:90e3acc479a2 | 3461 | uint16_t ExtTRGFilter); |
mbed_official | 157:90e3acc479a2 | 3462 | (#) Configure the Slave Timers using the following functions: |
mbed_official | 157:90e3acc479a2 | 3463 | (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); |
mbed_official | 157:90e3acc479a2 | 3464 | (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); |
mbed_official | 157:90e3acc479a2 | 3465 | |
mbed_official | 157:90e3acc479a2 | 3466 | @endverbatim |
mbed_official | 157:90e3acc479a2 | 3467 | * @{ |
mbed_official | 157:90e3acc479a2 | 3468 | */ |
mbed_official | 157:90e3acc479a2 | 3469 | |
mbed_official | 157:90e3acc479a2 | 3470 | /** |
mbed_official | 157:90e3acc479a2 | 3471 | * @brief Selects the Input Trigger source |
mbed_official | 157:90e3acc479a2 | 3472 | * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 |
mbed_official | 157:90e3acc479a2 | 3473 | * to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 3474 | * @param TIM_InputTriggerSource: The Input Trigger source. |
mbed_official | 157:90e3acc479a2 | 3475 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3476 | * @arg TIM_TS_ITR0: Internal Trigger 0 |
mbed_official | 157:90e3acc479a2 | 3477 | * @arg TIM_TS_ITR1: Internal Trigger 1 |
mbed_official | 157:90e3acc479a2 | 3478 | * @arg TIM_TS_ITR2: Internal Trigger 2 |
mbed_official | 157:90e3acc479a2 | 3479 | * @arg TIM_TS_ITR3: Internal Trigger 3 |
mbed_official | 157:90e3acc479a2 | 3480 | * @arg TIM_TS_TI1F_ED: TI1 Edge Detector |
mbed_official | 157:90e3acc479a2 | 3481 | * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 |
mbed_official | 157:90e3acc479a2 | 3482 | * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 |
mbed_official | 157:90e3acc479a2 | 3483 | * @arg TIM_TS_ETRF: External Trigger input |
mbed_official | 157:90e3acc479a2 | 3484 | * @retval None |
mbed_official | 157:90e3acc479a2 | 3485 | */ |
mbed_official | 157:90e3acc479a2 | 3486 | void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) |
mbed_official | 157:90e3acc479a2 | 3487 | { |
mbed_official | 157:90e3acc479a2 | 3488 | uint16_t tmpsmcr = 0; |
mbed_official | 157:90e3acc479a2 | 3489 | |
mbed_official | 157:90e3acc479a2 | 3490 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 3491 | assert_param(IS_TIM_LIST2_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 3492 | assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); |
mbed_official | 157:90e3acc479a2 | 3493 | |
mbed_official | 157:90e3acc479a2 | 3494 | /* Get the TIMx SMCR register value */ |
mbed_official | 157:90e3acc479a2 | 3495 | tmpsmcr = TIMx->SMCR; |
mbed_official | 157:90e3acc479a2 | 3496 | |
mbed_official | 157:90e3acc479a2 | 3497 | /* Reset the TS Bits */ |
mbed_official | 157:90e3acc479a2 | 3498 | tmpsmcr &= (uint16_t)~TIM_SMCR_TS; |
mbed_official | 157:90e3acc479a2 | 3499 | |
mbed_official | 157:90e3acc479a2 | 3500 | /* Set the Input Trigger source */ |
mbed_official | 157:90e3acc479a2 | 3501 | tmpsmcr |= TIM_InputTriggerSource; |
mbed_official | 157:90e3acc479a2 | 3502 | |
mbed_official | 157:90e3acc479a2 | 3503 | /* Write to TIMx SMCR */ |
mbed_official | 157:90e3acc479a2 | 3504 | TIMx->SMCR = tmpsmcr; |
mbed_official | 157:90e3acc479a2 | 3505 | } |
mbed_official | 157:90e3acc479a2 | 3506 | |
mbed_official | 157:90e3acc479a2 | 3507 | /** |
mbed_official | 157:90e3acc479a2 | 3508 | * @brief Selects the TIMx Trigger Output Mode. |
mbed_official | 157:90e3acc479a2 | 3509 | * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8 or 15 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 3510 | * |
mbed_official | 157:90e3acc479a2 | 3511 | * @param TIM_TRGOSource: specifies the Trigger Output source. |
mbed_official | 157:90e3acc479a2 | 3512 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3513 | * |
mbed_official | 157:90e3acc479a2 | 3514 | * - For all TIMx |
mbed_official | 157:90e3acc479a2 | 3515 | * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO) |
mbed_official | 157:90e3acc479a2 | 3516 | * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO) |
mbed_official | 157:90e3acc479a2 | 3517 | * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO) |
mbed_official | 157:90e3acc479a2 | 3518 | * |
mbed_official | 157:90e3acc479a2 | 3519 | * - For all TIMx except TIM6 and TIM7 |
mbed_official | 157:90e3acc479a2 | 3520 | * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag |
mbed_official | 157:90e3acc479a2 | 3521 | * is to be set, as soon as a capture or compare match occurs(TRGO) |
mbed_official | 157:90e3acc479a2 | 3522 | * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO) |
mbed_official | 157:90e3acc479a2 | 3523 | * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO) |
mbed_official | 157:90e3acc479a2 | 3524 | * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO) |
mbed_official | 157:90e3acc479a2 | 3525 | * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO) |
mbed_official | 157:90e3acc479a2 | 3526 | * |
mbed_official | 157:90e3acc479a2 | 3527 | * @retval None |
mbed_official | 157:90e3acc479a2 | 3528 | */ |
mbed_official | 157:90e3acc479a2 | 3529 | void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) |
mbed_official | 157:90e3acc479a2 | 3530 | { |
mbed_official | 157:90e3acc479a2 | 3531 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 3532 | assert_param(IS_TIM_LIST7_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 3533 | assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); |
mbed_official | 157:90e3acc479a2 | 3534 | |
mbed_official | 157:90e3acc479a2 | 3535 | /* Reset the MMS Bits */ |
mbed_official | 157:90e3acc479a2 | 3536 | TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS; |
mbed_official | 157:90e3acc479a2 | 3537 | /* Select the TRGO source */ |
mbed_official | 157:90e3acc479a2 | 3538 | TIMx->CR2 |= TIM_TRGOSource; |
mbed_official | 157:90e3acc479a2 | 3539 | } |
mbed_official | 157:90e3acc479a2 | 3540 | |
mbed_official | 157:90e3acc479a2 | 3541 | /** |
mbed_official | 157:90e3acc479a2 | 3542 | * @brief Selects the TIMx Trigger Output Mode2 (TRGO2). |
mbed_official | 157:90e3acc479a2 | 3543 | * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 3544 | * |
mbed_official | 157:90e3acc479a2 | 3545 | * @param TIM_TRGO2Source: specifies the Trigger Output source. |
mbed_official | 157:90e3acc479a2 | 3546 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3547 | * |
mbed_official | 157:90e3acc479a2 | 3548 | * - For all TIMx |
mbed_official | 157:90e3acc479a2 | 3549 | * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO2) |
mbed_official | 157:90e3acc479a2 | 3550 | * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO2) |
mbed_official | 157:90e3acc479a2 | 3551 | * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO2) |
mbed_official | 157:90e3acc479a2 | 3552 | * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag |
mbed_official | 157:90e3acc479a2 | 3553 | * is to be set, as soon as a capture or compare match occurs(TRGO2) |
mbed_official | 157:90e3acc479a2 | 3554 | * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO2) |
mbed_official | 157:90e3acc479a2 | 3555 | * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO2) |
mbed_official | 157:90e3acc479a2 | 3556 | * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO2) |
mbed_official | 157:90e3acc479a2 | 3557 | * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO2) |
mbed_official | 157:90e3acc479a2 | 3558 | * @arg TIM_TRGO2Source_OC4Ref_RisingFalling: OC4Ref Rising and Falling are used as the trigger output(TRGO2) |
mbed_official | 157:90e3acc479a2 | 3559 | * @arg TIM_TRGO2Source_OC6Ref_RisingFalling: OC6Ref Rising and Falling are used as the trigger output(TRGO2) |
mbed_official | 157:90e3acc479a2 | 3560 | * @arg TIM_TRGO2Source_OC4RefRising_OC6RefRising: OC4Ref Rising and OC6Ref Rising are used as the trigger output(TRGO2) |
mbed_official | 157:90e3acc479a2 | 3561 | * @arg TIM_TRGO2Source_OC4RefRising_OC6RefFalling: OC4Ref Rising and OC6Ref Falling are used as the trigger output(TRGO2) |
mbed_official | 157:90e3acc479a2 | 3562 | * @arg TIM_TRGO2Source_OC5RefRising_OC6RefRising: OC5Ref Rising and OC6Ref Rising are used as the trigger output(TRGO2) |
mbed_official | 157:90e3acc479a2 | 3563 | * @arg TIM_TRGO2Source_OC5RefRising_OC6RefFalling: OC5Ref Rising and OC6Ref Falling are used as the trigger output(TRGO2) |
mbed_official | 157:90e3acc479a2 | 3564 | * |
mbed_official | 157:90e3acc479a2 | 3565 | * @retval None |
mbed_official | 157:90e3acc479a2 | 3566 | */ |
mbed_official | 157:90e3acc479a2 | 3567 | void TIM_SelectOutputTrigger2(TIM_TypeDef* TIMx, uint32_t TIM_TRGO2Source) |
mbed_official | 157:90e3acc479a2 | 3568 | { |
mbed_official | 157:90e3acc479a2 | 3569 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 3570 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 3571 | assert_param(IS_TIM_TRGO2_SOURCE(TIM_TRGO2Source)); |
mbed_official | 157:90e3acc479a2 | 3572 | |
mbed_official | 157:90e3acc479a2 | 3573 | /* Reset the MMS Bits */ |
mbed_official | 157:90e3acc479a2 | 3574 | TIMx->CR2 &= (uint32_t)~TIM_CR2_MMS2; |
mbed_official | 157:90e3acc479a2 | 3575 | /* Select the TRGO source */ |
mbed_official | 157:90e3acc479a2 | 3576 | TIMx->CR2 |= TIM_TRGO2Source; |
mbed_official | 157:90e3acc479a2 | 3577 | } |
mbed_official | 157:90e3acc479a2 | 3578 | |
mbed_official | 157:90e3acc479a2 | 3579 | /** |
mbed_official | 157:90e3acc479a2 | 3580 | * @brief Selects the TIMx Slave Mode. |
mbed_official | 157:90e3acc479a2 | 3581 | * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 3582 | * @param TIM_SlaveMode: specifies the Timer Slave Mode. |
mbed_official | 157:90e3acc479a2 | 3583 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3584 | * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize |
mbed_official | 157:90e3acc479a2 | 3585 | * the counter and triggers an update of the registers |
mbed_official | 157:90e3acc479a2 | 3586 | * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high |
mbed_official | 157:90e3acc479a2 | 3587 | * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI |
mbed_official | 157:90e3acc479a2 | 3588 | * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter |
mbed_official | 157:90e3acc479a2 | 3589 | * @arg TIM_SlaveMode_Combined_ResetTrigger: Rising edge of the selected trigger input (TRGI) |
mbed_official | 157:90e3acc479a2 | 3590 | * reinitializes the counter, generates an update |
mbed_official | 157:90e3acc479a2 | 3591 | * of the registers and starts the counter. |
mbed_official | 157:90e3acc479a2 | 3592 | * @retval None |
mbed_official | 157:90e3acc479a2 | 3593 | */ |
mbed_official | 157:90e3acc479a2 | 3594 | void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode) |
mbed_official | 157:90e3acc479a2 | 3595 | { |
mbed_official | 157:90e3acc479a2 | 3596 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 3597 | assert_param(IS_TIM_LIST2_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 3598 | assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); |
mbed_official | 157:90e3acc479a2 | 3599 | |
mbed_official | 157:90e3acc479a2 | 3600 | /* Reset the SMS Bits */ |
mbed_official | 157:90e3acc479a2 | 3601 | TIMx->SMCR &= (uint32_t)~TIM_SMCR_SMS; |
mbed_official | 157:90e3acc479a2 | 3602 | |
mbed_official | 157:90e3acc479a2 | 3603 | /* Select the Slave Mode */ |
mbed_official | 157:90e3acc479a2 | 3604 | TIMx->SMCR |= (uint32_t)TIM_SlaveMode; |
mbed_official | 157:90e3acc479a2 | 3605 | } |
mbed_official | 157:90e3acc479a2 | 3606 | |
mbed_official | 157:90e3acc479a2 | 3607 | /** |
mbed_official | 157:90e3acc479a2 | 3608 | * @brief Sets or Resets the TIMx Master/Slave Mode. |
mbed_official | 157:90e3acc479a2 | 3609 | * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 3610 | * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. |
mbed_official | 157:90e3acc479a2 | 3611 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3612 | * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer |
mbed_official | 157:90e3acc479a2 | 3613 | * and its slaves (through TRGO) |
mbed_official | 157:90e3acc479a2 | 3614 | * @arg TIM_MasterSlaveMode_Disable: No action |
mbed_official | 157:90e3acc479a2 | 3615 | * @retval None |
mbed_official | 157:90e3acc479a2 | 3616 | */ |
mbed_official | 157:90e3acc479a2 | 3617 | void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) |
mbed_official | 157:90e3acc479a2 | 3618 | { |
mbed_official | 157:90e3acc479a2 | 3619 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 3620 | assert_param(IS_TIM_LIST2_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 3621 | assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); |
mbed_official | 157:90e3acc479a2 | 3622 | |
mbed_official | 157:90e3acc479a2 | 3623 | /* Reset the MSM Bit */ |
mbed_official | 157:90e3acc479a2 | 3624 | TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM; |
mbed_official | 157:90e3acc479a2 | 3625 | |
mbed_official | 157:90e3acc479a2 | 3626 | /* Set or Reset the MSM Bit */ |
mbed_official | 157:90e3acc479a2 | 3627 | TIMx->SMCR |= TIM_MasterSlaveMode; |
mbed_official | 157:90e3acc479a2 | 3628 | } |
mbed_official | 157:90e3acc479a2 | 3629 | |
mbed_official | 157:90e3acc479a2 | 3630 | /** |
mbed_official | 157:90e3acc479a2 | 3631 | * @brief Configures the TIMx External Trigger (ETR). |
mbed_official | 157:90e3acc479a2 | 3632 | * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 3633 | * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. |
mbed_official | 157:90e3acc479a2 | 3634 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3635 | * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. |
mbed_official | 157:90e3acc479a2 | 3636 | * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. |
mbed_official | 157:90e3acc479a2 | 3637 | * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. |
mbed_official | 157:90e3acc479a2 | 3638 | * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. |
mbed_official | 157:90e3acc479a2 | 3639 | * @param TIM_ExtTRGPolarity: The external Trigger Polarity. |
mbed_official | 157:90e3acc479a2 | 3640 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3641 | * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. |
mbed_official | 157:90e3acc479a2 | 3642 | * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. |
mbed_official | 157:90e3acc479a2 | 3643 | * @param ExtTRGFilter: External Trigger Filter. |
mbed_official | 157:90e3acc479a2 | 3644 | * This parameter must be a value between 0x00 and 0x0F |
mbed_official | 157:90e3acc479a2 | 3645 | * @retval None |
mbed_official | 157:90e3acc479a2 | 3646 | */ |
mbed_official | 157:90e3acc479a2 | 3647 | void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, |
mbed_official | 157:90e3acc479a2 | 3648 | uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) |
mbed_official | 157:90e3acc479a2 | 3649 | { |
mbed_official | 157:90e3acc479a2 | 3650 | uint16_t tmpsmcr = 0; |
mbed_official | 157:90e3acc479a2 | 3651 | |
mbed_official | 157:90e3acc479a2 | 3652 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 3653 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 3654 | assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); |
mbed_official | 157:90e3acc479a2 | 3655 | assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); |
mbed_official | 157:90e3acc479a2 | 3656 | assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); |
mbed_official | 157:90e3acc479a2 | 3657 | |
mbed_official | 157:90e3acc479a2 | 3658 | tmpsmcr = TIMx->SMCR; |
mbed_official | 157:90e3acc479a2 | 3659 | |
mbed_official | 157:90e3acc479a2 | 3660 | /* Reset the ETR Bits */ |
mbed_official | 157:90e3acc479a2 | 3661 | tmpsmcr &= SMCR_ETR_MASK; |
mbed_official | 157:90e3acc479a2 | 3662 | |
mbed_official | 157:90e3acc479a2 | 3663 | /* Set the Prescaler, the Filter value and the Polarity */ |
mbed_official | 157:90e3acc479a2 | 3664 | tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); |
mbed_official | 157:90e3acc479a2 | 3665 | |
mbed_official | 157:90e3acc479a2 | 3666 | /* Write to TIMx SMCR */ |
mbed_official | 157:90e3acc479a2 | 3667 | TIMx->SMCR = tmpsmcr; |
mbed_official | 157:90e3acc479a2 | 3668 | } |
mbed_official | 157:90e3acc479a2 | 3669 | /** |
mbed_official | 157:90e3acc479a2 | 3670 | * @} |
mbed_official | 157:90e3acc479a2 | 3671 | */ |
mbed_official | 157:90e3acc479a2 | 3672 | |
mbed_official | 157:90e3acc479a2 | 3673 | /** @defgroup TIM_Group8 Specific interface management functions |
mbed_official | 157:90e3acc479a2 | 3674 | * @brief Specific interface management functions |
mbed_official | 157:90e3acc479a2 | 3675 | * |
mbed_official | 157:90e3acc479a2 | 3676 | @verbatim |
mbed_official | 157:90e3acc479a2 | 3677 | =============================================================================== |
mbed_official | 157:90e3acc479a2 | 3678 | ##### Specific interface management functions ##### |
mbed_official | 157:90e3acc479a2 | 3679 | =============================================================================== |
mbed_official | 157:90e3acc479a2 | 3680 | |
mbed_official | 157:90e3acc479a2 | 3681 | @endverbatim |
mbed_official | 157:90e3acc479a2 | 3682 | * @{ |
mbed_official | 157:90e3acc479a2 | 3683 | */ |
mbed_official | 157:90e3acc479a2 | 3684 | |
mbed_official | 157:90e3acc479a2 | 3685 | /** |
mbed_official | 157:90e3acc479a2 | 3686 | * @brief Configures the TIMx Encoder Interface. |
mbed_official | 157:90e3acc479a2 | 3687 | * @param TIMx: where x can be 1, 2, 3, 4 or 8 to select the TIM |
mbed_official | 157:90e3acc479a2 | 3688 | * peripheral. |
mbed_official | 157:90e3acc479a2 | 3689 | * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. |
mbed_official | 157:90e3acc479a2 | 3690 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3691 | * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. |
mbed_official | 157:90e3acc479a2 | 3692 | * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. |
mbed_official | 157:90e3acc479a2 | 3693 | * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending |
mbed_official | 157:90e3acc479a2 | 3694 | * on the level of the other input. |
mbed_official | 157:90e3acc479a2 | 3695 | * @param TIM_IC1Polarity: specifies the IC1 Polarity |
mbed_official | 157:90e3acc479a2 | 3696 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3697 | * @arg TIM_ICPolarity_Falling: IC Falling edge. |
mbed_official | 157:90e3acc479a2 | 3698 | * @arg TIM_ICPolarity_Rising: IC Rising edge. |
mbed_official | 157:90e3acc479a2 | 3699 | * @param TIM_IC2Polarity: specifies the IC2 Polarity |
mbed_official | 157:90e3acc479a2 | 3700 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3701 | * @arg TIM_ICPolarity_Falling: IC Falling edge. |
mbed_official | 157:90e3acc479a2 | 3702 | * @arg TIM_ICPolarity_Rising: IC Rising edge. |
mbed_official | 157:90e3acc479a2 | 3703 | * @retval None |
mbed_official | 157:90e3acc479a2 | 3704 | */ |
mbed_official | 157:90e3acc479a2 | 3705 | void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, |
mbed_official | 157:90e3acc479a2 | 3706 | uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) |
mbed_official | 157:90e3acc479a2 | 3707 | { |
mbed_official | 157:90e3acc479a2 | 3708 | uint16_t tmpsmcr = 0; |
mbed_official | 157:90e3acc479a2 | 3709 | uint16_t tmpccmr1 = 0; |
mbed_official | 157:90e3acc479a2 | 3710 | uint16_t tmpccer = 0; |
mbed_official | 157:90e3acc479a2 | 3711 | |
mbed_official | 157:90e3acc479a2 | 3712 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 3713 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 3714 | assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); |
mbed_official | 157:90e3acc479a2 | 3715 | assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); |
mbed_official | 157:90e3acc479a2 | 3716 | assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); |
mbed_official | 157:90e3acc479a2 | 3717 | |
mbed_official | 157:90e3acc479a2 | 3718 | /* Get the TIMx SMCR register value */ |
mbed_official | 157:90e3acc479a2 | 3719 | tmpsmcr = TIMx->SMCR; |
mbed_official | 157:90e3acc479a2 | 3720 | |
mbed_official | 157:90e3acc479a2 | 3721 | /* Get the TIMx CCMR1 register value */ |
mbed_official | 157:90e3acc479a2 | 3722 | tmpccmr1 = TIMx->CCMR1; |
mbed_official | 157:90e3acc479a2 | 3723 | |
mbed_official | 157:90e3acc479a2 | 3724 | /* Get the TIMx CCER register value */ |
mbed_official | 157:90e3acc479a2 | 3725 | tmpccer = TIMx->CCER; |
mbed_official | 157:90e3acc479a2 | 3726 | |
mbed_official | 157:90e3acc479a2 | 3727 | /* Set the encoder Mode */ |
mbed_official | 157:90e3acc479a2 | 3728 | tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; |
mbed_official | 157:90e3acc479a2 | 3729 | tmpsmcr |= TIM_EncoderMode; |
mbed_official | 157:90e3acc479a2 | 3730 | |
mbed_official | 157:90e3acc479a2 | 3731 | /* Select the Capture Compare 1 and the Capture Compare 2 as input */ |
mbed_official | 157:90e3acc479a2 | 3732 | tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S); |
mbed_official | 157:90e3acc479a2 | 3733 | tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; |
mbed_official | 157:90e3acc479a2 | 3734 | |
mbed_official | 157:90e3acc479a2 | 3735 | /* Set the TI1 and the TI2 Polarities */ |
mbed_official | 157:90e3acc479a2 | 3736 | tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P); |
mbed_official | 157:90e3acc479a2 | 3737 | tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); |
mbed_official | 157:90e3acc479a2 | 3738 | |
mbed_official | 157:90e3acc479a2 | 3739 | /* Write to TIMx SMCR */ |
mbed_official | 157:90e3acc479a2 | 3740 | TIMx->SMCR = tmpsmcr; |
mbed_official | 157:90e3acc479a2 | 3741 | |
mbed_official | 157:90e3acc479a2 | 3742 | /* Write to TIMx CCMR1 */ |
mbed_official | 157:90e3acc479a2 | 3743 | TIMx->CCMR1 = tmpccmr1; |
mbed_official | 157:90e3acc479a2 | 3744 | |
mbed_official | 157:90e3acc479a2 | 3745 | /* Write to TIMx CCER */ |
mbed_official | 157:90e3acc479a2 | 3746 | TIMx->CCER = tmpccer; |
mbed_official | 157:90e3acc479a2 | 3747 | } |
mbed_official | 157:90e3acc479a2 | 3748 | |
mbed_official | 157:90e3acc479a2 | 3749 | /** |
mbed_official | 157:90e3acc479a2 | 3750 | * @brief Enables or disables the TIMx's Hall sensor interface. |
mbed_official | 157:90e3acc479a2 | 3751 | * @param TIMx: where x can be 1, 2, 3, 4, 8 or 15 to select the TIM |
mbed_official | 157:90e3acc479a2 | 3752 | * peripheral. |
mbed_official | 157:90e3acc479a2 | 3753 | * @param NewState: new state of the TIMx Hall sensor interface. |
mbed_official | 157:90e3acc479a2 | 3754 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 157:90e3acc479a2 | 3755 | * @retval None |
mbed_official | 157:90e3acc479a2 | 3756 | */ |
mbed_official | 157:90e3acc479a2 | 3757 | void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) |
mbed_official | 157:90e3acc479a2 | 3758 | { |
mbed_official | 157:90e3acc479a2 | 3759 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 3760 | assert_param(IS_TIM_LIST2_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 3761 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 157:90e3acc479a2 | 3762 | |
mbed_official | 157:90e3acc479a2 | 3763 | if (NewState != DISABLE) |
mbed_official | 157:90e3acc479a2 | 3764 | { |
mbed_official | 157:90e3acc479a2 | 3765 | /* Set the TI1S Bit */ |
mbed_official | 157:90e3acc479a2 | 3766 | TIMx->CR2 |= TIM_CR2_TI1S; |
mbed_official | 157:90e3acc479a2 | 3767 | } |
mbed_official | 157:90e3acc479a2 | 3768 | else |
mbed_official | 157:90e3acc479a2 | 3769 | { |
mbed_official | 157:90e3acc479a2 | 3770 | /* Reset the TI1S Bit */ |
mbed_official | 157:90e3acc479a2 | 3771 | TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S; |
mbed_official | 157:90e3acc479a2 | 3772 | } |
mbed_official | 157:90e3acc479a2 | 3773 | } |
mbed_official | 157:90e3acc479a2 | 3774 | /** |
mbed_official | 157:90e3acc479a2 | 3775 | * @} |
mbed_official | 157:90e3acc479a2 | 3776 | */ |
mbed_official | 157:90e3acc479a2 | 3777 | |
mbed_official | 157:90e3acc479a2 | 3778 | /** @defgroup TIM_Group9 Specific remapping management function |
mbed_official | 157:90e3acc479a2 | 3779 | * @brief Specific remapping management function |
mbed_official | 157:90e3acc479a2 | 3780 | * |
mbed_official | 157:90e3acc479a2 | 3781 | @verbatim |
mbed_official | 157:90e3acc479a2 | 3782 | =============================================================================== |
mbed_official | 157:90e3acc479a2 | 3783 | ##### Specific remapping management function ##### |
mbed_official | 157:90e3acc479a2 | 3784 | =============================================================================== |
mbed_official | 157:90e3acc479a2 | 3785 | |
mbed_official | 157:90e3acc479a2 | 3786 | @endverbatim |
mbed_official | 157:90e3acc479a2 | 3787 | * @{ |
mbed_official | 157:90e3acc479a2 | 3788 | */ |
mbed_official | 157:90e3acc479a2 | 3789 | |
mbed_official | 157:90e3acc479a2 | 3790 | /** |
mbed_official | 157:90e3acc479a2 | 3791 | * @brief Configures the TIM16 Remapping input Capabilities. |
mbed_official | 157:90e3acc479a2 | 3792 | * @param TIMx: where x can be 1, 8 or 16 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 3793 | * @param TIM_Remap: specifies the TIM input reampping source. |
mbed_official | 157:90e3acc479a2 | 3794 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3795 | * @arg TIM16_GPIO: TIM16 Channel 1 is connected to GPIO. |
mbed_official | 157:90e3acc479a2 | 3796 | * @arg TIM16_RTC_CLK: TIM16 Channel 1 is connected to RTC input clock. |
mbed_official | 157:90e3acc479a2 | 3797 | * @arg TIM16_HSE_DIV32: TIM16 Channel 1 is connected to HSE/32 clock. |
mbed_official | 157:90e3acc479a2 | 3798 | * @arg TIM16_MCO: TIM16 Channel 1 is connected to MCO clock. |
mbed_official | 157:90e3acc479a2 | 3799 | * @arg TIM1_ADC1_AWDG1: TIM1 ETR is connected to ADC1 AWDG1. |
mbed_official | 157:90e3acc479a2 | 3800 | * @arg TIM1_ADC1_AWDG2: TIM1 ETR is connected to ADC1 AWDG2. |
mbed_official | 157:90e3acc479a2 | 3801 | * @arg TIM1_ADC1_AWDG3: TIM1 ETR is connected to ADC1 AWDG3. |
mbed_official | 157:90e3acc479a2 | 3802 | * @arg TIM1_ADC4_AWDG1: TIM1 ETR is connected to ADC4 AWDG1. |
mbed_official | 157:90e3acc479a2 | 3803 | * @arg TIM1_ADC4_AWDG2: TIM1 ETR is connected to ADC4 AWDG2. |
mbed_official | 157:90e3acc479a2 | 3804 | * @arg TIM1_ADC4_AWDG3: TIM1 ETR is connected to ADC4 AWDG3. |
mbed_official | 157:90e3acc479a2 | 3805 | * @arg TIM8_ADC2_AWDG1: TIM8 ETR is connected to ADC2 AWDG1. |
mbed_official | 157:90e3acc479a2 | 3806 | * @arg TIM8_ADC2_AWDG2: TIM8 ETR is connected to ADC2 AWDG2. |
mbed_official | 157:90e3acc479a2 | 3807 | * @arg TIM8_ADC2_AWDG3: TIM8 ETR is connected to ADC2 AWDG3. |
mbed_official | 157:90e3acc479a2 | 3808 | * @arg TIM8_ADC4_AWDG1: TIM8 ETR is connected to ADC4 AWDG1. |
mbed_official | 157:90e3acc479a2 | 3809 | * @arg TIM8_ADC4_AWDG2: TIM8 ETR is connected to ADC4 AWDG2. |
mbed_official | 157:90e3acc479a2 | 3810 | * @arg TIM8_ADC4_AWDG3: TIM8 ETR is connected to ADC4 AWDG3. |
mbed_official | 157:90e3acc479a2 | 3811 | * @retval : None |
mbed_official | 157:90e3acc479a2 | 3812 | */ |
mbed_official | 157:90e3acc479a2 | 3813 | void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap) |
mbed_official | 157:90e3acc479a2 | 3814 | { |
mbed_official | 157:90e3acc479a2 | 3815 | /* Check the parameters */ |
mbed_official | 157:90e3acc479a2 | 3816 | assert_param(IS_TIM_LIST8_PERIPH(TIMx)); |
mbed_official | 157:90e3acc479a2 | 3817 | assert_param(IS_TIM_REMAP(TIM_Remap)); |
mbed_official | 157:90e3acc479a2 | 3818 | |
mbed_official | 157:90e3acc479a2 | 3819 | /* Set the Timer remapping configuration */ |
mbed_official | 157:90e3acc479a2 | 3820 | TIMx->OR = TIM_Remap; |
mbed_official | 157:90e3acc479a2 | 3821 | } |
mbed_official | 157:90e3acc479a2 | 3822 | /** |
mbed_official | 157:90e3acc479a2 | 3823 | * @} |
mbed_official | 157:90e3acc479a2 | 3824 | */ |
mbed_official | 157:90e3acc479a2 | 3825 | |
mbed_official | 157:90e3acc479a2 | 3826 | /** |
mbed_official | 157:90e3acc479a2 | 3827 | * @brief Configure the TI1 as Input. |
mbed_official | 157:90e3acc479a2 | 3828 | * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 |
mbed_official | 157:90e3acc479a2 | 3829 | * to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 3830 | * @param TIM_ICPolarity : The Input Polarity. |
mbed_official | 157:90e3acc479a2 | 3831 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3832 | * @arg TIM_ICPolarity_Rising |
mbed_official | 157:90e3acc479a2 | 3833 | * @arg TIM_ICPolarity_Falling |
mbed_official | 157:90e3acc479a2 | 3834 | * @arg TIM_ICPolarity_BothEdge |
mbed_official | 157:90e3acc479a2 | 3835 | * @param TIM_ICSelection: specifies the input to be used. |
mbed_official | 157:90e3acc479a2 | 3836 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3837 | * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. |
mbed_official | 157:90e3acc479a2 | 3838 | * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. |
mbed_official | 157:90e3acc479a2 | 3839 | * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. |
mbed_official | 157:90e3acc479a2 | 3840 | * @param TIM_ICFilter: Specifies the Input Capture Filter. |
mbed_official | 157:90e3acc479a2 | 3841 | * This parameter must be a value between 0x00 and 0x0F. |
mbed_official | 157:90e3acc479a2 | 3842 | * @retval None |
mbed_official | 157:90e3acc479a2 | 3843 | */ |
mbed_official | 157:90e3acc479a2 | 3844 | static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, |
mbed_official | 157:90e3acc479a2 | 3845 | uint16_t TIM_ICFilter) |
mbed_official | 157:90e3acc479a2 | 3846 | { |
mbed_official | 157:90e3acc479a2 | 3847 | uint32_t tmpccmr1 = 0, tmpccer = 0; |
mbed_official | 157:90e3acc479a2 | 3848 | |
mbed_official | 157:90e3acc479a2 | 3849 | /* Disable the Channel 1: Reset the CC1E Bit */ |
mbed_official | 157:90e3acc479a2 | 3850 | TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; |
mbed_official | 157:90e3acc479a2 | 3851 | tmpccmr1 = TIMx->CCMR1; |
mbed_official | 157:90e3acc479a2 | 3852 | tmpccer = TIMx->CCER; |
mbed_official | 157:90e3acc479a2 | 3853 | |
mbed_official | 157:90e3acc479a2 | 3854 | /* Select the Input and set the filter */ |
mbed_official | 157:90e3acc479a2 | 3855 | tmpccmr1 &= ((uint32_t)~TIM_CCMR1_CC1S) & ((uint32_t)~TIM_CCMR1_IC1F); |
mbed_official | 157:90e3acc479a2 | 3856 | tmpccmr1 |= (uint32_t)(TIM_ICSelection | (uint32_t)((uint32_t)TIM_ICFilter << 4)); |
mbed_official | 157:90e3acc479a2 | 3857 | |
mbed_official | 157:90e3acc479a2 | 3858 | /* Select the Polarity and set the CC1E Bit */ |
mbed_official | 157:90e3acc479a2 | 3859 | tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP); |
mbed_official | 157:90e3acc479a2 | 3860 | tmpccer |= (uint32_t)(TIM_ICPolarity | (uint32_t)TIM_CCER_CC1E); |
mbed_official | 157:90e3acc479a2 | 3861 | |
mbed_official | 157:90e3acc479a2 | 3862 | /* Write to TIMx CCMR1 and CCER registers */ |
mbed_official | 157:90e3acc479a2 | 3863 | TIMx->CCMR1 = tmpccmr1; |
mbed_official | 157:90e3acc479a2 | 3864 | TIMx->CCER = tmpccer; |
mbed_official | 157:90e3acc479a2 | 3865 | } |
mbed_official | 157:90e3acc479a2 | 3866 | |
mbed_official | 157:90e3acc479a2 | 3867 | /** |
mbed_official | 157:90e3acc479a2 | 3868 | * @brief Configure the TI2 as Input. |
mbed_official | 157:90e3acc479a2 | 3869 | * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM |
mbed_official | 157:90e3acc479a2 | 3870 | * peripheral. |
mbed_official | 157:90e3acc479a2 | 3871 | * @param TIM_ICPolarity : The Input Polarity. |
mbed_official | 157:90e3acc479a2 | 3872 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3873 | * @arg TIM_ICPolarity_Rising |
mbed_official | 157:90e3acc479a2 | 3874 | * @arg TIM_ICPolarity_Falling |
mbed_official | 157:90e3acc479a2 | 3875 | * @arg TIM_ICPolarity_BothEdge |
mbed_official | 157:90e3acc479a2 | 3876 | * @param TIM_ICSelection: specifies the input to be used. |
mbed_official | 157:90e3acc479a2 | 3877 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3878 | * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. |
mbed_official | 157:90e3acc479a2 | 3879 | * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. |
mbed_official | 157:90e3acc479a2 | 3880 | * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. |
mbed_official | 157:90e3acc479a2 | 3881 | * @param TIM_ICFilter: Specifies the Input Capture Filter. |
mbed_official | 157:90e3acc479a2 | 3882 | * This parameter must be a value between 0x00 and 0x0F. |
mbed_official | 157:90e3acc479a2 | 3883 | * @retval None |
mbed_official | 157:90e3acc479a2 | 3884 | */ |
mbed_official | 157:90e3acc479a2 | 3885 | static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, |
mbed_official | 157:90e3acc479a2 | 3886 | uint16_t TIM_ICFilter) |
mbed_official | 157:90e3acc479a2 | 3887 | { |
mbed_official | 157:90e3acc479a2 | 3888 | uint32_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; |
mbed_official | 157:90e3acc479a2 | 3889 | |
mbed_official | 157:90e3acc479a2 | 3890 | /* Disable the Channel 2: Reset the CC2E Bit */ |
mbed_official | 157:90e3acc479a2 | 3891 | TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; |
mbed_official | 157:90e3acc479a2 | 3892 | tmpccmr1 = TIMx->CCMR1; |
mbed_official | 157:90e3acc479a2 | 3893 | tmpccer = TIMx->CCER; |
mbed_official | 157:90e3acc479a2 | 3894 | tmp = (uint16_t)(TIM_ICPolarity << 4); |
mbed_official | 157:90e3acc479a2 | 3895 | |
mbed_official | 157:90e3acc479a2 | 3896 | /* Select the Input and set the filter */ |
mbed_official | 157:90e3acc479a2 | 3897 | tmpccmr1 &= ((uint32_t)~TIM_CCMR1_CC2S) & ((uint32_t)~TIM_CCMR1_IC2F); |
mbed_official | 157:90e3acc479a2 | 3898 | tmpccmr1 |= (uint32_t)((uint32_t)TIM_ICFilter << 12); |
mbed_official | 157:90e3acc479a2 | 3899 | tmpccmr1 |= (uint32_t)((uint32_t)TIM_ICSelection << 8); |
mbed_official | 157:90e3acc479a2 | 3900 | |
mbed_official | 157:90e3acc479a2 | 3901 | /* Select the Polarity and set the CC2E Bit */ |
mbed_official | 157:90e3acc479a2 | 3902 | tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP); |
mbed_official | 157:90e3acc479a2 | 3903 | tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); |
mbed_official | 157:90e3acc479a2 | 3904 | |
mbed_official | 157:90e3acc479a2 | 3905 | /* Write to TIMx CCMR1 and CCER registers */ |
mbed_official | 157:90e3acc479a2 | 3906 | TIMx->CCMR1 = tmpccmr1 ; |
mbed_official | 157:90e3acc479a2 | 3907 | TIMx->CCER = tmpccer; |
mbed_official | 157:90e3acc479a2 | 3908 | } |
mbed_official | 157:90e3acc479a2 | 3909 | |
mbed_official | 157:90e3acc479a2 | 3910 | /** |
mbed_official | 157:90e3acc479a2 | 3911 | * @brief Configure the TI3 as Input. |
mbed_official | 157:90e3acc479a2 | 3912 | * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 3913 | * @param TIM_ICPolarity : The Input Polarity. |
mbed_official | 157:90e3acc479a2 | 3914 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3915 | * @arg TIM_ICPolarity_Rising |
mbed_official | 157:90e3acc479a2 | 3916 | * @arg TIM_ICPolarity_Falling |
mbed_official | 157:90e3acc479a2 | 3917 | * @arg TIM_ICPolarity_BothEdge |
mbed_official | 157:90e3acc479a2 | 3918 | * @param TIM_ICSelection: specifies the input to be used. |
mbed_official | 157:90e3acc479a2 | 3919 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3920 | * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. |
mbed_official | 157:90e3acc479a2 | 3921 | * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. |
mbed_official | 157:90e3acc479a2 | 3922 | * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. |
mbed_official | 157:90e3acc479a2 | 3923 | * @param TIM_ICFilter: Specifies the Input Capture Filter. |
mbed_official | 157:90e3acc479a2 | 3924 | * This parameter must be a value between 0x00 and 0x0F. |
mbed_official | 157:90e3acc479a2 | 3925 | * @retval None |
mbed_official | 157:90e3acc479a2 | 3926 | */ |
mbed_official | 157:90e3acc479a2 | 3927 | static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, |
mbed_official | 157:90e3acc479a2 | 3928 | uint16_t TIM_ICFilter) |
mbed_official | 157:90e3acc479a2 | 3929 | { |
mbed_official | 157:90e3acc479a2 | 3930 | uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; |
mbed_official | 157:90e3acc479a2 | 3931 | |
mbed_official | 157:90e3acc479a2 | 3932 | /* Disable the Channel 3: Reset the CC3E Bit */ |
mbed_official | 157:90e3acc479a2 | 3933 | TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; |
mbed_official | 157:90e3acc479a2 | 3934 | tmpccmr2 = TIMx->CCMR2; |
mbed_official | 157:90e3acc479a2 | 3935 | tmpccer = TIMx->CCER; |
mbed_official | 157:90e3acc479a2 | 3936 | tmp = (uint16_t)(TIM_ICPolarity << 8); |
mbed_official | 157:90e3acc479a2 | 3937 | |
mbed_official | 157:90e3acc479a2 | 3938 | /* Select the Input and set the filter */ |
mbed_official | 157:90e3acc479a2 | 3939 | tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F); |
mbed_official | 157:90e3acc479a2 | 3940 | tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); |
mbed_official | 157:90e3acc479a2 | 3941 | |
mbed_official | 157:90e3acc479a2 | 3942 | /* Select the Polarity and set the CC3E Bit */ |
mbed_official | 157:90e3acc479a2 | 3943 | tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP); |
mbed_official | 157:90e3acc479a2 | 3944 | tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); |
mbed_official | 157:90e3acc479a2 | 3945 | |
mbed_official | 157:90e3acc479a2 | 3946 | /* Write to TIMx CCMR2 and CCER registers */ |
mbed_official | 157:90e3acc479a2 | 3947 | TIMx->CCMR2 = tmpccmr2; |
mbed_official | 157:90e3acc479a2 | 3948 | TIMx->CCER = tmpccer; |
mbed_official | 157:90e3acc479a2 | 3949 | } |
mbed_official | 157:90e3acc479a2 | 3950 | |
mbed_official | 157:90e3acc479a2 | 3951 | /** |
mbed_official | 157:90e3acc479a2 | 3952 | * @brief Configure the TI4 as Input. |
mbed_official | 157:90e3acc479a2 | 3953 | * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. |
mbed_official | 157:90e3acc479a2 | 3954 | * @param TIM_ICPolarity : The Input Polarity. |
mbed_official | 157:90e3acc479a2 | 3955 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3956 | * @arg TIM_ICPolarity_Rising |
mbed_official | 157:90e3acc479a2 | 3957 | * @arg TIM_ICPolarity_Falling |
mbed_official | 157:90e3acc479a2 | 3958 | * @arg TIM_ICPolarity_BothEdge |
mbed_official | 157:90e3acc479a2 | 3959 | * @param TIM_ICSelection: specifies the input to be used. |
mbed_official | 157:90e3acc479a2 | 3960 | * This parameter can be one of the following values: |
mbed_official | 157:90e3acc479a2 | 3961 | * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. |
mbed_official | 157:90e3acc479a2 | 3962 | * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. |
mbed_official | 157:90e3acc479a2 | 3963 | * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. |
mbed_official | 157:90e3acc479a2 | 3964 | * @param TIM_ICFilter: Specifies the Input Capture Filter. |
mbed_official | 157:90e3acc479a2 | 3965 | * This parameter must be a value between 0x00 and 0x0F. |
mbed_official | 157:90e3acc479a2 | 3966 | * @retval None |
mbed_official | 157:90e3acc479a2 | 3967 | */ |
mbed_official | 157:90e3acc479a2 | 3968 | static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, |
mbed_official | 157:90e3acc479a2 | 3969 | uint16_t TIM_ICFilter) |
mbed_official | 157:90e3acc479a2 | 3970 | { |
mbed_official | 157:90e3acc479a2 | 3971 | uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; |
mbed_official | 157:90e3acc479a2 | 3972 | |
mbed_official | 157:90e3acc479a2 | 3973 | /* Disable the Channel 4: Reset the CC4E Bit */ |
mbed_official | 157:90e3acc479a2 | 3974 | TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; |
mbed_official | 157:90e3acc479a2 | 3975 | tmpccmr2 = TIMx->CCMR2; |
mbed_official | 157:90e3acc479a2 | 3976 | tmpccer = TIMx->CCER; |
mbed_official | 157:90e3acc479a2 | 3977 | tmp = (uint16_t)(TIM_ICPolarity << 12); |
mbed_official | 157:90e3acc479a2 | 3978 | |
mbed_official | 157:90e3acc479a2 | 3979 | /* Select the Input and set the filter */ |
mbed_official | 157:90e3acc479a2 | 3980 | tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); |
mbed_official | 157:90e3acc479a2 | 3981 | tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); |
mbed_official | 157:90e3acc479a2 | 3982 | tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); |
mbed_official | 157:90e3acc479a2 | 3983 | |
mbed_official | 157:90e3acc479a2 | 3984 | /* Select the Polarity and set the CC4E Bit */ |
mbed_official | 157:90e3acc479a2 | 3985 | tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP); |
mbed_official | 157:90e3acc479a2 | 3986 | tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); |
mbed_official | 157:90e3acc479a2 | 3987 | |
mbed_official | 157:90e3acc479a2 | 3988 | /* Write to TIMx CCMR2 and CCER registers */ |
mbed_official | 157:90e3acc479a2 | 3989 | TIMx->CCMR2 = tmpccmr2; |
mbed_official | 157:90e3acc479a2 | 3990 | TIMx->CCER = tmpccer ; |
mbed_official | 157:90e3acc479a2 | 3991 | } |
mbed_official | 157:90e3acc479a2 | 3992 | |
mbed_official | 157:90e3acc479a2 | 3993 | /** |
mbed_official | 157:90e3acc479a2 | 3994 | * @} |
mbed_official | 157:90e3acc479a2 | 3995 | */ |
mbed_official | 157:90e3acc479a2 | 3996 | |
mbed_official | 157:90e3acc479a2 | 3997 | /** |
mbed_official | 157:90e3acc479a2 | 3998 | * @} |
mbed_official | 157:90e3acc479a2 | 3999 | */ |
mbed_official | 157:90e3acc479a2 | 4000 | |
mbed_official | 157:90e3acc479a2 | 4001 | /** |
mbed_official | 157:90e3acc479a2 | 4002 | * @} |
mbed_official | 157:90e3acc479a2 | 4003 | */ |
mbed_official | 157:90e3acc479a2 | 4004 | |
mbed_official | 157:90e3acc479a2 | 4005 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |