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targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/stm32l1xx_dma.c@80:66393a7b209d, 2014-01-30 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Jan 30 12:15:05 2014 +0000
- Revision:
- 80:66393a7b209d
- Parent:
- 76:aeb1df146756
- Child:
- 106:ced8cbb51063
Synchronized with git revision dba523f83fe09b7fce11fc1299dd1216e9776359
Full URL: https://github.com/mbedmicro/mbed/commit/dba523f83fe09b7fce11fc1299dd1216e9776359/
Update of I2C, SPI, SLEEP for NUCLEO_F103RB and L152RE
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 76:aeb1df146756 | 1 | /** |
mbed_official | 76:aeb1df146756 | 2 | ****************************************************************************** |
mbed_official | 76:aeb1df146756 | 3 | * @file stm32l1xx_dma.c |
mbed_official | 76:aeb1df146756 | 4 | * @author MCD Application Team |
mbed_official | 80:66393a7b209d | 5 | * @version V1.3.0 |
mbed_official | 80:66393a7b209d | 6 | * @date 31-January-2014 |
mbed_official | 76:aeb1df146756 | 7 | * @brief This file provides firmware functions to manage the following |
mbed_official | 76:aeb1df146756 | 8 | * functionalities of the Direct Memory Access controller (DMA): |
mbed_official | 76:aeb1df146756 | 9 | * + Initialization and Configuration |
mbed_official | 76:aeb1df146756 | 10 | * + Data Counter |
mbed_official | 76:aeb1df146756 | 11 | * + Interrupts and flags management |
mbed_official | 76:aeb1df146756 | 12 | * |
mbed_official | 76:aeb1df146756 | 13 | * @verbatim |
mbed_official | 76:aeb1df146756 | 14 | ============================================================================== |
mbed_official | 76:aeb1df146756 | 15 | ##### How to use this driver ##### |
mbed_official | 76:aeb1df146756 | 16 | ============================================================================== |
mbed_official | 76:aeb1df146756 | 17 | [..] |
mbed_official | 76:aeb1df146756 | 18 | (#) Enable The DMA controller clock using |
mbed_official | 76:aeb1df146756 | 19 | RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1 or |
mbed_official | 76:aeb1df146756 | 20 | using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE) function for DMA2. |
mbed_official | 76:aeb1df146756 | 21 | (#) Enable and configure the peripheral to be connected to the DMA channel |
mbed_official | 76:aeb1df146756 | 22 | (except for internal SRAM / FLASH memories: no initialization is |
mbed_official | 76:aeb1df146756 | 23 | necessary). |
mbed_official | 76:aeb1df146756 | 24 | (#) For a given Channel, program the Source and Destination addresses, |
mbed_official | 76:aeb1df146756 | 25 | the transfer Direction, the Buffer Size, the Peripheral and Memory |
mbed_official | 76:aeb1df146756 | 26 | Incrementation mode and Data Size, the Circular or Normal mode, |
mbed_official | 76:aeb1df146756 | 27 | the channel transfer Priority and the Memory-to-Memory transfer |
mbed_official | 76:aeb1df146756 | 28 | mode (if needed) using the DMA_Init() function. |
mbed_official | 76:aeb1df146756 | 29 | (#) Enable the NVIC and the corresponding interrupt(s) using the function |
mbed_official | 76:aeb1df146756 | 30 | DMA_ITConfig() if you need to use DMA interrupts. |
mbed_official | 76:aeb1df146756 | 31 | (#) Enable the DMA channel using the DMA_Cmd() function. |
mbed_official | 76:aeb1df146756 | 32 | (#) Activate the needed channel Request using PPP_DMACmd() function for |
mbed_official | 76:aeb1df146756 | 33 | any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) |
mbed_official | 76:aeb1df146756 | 34 | The function allowing this operation is provided in each PPP peripheral |
mbed_official | 76:aeb1df146756 | 35 | driver (ie. SPI_DMACmd for SPI peripheral). |
mbed_official | 76:aeb1df146756 | 36 | (#) Optionally, you can configure the number of data to be transferred |
mbed_official | 76:aeb1df146756 | 37 | when the channel is disabled (ie. after each Transfer Complete event |
mbed_official | 76:aeb1df146756 | 38 | or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter(). |
mbed_official | 76:aeb1df146756 | 39 | And you can get the number of remaining data to be transferred using |
mbed_official | 76:aeb1df146756 | 40 | the function DMA_GetCurrDataCounter() at run time (when the DMA channel is |
mbed_official | 76:aeb1df146756 | 41 | enabled and running). |
mbed_official | 76:aeb1df146756 | 42 | (#) To control DMA events you can use one of the following two methods: |
mbed_official | 76:aeb1df146756 | 43 | (##) Check on DMA channel flags using the function DMA_GetFlagStatus(). |
mbed_official | 76:aeb1df146756 | 44 | (##) Use DMA interrupts through the function DMA_ITConfig() at initialization |
mbed_official | 76:aeb1df146756 | 45 | phase and DMA_GetITStatus() function into interrupt routines in |
mbed_official | 76:aeb1df146756 | 46 | communication phase. |
mbed_official | 76:aeb1df146756 | 47 | After checking on a flag you should clear it using DMA_ClearFlag() |
mbed_official | 76:aeb1df146756 | 48 | function. And after checking on an interrupt event you should |
mbed_official | 76:aeb1df146756 | 49 | clear it using DMA_ClearITPendingBit() function. |
mbed_official | 76:aeb1df146756 | 50 | @endverbatim |
mbed_official | 76:aeb1df146756 | 51 | |
mbed_official | 76:aeb1df146756 | 52 | ****************************************************************************** |
mbed_official | 76:aeb1df146756 | 53 | * @attention |
mbed_official | 76:aeb1df146756 | 54 | * |
mbed_official | 80:66393a7b209d | 55 | * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> |
mbed_official | 76:aeb1df146756 | 56 | * |
mbed_official | 76:aeb1df146756 | 57 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); |
mbed_official | 76:aeb1df146756 | 58 | * You may not use this file except in compliance with the License. |
mbed_official | 76:aeb1df146756 | 59 | * You may obtain a copy of the License at: |
mbed_official | 76:aeb1df146756 | 60 | * |
mbed_official | 76:aeb1df146756 | 61 | * http://www.st.com/software_license_agreement_liberty_v2 |
mbed_official | 76:aeb1df146756 | 62 | * |
mbed_official | 76:aeb1df146756 | 63 | * Unless required by applicable law or agreed to in writing, software |
mbed_official | 76:aeb1df146756 | 64 | * distributed under the License is distributed on an "AS IS" BASIS, |
mbed_official | 76:aeb1df146756 | 65 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
mbed_official | 76:aeb1df146756 | 66 | * See the License for the specific language governing permissions and |
mbed_official | 76:aeb1df146756 | 67 | * limitations under the License. |
mbed_official | 76:aeb1df146756 | 68 | * |
mbed_official | 76:aeb1df146756 | 69 | ****************************************************************************** |
mbed_official | 76:aeb1df146756 | 70 | */ |
mbed_official | 76:aeb1df146756 | 71 | |
mbed_official | 76:aeb1df146756 | 72 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 76:aeb1df146756 | 73 | #include "stm32l1xx_dma.h" |
mbed_official | 76:aeb1df146756 | 74 | #include "stm32l1xx_rcc.h" |
mbed_official | 76:aeb1df146756 | 75 | |
mbed_official | 76:aeb1df146756 | 76 | /** @addtogroup STM32L1xx_StdPeriph_Driver |
mbed_official | 76:aeb1df146756 | 77 | * @{ |
mbed_official | 76:aeb1df146756 | 78 | */ |
mbed_official | 76:aeb1df146756 | 79 | |
mbed_official | 76:aeb1df146756 | 80 | /** @defgroup DMA |
mbed_official | 76:aeb1df146756 | 81 | * @brief DMA driver modules |
mbed_official | 76:aeb1df146756 | 82 | * @{ |
mbed_official | 76:aeb1df146756 | 83 | */ |
mbed_official | 76:aeb1df146756 | 84 | |
mbed_official | 76:aeb1df146756 | 85 | /* Private typedef -----------------------------------------------------------*/ |
mbed_official | 76:aeb1df146756 | 86 | /* Private define ------------------------------------------------------------*/ |
mbed_official | 76:aeb1df146756 | 87 | |
mbed_official | 76:aeb1df146756 | 88 | /* DMA1 Channelx interrupt pending bit masks */ |
mbed_official | 76:aeb1df146756 | 89 | #define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) |
mbed_official | 76:aeb1df146756 | 90 | #define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) |
mbed_official | 76:aeb1df146756 | 91 | #define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) |
mbed_official | 76:aeb1df146756 | 92 | #define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) |
mbed_official | 76:aeb1df146756 | 93 | #define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) |
mbed_official | 76:aeb1df146756 | 94 | #define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6)) |
mbed_official | 76:aeb1df146756 | 95 | #define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7)) |
mbed_official | 76:aeb1df146756 | 96 | |
mbed_official | 76:aeb1df146756 | 97 | /* DMA2 Channelx interrupt pending bit masks */ |
mbed_official | 76:aeb1df146756 | 98 | #define DMA2_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) |
mbed_official | 76:aeb1df146756 | 99 | #define DMA2_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) |
mbed_official | 76:aeb1df146756 | 100 | #define DMA2_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) |
mbed_official | 76:aeb1df146756 | 101 | #define DMA2_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) |
mbed_official | 76:aeb1df146756 | 102 | #define DMA2_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) |
mbed_official | 76:aeb1df146756 | 103 | |
mbed_official | 76:aeb1df146756 | 104 | /* DMA FLAG mask */ |
mbed_official | 76:aeb1df146756 | 105 | #define FLAG_MASK ((uint32_t)0x10000000) |
mbed_official | 76:aeb1df146756 | 106 | |
mbed_official | 76:aeb1df146756 | 107 | /* DMA registers Masks */ |
mbed_official | 76:aeb1df146756 | 108 | #define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F) |
mbed_official | 76:aeb1df146756 | 109 | |
mbed_official | 76:aeb1df146756 | 110 | /* Private macro -------------------------------------------------------------*/ |
mbed_official | 76:aeb1df146756 | 111 | /* Private variables ---------------------------------------------------------*/ |
mbed_official | 76:aeb1df146756 | 112 | /* Private function prototypes -----------------------------------------------*/ |
mbed_official | 76:aeb1df146756 | 113 | /* Private functions ---------------------------------------------------------*/ |
mbed_official | 76:aeb1df146756 | 114 | |
mbed_official | 76:aeb1df146756 | 115 | |
mbed_official | 76:aeb1df146756 | 116 | /** @defgroup DMA_Private_Functions |
mbed_official | 76:aeb1df146756 | 117 | * @{ |
mbed_official | 76:aeb1df146756 | 118 | */ |
mbed_official | 76:aeb1df146756 | 119 | |
mbed_official | 76:aeb1df146756 | 120 | /** @defgroup DMA_Group1 Initialization and Configuration functions |
mbed_official | 76:aeb1df146756 | 121 | * @brief Initialization and Configuration functions |
mbed_official | 76:aeb1df146756 | 122 | * |
mbed_official | 76:aeb1df146756 | 123 | @verbatim |
mbed_official | 76:aeb1df146756 | 124 | =============================================================================== |
mbed_official | 76:aeb1df146756 | 125 | ##### Initialization and Configuration functions ##### |
mbed_official | 76:aeb1df146756 | 126 | =============================================================================== |
mbed_official | 76:aeb1df146756 | 127 | [..] This subsection provides functions allowing to initialize the DMA channel |
mbed_official | 76:aeb1df146756 | 128 | source and destination addresses, incrementation and data sizes, transfer |
mbed_official | 76:aeb1df146756 | 129 | direction, buffer size, circular/normal mode selection, memory-to-memory |
mbed_official | 76:aeb1df146756 | 130 | mode selection and channel priority value. |
mbed_official | 76:aeb1df146756 | 131 | [..] The DMA_Init() function follows the DMA configuration procedures as described |
mbed_official | 76:aeb1df146756 | 132 | in reference manual (RM0038). |
mbed_official | 76:aeb1df146756 | 133 | @endverbatim |
mbed_official | 76:aeb1df146756 | 134 | * @{ |
mbed_official | 76:aeb1df146756 | 135 | */ |
mbed_official | 76:aeb1df146756 | 136 | |
mbed_official | 76:aeb1df146756 | 137 | /** |
mbed_official | 76:aeb1df146756 | 138 | * @brief Deinitializes the DMAy Channelx registers to their default reset |
mbed_official | 76:aeb1df146756 | 139 | * values. |
mbed_official | 76:aeb1df146756 | 140 | * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be |
mbed_official | 76:aeb1df146756 | 141 | * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. |
mbed_official | 76:aeb1df146756 | 142 | * @retval None |
mbed_official | 76:aeb1df146756 | 143 | */ |
mbed_official | 76:aeb1df146756 | 144 | void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) |
mbed_official | 76:aeb1df146756 | 145 | { |
mbed_official | 76:aeb1df146756 | 146 | /* Check the parameters */ |
mbed_official | 76:aeb1df146756 | 147 | assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
mbed_official | 76:aeb1df146756 | 148 | |
mbed_official | 76:aeb1df146756 | 149 | /* Disable the selected DMAy Channelx */ |
mbed_official | 76:aeb1df146756 | 150 | DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); |
mbed_official | 76:aeb1df146756 | 151 | |
mbed_official | 76:aeb1df146756 | 152 | /* Reset DMAy Channelx control register */ |
mbed_official | 76:aeb1df146756 | 153 | DMAy_Channelx->CCR = 0; |
mbed_official | 76:aeb1df146756 | 154 | |
mbed_official | 76:aeb1df146756 | 155 | /* Reset DMAy Channelx remaining bytes register */ |
mbed_official | 76:aeb1df146756 | 156 | DMAy_Channelx->CNDTR = 0; |
mbed_official | 76:aeb1df146756 | 157 | |
mbed_official | 76:aeb1df146756 | 158 | /* Reset DMAy Channelx peripheral address register */ |
mbed_official | 76:aeb1df146756 | 159 | DMAy_Channelx->CPAR = 0; |
mbed_official | 76:aeb1df146756 | 160 | |
mbed_official | 76:aeb1df146756 | 161 | /* Reset DMAy Channelx memory address register */ |
mbed_official | 76:aeb1df146756 | 162 | DMAy_Channelx->CMAR = 0; |
mbed_official | 76:aeb1df146756 | 163 | |
mbed_official | 76:aeb1df146756 | 164 | if (DMAy_Channelx == DMA1_Channel1) |
mbed_official | 76:aeb1df146756 | 165 | { |
mbed_official | 76:aeb1df146756 | 166 | /* Reset interrupt pending bits for DMA1 Channel1 */ |
mbed_official | 76:aeb1df146756 | 167 | DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK; |
mbed_official | 76:aeb1df146756 | 168 | } |
mbed_official | 76:aeb1df146756 | 169 | else if (DMAy_Channelx == DMA1_Channel2) |
mbed_official | 76:aeb1df146756 | 170 | { |
mbed_official | 76:aeb1df146756 | 171 | /* Reset interrupt pending bits for DMA1 Channel2 */ |
mbed_official | 76:aeb1df146756 | 172 | DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK; |
mbed_official | 76:aeb1df146756 | 173 | } |
mbed_official | 76:aeb1df146756 | 174 | else if (DMAy_Channelx == DMA1_Channel3) |
mbed_official | 76:aeb1df146756 | 175 | { |
mbed_official | 76:aeb1df146756 | 176 | /* Reset interrupt pending bits for DMA1 Channel3 */ |
mbed_official | 76:aeb1df146756 | 177 | DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK; |
mbed_official | 76:aeb1df146756 | 178 | } |
mbed_official | 76:aeb1df146756 | 179 | else if (DMAy_Channelx == DMA1_Channel4) |
mbed_official | 76:aeb1df146756 | 180 | { |
mbed_official | 76:aeb1df146756 | 181 | /* Reset interrupt pending bits for DMA1 Channel4 */ |
mbed_official | 76:aeb1df146756 | 182 | DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK; |
mbed_official | 76:aeb1df146756 | 183 | } |
mbed_official | 76:aeb1df146756 | 184 | else if (DMAy_Channelx == DMA1_Channel5) |
mbed_official | 76:aeb1df146756 | 185 | { |
mbed_official | 76:aeb1df146756 | 186 | /* Reset interrupt pending bits for DMA1 Channel5 */ |
mbed_official | 76:aeb1df146756 | 187 | DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK; |
mbed_official | 76:aeb1df146756 | 188 | } |
mbed_official | 76:aeb1df146756 | 189 | else if (DMAy_Channelx == DMA1_Channel6) |
mbed_official | 76:aeb1df146756 | 190 | { |
mbed_official | 76:aeb1df146756 | 191 | /* Reset interrupt pending bits for DMA1 Channel6 */ |
mbed_official | 76:aeb1df146756 | 192 | DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK; |
mbed_official | 76:aeb1df146756 | 193 | } |
mbed_official | 76:aeb1df146756 | 194 | else if (DMAy_Channelx == DMA1_Channel7) |
mbed_official | 76:aeb1df146756 | 195 | { |
mbed_official | 76:aeb1df146756 | 196 | /* Reset interrupt pending bits for DMA1 Channel7 */ |
mbed_official | 76:aeb1df146756 | 197 | DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK; |
mbed_official | 76:aeb1df146756 | 198 | } |
mbed_official | 76:aeb1df146756 | 199 | else if (DMAy_Channelx == DMA2_Channel1) |
mbed_official | 76:aeb1df146756 | 200 | { |
mbed_official | 76:aeb1df146756 | 201 | /* Reset interrupt pending bits for DMA2 Channel1 */ |
mbed_official | 76:aeb1df146756 | 202 | DMA2->IFCR |= DMA2_CHANNEL1_IT_MASK; |
mbed_official | 76:aeb1df146756 | 203 | } |
mbed_official | 76:aeb1df146756 | 204 | else if (DMAy_Channelx == DMA2_Channel2) |
mbed_official | 76:aeb1df146756 | 205 | { |
mbed_official | 76:aeb1df146756 | 206 | /* Reset interrupt pending bits for DMA2 Channel2 */ |
mbed_official | 76:aeb1df146756 | 207 | DMA2->IFCR |= DMA2_CHANNEL2_IT_MASK; |
mbed_official | 76:aeb1df146756 | 208 | } |
mbed_official | 76:aeb1df146756 | 209 | else if (DMAy_Channelx == DMA2_Channel3) |
mbed_official | 76:aeb1df146756 | 210 | { |
mbed_official | 76:aeb1df146756 | 211 | /* Reset interrupt pending bits for DMA2 Channel3 */ |
mbed_official | 76:aeb1df146756 | 212 | DMA2->IFCR |= DMA2_CHANNEL3_IT_MASK; |
mbed_official | 76:aeb1df146756 | 213 | } |
mbed_official | 76:aeb1df146756 | 214 | else if (DMAy_Channelx == DMA2_Channel4) |
mbed_official | 76:aeb1df146756 | 215 | { |
mbed_official | 76:aeb1df146756 | 216 | /* Reset interrupt pending bits for DMA2 Channel4 */ |
mbed_official | 76:aeb1df146756 | 217 | DMA2->IFCR |= DMA2_CHANNEL4_IT_MASK; |
mbed_official | 76:aeb1df146756 | 218 | } |
mbed_official | 76:aeb1df146756 | 219 | else |
mbed_official | 76:aeb1df146756 | 220 | { |
mbed_official | 76:aeb1df146756 | 221 | if (DMAy_Channelx == DMA2_Channel5) |
mbed_official | 76:aeb1df146756 | 222 | { |
mbed_official | 76:aeb1df146756 | 223 | /* Reset interrupt pending bits for DMA2 Channel5 */ |
mbed_official | 76:aeb1df146756 | 224 | DMA2->IFCR |= DMA2_CHANNEL5_IT_MASK; |
mbed_official | 76:aeb1df146756 | 225 | } |
mbed_official | 76:aeb1df146756 | 226 | } |
mbed_official | 76:aeb1df146756 | 227 | } |
mbed_official | 76:aeb1df146756 | 228 | |
mbed_official | 76:aeb1df146756 | 229 | /** |
mbed_official | 76:aeb1df146756 | 230 | * @brief Initializes the DMAy Channelx according to the specified |
mbed_official | 76:aeb1df146756 | 231 | * parameters in the DMA_InitStruct. |
mbed_official | 76:aeb1df146756 | 232 | * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be |
mbed_official | 76:aeb1df146756 | 233 | * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. |
mbed_official | 76:aeb1df146756 | 234 | * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that |
mbed_official | 76:aeb1df146756 | 235 | * contains the configuration information for the specified DMA Channel. |
mbed_official | 76:aeb1df146756 | 236 | * @retval None |
mbed_official | 76:aeb1df146756 | 237 | */ |
mbed_official | 76:aeb1df146756 | 238 | void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) |
mbed_official | 76:aeb1df146756 | 239 | { |
mbed_official | 76:aeb1df146756 | 240 | uint32_t tmpreg = 0; |
mbed_official | 76:aeb1df146756 | 241 | |
mbed_official | 76:aeb1df146756 | 242 | /* Check the parameters */ |
mbed_official | 76:aeb1df146756 | 243 | assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
mbed_official | 76:aeb1df146756 | 244 | assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); |
mbed_official | 76:aeb1df146756 | 245 | assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); |
mbed_official | 76:aeb1df146756 | 246 | assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); |
mbed_official | 76:aeb1df146756 | 247 | assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); |
mbed_official | 76:aeb1df146756 | 248 | assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); |
mbed_official | 76:aeb1df146756 | 249 | assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); |
mbed_official | 76:aeb1df146756 | 250 | assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); |
mbed_official | 76:aeb1df146756 | 251 | assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); |
mbed_official | 76:aeb1df146756 | 252 | assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); |
mbed_official | 76:aeb1df146756 | 253 | |
mbed_official | 76:aeb1df146756 | 254 | /*--------------------------- DMAy Channelx CCR Configuration -----------------*/ |
mbed_official | 76:aeb1df146756 | 255 | /* Get the DMAy_Channelx CCR value */ |
mbed_official | 76:aeb1df146756 | 256 | tmpreg = DMAy_Channelx->CCR; |
mbed_official | 76:aeb1df146756 | 257 | /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ |
mbed_official | 76:aeb1df146756 | 258 | tmpreg &= CCR_CLEAR_MASK; |
mbed_official | 76:aeb1df146756 | 259 | /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ |
mbed_official | 76:aeb1df146756 | 260 | /* Set DIR bit according to DMA_DIR value */ |
mbed_official | 76:aeb1df146756 | 261 | /* Set CIRC bit according to DMA_Mode value */ |
mbed_official | 76:aeb1df146756 | 262 | /* Set PINC bit according to DMA_PeripheralInc value */ |
mbed_official | 76:aeb1df146756 | 263 | /* Set MINC bit according to DMA_MemoryInc value */ |
mbed_official | 76:aeb1df146756 | 264 | /* Set PSIZE bits according to DMA_PeripheralDataSize value */ |
mbed_official | 76:aeb1df146756 | 265 | /* Set MSIZE bits according to DMA_MemoryDataSize value */ |
mbed_official | 76:aeb1df146756 | 266 | /* Set PL bits according to DMA_Priority value */ |
mbed_official | 76:aeb1df146756 | 267 | /* Set the MEM2MEM bit according to DMA_M2M value */ |
mbed_official | 76:aeb1df146756 | 268 | tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | |
mbed_official | 76:aeb1df146756 | 269 | DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | |
mbed_official | 76:aeb1df146756 | 270 | DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | |
mbed_official | 76:aeb1df146756 | 271 | DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; |
mbed_official | 76:aeb1df146756 | 272 | |
mbed_official | 76:aeb1df146756 | 273 | /* Write to DMAy Channelx CCR */ |
mbed_official | 76:aeb1df146756 | 274 | DMAy_Channelx->CCR = tmpreg; |
mbed_official | 76:aeb1df146756 | 275 | |
mbed_official | 76:aeb1df146756 | 276 | /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ |
mbed_official | 76:aeb1df146756 | 277 | /* Write to DMAy Channelx CNDTR */ |
mbed_official | 76:aeb1df146756 | 278 | DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; |
mbed_official | 76:aeb1df146756 | 279 | |
mbed_official | 76:aeb1df146756 | 280 | /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/ |
mbed_official | 76:aeb1df146756 | 281 | /* Write to DMAy Channelx CPAR */ |
mbed_official | 76:aeb1df146756 | 282 | DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; |
mbed_official | 76:aeb1df146756 | 283 | |
mbed_official | 76:aeb1df146756 | 284 | /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/ |
mbed_official | 76:aeb1df146756 | 285 | /* Write to DMAy Channelx CMAR */ |
mbed_official | 76:aeb1df146756 | 286 | DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; |
mbed_official | 76:aeb1df146756 | 287 | } |
mbed_official | 76:aeb1df146756 | 288 | |
mbed_official | 76:aeb1df146756 | 289 | /** |
mbed_official | 76:aeb1df146756 | 290 | * @brief Fills each DMA_InitStruct member with its default value. |
mbed_official | 76:aeb1df146756 | 291 | * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will |
mbed_official | 76:aeb1df146756 | 292 | * be initialized. |
mbed_official | 76:aeb1df146756 | 293 | * @retval None |
mbed_official | 76:aeb1df146756 | 294 | */ |
mbed_official | 76:aeb1df146756 | 295 | void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) |
mbed_official | 76:aeb1df146756 | 296 | { |
mbed_official | 76:aeb1df146756 | 297 | /*-------------- Reset DMA init structure parameters values ------------------*/ |
mbed_official | 76:aeb1df146756 | 298 | /* Initialize the DMA_PeripheralBaseAddr member */ |
mbed_official | 76:aeb1df146756 | 299 | DMA_InitStruct->DMA_PeripheralBaseAddr = 0; |
mbed_official | 76:aeb1df146756 | 300 | /* Initialize the DMA_MemoryBaseAddr member */ |
mbed_official | 76:aeb1df146756 | 301 | DMA_InitStruct->DMA_MemoryBaseAddr = 0; |
mbed_official | 76:aeb1df146756 | 302 | /* Initialize the DMA_DIR member */ |
mbed_official | 76:aeb1df146756 | 303 | DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; |
mbed_official | 76:aeb1df146756 | 304 | /* Initialize the DMA_BufferSize member */ |
mbed_official | 76:aeb1df146756 | 305 | DMA_InitStruct->DMA_BufferSize = 0; |
mbed_official | 76:aeb1df146756 | 306 | /* Initialize the DMA_PeripheralInc member */ |
mbed_official | 76:aeb1df146756 | 307 | DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; |
mbed_official | 76:aeb1df146756 | 308 | /* Initialize the DMA_MemoryInc member */ |
mbed_official | 76:aeb1df146756 | 309 | DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; |
mbed_official | 76:aeb1df146756 | 310 | /* Initialize the DMA_PeripheralDataSize member */ |
mbed_official | 76:aeb1df146756 | 311 | DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; |
mbed_official | 76:aeb1df146756 | 312 | /* Initialize the DMA_MemoryDataSize member */ |
mbed_official | 76:aeb1df146756 | 313 | DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; |
mbed_official | 76:aeb1df146756 | 314 | /* Initialize the DMA_Mode member */ |
mbed_official | 76:aeb1df146756 | 315 | DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; |
mbed_official | 76:aeb1df146756 | 316 | /* Initialize the DMA_Priority member */ |
mbed_official | 76:aeb1df146756 | 317 | DMA_InitStruct->DMA_Priority = DMA_Priority_Low; |
mbed_official | 76:aeb1df146756 | 318 | /* Initialize the DMA_M2M member */ |
mbed_official | 76:aeb1df146756 | 319 | DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; |
mbed_official | 76:aeb1df146756 | 320 | } |
mbed_official | 76:aeb1df146756 | 321 | |
mbed_official | 76:aeb1df146756 | 322 | /** |
mbed_official | 76:aeb1df146756 | 323 | * @brief Enables or disables the specified DMAy Channelx. |
mbed_official | 76:aeb1df146756 | 324 | * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be |
mbed_official | 76:aeb1df146756 | 325 | * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. |
mbed_official | 76:aeb1df146756 | 326 | * @param NewState: new state of the DMAy Channelx. |
mbed_official | 76:aeb1df146756 | 327 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 76:aeb1df146756 | 328 | * @retval None |
mbed_official | 76:aeb1df146756 | 329 | */ |
mbed_official | 76:aeb1df146756 | 330 | void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) |
mbed_official | 76:aeb1df146756 | 331 | { |
mbed_official | 76:aeb1df146756 | 332 | /* Check the parameters */ |
mbed_official | 76:aeb1df146756 | 333 | assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
mbed_official | 76:aeb1df146756 | 334 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 76:aeb1df146756 | 335 | |
mbed_official | 76:aeb1df146756 | 336 | if (NewState != DISABLE) |
mbed_official | 76:aeb1df146756 | 337 | { |
mbed_official | 76:aeb1df146756 | 338 | /* Enable the selected DMAy Channelx */ |
mbed_official | 76:aeb1df146756 | 339 | DMAy_Channelx->CCR |= DMA_CCR1_EN; |
mbed_official | 76:aeb1df146756 | 340 | } |
mbed_official | 76:aeb1df146756 | 341 | else |
mbed_official | 76:aeb1df146756 | 342 | { |
mbed_official | 76:aeb1df146756 | 343 | /* Disable the selected DMAy Channelx */ |
mbed_official | 76:aeb1df146756 | 344 | DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN); |
mbed_official | 76:aeb1df146756 | 345 | } |
mbed_official | 76:aeb1df146756 | 346 | } |
mbed_official | 76:aeb1df146756 | 347 | |
mbed_official | 76:aeb1df146756 | 348 | /** |
mbed_official | 76:aeb1df146756 | 349 | * @} |
mbed_official | 76:aeb1df146756 | 350 | */ |
mbed_official | 76:aeb1df146756 | 351 | |
mbed_official | 76:aeb1df146756 | 352 | /** @defgroup DMA_Group2 Data Counter functions |
mbed_official | 76:aeb1df146756 | 353 | * @brief Data Counter functions |
mbed_official | 76:aeb1df146756 | 354 | * |
mbed_official | 76:aeb1df146756 | 355 | @verbatim |
mbed_official | 76:aeb1df146756 | 356 | =============================================================================== |
mbed_official | 76:aeb1df146756 | 357 | ##### Data Counter functions ##### |
mbed_official | 76:aeb1df146756 | 358 | =============================================================================== |
mbed_official | 76:aeb1df146756 | 359 | [..] This subsection provides function allowing to configure and read the buffer |
mbed_official | 76:aeb1df146756 | 360 | size (number of data to be transferred).The DMA data counter can be written |
mbed_official | 76:aeb1df146756 | 361 | only when the DMA channel is disabled (ie. after transfer complete event). |
mbed_official | 76:aeb1df146756 | 362 | [..] The following function can be used to write the Channel data counter value: |
mbed_official | 76:aeb1df146756 | 363 | (+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t |
mbed_official | 76:aeb1df146756 | 364 | DataNumber). |
mbed_official | 76:aeb1df146756 | 365 | -@- It is advised to use this function rather than DMA_Init() in situations |
mbed_official | 76:aeb1df146756 | 366 | where only the Data buffer needs to be reloaded. |
mbed_official | 76:aeb1df146756 | 367 | [..] The DMA data counter can be read to indicate the number of remaining transfers |
mbed_official | 76:aeb1df146756 | 368 | for the relative DMA channel. This counter is decremented at the end of each |
mbed_official | 76:aeb1df146756 | 369 | data transfer and when the transfer is complete: |
mbed_official | 76:aeb1df146756 | 370 | (+) If Normal mode is selected: the counter is set to 0. |
mbed_official | 76:aeb1df146756 | 371 | (+) If Circular mode is selected: the counter is reloaded with the initial |
mbed_official | 76:aeb1df146756 | 372 | value(configured before enabling the DMA channel). |
mbed_official | 76:aeb1df146756 | 373 | [..] The following function can be used to read the Channel data counter value: |
mbed_official | 76:aeb1df146756 | 374 | (+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx). |
mbed_official | 76:aeb1df146756 | 375 | |
mbed_official | 76:aeb1df146756 | 376 | @endverbatim |
mbed_official | 76:aeb1df146756 | 377 | * @{ |
mbed_official | 76:aeb1df146756 | 378 | */ |
mbed_official | 76:aeb1df146756 | 379 | |
mbed_official | 76:aeb1df146756 | 380 | /** |
mbed_official | 76:aeb1df146756 | 381 | * @brief Sets the number of data units in the current DMAy Channelx transfer. |
mbed_official | 76:aeb1df146756 | 382 | * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be |
mbed_official | 76:aeb1df146756 | 383 | * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. |
mbed_official | 76:aeb1df146756 | 384 | * @param DataNumber: The number of data units in the current DMAy Channelx |
mbed_official | 76:aeb1df146756 | 385 | * transfer. |
mbed_official | 76:aeb1df146756 | 386 | * @note This function can only be used when the DMAy_Channelx is disabled. |
mbed_official | 76:aeb1df146756 | 387 | * @retval None. |
mbed_official | 76:aeb1df146756 | 388 | */ |
mbed_official | 76:aeb1df146756 | 389 | void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber) |
mbed_official | 76:aeb1df146756 | 390 | { |
mbed_official | 76:aeb1df146756 | 391 | /* Check the parameters */ |
mbed_official | 76:aeb1df146756 | 392 | assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
mbed_official | 76:aeb1df146756 | 393 | |
mbed_official | 76:aeb1df146756 | 394 | /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/ |
mbed_official | 76:aeb1df146756 | 395 | /* Write to DMAy Channelx CNDTR */ |
mbed_official | 76:aeb1df146756 | 396 | DMAy_Channelx->CNDTR = DataNumber; |
mbed_official | 76:aeb1df146756 | 397 | } |
mbed_official | 76:aeb1df146756 | 398 | |
mbed_official | 76:aeb1df146756 | 399 | /** |
mbed_official | 76:aeb1df146756 | 400 | * @brief Returns the number of remaining data units in the current |
mbed_official | 76:aeb1df146756 | 401 | * DMAy Channelx transfer. |
mbed_official | 76:aeb1df146756 | 402 | * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be |
mbed_official | 76:aeb1df146756 | 403 | * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. |
mbed_official | 76:aeb1df146756 | 404 | * @retval The number of remaining data units in the current DMAy Channelx |
mbed_official | 76:aeb1df146756 | 405 | * transfer. |
mbed_official | 76:aeb1df146756 | 406 | */ |
mbed_official | 76:aeb1df146756 | 407 | uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) |
mbed_official | 76:aeb1df146756 | 408 | { |
mbed_official | 76:aeb1df146756 | 409 | /* Check the parameters */ |
mbed_official | 76:aeb1df146756 | 410 | assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
mbed_official | 76:aeb1df146756 | 411 | /* Return the number of remaining data units for DMAy Channelx */ |
mbed_official | 76:aeb1df146756 | 412 | return ((uint16_t)(DMAy_Channelx->CNDTR)); |
mbed_official | 76:aeb1df146756 | 413 | } |
mbed_official | 76:aeb1df146756 | 414 | |
mbed_official | 76:aeb1df146756 | 415 | /** |
mbed_official | 76:aeb1df146756 | 416 | * @} |
mbed_official | 76:aeb1df146756 | 417 | */ |
mbed_official | 76:aeb1df146756 | 418 | |
mbed_official | 76:aeb1df146756 | 419 | /** @defgroup DMA_Group3 Interrupts and flags management functions |
mbed_official | 76:aeb1df146756 | 420 | * @brief Interrupts and flags management functions |
mbed_official | 76:aeb1df146756 | 421 | * |
mbed_official | 76:aeb1df146756 | 422 | @verbatim |
mbed_official | 76:aeb1df146756 | 423 | =============================================================================== |
mbed_official | 76:aeb1df146756 | 424 | ##### Interrupts and flags management functions ##### |
mbed_official | 76:aeb1df146756 | 425 | =============================================================================== |
mbed_official | 76:aeb1df146756 | 426 | [..] This subsection provides functions allowing to configure the DMA Interrupts |
mbed_official | 76:aeb1df146756 | 427 | sources and check or clear the flags or pending bits status. |
mbed_official | 76:aeb1df146756 | 428 | The user should identify which mode will be used in his application to manage |
mbed_official | 76:aeb1df146756 | 429 | the DMA controller events: Polling mode or Interrupt mode. |
mbed_official | 76:aeb1df146756 | 430 | *** Polling Mode *** |
mbed_official | 76:aeb1df146756 | 431 | ==================== |
mbed_official | 76:aeb1df146756 | 432 | [..] Each DMA channel can be managed through 4 event Flags:(y : DMA Controller |
mbed_official | 76:aeb1df146756 | 433 | number x : DMA channel number ). |
mbed_official | 76:aeb1df146756 | 434 | (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred. |
mbed_official | 76:aeb1df146756 | 435 | (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred. |
mbed_official | 76:aeb1df146756 | 436 | (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred. |
mbed_official | 76:aeb1df146756 | 437 | (#) DMAy_FLAG_GLx : to indicate that at least one of the events described |
mbed_official | 76:aeb1df146756 | 438 | above occurred. |
mbed_official | 76:aeb1df146756 | 439 | -@- Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the |
mbed_official | 76:aeb1df146756 | 440 | same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). |
mbed_official | 76:aeb1df146756 | 441 | [..]In this Mode it is advised to use the following functions: |
mbed_official | 76:aeb1df146756 | 442 | (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG); |
mbed_official | 76:aeb1df146756 | 443 | (+) void DMA_ClearFlag(uint32_t DMA_FLAG); |
mbed_official | 76:aeb1df146756 | 444 | |
mbed_official | 76:aeb1df146756 | 445 | *** Interrupt Mode *** |
mbed_official | 76:aeb1df146756 | 446 | ====================== |
mbed_official | 76:aeb1df146756 | 447 | [..] Each DMA channel can be managed through 4 Interrupts: |
mbed_official | 76:aeb1df146756 | 448 | (+) Interrupt Source |
mbed_official | 76:aeb1df146756 | 449 | (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete |
mbed_official | 76:aeb1df146756 | 450 | event. |
mbed_official | 76:aeb1df146756 | 451 | (##) DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete |
mbed_official | 76:aeb1df146756 | 452 | event. |
mbed_official | 76:aeb1df146756 | 453 | (##) DMA_IT_TE : specifies the interrupt source for the transfer errors event. |
mbed_official | 76:aeb1df146756 | 454 | (##) DMA_IT_GL : to indicate that at least one of the interrupts described |
mbed_official | 76:aeb1df146756 | 455 | above occurred. |
mbed_official | 76:aeb1df146756 | 456 | -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of |
mbed_official | 76:aeb1df146756 | 457 | the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE). |
mbed_official | 76:aeb1df146756 | 458 | [..]In this Mode it is advised to use the following functions: |
mbed_official | 76:aeb1df146756 | 459 | (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, |
mbed_official | 76:aeb1df146756 | 460 | FunctionalState NewState); |
mbed_official | 76:aeb1df146756 | 461 | (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT); |
mbed_official | 76:aeb1df146756 | 462 | (+) void DMA_ClearITPendingBit(uint32_t DMA_IT); |
mbed_official | 76:aeb1df146756 | 463 | |
mbed_official | 76:aeb1df146756 | 464 | @endverbatim |
mbed_official | 76:aeb1df146756 | 465 | * @{ |
mbed_official | 76:aeb1df146756 | 466 | */ |
mbed_official | 76:aeb1df146756 | 467 | |
mbed_official | 76:aeb1df146756 | 468 | /** |
mbed_official | 76:aeb1df146756 | 469 | * @brief Enables or disables the specified DMAy Channelx interrupts. |
mbed_official | 76:aeb1df146756 | 470 | * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be |
mbed_official | 76:aeb1df146756 | 471 | * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. |
mbed_official | 76:aeb1df146756 | 472 | * @param DMA_IT: specifies the DMA interrupts sources to be enabled |
mbed_official | 76:aeb1df146756 | 473 | * or disabled. |
mbed_official | 76:aeb1df146756 | 474 | * This parameter can be any combination of the following values: |
mbed_official | 76:aeb1df146756 | 475 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
mbed_official | 76:aeb1df146756 | 476 | * @arg DMA_IT_HT: Half transfer interrupt mask |
mbed_official | 76:aeb1df146756 | 477 | * @arg DMA_IT_TE: Transfer error interrupt mask |
mbed_official | 76:aeb1df146756 | 478 | * @param NewState: new state of the specified DMA interrupts. |
mbed_official | 76:aeb1df146756 | 479 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 76:aeb1df146756 | 480 | * @retval None |
mbed_official | 76:aeb1df146756 | 481 | */ |
mbed_official | 76:aeb1df146756 | 482 | void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) |
mbed_official | 76:aeb1df146756 | 483 | { |
mbed_official | 76:aeb1df146756 | 484 | /* Check the parameters */ |
mbed_official | 76:aeb1df146756 | 485 | assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
mbed_official | 76:aeb1df146756 | 486 | assert_param(IS_DMA_CONFIG_IT(DMA_IT)); |
mbed_official | 76:aeb1df146756 | 487 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 76:aeb1df146756 | 488 | |
mbed_official | 76:aeb1df146756 | 489 | if (NewState != DISABLE) |
mbed_official | 76:aeb1df146756 | 490 | { |
mbed_official | 76:aeb1df146756 | 491 | /* Enable the selected DMA interrupts */ |
mbed_official | 76:aeb1df146756 | 492 | DMAy_Channelx->CCR |= DMA_IT; |
mbed_official | 76:aeb1df146756 | 493 | } |
mbed_official | 76:aeb1df146756 | 494 | else |
mbed_official | 76:aeb1df146756 | 495 | { |
mbed_official | 76:aeb1df146756 | 496 | /* Disable the selected DMA interrupts */ |
mbed_official | 76:aeb1df146756 | 497 | DMAy_Channelx->CCR &= ~DMA_IT; |
mbed_official | 76:aeb1df146756 | 498 | } |
mbed_official | 76:aeb1df146756 | 499 | } |
mbed_official | 76:aeb1df146756 | 500 | |
mbed_official | 76:aeb1df146756 | 501 | /** |
mbed_official | 76:aeb1df146756 | 502 | * @brief Checks whether the specified DMAy Channelx flag is set or not. |
mbed_official | 76:aeb1df146756 | 503 | * @param DMAy_FLAG: specifies the flag to check. |
mbed_official | 76:aeb1df146756 | 504 | * This parameter can be one of the following values: |
mbed_official | 76:aeb1df146756 | 505 | * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. |
mbed_official | 76:aeb1df146756 | 506 | * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. |
mbed_official | 76:aeb1df146756 | 507 | * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. |
mbed_official | 76:aeb1df146756 | 508 | * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. |
mbed_official | 76:aeb1df146756 | 509 | * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. |
mbed_official | 76:aeb1df146756 | 510 | * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. |
mbed_official | 76:aeb1df146756 | 511 | * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. |
mbed_official | 76:aeb1df146756 | 512 | * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. |
mbed_official | 76:aeb1df146756 | 513 | * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. |
mbed_official | 76:aeb1df146756 | 514 | * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. |
mbed_official | 76:aeb1df146756 | 515 | * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. |
mbed_official | 76:aeb1df146756 | 516 | * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. |
mbed_official | 76:aeb1df146756 | 517 | * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. |
mbed_official | 76:aeb1df146756 | 518 | * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. |
mbed_official | 76:aeb1df146756 | 519 | * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. |
mbed_official | 76:aeb1df146756 | 520 | * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. |
mbed_official | 76:aeb1df146756 | 521 | * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. |
mbed_official | 76:aeb1df146756 | 522 | * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. |
mbed_official | 76:aeb1df146756 | 523 | * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. |
mbed_official | 76:aeb1df146756 | 524 | * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. |
mbed_official | 76:aeb1df146756 | 525 | * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. |
mbed_official | 76:aeb1df146756 | 526 | * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. |
mbed_official | 76:aeb1df146756 | 527 | * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. |
mbed_official | 76:aeb1df146756 | 528 | * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. |
mbed_official | 76:aeb1df146756 | 529 | * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. |
mbed_official | 76:aeb1df146756 | 530 | * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. |
mbed_official | 76:aeb1df146756 | 531 | * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. |
mbed_official | 76:aeb1df146756 | 532 | * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. |
mbed_official | 76:aeb1df146756 | 533 | * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. |
mbed_official | 76:aeb1df146756 | 534 | * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. |
mbed_official | 76:aeb1df146756 | 535 | * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. |
mbed_official | 76:aeb1df146756 | 536 | * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. |
mbed_official | 76:aeb1df146756 | 537 | * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. |
mbed_official | 76:aeb1df146756 | 538 | * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. |
mbed_official | 76:aeb1df146756 | 539 | * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. |
mbed_official | 76:aeb1df146756 | 540 | * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. |
mbed_official | 76:aeb1df146756 | 541 | * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. |
mbed_official | 76:aeb1df146756 | 542 | * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. |
mbed_official | 76:aeb1df146756 | 543 | * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. |
mbed_official | 76:aeb1df146756 | 544 | * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. |
mbed_official | 76:aeb1df146756 | 545 | * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. |
mbed_official | 76:aeb1df146756 | 546 | * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. |
mbed_official | 76:aeb1df146756 | 547 | * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. |
mbed_official | 76:aeb1df146756 | 548 | * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. |
mbed_official | 76:aeb1df146756 | 549 | * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. |
mbed_official | 76:aeb1df146756 | 550 | * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. |
mbed_official | 76:aeb1df146756 | 551 | * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. |
mbed_official | 76:aeb1df146756 | 552 | * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. |
mbed_official | 76:aeb1df146756 | 553 | * |
mbed_official | 76:aeb1df146756 | 554 | * @note |
mbed_official | 76:aeb1df146756 | 555 | * The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags |
mbed_official | 76:aeb1df146756 | 556 | * relative to the same channel is set (Transfer Complete, Half-transfer |
mbed_official | 76:aeb1df146756 | 557 | * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or |
mbed_official | 76:aeb1df146756 | 558 | * DMAy_FLAG_TEx). |
mbed_official | 76:aeb1df146756 | 559 | * |
mbed_official | 76:aeb1df146756 | 560 | * @retval The new state of DMAy_FLAG (SET or RESET). |
mbed_official | 76:aeb1df146756 | 561 | */ |
mbed_official | 76:aeb1df146756 | 562 | FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) |
mbed_official | 76:aeb1df146756 | 563 | { |
mbed_official | 76:aeb1df146756 | 564 | FlagStatus bitstatus = RESET; |
mbed_official | 76:aeb1df146756 | 565 | uint32_t tmpreg = 0; |
mbed_official | 76:aeb1df146756 | 566 | |
mbed_official | 76:aeb1df146756 | 567 | /* Check the parameters */ |
mbed_official | 76:aeb1df146756 | 568 | assert_param(IS_DMA_GET_FLAG(DMAy_FLAG)); |
mbed_official | 76:aeb1df146756 | 569 | |
mbed_official | 76:aeb1df146756 | 570 | /* Calculate the used DMAy */ |
mbed_official | 76:aeb1df146756 | 571 | if ((DMAy_FLAG & FLAG_MASK) == (uint32_t)RESET) |
mbed_official | 76:aeb1df146756 | 572 | { |
mbed_official | 76:aeb1df146756 | 573 | /* Get DMA1 ISR register value */ |
mbed_official | 76:aeb1df146756 | 574 | tmpreg = DMA1->ISR; |
mbed_official | 76:aeb1df146756 | 575 | } |
mbed_official | 76:aeb1df146756 | 576 | else |
mbed_official | 76:aeb1df146756 | 577 | { |
mbed_official | 76:aeb1df146756 | 578 | /* Get DMA2 ISR register value */ |
mbed_official | 76:aeb1df146756 | 579 | tmpreg = DMA2->ISR; |
mbed_official | 76:aeb1df146756 | 580 | } |
mbed_official | 76:aeb1df146756 | 581 | |
mbed_official | 76:aeb1df146756 | 582 | /* Check the status of the specified DMAy flag */ |
mbed_official | 76:aeb1df146756 | 583 | if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET) |
mbed_official | 76:aeb1df146756 | 584 | { |
mbed_official | 76:aeb1df146756 | 585 | /* DMAy_FLAG is set */ |
mbed_official | 76:aeb1df146756 | 586 | bitstatus = SET; |
mbed_official | 76:aeb1df146756 | 587 | } |
mbed_official | 76:aeb1df146756 | 588 | else |
mbed_official | 76:aeb1df146756 | 589 | { |
mbed_official | 76:aeb1df146756 | 590 | /* DMAy_FLAG is reset */ |
mbed_official | 76:aeb1df146756 | 591 | bitstatus = RESET; |
mbed_official | 76:aeb1df146756 | 592 | } |
mbed_official | 76:aeb1df146756 | 593 | |
mbed_official | 76:aeb1df146756 | 594 | /* Return the DMAy_FLAG status */ |
mbed_official | 76:aeb1df146756 | 595 | return bitstatus; |
mbed_official | 76:aeb1df146756 | 596 | } |
mbed_official | 76:aeb1df146756 | 597 | |
mbed_official | 76:aeb1df146756 | 598 | /** |
mbed_official | 76:aeb1df146756 | 599 | * @brief Clears the DMAy Channelx's pending flags. |
mbed_official | 76:aeb1df146756 | 600 | * @param DMAy_FLAG: specifies the flag to clear. |
mbed_official | 76:aeb1df146756 | 601 | * This parameter can be any combination (for the same DMA) of the following values: |
mbed_official | 76:aeb1df146756 | 602 | * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. |
mbed_official | 76:aeb1df146756 | 603 | * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. |
mbed_official | 76:aeb1df146756 | 604 | * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. |
mbed_official | 76:aeb1df146756 | 605 | * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. |
mbed_official | 76:aeb1df146756 | 606 | * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. |
mbed_official | 76:aeb1df146756 | 607 | * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. |
mbed_official | 76:aeb1df146756 | 608 | * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. |
mbed_official | 76:aeb1df146756 | 609 | * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. |
mbed_official | 76:aeb1df146756 | 610 | * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. |
mbed_official | 76:aeb1df146756 | 611 | * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. |
mbed_official | 76:aeb1df146756 | 612 | * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. |
mbed_official | 76:aeb1df146756 | 613 | * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. |
mbed_official | 76:aeb1df146756 | 614 | * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. |
mbed_official | 76:aeb1df146756 | 615 | * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. |
mbed_official | 76:aeb1df146756 | 616 | * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. |
mbed_official | 76:aeb1df146756 | 617 | * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. |
mbed_official | 76:aeb1df146756 | 618 | * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. |
mbed_official | 76:aeb1df146756 | 619 | * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. |
mbed_official | 76:aeb1df146756 | 620 | * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. |
mbed_official | 76:aeb1df146756 | 621 | * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. |
mbed_official | 76:aeb1df146756 | 622 | * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag. |
mbed_official | 76:aeb1df146756 | 623 | * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag. |
mbed_official | 76:aeb1df146756 | 624 | * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag. |
mbed_official | 76:aeb1df146756 | 625 | * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag. |
mbed_official | 76:aeb1df146756 | 626 | * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag. |
mbed_official | 76:aeb1df146756 | 627 | * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag. |
mbed_official | 76:aeb1df146756 | 628 | * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag. |
mbed_official | 76:aeb1df146756 | 629 | * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag. |
mbed_official | 76:aeb1df146756 | 630 | * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag. |
mbed_official | 76:aeb1df146756 | 631 | * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag. |
mbed_official | 76:aeb1df146756 | 632 | * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag. |
mbed_official | 76:aeb1df146756 | 633 | * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag. |
mbed_official | 76:aeb1df146756 | 634 | * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag. |
mbed_official | 76:aeb1df146756 | 635 | * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag. |
mbed_official | 76:aeb1df146756 | 636 | * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag. |
mbed_official | 76:aeb1df146756 | 637 | * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag. |
mbed_official | 76:aeb1df146756 | 638 | * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag. |
mbed_official | 76:aeb1df146756 | 639 | * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag. |
mbed_official | 76:aeb1df146756 | 640 | * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag. |
mbed_official | 76:aeb1df146756 | 641 | * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag. |
mbed_official | 76:aeb1df146756 | 642 | * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag. |
mbed_official | 76:aeb1df146756 | 643 | * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag. |
mbed_official | 76:aeb1df146756 | 644 | * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag. |
mbed_official | 76:aeb1df146756 | 645 | * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag. |
mbed_official | 76:aeb1df146756 | 646 | * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag. |
mbed_official | 76:aeb1df146756 | 647 | * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag. |
mbed_official | 76:aeb1df146756 | 648 | * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag. |
mbed_official | 76:aeb1df146756 | 649 | * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag. |
mbed_official | 76:aeb1df146756 | 650 | * |
mbed_official | 76:aeb1df146756 | 651 | * @note |
mbed_official | 76:aeb1df146756 | 652 | * Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags |
mbed_official | 76:aeb1df146756 | 653 | * relative to the same channel (Transfer Complete, Half-transfer Complete and |
mbed_official | 76:aeb1df146756 | 654 | * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). |
mbed_official | 76:aeb1df146756 | 655 | * |
mbed_official | 76:aeb1df146756 | 656 | * @retval None |
mbed_official | 76:aeb1df146756 | 657 | */ |
mbed_official | 76:aeb1df146756 | 658 | void DMA_ClearFlag(uint32_t DMAy_FLAG) |
mbed_official | 76:aeb1df146756 | 659 | { |
mbed_official | 76:aeb1df146756 | 660 | /* Check the parameters */ |
mbed_official | 76:aeb1df146756 | 661 | assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG)); |
mbed_official | 76:aeb1df146756 | 662 | |
mbed_official | 76:aeb1df146756 | 663 | if ((DMAy_FLAG & FLAG_MASK) == (uint32_t)RESET) |
mbed_official | 76:aeb1df146756 | 664 | { |
mbed_official | 76:aeb1df146756 | 665 | /* Clear the selected DMAy flags */ |
mbed_official | 76:aeb1df146756 | 666 | DMA1->IFCR = DMAy_FLAG; |
mbed_official | 76:aeb1df146756 | 667 | } |
mbed_official | 76:aeb1df146756 | 668 | else |
mbed_official | 76:aeb1df146756 | 669 | { |
mbed_official | 76:aeb1df146756 | 670 | /* Clear the selected DMAy flags */ |
mbed_official | 76:aeb1df146756 | 671 | DMA2->IFCR = DMAy_FLAG; |
mbed_official | 76:aeb1df146756 | 672 | } |
mbed_official | 76:aeb1df146756 | 673 | } |
mbed_official | 76:aeb1df146756 | 674 | |
mbed_official | 76:aeb1df146756 | 675 | /** |
mbed_official | 76:aeb1df146756 | 676 | * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. |
mbed_official | 76:aeb1df146756 | 677 | * @param DMAy_IT: specifies the DMAy interrupt source to check. |
mbed_official | 76:aeb1df146756 | 678 | * This parameter can be one of the following values: |
mbed_official | 76:aeb1df146756 | 679 | * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. |
mbed_official | 76:aeb1df146756 | 680 | * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. |
mbed_official | 76:aeb1df146756 | 681 | * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. |
mbed_official | 76:aeb1df146756 | 682 | * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. |
mbed_official | 76:aeb1df146756 | 683 | * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. |
mbed_official | 76:aeb1df146756 | 684 | * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. |
mbed_official | 76:aeb1df146756 | 685 | * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. |
mbed_official | 76:aeb1df146756 | 686 | * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. |
mbed_official | 76:aeb1df146756 | 687 | * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. |
mbed_official | 76:aeb1df146756 | 688 | * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. |
mbed_official | 76:aeb1df146756 | 689 | * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. |
mbed_official | 76:aeb1df146756 | 690 | * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. |
mbed_official | 76:aeb1df146756 | 691 | * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. |
mbed_official | 76:aeb1df146756 | 692 | * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. |
mbed_official | 76:aeb1df146756 | 693 | * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. |
mbed_official | 76:aeb1df146756 | 694 | * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. |
mbed_official | 76:aeb1df146756 | 695 | * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. |
mbed_official | 76:aeb1df146756 | 696 | * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. |
mbed_official | 76:aeb1df146756 | 697 | * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. |
mbed_official | 76:aeb1df146756 | 698 | * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. |
mbed_official | 76:aeb1df146756 | 699 | * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. |
mbed_official | 76:aeb1df146756 | 700 | * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. |
mbed_official | 76:aeb1df146756 | 701 | * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. |
mbed_official | 76:aeb1df146756 | 702 | * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. |
mbed_official | 76:aeb1df146756 | 703 | * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. |
mbed_official | 76:aeb1df146756 | 704 | * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. |
mbed_official | 76:aeb1df146756 | 705 | * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. |
mbed_official | 76:aeb1df146756 | 706 | * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. |
mbed_official | 76:aeb1df146756 | 707 | * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. |
mbed_official | 76:aeb1df146756 | 708 | * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. |
mbed_official | 76:aeb1df146756 | 709 | * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. |
mbed_official | 76:aeb1df146756 | 710 | * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. |
mbed_official | 76:aeb1df146756 | 711 | * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. |
mbed_official | 76:aeb1df146756 | 712 | * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. |
mbed_official | 76:aeb1df146756 | 713 | * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. |
mbed_official | 76:aeb1df146756 | 714 | * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. |
mbed_official | 76:aeb1df146756 | 715 | * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. |
mbed_official | 76:aeb1df146756 | 716 | * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. |
mbed_official | 76:aeb1df146756 | 717 | * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. |
mbed_official | 76:aeb1df146756 | 718 | * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. |
mbed_official | 76:aeb1df146756 | 719 | * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. |
mbed_official | 76:aeb1df146756 | 720 | * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. |
mbed_official | 76:aeb1df146756 | 721 | * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. |
mbed_official | 76:aeb1df146756 | 722 | * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. |
mbed_official | 76:aeb1df146756 | 723 | * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. |
mbed_official | 76:aeb1df146756 | 724 | * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. |
mbed_official | 76:aeb1df146756 | 725 | * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. |
mbed_official | 76:aeb1df146756 | 726 | * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. |
mbed_official | 76:aeb1df146756 | 727 | * |
mbed_official | 76:aeb1df146756 | 728 | * @note |
mbed_official | 76:aeb1df146756 | 729 | * The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other |
mbed_official | 76:aeb1df146756 | 730 | * interrupts relative to the same channel is set (Transfer Complete, |
mbed_official | 76:aeb1df146756 | 731 | * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, |
mbed_official | 76:aeb1df146756 | 732 | * DMAy_IT_HTx or DMAy_IT_TEx). |
mbed_official | 76:aeb1df146756 | 733 | * |
mbed_official | 76:aeb1df146756 | 734 | * @retval The new state of DMAy_IT (SET or RESET). |
mbed_official | 76:aeb1df146756 | 735 | */ |
mbed_official | 76:aeb1df146756 | 736 | ITStatus DMA_GetITStatus(uint32_t DMAy_IT) |
mbed_official | 76:aeb1df146756 | 737 | { |
mbed_official | 76:aeb1df146756 | 738 | ITStatus bitstatus = RESET; |
mbed_official | 76:aeb1df146756 | 739 | uint32_t tmpreg = 0; |
mbed_official | 76:aeb1df146756 | 740 | |
mbed_official | 76:aeb1df146756 | 741 | /* Check the parameters */ |
mbed_official | 76:aeb1df146756 | 742 | assert_param(IS_DMA_GET_IT(DMAy_IT)); |
mbed_official | 76:aeb1df146756 | 743 | |
mbed_official | 76:aeb1df146756 | 744 | /* Calculate the used DMAy */ |
mbed_official | 76:aeb1df146756 | 745 | if ((DMAy_IT & FLAG_MASK) == (uint32_t)RESET) |
mbed_official | 76:aeb1df146756 | 746 | { |
mbed_official | 76:aeb1df146756 | 747 | /* Get DMA1 ISR register value */ |
mbed_official | 76:aeb1df146756 | 748 | tmpreg = DMA1->ISR; |
mbed_official | 76:aeb1df146756 | 749 | } |
mbed_official | 76:aeb1df146756 | 750 | else |
mbed_official | 76:aeb1df146756 | 751 | { |
mbed_official | 76:aeb1df146756 | 752 | /* Get DMA2 ISR register value */ |
mbed_official | 76:aeb1df146756 | 753 | tmpreg = DMA2->ISR; |
mbed_official | 76:aeb1df146756 | 754 | } |
mbed_official | 76:aeb1df146756 | 755 | |
mbed_official | 76:aeb1df146756 | 756 | /* Check the status of the specified DMAy interrupt */ |
mbed_official | 76:aeb1df146756 | 757 | if ((tmpreg & DMAy_IT) != (uint32_t)RESET) |
mbed_official | 76:aeb1df146756 | 758 | { |
mbed_official | 76:aeb1df146756 | 759 | /* DMAy_IT is set */ |
mbed_official | 76:aeb1df146756 | 760 | bitstatus = SET; |
mbed_official | 76:aeb1df146756 | 761 | } |
mbed_official | 76:aeb1df146756 | 762 | else |
mbed_official | 76:aeb1df146756 | 763 | { |
mbed_official | 76:aeb1df146756 | 764 | /* DMAy_IT is reset */ |
mbed_official | 76:aeb1df146756 | 765 | bitstatus = RESET; |
mbed_official | 76:aeb1df146756 | 766 | } |
mbed_official | 76:aeb1df146756 | 767 | /* Return the DMAy_IT status */ |
mbed_official | 76:aeb1df146756 | 768 | return bitstatus; |
mbed_official | 76:aeb1df146756 | 769 | } |
mbed_official | 76:aeb1df146756 | 770 | |
mbed_official | 76:aeb1df146756 | 771 | /** |
mbed_official | 76:aeb1df146756 | 772 | * @brief Clears the DMAy Channelx's interrupt pending bits. |
mbed_official | 76:aeb1df146756 | 773 | * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear. |
mbed_official | 76:aeb1df146756 | 774 | * This parameter can be any combination (for the same DMA) of the following values: |
mbed_official | 76:aeb1df146756 | 775 | * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. |
mbed_official | 76:aeb1df146756 | 776 | * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. |
mbed_official | 76:aeb1df146756 | 777 | * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. |
mbed_official | 76:aeb1df146756 | 778 | * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. |
mbed_official | 76:aeb1df146756 | 779 | * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. |
mbed_official | 76:aeb1df146756 | 780 | * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. |
mbed_official | 76:aeb1df146756 | 781 | * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. |
mbed_official | 76:aeb1df146756 | 782 | * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. |
mbed_official | 76:aeb1df146756 | 783 | * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. |
mbed_official | 76:aeb1df146756 | 784 | * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. |
mbed_official | 76:aeb1df146756 | 785 | * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. |
mbed_official | 76:aeb1df146756 | 786 | * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. |
mbed_official | 76:aeb1df146756 | 787 | * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. |
mbed_official | 76:aeb1df146756 | 788 | * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. |
mbed_official | 76:aeb1df146756 | 789 | * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. |
mbed_official | 76:aeb1df146756 | 790 | * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. |
mbed_official | 76:aeb1df146756 | 791 | * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. |
mbed_official | 76:aeb1df146756 | 792 | * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. |
mbed_official | 76:aeb1df146756 | 793 | * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. |
mbed_official | 76:aeb1df146756 | 794 | * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. |
mbed_official | 76:aeb1df146756 | 795 | * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt. |
mbed_official | 76:aeb1df146756 | 796 | * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt. |
mbed_official | 76:aeb1df146756 | 797 | * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt. |
mbed_official | 76:aeb1df146756 | 798 | * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt. |
mbed_official | 76:aeb1df146756 | 799 | * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt. |
mbed_official | 76:aeb1df146756 | 800 | * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt. |
mbed_official | 76:aeb1df146756 | 801 | * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt. |
mbed_official | 76:aeb1df146756 | 802 | * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt. |
mbed_official | 76:aeb1df146756 | 803 | * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt. |
mbed_official | 76:aeb1df146756 | 804 | * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt. |
mbed_official | 76:aeb1df146756 | 805 | * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt. |
mbed_official | 76:aeb1df146756 | 806 | * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt. |
mbed_official | 76:aeb1df146756 | 807 | * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt. |
mbed_official | 76:aeb1df146756 | 808 | * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt. |
mbed_official | 76:aeb1df146756 | 809 | * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt. |
mbed_official | 76:aeb1df146756 | 810 | * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt. |
mbed_official | 76:aeb1df146756 | 811 | * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt. |
mbed_official | 76:aeb1df146756 | 812 | * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt. |
mbed_official | 76:aeb1df146756 | 813 | * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt. |
mbed_official | 76:aeb1df146756 | 814 | * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt. |
mbed_official | 76:aeb1df146756 | 815 | * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt. |
mbed_official | 76:aeb1df146756 | 816 | * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt. |
mbed_official | 76:aeb1df146756 | 817 | * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt. |
mbed_official | 76:aeb1df146756 | 818 | * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt. |
mbed_official | 76:aeb1df146756 | 819 | * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt. |
mbed_official | 76:aeb1df146756 | 820 | * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt. |
mbed_official | 76:aeb1df146756 | 821 | * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt. |
mbed_official | 76:aeb1df146756 | 822 | * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt. |
mbed_official | 76:aeb1df146756 | 823 | * |
mbed_official | 76:aeb1df146756 | 824 | * @note |
mbed_official | 76:aeb1df146756 | 825 | * Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other |
mbed_official | 76:aeb1df146756 | 826 | * interrupts relative to the same channel (Transfer Complete, Half-transfer |
mbed_official | 76:aeb1df146756 | 827 | * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and |
mbed_official | 76:aeb1df146756 | 828 | * DMAy_IT_TEx). |
mbed_official | 76:aeb1df146756 | 829 | * |
mbed_official | 76:aeb1df146756 | 830 | * @retval None |
mbed_official | 76:aeb1df146756 | 831 | */ |
mbed_official | 76:aeb1df146756 | 832 | void DMA_ClearITPendingBit(uint32_t DMAy_IT) |
mbed_official | 76:aeb1df146756 | 833 | { |
mbed_official | 76:aeb1df146756 | 834 | /* Check the parameters */ |
mbed_official | 76:aeb1df146756 | 835 | assert_param(IS_DMA_CLEAR_IT(DMAy_IT)); |
mbed_official | 76:aeb1df146756 | 836 | |
mbed_official | 76:aeb1df146756 | 837 | /* Calculate the used DMAy */ |
mbed_official | 76:aeb1df146756 | 838 | if ((DMAy_IT & FLAG_MASK) == (uint32_t)RESET) |
mbed_official | 76:aeb1df146756 | 839 | { |
mbed_official | 76:aeb1df146756 | 840 | /* Clear the selected DMAy interrupt pending bits */ |
mbed_official | 76:aeb1df146756 | 841 | DMA1->IFCR = DMAy_IT; |
mbed_official | 76:aeb1df146756 | 842 | } |
mbed_official | 76:aeb1df146756 | 843 | else |
mbed_official | 76:aeb1df146756 | 844 | { |
mbed_official | 76:aeb1df146756 | 845 | /* Clear the selected DMAy interrupt pending bits */ |
mbed_official | 76:aeb1df146756 | 846 | DMA2->IFCR = DMAy_IT; |
mbed_official | 76:aeb1df146756 | 847 | } |
mbed_official | 76:aeb1df146756 | 848 | } |
mbed_official | 76:aeb1df146756 | 849 | |
mbed_official | 76:aeb1df146756 | 850 | /** |
mbed_official | 76:aeb1df146756 | 851 | * @} |
mbed_official | 76:aeb1df146756 | 852 | */ |
mbed_official | 76:aeb1df146756 | 853 | |
mbed_official | 76:aeb1df146756 | 854 | /** |
mbed_official | 76:aeb1df146756 | 855 | * @} |
mbed_official | 76:aeb1df146756 | 856 | */ |
mbed_official | 76:aeb1df146756 | 857 | |
mbed_official | 76:aeb1df146756 | 858 | /** |
mbed_official | 76:aeb1df146756 | 859 | * @} |
mbed_official | 76:aeb1df146756 | 860 | */ |
mbed_official | 76:aeb1df146756 | 861 | |
mbed_official | 76:aeb1df146756 | 862 | /** |
mbed_official | 76:aeb1df146756 | 863 | * @} |
mbed_official | 76:aeb1df146756 | 864 | */ |
mbed_official | 76:aeb1df146756 | 865 | |
mbed_official | 76:aeb1df146756 | 866 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |