mbed library sources
Fork of mbed-src by
targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_tim.c@308:59cc78a25982, 2014-09-05 (annotated)
- Committer:
- todotani
- Date:
- Fri Sep 05 14:20:33 2014 +0000
- Revision:
- 308:59cc78a25982
- Parent:
- 130:1dec54e4aec3
BLE_Health_Thermometer for mbed HRM1017 with BLE library 0.1.0
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 130:1dec54e4aec3 | 1 | /** |
mbed_official | 130:1dec54e4aec3 | 2 | ****************************************************************************** |
mbed_official | 130:1dec54e4aec3 | 3 | * @file stm32f0xx_tim.c |
mbed_official | 130:1dec54e4aec3 | 4 | * @author MCD Application Team |
mbed_official | 130:1dec54e4aec3 | 5 | * @version V1.3.0 |
mbed_official | 130:1dec54e4aec3 | 6 | * @date 16-January-2014 |
mbed_official | 130:1dec54e4aec3 | 7 | * @brief This file provides firmware functions to manage the following |
mbed_official | 130:1dec54e4aec3 | 8 | * functionalities of the TIM peripheral: |
mbed_official | 130:1dec54e4aec3 | 9 | * + TimeBase management |
mbed_official | 130:1dec54e4aec3 | 10 | * + Output Compare management |
mbed_official | 130:1dec54e4aec3 | 11 | * + Input Capture management |
mbed_official | 130:1dec54e4aec3 | 12 | * + Interrupts, DMA and flags management |
mbed_official | 130:1dec54e4aec3 | 13 | * + Clocks management |
mbed_official | 130:1dec54e4aec3 | 14 | * + Synchronization management |
mbed_official | 130:1dec54e4aec3 | 15 | * + Specific interface management |
mbed_official | 130:1dec54e4aec3 | 16 | * + Specific remapping management |
mbed_official | 130:1dec54e4aec3 | 17 | * |
mbed_official | 130:1dec54e4aec3 | 18 | * @verbatim |
mbed_official | 130:1dec54e4aec3 | 19 | |
mbed_official | 130:1dec54e4aec3 | 20 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 21 | ##### How to use this driver ##### |
mbed_official | 130:1dec54e4aec3 | 22 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 23 | [..] This driver provides functions to configure and program the TIM |
mbed_official | 130:1dec54e4aec3 | 24 | of all STM32F0xx devices These functions are split in 8 groups: |
mbed_official | 130:1dec54e4aec3 | 25 | (#) TIM TimeBase management: this group includes all needed functions |
mbed_official | 130:1dec54e4aec3 | 26 | to configure the TM Timebase unit: |
mbed_official | 130:1dec54e4aec3 | 27 | (++) Set/Get Prescaler. |
mbed_official | 130:1dec54e4aec3 | 28 | (++) Set/Get Autoreload. |
mbed_official | 130:1dec54e4aec3 | 29 | (++) Counter modes configuration. |
mbed_official | 130:1dec54e4aec3 | 30 | (++) Set Clock division. |
mbed_official | 130:1dec54e4aec3 | 31 | (++) Select the One Pulse mode. |
mbed_official | 130:1dec54e4aec3 | 32 | (++) Update Request Configuration. |
mbed_official | 130:1dec54e4aec3 | 33 | (++) Update Disable Configuration. |
mbed_official | 130:1dec54e4aec3 | 34 | (++) Auto-Preload Configuration. |
mbed_official | 130:1dec54e4aec3 | 35 | (++) Enable/Disable the counter. |
mbed_official | 130:1dec54e4aec3 | 36 | |
mbed_official | 130:1dec54e4aec3 | 37 | (#) TIM Output Compare management: this group includes all needed |
mbed_official | 130:1dec54e4aec3 | 38 | functions to configure the Capture/Compare unit used in Output |
mbed_official | 130:1dec54e4aec3 | 39 | compare mode: |
mbed_official | 130:1dec54e4aec3 | 40 | (++) Configure each channel, independently, in Output Compare mode. |
mbed_official | 130:1dec54e4aec3 | 41 | (++) Select the output compare modes. |
mbed_official | 130:1dec54e4aec3 | 42 | (++) Select the Polarities of each channel. |
mbed_official | 130:1dec54e4aec3 | 43 | (++) Set/Get the Capture/Compare register values. |
mbed_official | 130:1dec54e4aec3 | 44 | (++) Select the Output Compare Fast mode. |
mbed_official | 130:1dec54e4aec3 | 45 | (++) Select the Output Compare Forced mode. |
mbed_official | 130:1dec54e4aec3 | 46 | (++) Output Compare-Preload Configuration. |
mbed_official | 130:1dec54e4aec3 | 47 | (++) Clear Output Compare Reference. |
mbed_official | 130:1dec54e4aec3 | 48 | (++) Select the OCREF Clear signal. |
mbed_official | 130:1dec54e4aec3 | 49 | (++) Enable/Disable the Capture/Compare Channels. |
mbed_official | 130:1dec54e4aec3 | 50 | |
mbed_official | 130:1dec54e4aec3 | 51 | (#) TIM Input Capture management: this group includes all needed |
mbed_official | 130:1dec54e4aec3 | 52 | functions to configure the Capture/Compare unit used in |
mbed_official | 130:1dec54e4aec3 | 53 | Input Capture mode: |
mbed_official | 130:1dec54e4aec3 | 54 | (++) Configure each channel in input capture mode. |
mbed_official | 130:1dec54e4aec3 | 55 | (++) Configure Channel1/2 in PWM Input mode. |
mbed_official | 130:1dec54e4aec3 | 56 | (++) Set the Input Capture Prescaler. |
mbed_official | 130:1dec54e4aec3 | 57 | (++) Get the Capture/Compare values. |
mbed_official | 130:1dec54e4aec3 | 58 | |
mbed_official | 130:1dec54e4aec3 | 59 | (#) Advanced-control timers (TIM1) specific features |
mbed_official | 130:1dec54e4aec3 | 60 | (++) Configures the Break input, dead time, Lock level, the OSSI, |
mbed_official | 130:1dec54e4aec3 | 61 | the OSSR State and the AOE(automatic output enable) |
mbed_official | 130:1dec54e4aec3 | 62 | (++) Enable/Disable the TIM peripheral Main Outputs |
mbed_official | 130:1dec54e4aec3 | 63 | (++) Select the Commutation event |
mbed_official | 130:1dec54e4aec3 | 64 | (++) Set/Reset the Capture Compare Preload Control bit |
mbed_official | 130:1dec54e4aec3 | 65 | |
mbed_official | 130:1dec54e4aec3 | 66 | (#) TIM interrupts, DMA and flags management. |
mbed_official | 130:1dec54e4aec3 | 67 | (++) Enable/Disable interrupt sources. |
mbed_official | 130:1dec54e4aec3 | 68 | (++) Get flags status. |
mbed_official | 130:1dec54e4aec3 | 69 | (++) Clear flags/ Pending bits. |
mbed_official | 130:1dec54e4aec3 | 70 | (++) Enable/Disable DMA requests. |
mbed_official | 130:1dec54e4aec3 | 71 | (++) Configure DMA burst mode. |
mbed_official | 130:1dec54e4aec3 | 72 | (++) Select CaptureCompare DMA request. |
mbed_official | 130:1dec54e4aec3 | 73 | |
mbed_official | 130:1dec54e4aec3 | 74 | (#) TIM clocks management: this group includes all needed functions |
mbed_official | 130:1dec54e4aec3 | 75 | to configure the clock controller unit: |
mbed_official | 130:1dec54e4aec3 | 76 | (++) Select internal/External clock. |
mbed_official | 130:1dec54e4aec3 | 77 | (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx. |
mbed_official | 130:1dec54e4aec3 | 78 | |
mbed_official | 130:1dec54e4aec3 | 79 | (#) TIM synchronization management: this group includes all needed. |
mbed_official | 130:1dec54e4aec3 | 80 | functions to configure the Synchronization unit: |
mbed_official | 130:1dec54e4aec3 | 81 | (++) Select Input Trigger. |
mbed_official | 130:1dec54e4aec3 | 82 | (++) Select Output Trigger. |
mbed_official | 130:1dec54e4aec3 | 83 | (++) Select Master Slave Mode. |
mbed_official | 130:1dec54e4aec3 | 84 | (++) ETR Configuration when used as external trigger. |
mbed_official | 130:1dec54e4aec3 | 85 | |
mbed_official | 130:1dec54e4aec3 | 86 | (#) TIM specific interface management, this group includes all |
mbed_official | 130:1dec54e4aec3 | 87 | needed functions to use the specific TIM interface: |
mbed_official | 130:1dec54e4aec3 | 88 | (++) Encoder Interface Configuration. |
mbed_official | 130:1dec54e4aec3 | 89 | (++) Select Hall Sensor. |
mbed_official | 130:1dec54e4aec3 | 90 | |
mbed_official | 130:1dec54e4aec3 | 91 | (#) TIM specific remapping management includes the Remapping |
mbed_official | 130:1dec54e4aec3 | 92 | configuration of specific timers |
mbed_official | 130:1dec54e4aec3 | 93 | |
mbed_official | 130:1dec54e4aec3 | 94 | @endverbatim |
mbed_official | 130:1dec54e4aec3 | 95 | * |
mbed_official | 130:1dec54e4aec3 | 96 | ****************************************************************************** |
mbed_official | 130:1dec54e4aec3 | 97 | * @attention |
mbed_official | 130:1dec54e4aec3 | 98 | * |
mbed_official | 130:1dec54e4aec3 | 99 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 130:1dec54e4aec3 | 100 | * |
mbed_official | 130:1dec54e4aec3 | 101 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 130:1dec54e4aec3 | 102 | * are permitted provided that the following conditions are met: |
mbed_official | 130:1dec54e4aec3 | 103 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 130:1dec54e4aec3 | 104 | * this list of conditions and the following disclaimer. |
mbed_official | 130:1dec54e4aec3 | 105 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 130:1dec54e4aec3 | 106 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 130:1dec54e4aec3 | 107 | * and/or other materials provided with the distribution. |
mbed_official | 130:1dec54e4aec3 | 108 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 130:1dec54e4aec3 | 109 | * may be used to endorse or promote products derived from this software |
mbed_official | 130:1dec54e4aec3 | 110 | * without specific prior written permission. |
mbed_official | 130:1dec54e4aec3 | 111 | * |
mbed_official | 130:1dec54e4aec3 | 112 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 130:1dec54e4aec3 | 113 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 130:1dec54e4aec3 | 114 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 130:1dec54e4aec3 | 115 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 130:1dec54e4aec3 | 116 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 130:1dec54e4aec3 | 117 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 130:1dec54e4aec3 | 118 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 130:1dec54e4aec3 | 119 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 130:1dec54e4aec3 | 120 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 130:1dec54e4aec3 | 121 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 130:1dec54e4aec3 | 122 | * |
mbed_official | 130:1dec54e4aec3 | 123 | ****************************************************************************** |
mbed_official | 130:1dec54e4aec3 | 124 | */ |
mbed_official | 130:1dec54e4aec3 | 125 | |
mbed_official | 130:1dec54e4aec3 | 126 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 130:1dec54e4aec3 | 127 | #include "stm32f0xx_tim.h" |
mbed_official | 130:1dec54e4aec3 | 128 | #include "stm32f0xx_rcc.h" |
mbed_official | 130:1dec54e4aec3 | 129 | |
mbed_official | 130:1dec54e4aec3 | 130 | /** @addtogroup STM32F0xx_StdPeriph_Driver |
mbed_official | 130:1dec54e4aec3 | 131 | * @{ |
mbed_official | 130:1dec54e4aec3 | 132 | */ |
mbed_official | 130:1dec54e4aec3 | 133 | |
mbed_official | 130:1dec54e4aec3 | 134 | /** @defgroup TIM |
mbed_official | 130:1dec54e4aec3 | 135 | * @brief TIM driver modules |
mbed_official | 130:1dec54e4aec3 | 136 | * @{ |
mbed_official | 130:1dec54e4aec3 | 137 | */ |
mbed_official | 130:1dec54e4aec3 | 138 | |
mbed_official | 130:1dec54e4aec3 | 139 | /* Private typedef -----------------------------------------------------------*/ |
mbed_official | 130:1dec54e4aec3 | 140 | /* Private define ------------------------------------------------------------*/ |
mbed_official | 130:1dec54e4aec3 | 141 | |
mbed_official | 130:1dec54e4aec3 | 142 | /* ---------------------- TIM registers bit mask ------------------------ */ |
mbed_official | 130:1dec54e4aec3 | 143 | #define SMCR_ETR_MASK ((uint16_t)0x00FF) |
mbed_official | 130:1dec54e4aec3 | 144 | #define CCMR_OFFSET ((uint16_t)0x0018) |
mbed_official | 130:1dec54e4aec3 | 145 | #define CCER_CCE_SET ((uint16_t)0x0001) |
mbed_official | 130:1dec54e4aec3 | 146 | #define CCER_CCNE_SET ((uint16_t)0x0004) |
mbed_official | 130:1dec54e4aec3 | 147 | |
mbed_official | 130:1dec54e4aec3 | 148 | /* Private macro -------------------------------------------------------------*/ |
mbed_official | 130:1dec54e4aec3 | 149 | /* Private variables ---------------------------------------------------------*/ |
mbed_official | 130:1dec54e4aec3 | 150 | /* Private function prototypes -----------------------------------------------*/ |
mbed_official | 130:1dec54e4aec3 | 151 | |
mbed_official | 130:1dec54e4aec3 | 152 | static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, |
mbed_official | 130:1dec54e4aec3 | 153 | uint16_t TIM_ICFilter); |
mbed_official | 130:1dec54e4aec3 | 154 | static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, |
mbed_official | 130:1dec54e4aec3 | 155 | uint16_t TIM_ICFilter); |
mbed_official | 130:1dec54e4aec3 | 156 | static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, |
mbed_official | 130:1dec54e4aec3 | 157 | uint16_t TIM_ICFilter); |
mbed_official | 130:1dec54e4aec3 | 158 | static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, |
mbed_official | 130:1dec54e4aec3 | 159 | uint16_t TIM_ICFilter); |
mbed_official | 130:1dec54e4aec3 | 160 | /* Private functions ---------------------------------------------------------*/ |
mbed_official | 130:1dec54e4aec3 | 161 | |
mbed_official | 130:1dec54e4aec3 | 162 | /** @defgroup TIM_Private_Functions |
mbed_official | 130:1dec54e4aec3 | 163 | * @{ |
mbed_official | 130:1dec54e4aec3 | 164 | */ |
mbed_official | 130:1dec54e4aec3 | 165 | |
mbed_official | 130:1dec54e4aec3 | 166 | /** @defgroup TIM_Group1 TimeBase management functions |
mbed_official | 130:1dec54e4aec3 | 167 | * @brief TimeBase management functions |
mbed_official | 130:1dec54e4aec3 | 168 | * |
mbed_official | 130:1dec54e4aec3 | 169 | @verbatim |
mbed_official | 130:1dec54e4aec3 | 170 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 171 | ##### TimeBase management functions ##### |
mbed_official | 130:1dec54e4aec3 | 172 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 173 | |
mbed_official | 130:1dec54e4aec3 | 174 | *** TIM Driver: how to use it in Timing(Time base) Mode *** |
mbed_official | 130:1dec54e4aec3 | 175 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 176 | [..] To use the Timer in Timing(Time base) mode, the following steps are |
mbed_official | 130:1dec54e4aec3 | 177 | mandatory: |
mbed_official | 130:1dec54e4aec3 | 178 | (#) Enable TIM clock using |
mbed_official | 130:1dec54e4aec3 | 179 | RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function. |
mbed_official | 130:1dec54e4aec3 | 180 | (#) Fill the TIM_TimeBaseInitStruct with the desired parameters. |
mbed_official | 130:1dec54e4aec3 | 181 | (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure |
mbed_official | 130:1dec54e4aec3 | 182 | the Time Base unit with the corresponding configuration. |
mbed_official | 130:1dec54e4aec3 | 183 | (#) Enable the NVIC if you need to generate the update interrupt. |
mbed_official | 130:1dec54e4aec3 | 184 | (#) Enable the corresponding interrupt using the function |
mbed_official | 130:1dec54e4aec3 | 185 | TIM_ITConfig(TIMx, TIM_IT_Update). |
mbed_official | 130:1dec54e4aec3 | 186 | (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. |
mbed_official | 130:1dec54e4aec3 | 187 | [..] |
mbed_official | 130:1dec54e4aec3 | 188 | (@) All other functions can be used seperatly to modify, if needed, |
mbed_official | 130:1dec54e4aec3 | 189 | a specific feature of the Timer. |
mbed_official | 130:1dec54e4aec3 | 190 | |
mbed_official | 130:1dec54e4aec3 | 191 | @endverbatim |
mbed_official | 130:1dec54e4aec3 | 192 | * @{ |
mbed_official | 130:1dec54e4aec3 | 193 | */ |
mbed_official | 130:1dec54e4aec3 | 194 | |
mbed_official | 130:1dec54e4aec3 | 195 | /** |
mbed_official | 130:1dec54e4aec3 | 196 | * @brief Deinitializes the TIMx peripheral registers to their default reset values. |
mbed_official | 130:1dec54e4aec3 | 197 | * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 198 | * @note TIM7 is applicable only for STM32F072 devices |
mbed_official | 130:1dec54e4aec3 | 199 | * @note TIM6 is not applivable for STM32F031 devices. |
mbed_official | 130:1dec54e4aec3 | 200 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 201 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 202 | * |
mbed_official | 130:1dec54e4aec3 | 203 | */ |
mbed_official | 130:1dec54e4aec3 | 204 | void TIM_DeInit(TIM_TypeDef* TIMx) |
mbed_official | 130:1dec54e4aec3 | 205 | { |
mbed_official | 130:1dec54e4aec3 | 206 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 207 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 208 | |
mbed_official | 130:1dec54e4aec3 | 209 | if (TIMx == TIM1) |
mbed_official | 130:1dec54e4aec3 | 210 | { |
mbed_official | 130:1dec54e4aec3 | 211 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); |
mbed_official | 130:1dec54e4aec3 | 212 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); |
mbed_official | 130:1dec54e4aec3 | 213 | } |
mbed_official | 130:1dec54e4aec3 | 214 | else if (TIMx == TIM2) |
mbed_official | 130:1dec54e4aec3 | 215 | { |
mbed_official | 130:1dec54e4aec3 | 216 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); |
mbed_official | 130:1dec54e4aec3 | 217 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); |
mbed_official | 130:1dec54e4aec3 | 218 | } |
mbed_official | 130:1dec54e4aec3 | 219 | else if (TIMx == TIM3) |
mbed_official | 130:1dec54e4aec3 | 220 | { |
mbed_official | 130:1dec54e4aec3 | 221 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); |
mbed_official | 130:1dec54e4aec3 | 222 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); |
mbed_official | 130:1dec54e4aec3 | 223 | } |
mbed_official | 130:1dec54e4aec3 | 224 | else if (TIMx == TIM6) |
mbed_official | 130:1dec54e4aec3 | 225 | { |
mbed_official | 130:1dec54e4aec3 | 226 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); |
mbed_official | 130:1dec54e4aec3 | 227 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); |
mbed_official | 130:1dec54e4aec3 | 228 | } |
mbed_official | 130:1dec54e4aec3 | 229 | else if (TIMx == TIM7) |
mbed_official | 130:1dec54e4aec3 | 230 | { |
mbed_official | 130:1dec54e4aec3 | 231 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); |
mbed_official | 130:1dec54e4aec3 | 232 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); |
mbed_official | 130:1dec54e4aec3 | 233 | } |
mbed_official | 130:1dec54e4aec3 | 234 | else if (TIMx == TIM14) |
mbed_official | 130:1dec54e4aec3 | 235 | { |
mbed_official | 130:1dec54e4aec3 | 236 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); |
mbed_official | 130:1dec54e4aec3 | 237 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); |
mbed_official | 130:1dec54e4aec3 | 238 | } |
mbed_official | 130:1dec54e4aec3 | 239 | else if (TIMx == TIM15) |
mbed_official | 130:1dec54e4aec3 | 240 | { |
mbed_official | 130:1dec54e4aec3 | 241 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE); |
mbed_official | 130:1dec54e4aec3 | 242 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE); |
mbed_official | 130:1dec54e4aec3 | 243 | } |
mbed_official | 130:1dec54e4aec3 | 244 | else if (TIMx == TIM16) |
mbed_official | 130:1dec54e4aec3 | 245 | { |
mbed_official | 130:1dec54e4aec3 | 246 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE); |
mbed_official | 130:1dec54e4aec3 | 247 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE); |
mbed_official | 130:1dec54e4aec3 | 248 | } |
mbed_official | 130:1dec54e4aec3 | 249 | else |
mbed_official | 130:1dec54e4aec3 | 250 | { |
mbed_official | 130:1dec54e4aec3 | 251 | if (TIMx == TIM17) |
mbed_official | 130:1dec54e4aec3 | 252 | { |
mbed_official | 130:1dec54e4aec3 | 253 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE); |
mbed_official | 130:1dec54e4aec3 | 254 | RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); |
mbed_official | 130:1dec54e4aec3 | 255 | } |
mbed_official | 130:1dec54e4aec3 | 256 | } |
mbed_official | 130:1dec54e4aec3 | 257 | |
mbed_official | 130:1dec54e4aec3 | 258 | } |
mbed_official | 130:1dec54e4aec3 | 259 | |
mbed_official | 130:1dec54e4aec3 | 260 | /** |
mbed_official | 130:1dec54e4aec3 | 261 | * @brief Initializes the TIMx Time Base Unit peripheral according to |
mbed_official | 130:1dec54e4aec3 | 262 | * the specified parameters in the TIM_TimeBaseInitStruct. |
mbed_official | 130:1dec54e4aec3 | 263 | * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM |
mbed_official | 130:1dec54e4aec3 | 264 | * peripheral. |
mbed_official | 130:1dec54e4aec3 | 265 | * @note TIM7 is applicable only for STM32F072 devices |
mbed_official | 130:1dec54e4aec3 | 266 | * @note TIM6 is not applivable for STM32F031 devices. |
mbed_official | 130:1dec54e4aec3 | 267 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 268 | * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef |
mbed_official | 130:1dec54e4aec3 | 269 | * structure that contains the configuration information for |
mbed_official | 130:1dec54e4aec3 | 270 | * the specified TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 271 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 272 | */ |
mbed_official | 130:1dec54e4aec3 | 273 | void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) |
mbed_official | 130:1dec54e4aec3 | 274 | { |
mbed_official | 130:1dec54e4aec3 | 275 | uint16_t tmpcr1 = 0; |
mbed_official | 130:1dec54e4aec3 | 276 | |
mbed_official | 130:1dec54e4aec3 | 277 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 278 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 279 | assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); |
mbed_official | 130:1dec54e4aec3 | 280 | assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); |
mbed_official | 130:1dec54e4aec3 | 281 | |
mbed_official | 130:1dec54e4aec3 | 282 | tmpcr1 = TIMx->CR1; |
mbed_official | 130:1dec54e4aec3 | 283 | |
mbed_official | 130:1dec54e4aec3 | 284 | if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3)) |
mbed_official | 130:1dec54e4aec3 | 285 | { |
mbed_official | 130:1dec54e4aec3 | 286 | /* Select the Counter Mode */ |
mbed_official | 130:1dec54e4aec3 | 287 | tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); |
mbed_official | 130:1dec54e4aec3 | 288 | tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; |
mbed_official | 130:1dec54e4aec3 | 289 | } |
mbed_official | 130:1dec54e4aec3 | 290 | |
mbed_official | 130:1dec54e4aec3 | 291 | if(TIMx != TIM6) |
mbed_official | 130:1dec54e4aec3 | 292 | { |
mbed_official | 130:1dec54e4aec3 | 293 | /* Set the clock division */ |
mbed_official | 130:1dec54e4aec3 | 294 | tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD)); |
mbed_official | 130:1dec54e4aec3 | 295 | tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; |
mbed_official | 130:1dec54e4aec3 | 296 | } |
mbed_official | 130:1dec54e4aec3 | 297 | |
mbed_official | 130:1dec54e4aec3 | 298 | TIMx->CR1 = tmpcr1; |
mbed_official | 130:1dec54e4aec3 | 299 | |
mbed_official | 130:1dec54e4aec3 | 300 | /* Set the Autoreload value */ |
mbed_official | 130:1dec54e4aec3 | 301 | TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; |
mbed_official | 130:1dec54e4aec3 | 302 | |
mbed_official | 130:1dec54e4aec3 | 303 | /* Set the Prescaler value */ |
mbed_official | 130:1dec54e4aec3 | 304 | TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; |
mbed_official | 130:1dec54e4aec3 | 305 | |
mbed_official | 130:1dec54e4aec3 | 306 | if ((TIMx == TIM1) || (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17)) |
mbed_official | 130:1dec54e4aec3 | 307 | { |
mbed_official | 130:1dec54e4aec3 | 308 | /* Set the Repetition Counter value */ |
mbed_official | 130:1dec54e4aec3 | 309 | TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; |
mbed_official | 130:1dec54e4aec3 | 310 | } |
mbed_official | 130:1dec54e4aec3 | 311 | |
mbed_official | 130:1dec54e4aec3 | 312 | /* Generate an update event to reload the Prescaler and the Repetition counter |
mbed_official | 130:1dec54e4aec3 | 313 | values immediately */ |
mbed_official | 130:1dec54e4aec3 | 314 | TIMx->EGR = TIM_PSCReloadMode_Immediate; |
mbed_official | 130:1dec54e4aec3 | 315 | } |
mbed_official | 130:1dec54e4aec3 | 316 | |
mbed_official | 130:1dec54e4aec3 | 317 | /** |
mbed_official | 130:1dec54e4aec3 | 318 | * @brief Fills each TIM_TimeBaseInitStruct member with its default value. |
mbed_official | 130:1dec54e4aec3 | 319 | * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure |
mbed_official | 130:1dec54e4aec3 | 320 | * which will be initialized. |
mbed_official | 130:1dec54e4aec3 | 321 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 322 | */ |
mbed_official | 130:1dec54e4aec3 | 323 | void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) |
mbed_official | 130:1dec54e4aec3 | 324 | { |
mbed_official | 130:1dec54e4aec3 | 325 | /* Set the default configuration */ |
mbed_official | 130:1dec54e4aec3 | 326 | TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF; |
mbed_official | 130:1dec54e4aec3 | 327 | TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; |
mbed_official | 130:1dec54e4aec3 | 328 | TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; |
mbed_official | 130:1dec54e4aec3 | 329 | TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; |
mbed_official | 130:1dec54e4aec3 | 330 | TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; |
mbed_official | 130:1dec54e4aec3 | 331 | } |
mbed_official | 130:1dec54e4aec3 | 332 | |
mbed_official | 130:1dec54e4aec3 | 333 | /** |
mbed_official | 130:1dec54e4aec3 | 334 | * @brief Configures the TIMx Prescaler. |
mbed_official | 130:1dec54e4aec3 | 335 | * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 336 | * @note TIM7 is applicable only for STM32F072 devices |
mbed_official | 130:1dec54e4aec3 | 337 | * @note TIM6 is not applivable for STM32F031 devices. |
mbed_official | 130:1dec54e4aec3 | 338 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 339 | * @param Prescaler: specifies the Prescaler Register value |
mbed_official | 130:1dec54e4aec3 | 340 | * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode |
mbed_official | 130:1dec54e4aec3 | 341 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 342 | * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. |
mbed_official | 130:1dec54e4aec3 | 343 | * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly. |
mbed_official | 130:1dec54e4aec3 | 344 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 345 | */ |
mbed_official | 130:1dec54e4aec3 | 346 | void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) |
mbed_official | 130:1dec54e4aec3 | 347 | { |
mbed_official | 130:1dec54e4aec3 | 348 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 349 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 350 | assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); |
mbed_official | 130:1dec54e4aec3 | 351 | |
mbed_official | 130:1dec54e4aec3 | 352 | /* Set the Prescaler value */ |
mbed_official | 130:1dec54e4aec3 | 353 | TIMx->PSC = Prescaler; |
mbed_official | 130:1dec54e4aec3 | 354 | /* Set or reset the UG Bit */ |
mbed_official | 130:1dec54e4aec3 | 355 | TIMx->EGR = TIM_PSCReloadMode; |
mbed_official | 130:1dec54e4aec3 | 356 | } |
mbed_official | 130:1dec54e4aec3 | 357 | |
mbed_official | 130:1dec54e4aec3 | 358 | /** |
mbed_official | 130:1dec54e4aec3 | 359 | * @brief Specifies the TIMx Counter Mode to be used. |
mbed_official | 130:1dec54e4aec3 | 360 | * @param TIMx: where x can be 1, 2, or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 361 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 362 | * @param TIM_CounterMode: specifies the Counter Mode to be used |
mbed_official | 130:1dec54e4aec3 | 363 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 364 | * @arg TIM_CounterMode_Up: TIM Up Counting Mode |
mbed_official | 130:1dec54e4aec3 | 365 | * @arg TIM_CounterMode_Down: TIM Down Counting Mode |
mbed_official | 130:1dec54e4aec3 | 366 | * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 |
mbed_official | 130:1dec54e4aec3 | 367 | * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 |
mbed_official | 130:1dec54e4aec3 | 368 | * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 |
mbed_official | 130:1dec54e4aec3 | 369 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 370 | */ |
mbed_official | 130:1dec54e4aec3 | 371 | void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) |
mbed_official | 130:1dec54e4aec3 | 372 | { |
mbed_official | 130:1dec54e4aec3 | 373 | uint16_t tmpcr1 = 0; |
mbed_official | 130:1dec54e4aec3 | 374 | |
mbed_official | 130:1dec54e4aec3 | 375 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 376 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 377 | assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); |
mbed_official | 130:1dec54e4aec3 | 378 | |
mbed_official | 130:1dec54e4aec3 | 379 | tmpcr1 = TIMx->CR1; |
mbed_official | 130:1dec54e4aec3 | 380 | /* Reset the CMS and DIR Bits */ |
mbed_official | 130:1dec54e4aec3 | 381 | tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); |
mbed_official | 130:1dec54e4aec3 | 382 | /* Set the Counter Mode */ |
mbed_official | 130:1dec54e4aec3 | 383 | tmpcr1 |= TIM_CounterMode; |
mbed_official | 130:1dec54e4aec3 | 384 | /* Write to TIMx CR1 register */ |
mbed_official | 130:1dec54e4aec3 | 385 | TIMx->CR1 = tmpcr1; |
mbed_official | 130:1dec54e4aec3 | 386 | } |
mbed_official | 130:1dec54e4aec3 | 387 | |
mbed_official | 130:1dec54e4aec3 | 388 | /** |
mbed_official | 130:1dec54e4aec3 | 389 | * @brief Sets the TIMx Counter Register value |
mbed_official | 130:1dec54e4aec3 | 390 | * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM |
mbed_official | 130:1dec54e4aec3 | 391 | * peripheral. |
mbed_official | 130:1dec54e4aec3 | 392 | * @note TIM7 is applicable only for STM32F072 devices |
mbed_official | 130:1dec54e4aec3 | 393 | * @note TIM6 is not applivable for STM32F031 devices. |
mbed_official | 130:1dec54e4aec3 | 394 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 395 | * @param Counter: specifies the Counter register new value. |
mbed_official | 130:1dec54e4aec3 | 396 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 397 | */ |
mbed_official | 130:1dec54e4aec3 | 398 | void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) |
mbed_official | 130:1dec54e4aec3 | 399 | { |
mbed_official | 130:1dec54e4aec3 | 400 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 401 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 402 | |
mbed_official | 130:1dec54e4aec3 | 403 | /* Set the Counter Register value */ |
mbed_official | 130:1dec54e4aec3 | 404 | TIMx->CNT = Counter; |
mbed_official | 130:1dec54e4aec3 | 405 | } |
mbed_official | 130:1dec54e4aec3 | 406 | |
mbed_official | 130:1dec54e4aec3 | 407 | /** |
mbed_official | 130:1dec54e4aec3 | 408 | * @brief Sets the TIMx Autoreload Register value |
mbed_official | 130:1dec54e4aec3 | 409 | * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 410 | * @note TIM7 is applicable only for STM32F072 devices |
mbed_official | 130:1dec54e4aec3 | 411 | * @note TIM6 is not applivable for STM32F031 devices. |
mbed_official | 130:1dec54e4aec3 | 412 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 413 | * @param Autoreload: specifies the Autoreload register new value. |
mbed_official | 130:1dec54e4aec3 | 414 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 415 | */ |
mbed_official | 130:1dec54e4aec3 | 416 | void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload) |
mbed_official | 130:1dec54e4aec3 | 417 | { |
mbed_official | 130:1dec54e4aec3 | 418 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 419 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 420 | |
mbed_official | 130:1dec54e4aec3 | 421 | /* Set the Autoreload Register value */ |
mbed_official | 130:1dec54e4aec3 | 422 | TIMx->ARR = Autoreload; |
mbed_official | 130:1dec54e4aec3 | 423 | } |
mbed_official | 130:1dec54e4aec3 | 424 | |
mbed_official | 130:1dec54e4aec3 | 425 | /** |
mbed_official | 130:1dec54e4aec3 | 426 | * @brief Gets the TIMx Counter value. |
mbed_official | 130:1dec54e4aec3 | 427 | * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM |
mbed_official | 130:1dec54e4aec3 | 428 | * peripheral. |
mbed_official | 130:1dec54e4aec3 | 429 | * @note TIM7 is applicable only for STM32F072 devices |
mbed_official | 130:1dec54e4aec3 | 430 | * @note TIM6 is not applivable for STM32F031 devices. |
mbed_official | 130:1dec54e4aec3 | 431 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 432 | * @retval Counter Register value. |
mbed_official | 130:1dec54e4aec3 | 433 | */ |
mbed_official | 130:1dec54e4aec3 | 434 | uint32_t TIM_GetCounter(TIM_TypeDef* TIMx) |
mbed_official | 130:1dec54e4aec3 | 435 | { |
mbed_official | 130:1dec54e4aec3 | 436 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 437 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 438 | |
mbed_official | 130:1dec54e4aec3 | 439 | /* Get the Counter Register value */ |
mbed_official | 130:1dec54e4aec3 | 440 | return TIMx->CNT; |
mbed_official | 130:1dec54e4aec3 | 441 | } |
mbed_official | 130:1dec54e4aec3 | 442 | |
mbed_official | 130:1dec54e4aec3 | 443 | /** |
mbed_official | 130:1dec54e4aec3 | 444 | * @brief Gets the TIMx Prescaler value. |
mbed_official | 130:1dec54e4aec3 | 445 | * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM |
mbed_official | 130:1dec54e4aec3 | 446 | * peripheral. |
mbed_official | 130:1dec54e4aec3 | 447 | * @note TIM7 is applicable only for STM32F072 devices |
mbed_official | 130:1dec54e4aec3 | 448 | * @note TIM6 is not applivable for STM32F031 devices. |
mbed_official | 130:1dec54e4aec3 | 449 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 450 | * @retval Prescaler Register value. |
mbed_official | 130:1dec54e4aec3 | 451 | */ |
mbed_official | 130:1dec54e4aec3 | 452 | uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) |
mbed_official | 130:1dec54e4aec3 | 453 | { |
mbed_official | 130:1dec54e4aec3 | 454 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 455 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 456 | |
mbed_official | 130:1dec54e4aec3 | 457 | /* Get the Prescaler Register value */ |
mbed_official | 130:1dec54e4aec3 | 458 | return TIMx->PSC; |
mbed_official | 130:1dec54e4aec3 | 459 | } |
mbed_official | 130:1dec54e4aec3 | 460 | |
mbed_official | 130:1dec54e4aec3 | 461 | /** |
mbed_official | 130:1dec54e4aec3 | 462 | * @brief Enables or Disables the TIMx Update event. |
mbed_official | 130:1dec54e4aec3 | 463 | * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM |
mbed_official | 130:1dec54e4aec3 | 464 | * peripheral. |
mbed_official | 130:1dec54e4aec3 | 465 | * @note TIM7 is applicable only for STM32F072 devices |
mbed_official | 130:1dec54e4aec3 | 466 | * @note TIM6 is not applivable for STM32F031 devices. |
mbed_official | 130:1dec54e4aec3 | 467 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 468 | * @param NewState: new state of the TIMx UDIS bit |
mbed_official | 130:1dec54e4aec3 | 469 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 130:1dec54e4aec3 | 470 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 471 | */ |
mbed_official | 130:1dec54e4aec3 | 472 | void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) |
mbed_official | 130:1dec54e4aec3 | 473 | { |
mbed_official | 130:1dec54e4aec3 | 474 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 475 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 476 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 130:1dec54e4aec3 | 477 | |
mbed_official | 130:1dec54e4aec3 | 478 | if (NewState != DISABLE) |
mbed_official | 130:1dec54e4aec3 | 479 | { |
mbed_official | 130:1dec54e4aec3 | 480 | /* Set the Update Disable Bit */ |
mbed_official | 130:1dec54e4aec3 | 481 | TIMx->CR1 |= TIM_CR1_UDIS; |
mbed_official | 130:1dec54e4aec3 | 482 | } |
mbed_official | 130:1dec54e4aec3 | 483 | else |
mbed_official | 130:1dec54e4aec3 | 484 | { |
mbed_official | 130:1dec54e4aec3 | 485 | /* Reset the Update Disable Bit */ |
mbed_official | 130:1dec54e4aec3 | 486 | TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS); |
mbed_official | 130:1dec54e4aec3 | 487 | } |
mbed_official | 130:1dec54e4aec3 | 488 | } |
mbed_official | 130:1dec54e4aec3 | 489 | |
mbed_official | 130:1dec54e4aec3 | 490 | /** |
mbed_official | 130:1dec54e4aec3 | 491 | * @brief Configures the TIMx Update Request Interrupt source. |
mbed_official | 130:1dec54e4aec3 | 492 | * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM |
mbed_official | 130:1dec54e4aec3 | 493 | * peripheral. |
mbed_official | 130:1dec54e4aec3 | 494 | * @note TIM7 is applicable only for STM32F072 devices |
mbed_official | 130:1dec54e4aec3 | 495 | * @note TIM6 is not applivable for STM32F031 devices. |
mbed_official | 130:1dec54e4aec3 | 496 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 497 | * @param TIM_UpdateSource: specifies the Update source. |
mbed_official | 130:1dec54e4aec3 | 498 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 499 | * @arg TIM_UpdateSource_Regular: Source of update is the counter |
mbed_official | 130:1dec54e4aec3 | 500 | * overflow/underflow or the setting of UG bit, or an update |
mbed_official | 130:1dec54e4aec3 | 501 | * generation through the slave mode controller. |
mbed_official | 130:1dec54e4aec3 | 502 | * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. |
mbed_official | 130:1dec54e4aec3 | 503 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 504 | */ |
mbed_official | 130:1dec54e4aec3 | 505 | void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) |
mbed_official | 130:1dec54e4aec3 | 506 | { |
mbed_official | 130:1dec54e4aec3 | 507 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 508 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 509 | assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); |
mbed_official | 130:1dec54e4aec3 | 510 | |
mbed_official | 130:1dec54e4aec3 | 511 | if (TIM_UpdateSource != TIM_UpdateSource_Global) |
mbed_official | 130:1dec54e4aec3 | 512 | { |
mbed_official | 130:1dec54e4aec3 | 513 | /* Set the URS Bit */ |
mbed_official | 130:1dec54e4aec3 | 514 | TIMx->CR1 |= TIM_CR1_URS; |
mbed_official | 130:1dec54e4aec3 | 515 | } |
mbed_official | 130:1dec54e4aec3 | 516 | else |
mbed_official | 130:1dec54e4aec3 | 517 | { |
mbed_official | 130:1dec54e4aec3 | 518 | /* Reset the URS Bit */ |
mbed_official | 130:1dec54e4aec3 | 519 | TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS); |
mbed_official | 130:1dec54e4aec3 | 520 | } |
mbed_official | 130:1dec54e4aec3 | 521 | } |
mbed_official | 130:1dec54e4aec3 | 522 | |
mbed_official | 130:1dec54e4aec3 | 523 | /** |
mbed_official | 130:1dec54e4aec3 | 524 | * @brief Enables or disables TIMx peripheral Preload register on ARR. |
mbed_official | 130:1dec54e4aec3 | 525 | * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM |
mbed_official | 130:1dec54e4aec3 | 526 | * peripheral. |
mbed_official | 130:1dec54e4aec3 | 527 | * @note TIM7 is applicable only for STM32F072 devices |
mbed_official | 130:1dec54e4aec3 | 528 | * @note TIM6 is not applivable for STM32F031 devices. |
mbed_official | 130:1dec54e4aec3 | 529 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 530 | * @param NewState: new state of the TIMx peripheral Preload register |
mbed_official | 130:1dec54e4aec3 | 531 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 130:1dec54e4aec3 | 532 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 533 | */ |
mbed_official | 130:1dec54e4aec3 | 534 | void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) |
mbed_official | 130:1dec54e4aec3 | 535 | { |
mbed_official | 130:1dec54e4aec3 | 536 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 537 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 538 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 130:1dec54e4aec3 | 539 | |
mbed_official | 130:1dec54e4aec3 | 540 | if (NewState != DISABLE) |
mbed_official | 130:1dec54e4aec3 | 541 | { |
mbed_official | 130:1dec54e4aec3 | 542 | /* Set the ARR Preload Bit */ |
mbed_official | 130:1dec54e4aec3 | 543 | TIMx->CR1 |= TIM_CR1_ARPE; |
mbed_official | 130:1dec54e4aec3 | 544 | } |
mbed_official | 130:1dec54e4aec3 | 545 | else |
mbed_official | 130:1dec54e4aec3 | 546 | { |
mbed_official | 130:1dec54e4aec3 | 547 | /* Reset the ARR Preload Bit */ |
mbed_official | 130:1dec54e4aec3 | 548 | TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE); |
mbed_official | 130:1dec54e4aec3 | 549 | } |
mbed_official | 130:1dec54e4aec3 | 550 | } |
mbed_official | 130:1dec54e4aec3 | 551 | |
mbed_official | 130:1dec54e4aec3 | 552 | /** |
mbed_official | 130:1dec54e4aec3 | 553 | * @brief Selects the TIMx's One Pulse Mode. |
mbed_official | 130:1dec54e4aec3 | 554 | * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM |
mbed_official | 130:1dec54e4aec3 | 555 | * peripheral. |
mbed_official | 130:1dec54e4aec3 | 556 | * @note TIM7 is applicable only for STM32F072 devices |
mbed_official | 130:1dec54e4aec3 | 557 | * @note TIM6 is not applivable for STM32F031 devices. |
mbed_official | 130:1dec54e4aec3 | 558 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 559 | * @param TIM_OPMode: specifies the OPM Mode to be used. |
mbed_official | 130:1dec54e4aec3 | 560 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 561 | * @arg TIM_OPMode_Single |
mbed_official | 130:1dec54e4aec3 | 562 | * @arg TIM_OPMode_Repetitive |
mbed_official | 130:1dec54e4aec3 | 563 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 564 | */ |
mbed_official | 130:1dec54e4aec3 | 565 | void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) |
mbed_official | 130:1dec54e4aec3 | 566 | { |
mbed_official | 130:1dec54e4aec3 | 567 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 568 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 569 | assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); |
mbed_official | 130:1dec54e4aec3 | 570 | |
mbed_official | 130:1dec54e4aec3 | 571 | /* Reset the OPM Bit */ |
mbed_official | 130:1dec54e4aec3 | 572 | TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM); |
mbed_official | 130:1dec54e4aec3 | 573 | /* Configure the OPM Mode */ |
mbed_official | 130:1dec54e4aec3 | 574 | TIMx->CR1 |= TIM_OPMode; |
mbed_official | 130:1dec54e4aec3 | 575 | } |
mbed_official | 130:1dec54e4aec3 | 576 | |
mbed_official | 130:1dec54e4aec3 | 577 | /** |
mbed_official | 130:1dec54e4aec3 | 578 | * @brief Sets the TIMx Clock Division value. |
mbed_official | 130:1dec54e4aec3 | 579 | * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 580 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 581 | * @param TIM_CKD: specifies the clock division value. |
mbed_official | 130:1dec54e4aec3 | 582 | * This parameter can be one of the following value: |
mbed_official | 130:1dec54e4aec3 | 583 | * @arg TIM_CKD_DIV1: TDTS = Tck_tim |
mbed_official | 130:1dec54e4aec3 | 584 | * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim |
mbed_official | 130:1dec54e4aec3 | 585 | * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim |
mbed_official | 130:1dec54e4aec3 | 586 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 587 | */ |
mbed_official | 130:1dec54e4aec3 | 588 | void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) |
mbed_official | 130:1dec54e4aec3 | 589 | { |
mbed_official | 130:1dec54e4aec3 | 590 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 591 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 592 | assert_param(IS_TIM_CKD_DIV(TIM_CKD)); |
mbed_official | 130:1dec54e4aec3 | 593 | |
mbed_official | 130:1dec54e4aec3 | 594 | /* Reset the CKD Bits */ |
mbed_official | 130:1dec54e4aec3 | 595 | TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD); |
mbed_official | 130:1dec54e4aec3 | 596 | /* Set the CKD value */ |
mbed_official | 130:1dec54e4aec3 | 597 | TIMx->CR1 |= TIM_CKD; |
mbed_official | 130:1dec54e4aec3 | 598 | } |
mbed_official | 130:1dec54e4aec3 | 599 | |
mbed_official | 130:1dec54e4aec3 | 600 | /** |
mbed_official | 130:1dec54e4aec3 | 601 | * @brief Enables or disables the specified TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 602 | * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17to select the TIMx |
mbed_official | 130:1dec54e4aec3 | 603 | * peripheral. |
mbed_official | 130:1dec54e4aec3 | 604 | * @note TIM7 is applicable only for STM32F072 devices |
mbed_official | 130:1dec54e4aec3 | 605 | * @note TIM6 is not applivable for STM32F031 devices. |
mbed_official | 130:1dec54e4aec3 | 606 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 607 | * @param NewState: new state of the TIMx peripheral. |
mbed_official | 130:1dec54e4aec3 | 608 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 130:1dec54e4aec3 | 609 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 610 | */ |
mbed_official | 130:1dec54e4aec3 | 611 | void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) |
mbed_official | 130:1dec54e4aec3 | 612 | { |
mbed_official | 130:1dec54e4aec3 | 613 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 614 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 615 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 130:1dec54e4aec3 | 616 | |
mbed_official | 130:1dec54e4aec3 | 617 | if (NewState != DISABLE) |
mbed_official | 130:1dec54e4aec3 | 618 | { |
mbed_official | 130:1dec54e4aec3 | 619 | /* Enable the TIM Counter */ |
mbed_official | 130:1dec54e4aec3 | 620 | TIMx->CR1 |= TIM_CR1_CEN; |
mbed_official | 130:1dec54e4aec3 | 621 | } |
mbed_official | 130:1dec54e4aec3 | 622 | else |
mbed_official | 130:1dec54e4aec3 | 623 | { |
mbed_official | 130:1dec54e4aec3 | 624 | /* Disable the TIM Counter */ |
mbed_official | 130:1dec54e4aec3 | 625 | TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN)); |
mbed_official | 130:1dec54e4aec3 | 626 | } |
mbed_official | 130:1dec54e4aec3 | 627 | } |
mbed_official | 130:1dec54e4aec3 | 628 | |
mbed_official | 130:1dec54e4aec3 | 629 | /** |
mbed_official | 130:1dec54e4aec3 | 630 | * @} |
mbed_official | 130:1dec54e4aec3 | 631 | */ |
mbed_official | 130:1dec54e4aec3 | 632 | |
mbed_official | 130:1dec54e4aec3 | 633 | /** @defgroup TIM_Group2 Advanced-control timers (TIM1) specific features |
mbed_official | 130:1dec54e4aec3 | 634 | * @brief Advanced-control timers (TIM1) specific features |
mbed_official | 130:1dec54e4aec3 | 635 | * |
mbed_official | 130:1dec54e4aec3 | 636 | @verbatim |
mbed_official | 130:1dec54e4aec3 | 637 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 638 | ##### Advanced-control timers (TIM1) specific features ##### |
mbed_official | 130:1dec54e4aec3 | 639 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 640 | |
mbed_official | 130:1dec54e4aec3 | 641 | =================================================================== |
mbed_official | 130:1dec54e4aec3 | 642 | *** TIM Driver: how to use the Break feature *** |
mbed_official | 130:1dec54e4aec3 | 643 | =================================================================== |
mbed_official | 130:1dec54e4aec3 | 644 | [..] After configuring the Timer channel(s) in the appropriate Output Compare mode: |
mbed_official | 130:1dec54e4aec3 | 645 | |
mbed_official | 130:1dec54e4aec3 | 646 | (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer |
mbed_official | 130:1dec54e4aec3 | 647 | Break Polarity, dead time, Lock level, the OSSI/OSSR State and the |
mbed_official | 130:1dec54e4aec3 | 648 | AOE(automatic output enable). |
mbed_official | 130:1dec54e4aec3 | 649 | |
mbed_official | 130:1dec54e4aec3 | 650 | (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer |
mbed_official | 130:1dec54e4aec3 | 651 | |
mbed_official | 130:1dec54e4aec3 | 652 | (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) |
mbed_official | 130:1dec54e4aec3 | 653 | |
mbed_official | 130:1dec54e4aec3 | 654 | (#) Once the break even occurs, the Timer's output signals are put in reset |
mbed_official | 130:1dec54e4aec3 | 655 | state or in a known state (according to the configuration made in |
mbed_official | 130:1dec54e4aec3 | 656 | TIM_BDTRConfig() function). |
mbed_official | 130:1dec54e4aec3 | 657 | |
mbed_official | 130:1dec54e4aec3 | 658 | @endverbatim |
mbed_official | 130:1dec54e4aec3 | 659 | * @{ |
mbed_official | 130:1dec54e4aec3 | 660 | */ |
mbed_official | 130:1dec54e4aec3 | 661 | /** |
mbed_official | 130:1dec54e4aec3 | 662 | * @brief Configures the: Break feature, dead time, Lock level, OSSI/OSSR State |
mbed_official | 130:1dec54e4aec3 | 663 | * and the AOE(automatic output enable). |
mbed_official | 130:1dec54e4aec3 | 664 | * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM |
mbed_official | 130:1dec54e4aec3 | 665 | * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that |
mbed_official | 130:1dec54e4aec3 | 666 | * contains the BDTR Register configuration information for the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 667 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 668 | */ |
mbed_official | 130:1dec54e4aec3 | 669 | void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) |
mbed_official | 130:1dec54e4aec3 | 670 | { |
mbed_official | 130:1dec54e4aec3 | 671 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 672 | assert_param(IS_TIM_LIST2_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 673 | assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); |
mbed_official | 130:1dec54e4aec3 | 674 | assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); |
mbed_official | 130:1dec54e4aec3 | 675 | assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); |
mbed_official | 130:1dec54e4aec3 | 676 | assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); |
mbed_official | 130:1dec54e4aec3 | 677 | assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); |
mbed_official | 130:1dec54e4aec3 | 678 | assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); |
mbed_official | 130:1dec54e4aec3 | 679 | /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, |
mbed_official | 130:1dec54e4aec3 | 680 | the OSSI State, the dead time value and the Automatic Output Enable Bit */ |
mbed_official | 130:1dec54e4aec3 | 681 | TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | |
mbed_official | 130:1dec54e4aec3 | 682 | TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | |
mbed_official | 130:1dec54e4aec3 | 683 | TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | |
mbed_official | 130:1dec54e4aec3 | 684 | TIM_BDTRInitStruct->TIM_AutomaticOutput; |
mbed_official | 130:1dec54e4aec3 | 685 | } |
mbed_official | 130:1dec54e4aec3 | 686 | |
mbed_official | 130:1dec54e4aec3 | 687 | /** |
mbed_official | 130:1dec54e4aec3 | 688 | * @brief Fills each TIM_BDTRInitStruct member with its default value. |
mbed_official | 130:1dec54e4aec3 | 689 | * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which |
mbed_official | 130:1dec54e4aec3 | 690 | * will be initialized. |
mbed_official | 130:1dec54e4aec3 | 691 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 692 | */ |
mbed_official | 130:1dec54e4aec3 | 693 | void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) |
mbed_official | 130:1dec54e4aec3 | 694 | { |
mbed_official | 130:1dec54e4aec3 | 695 | /* Set the default configuration */ |
mbed_official | 130:1dec54e4aec3 | 696 | TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; |
mbed_official | 130:1dec54e4aec3 | 697 | TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; |
mbed_official | 130:1dec54e4aec3 | 698 | TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; |
mbed_official | 130:1dec54e4aec3 | 699 | TIM_BDTRInitStruct->TIM_DeadTime = 0x00; |
mbed_official | 130:1dec54e4aec3 | 700 | TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; |
mbed_official | 130:1dec54e4aec3 | 701 | TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; |
mbed_official | 130:1dec54e4aec3 | 702 | TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; |
mbed_official | 130:1dec54e4aec3 | 703 | } |
mbed_official | 130:1dec54e4aec3 | 704 | |
mbed_official | 130:1dec54e4aec3 | 705 | /** |
mbed_official | 130:1dec54e4aec3 | 706 | * @brief Enables or disables the TIM peripheral Main Outputs. |
mbed_official | 130:1dec54e4aec3 | 707 | * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIMx peripheral. |
mbed_official | 130:1dec54e4aec3 | 708 | * @param NewState: new state of the TIM peripheral Main Outputs. |
mbed_official | 130:1dec54e4aec3 | 709 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 130:1dec54e4aec3 | 710 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 711 | */ |
mbed_official | 130:1dec54e4aec3 | 712 | void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) |
mbed_official | 130:1dec54e4aec3 | 713 | { |
mbed_official | 130:1dec54e4aec3 | 714 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 715 | assert_param(IS_TIM_LIST2_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 716 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 130:1dec54e4aec3 | 717 | if (NewState != DISABLE) |
mbed_official | 130:1dec54e4aec3 | 718 | { |
mbed_official | 130:1dec54e4aec3 | 719 | /* Enable the TIM Main Output */ |
mbed_official | 130:1dec54e4aec3 | 720 | TIMx->BDTR |= TIM_BDTR_MOE; |
mbed_official | 130:1dec54e4aec3 | 721 | } |
mbed_official | 130:1dec54e4aec3 | 722 | else |
mbed_official | 130:1dec54e4aec3 | 723 | { |
mbed_official | 130:1dec54e4aec3 | 724 | /* Disable the TIM Main Output */ |
mbed_official | 130:1dec54e4aec3 | 725 | TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE)); |
mbed_official | 130:1dec54e4aec3 | 726 | } |
mbed_official | 130:1dec54e4aec3 | 727 | } |
mbed_official | 130:1dec54e4aec3 | 728 | |
mbed_official | 130:1dec54e4aec3 | 729 | /** |
mbed_official | 130:1dec54e4aec3 | 730 | * @} |
mbed_official | 130:1dec54e4aec3 | 731 | */ |
mbed_official | 130:1dec54e4aec3 | 732 | |
mbed_official | 130:1dec54e4aec3 | 733 | /** @defgroup TIM_Group3 Output Compare management functions |
mbed_official | 130:1dec54e4aec3 | 734 | * @brief Output Compare management functions |
mbed_official | 130:1dec54e4aec3 | 735 | * |
mbed_official | 130:1dec54e4aec3 | 736 | @verbatim |
mbed_official | 130:1dec54e4aec3 | 737 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 738 | ##### Output Compare management functions ##### |
mbed_official | 130:1dec54e4aec3 | 739 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 740 | *** TIM Driver: how to use it in Output Compare Mode *** |
mbed_official | 130:1dec54e4aec3 | 741 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 742 | [..] To use the Timer in Output Compare mode, the following steps are mandatory: |
mbed_official | 130:1dec54e4aec3 | 743 | (#) Enable TIM clock using |
mbed_official | 130:1dec54e4aec3 | 744 | RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function. |
mbed_official | 130:1dec54e4aec3 | 745 | (#) Configure the TIM pins by configuring the corresponding GPIO pins |
mbed_official | 130:1dec54e4aec3 | 746 | (#) Configure the Time base unit as described in the first part of this |
mbed_official | 130:1dec54e4aec3 | 747 | driver, if needed, else the Timer will run with the default |
mbed_official | 130:1dec54e4aec3 | 748 | configuration: |
mbed_official | 130:1dec54e4aec3 | 749 | (++) Autoreload value = 0xFFFF. |
mbed_official | 130:1dec54e4aec3 | 750 | (++) Prescaler value = 0x0000. |
mbed_official | 130:1dec54e4aec3 | 751 | (++) Counter mode = Up counting. |
mbed_official | 130:1dec54e4aec3 | 752 | (++) Clock Division = TIM_CKD_DIV1. |
mbed_official | 130:1dec54e4aec3 | 753 | (#) Fill the TIM_OCInitStruct with the desired parameters including: |
mbed_official | 130:1dec54e4aec3 | 754 | (++) The TIM Output Compare mode: TIM_OCMode. |
mbed_official | 130:1dec54e4aec3 | 755 | (++) TIM Output State: TIM_OutputState. |
mbed_official | 130:1dec54e4aec3 | 756 | (++) TIM Pulse value: TIM_Pulse. |
mbed_official | 130:1dec54e4aec3 | 757 | (++) TIM Output Compare Polarity : TIM_OCPolarity. |
mbed_official | 130:1dec54e4aec3 | 758 | (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired |
mbed_official | 130:1dec54e4aec3 | 759 | channel with the corresponding configuration. |
mbed_official | 130:1dec54e4aec3 | 760 | (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. |
mbed_official | 130:1dec54e4aec3 | 761 | [..] |
mbed_official | 130:1dec54e4aec3 | 762 | (@) All other functions can be used separately to modify, if needed, |
mbed_official | 130:1dec54e4aec3 | 763 | a specific feature of the Timer. |
mbed_official | 130:1dec54e4aec3 | 764 | (@) In case of PWM mode, this function is mandatory: |
mbed_official | 130:1dec54e4aec3 | 765 | TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE). |
mbed_official | 130:1dec54e4aec3 | 766 | (@) If the corresponding interrupt or DMA request are needed, the user should: |
mbed_official | 130:1dec54e4aec3 | 767 | (#@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). |
mbed_official | 130:1dec54e4aec3 | 768 | (#@) Enable the corresponding interrupt (or DMA request) using the function |
mbed_official | 130:1dec54e4aec3 | 769 | TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)). |
mbed_official | 130:1dec54e4aec3 | 770 | |
mbed_official | 130:1dec54e4aec3 | 771 | @endverbatim |
mbed_official | 130:1dec54e4aec3 | 772 | * @{ |
mbed_official | 130:1dec54e4aec3 | 773 | */ |
mbed_official | 130:1dec54e4aec3 | 774 | |
mbed_official | 130:1dec54e4aec3 | 775 | /** |
mbed_official | 130:1dec54e4aec3 | 776 | * @brief Initializes the TIMx Channel1 according to the specified |
mbed_official | 130:1dec54e4aec3 | 777 | * parameters in the TIM_OCInitStruct. |
mbed_official | 130:1dec54e4aec3 | 778 | * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 779 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 780 | * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure |
mbed_official | 130:1dec54e4aec3 | 781 | * that contains the configuration information for the specified TIM |
mbed_official | 130:1dec54e4aec3 | 782 | * peripheral. |
mbed_official | 130:1dec54e4aec3 | 783 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 784 | */ |
mbed_official | 130:1dec54e4aec3 | 785 | void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) |
mbed_official | 130:1dec54e4aec3 | 786 | { |
mbed_official | 130:1dec54e4aec3 | 787 | uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; |
mbed_official | 130:1dec54e4aec3 | 788 | |
mbed_official | 130:1dec54e4aec3 | 789 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 790 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 791 | assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); |
mbed_official | 130:1dec54e4aec3 | 792 | assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); |
mbed_official | 130:1dec54e4aec3 | 793 | assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); |
mbed_official | 130:1dec54e4aec3 | 794 | /* Disable the Channel 1: Reset the CC1E Bit */ |
mbed_official | 130:1dec54e4aec3 | 795 | TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E); |
mbed_official | 130:1dec54e4aec3 | 796 | /* Get the TIMx CCER register value */ |
mbed_official | 130:1dec54e4aec3 | 797 | tmpccer = TIMx->CCER; |
mbed_official | 130:1dec54e4aec3 | 798 | /* Get the TIMx CR2 register value */ |
mbed_official | 130:1dec54e4aec3 | 799 | tmpcr2 = TIMx->CR2; |
mbed_official | 130:1dec54e4aec3 | 800 | |
mbed_official | 130:1dec54e4aec3 | 801 | /* Get the TIMx CCMR1 register value */ |
mbed_official | 130:1dec54e4aec3 | 802 | tmpccmrx = TIMx->CCMR1; |
mbed_official | 130:1dec54e4aec3 | 803 | |
mbed_official | 130:1dec54e4aec3 | 804 | /* Reset the Output Compare Mode Bits */ |
mbed_official | 130:1dec54e4aec3 | 805 | tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M)); |
mbed_official | 130:1dec54e4aec3 | 806 | tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S)); |
mbed_official | 130:1dec54e4aec3 | 807 | |
mbed_official | 130:1dec54e4aec3 | 808 | /* Select the Output Compare Mode */ |
mbed_official | 130:1dec54e4aec3 | 809 | tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; |
mbed_official | 130:1dec54e4aec3 | 810 | |
mbed_official | 130:1dec54e4aec3 | 811 | /* Reset the Output Polarity level */ |
mbed_official | 130:1dec54e4aec3 | 812 | tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P)); |
mbed_official | 130:1dec54e4aec3 | 813 | /* Set the Output Compare Polarity */ |
mbed_official | 130:1dec54e4aec3 | 814 | tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; |
mbed_official | 130:1dec54e4aec3 | 815 | |
mbed_official | 130:1dec54e4aec3 | 816 | /* Set the Output State */ |
mbed_official | 130:1dec54e4aec3 | 817 | tmpccer |= TIM_OCInitStruct->TIM_OutputState; |
mbed_official | 130:1dec54e4aec3 | 818 | |
mbed_official | 130:1dec54e4aec3 | 819 | if((TIMx == TIM1) || (TIMx == TIM15) || (TIMx == TIM16) || (TIMx == TIM17)) |
mbed_official | 130:1dec54e4aec3 | 820 | { |
mbed_official | 130:1dec54e4aec3 | 821 | assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); |
mbed_official | 130:1dec54e4aec3 | 822 | assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); |
mbed_official | 130:1dec54e4aec3 | 823 | assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); |
mbed_official | 130:1dec54e4aec3 | 824 | assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); |
mbed_official | 130:1dec54e4aec3 | 825 | |
mbed_official | 130:1dec54e4aec3 | 826 | /* Reset the Output N Polarity level */ |
mbed_official | 130:1dec54e4aec3 | 827 | tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP)); |
mbed_official | 130:1dec54e4aec3 | 828 | /* Set the Output N Polarity */ |
mbed_official | 130:1dec54e4aec3 | 829 | tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; |
mbed_official | 130:1dec54e4aec3 | 830 | |
mbed_official | 130:1dec54e4aec3 | 831 | /* Reset the Output N State */ |
mbed_official | 130:1dec54e4aec3 | 832 | tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE)); |
mbed_official | 130:1dec54e4aec3 | 833 | /* Set the Output N State */ |
mbed_official | 130:1dec54e4aec3 | 834 | tmpccer |= TIM_OCInitStruct->TIM_OutputNState; |
mbed_official | 130:1dec54e4aec3 | 835 | |
mbed_official | 130:1dec54e4aec3 | 836 | /* Reset the Ouput Compare and Output Compare N IDLE State */ |
mbed_official | 130:1dec54e4aec3 | 837 | tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1)); |
mbed_official | 130:1dec54e4aec3 | 838 | tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N)); |
mbed_official | 130:1dec54e4aec3 | 839 | |
mbed_official | 130:1dec54e4aec3 | 840 | /* Set the Output Idle state */ |
mbed_official | 130:1dec54e4aec3 | 841 | tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; |
mbed_official | 130:1dec54e4aec3 | 842 | /* Set the Output N Idle state */ |
mbed_official | 130:1dec54e4aec3 | 843 | tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; |
mbed_official | 130:1dec54e4aec3 | 844 | } |
mbed_official | 130:1dec54e4aec3 | 845 | /* Write to TIMx CR2 */ |
mbed_official | 130:1dec54e4aec3 | 846 | TIMx->CR2 = tmpcr2; |
mbed_official | 130:1dec54e4aec3 | 847 | |
mbed_official | 130:1dec54e4aec3 | 848 | /* Write to TIMx CCMR1 */ |
mbed_official | 130:1dec54e4aec3 | 849 | TIMx->CCMR1 = tmpccmrx; |
mbed_official | 130:1dec54e4aec3 | 850 | |
mbed_official | 130:1dec54e4aec3 | 851 | /* Set the Capture Compare Register value */ |
mbed_official | 130:1dec54e4aec3 | 852 | TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; |
mbed_official | 130:1dec54e4aec3 | 853 | |
mbed_official | 130:1dec54e4aec3 | 854 | /* Write to TIMx CCER */ |
mbed_official | 130:1dec54e4aec3 | 855 | TIMx->CCER = tmpccer; |
mbed_official | 130:1dec54e4aec3 | 856 | } |
mbed_official | 130:1dec54e4aec3 | 857 | |
mbed_official | 130:1dec54e4aec3 | 858 | /** |
mbed_official | 130:1dec54e4aec3 | 859 | * @brief Initializes the TIMx Channel2 according to the specified |
mbed_official | 130:1dec54e4aec3 | 860 | * parameters in the TIM_OCInitStruct. |
mbed_official | 130:1dec54e4aec3 | 861 | * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 862 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 863 | * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure |
mbed_official | 130:1dec54e4aec3 | 864 | * that contains the configuration information for the specified TIM |
mbed_official | 130:1dec54e4aec3 | 865 | * peripheral. |
mbed_official | 130:1dec54e4aec3 | 866 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 867 | */ |
mbed_official | 130:1dec54e4aec3 | 868 | void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) |
mbed_official | 130:1dec54e4aec3 | 869 | { |
mbed_official | 130:1dec54e4aec3 | 870 | uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; |
mbed_official | 130:1dec54e4aec3 | 871 | |
mbed_official | 130:1dec54e4aec3 | 872 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 873 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 874 | assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); |
mbed_official | 130:1dec54e4aec3 | 875 | assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); |
mbed_official | 130:1dec54e4aec3 | 876 | assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); |
mbed_official | 130:1dec54e4aec3 | 877 | /* Disable the Channel 2: Reset the CC2E Bit */ |
mbed_official | 130:1dec54e4aec3 | 878 | TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E)); |
mbed_official | 130:1dec54e4aec3 | 879 | |
mbed_official | 130:1dec54e4aec3 | 880 | /* Get the TIMx CCER register value */ |
mbed_official | 130:1dec54e4aec3 | 881 | tmpccer = TIMx->CCER; |
mbed_official | 130:1dec54e4aec3 | 882 | /* Get the TIMx CR2 register value */ |
mbed_official | 130:1dec54e4aec3 | 883 | tmpcr2 = TIMx->CR2; |
mbed_official | 130:1dec54e4aec3 | 884 | |
mbed_official | 130:1dec54e4aec3 | 885 | /* Get the TIMx CCMR1 register value */ |
mbed_official | 130:1dec54e4aec3 | 886 | tmpccmrx = TIMx->CCMR1; |
mbed_official | 130:1dec54e4aec3 | 887 | |
mbed_official | 130:1dec54e4aec3 | 888 | /* Reset the Output Compare mode and Capture/Compare selection Bits */ |
mbed_official | 130:1dec54e4aec3 | 889 | tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M)); |
mbed_official | 130:1dec54e4aec3 | 890 | tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)); |
mbed_official | 130:1dec54e4aec3 | 891 | |
mbed_official | 130:1dec54e4aec3 | 892 | /* Select the Output Compare Mode */ |
mbed_official | 130:1dec54e4aec3 | 893 | tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); |
mbed_official | 130:1dec54e4aec3 | 894 | |
mbed_official | 130:1dec54e4aec3 | 895 | /* Reset the Output Polarity level */ |
mbed_official | 130:1dec54e4aec3 | 896 | tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P)); |
mbed_official | 130:1dec54e4aec3 | 897 | /* Set the Output Compare Polarity */ |
mbed_official | 130:1dec54e4aec3 | 898 | tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); |
mbed_official | 130:1dec54e4aec3 | 899 | |
mbed_official | 130:1dec54e4aec3 | 900 | /* Set the Output State */ |
mbed_official | 130:1dec54e4aec3 | 901 | tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); |
mbed_official | 130:1dec54e4aec3 | 902 | |
mbed_official | 130:1dec54e4aec3 | 903 | if((TIMx == TIM1) || (TIMx == TIM15)) |
mbed_official | 130:1dec54e4aec3 | 904 | { |
mbed_official | 130:1dec54e4aec3 | 905 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 906 | assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); |
mbed_official | 130:1dec54e4aec3 | 907 | |
mbed_official | 130:1dec54e4aec3 | 908 | /* Reset the Ouput Compare State */ |
mbed_official | 130:1dec54e4aec3 | 909 | tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2)); |
mbed_official | 130:1dec54e4aec3 | 910 | |
mbed_official | 130:1dec54e4aec3 | 911 | /* Set the Output Idle state */ |
mbed_official | 130:1dec54e4aec3 | 912 | tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); |
mbed_official | 130:1dec54e4aec3 | 913 | |
mbed_official | 130:1dec54e4aec3 | 914 | if (TIMx == TIM1) |
mbed_official | 130:1dec54e4aec3 | 915 | { |
mbed_official | 130:1dec54e4aec3 | 916 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 917 | assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); |
mbed_official | 130:1dec54e4aec3 | 918 | assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); |
mbed_official | 130:1dec54e4aec3 | 919 | assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); |
mbed_official | 130:1dec54e4aec3 | 920 | |
mbed_official | 130:1dec54e4aec3 | 921 | /* Reset the Output N Polarity level */ |
mbed_official | 130:1dec54e4aec3 | 922 | tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP)); |
mbed_official | 130:1dec54e4aec3 | 923 | /* Set the Output N Polarity */ |
mbed_official | 130:1dec54e4aec3 | 924 | tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); |
mbed_official | 130:1dec54e4aec3 | 925 | |
mbed_official | 130:1dec54e4aec3 | 926 | /* Reset the Output N State */ |
mbed_official | 130:1dec54e4aec3 | 927 | tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); |
mbed_official | 130:1dec54e4aec3 | 928 | /* Set the Output N State */ |
mbed_official | 130:1dec54e4aec3 | 929 | tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); |
mbed_official | 130:1dec54e4aec3 | 930 | |
mbed_official | 130:1dec54e4aec3 | 931 | /* Reset the Output Compare N IDLE State */ |
mbed_official | 130:1dec54e4aec3 | 932 | tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N)); |
mbed_official | 130:1dec54e4aec3 | 933 | |
mbed_official | 130:1dec54e4aec3 | 934 | /* Set the Output N Idle state */ |
mbed_official | 130:1dec54e4aec3 | 935 | tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); |
mbed_official | 130:1dec54e4aec3 | 936 | } |
mbed_official | 130:1dec54e4aec3 | 937 | } |
mbed_official | 130:1dec54e4aec3 | 938 | /* Write to TIMx CR2 */ |
mbed_official | 130:1dec54e4aec3 | 939 | TIMx->CR2 = tmpcr2; |
mbed_official | 130:1dec54e4aec3 | 940 | |
mbed_official | 130:1dec54e4aec3 | 941 | /* Write to TIMx CCMR1 */ |
mbed_official | 130:1dec54e4aec3 | 942 | TIMx->CCMR1 = tmpccmrx; |
mbed_official | 130:1dec54e4aec3 | 943 | |
mbed_official | 130:1dec54e4aec3 | 944 | /* Set the Capture Compare Register value */ |
mbed_official | 130:1dec54e4aec3 | 945 | TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; |
mbed_official | 130:1dec54e4aec3 | 946 | |
mbed_official | 130:1dec54e4aec3 | 947 | /* Write to TIMx CCER */ |
mbed_official | 130:1dec54e4aec3 | 948 | TIMx->CCER = tmpccer; |
mbed_official | 130:1dec54e4aec3 | 949 | } |
mbed_official | 130:1dec54e4aec3 | 950 | |
mbed_official | 130:1dec54e4aec3 | 951 | /** |
mbed_official | 130:1dec54e4aec3 | 952 | * @brief Initializes the TIMx Channel3 according to the specified |
mbed_official | 130:1dec54e4aec3 | 953 | * parameters in the TIM_OCInitStruct. |
mbed_official | 130:1dec54e4aec3 | 954 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 955 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 956 | * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure |
mbed_official | 130:1dec54e4aec3 | 957 | * that contains the configuration information for the specified TIM |
mbed_official | 130:1dec54e4aec3 | 958 | * peripheral. |
mbed_official | 130:1dec54e4aec3 | 959 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 960 | */ |
mbed_official | 130:1dec54e4aec3 | 961 | void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) |
mbed_official | 130:1dec54e4aec3 | 962 | { |
mbed_official | 130:1dec54e4aec3 | 963 | uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; |
mbed_official | 130:1dec54e4aec3 | 964 | |
mbed_official | 130:1dec54e4aec3 | 965 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 966 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 967 | assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); |
mbed_official | 130:1dec54e4aec3 | 968 | assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); |
mbed_official | 130:1dec54e4aec3 | 969 | assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); |
mbed_official | 130:1dec54e4aec3 | 970 | /* Disable the Channel 2: Reset the CC2E Bit */ |
mbed_official | 130:1dec54e4aec3 | 971 | TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E)); |
mbed_official | 130:1dec54e4aec3 | 972 | |
mbed_official | 130:1dec54e4aec3 | 973 | /* Get the TIMx CCER register value */ |
mbed_official | 130:1dec54e4aec3 | 974 | tmpccer = TIMx->CCER; |
mbed_official | 130:1dec54e4aec3 | 975 | /* Get the TIMx CR2 register value */ |
mbed_official | 130:1dec54e4aec3 | 976 | tmpcr2 = TIMx->CR2; |
mbed_official | 130:1dec54e4aec3 | 977 | |
mbed_official | 130:1dec54e4aec3 | 978 | /* Get the TIMx CCMR2 register value */ |
mbed_official | 130:1dec54e4aec3 | 979 | tmpccmrx = TIMx->CCMR2; |
mbed_official | 130:1dec54e4aec3 | 980 | |
mbed_official | 130:1dec54e4aec3 | 981 | /* Reset the Output Compare mode and Capture/Compare selection Bits */ |
mbed_official | 130:1dec54e4aec3 | 982 | tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M)); |
mbed_official | 130:1dec54e4aec3 | 983 | tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); |
mbed_official | 130:1dec54e4aec3 | 984 | /* Select the Output Compare Mode */ |
mbed_official | 130:1dec54e4aec3 | 985 | tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; |
mbed_official | 130:1dec54e4aec3 | 986 | |
mbed_official | 130:1dec54e4aec3 | 987 | /* Reset the Output Polarity level */ |
mbed_official | 130:1dec54e4aec3 | 988 | tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P)); |
mbed_official | 130:1dec54e4aec3 | 989 | /* Set the Output Compare Polarity */ |
mbed_official | 130:1dec54e4aec3 | 990 | tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); |
mbed_official | 130:1dec54e4aec3 | 991 | |
mbed_official | 130:1dec54e4aec3 | 992 | /* Set the Output State */ |
mbed_official | 130:1dec54e4aec3 | 993 | tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); |
mbed_official | 130:1dec54e4aec3 | 994 | |
mbed_official | 130:1dec54e4aec3 | 995 | if(TIMx == TIM1) |
mbed_official | 130:1dec54e4aec3 | 996 | { |
mbed_official | 130:1dec54e4aec3 | 997 | assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); |
mbed_official | 130:1dec54e4aec3 | 998 | assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); |
mbed_official | 130:1dec54e4aec3 | 999 | assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); |
mbed_official | 130:1dec54e4aec3 | 1000 | assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); |
mbed_official | 130:1dec54e4aec3 | 1001 | |
mbed_official | 130:1dec54e4aec3 | 1002 | /* Reset the Output N Polarity level */ |
mbed_official | 130:1dec54e4aec3 | 1003 | tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP)); |
mbed_official | 130:1dec54e4aec3 | 1004 | /* Set the Output N Polarity */ |
mbed_official | 130:1dec54e4aec3 | 1005 | tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); |
mbed_official | 130:1dec54e4aec3 | 1006 | /* Reset the Output N State */ |
mbed_official | 130:1dec54e4aec3 | 1007 | tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE)); |
mbed_official | 130:1dec54e4aec3 | 1008 | |
mbed_official | 130:1dec54e4aec3 | 1009 | /* Set the Output N State */ |
mbed_official | 130:1dec54e4aec3 | 1010 | tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); |
mbed_official | 130:1dec54e4aec3 | 1011 | /* Reset the Ouput Compare and Output Compare N IDLE State */ |
mbed_official | 130:1dec54e4aec3 | 1012 | tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3)); |
mbed_official | 130:1dec54e4aec3 | 1013 | tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N)); |
mbed_official | 130:1dec54e4aec3 | 1014 | /* Set the Output Idle state */ |
mbed_official | 130:1dec54e4aec3 | 1015 | tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); |
mbed_official | 130:1dec54e4aec3 | 1016 | /* Set the Output N Idle state */ |
mbed_official | 130:1dec54e4aec3 | 1017 | tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); |
mbed_official | 130:1dec54e4aec3 | 1018 | } |
mbed_official | 130:1dec54e4aec3 | 1019 | /* Write to TIMx CR2 */ |
mbed_official | 130:1dec54e4aec3 | 1020 | TIMx->CR2 = tmpcr2; |
mbed_official | 130:1dec54e4aec3 | 1021 | |
mbed_official | 130:1dec54e4aec3 | 1022 | /* Write to TIMx CCMR2 */ |
mbed_official | 130:1dec54e4aec3 | 1023 | TIMx->CCMR2 = tmpccmrx; |
mbed_official | 130:1dec54e4aec3 | 1024 | |
mbed_official | 130:1dec54e4aec3 | 1025 | /* Set the Capture Compare Register value */ |
mbed_official | 130:1dec54e4aec3 | 1026 | TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; |
mbed_official | 130:1dec54e4aec3 | 1027 | |
mbed_official | 130:1dec54e4aec3 | 1028 | /* Write to TIMx CCER */ |
mbed_official | 130:1dec54e4aec3 | 1029 | TIMx->CCER = tmpccer; |
mbed_official | 130:1dec54e4aec3 | 1030 | } |
mbed_official | 130:1dec54e4aec3 | 1031 | |
mbed_official | 130:1dec54e4aec3 | 1032 | /** |
mbed_official | 130:1dec54e4aec3 | 1033 | * @brief Initializes the TIMx Channel4 according to the specified |
mbed_official | 130:1dec54e4aec3 | 1034 | * parameters in the TIM_OCInitStruct. |
mbed_official | 130:1dec54e4aec3 | 1035 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1036 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1037 | * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure |
mbed_official | 130:1dec54e4aec3 | 1038 | * that contains the configuration information for the specified TIM |
mbed_official | 130:1dec54e4aec3 | 1039 | * peripheral. |
mbed_official | 130:1dec54e4aec3 | 1040 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1041 | */ |
mbed_official | 130:1dec54e4aec3 | 1042 | void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) |
mbed_official | 130:1dec54e4aec3 | 1043 | { |
mbed_official | 130:1dec54e4aec3 | 1044 | uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; |
mbed_official | 130:1dec54e4aec3 | 1045 | |
mbed_official | 130:1dec54e4aec3 | 1046 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1047 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1048 | assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); |
mbed_official | 130:1dec54e4aec3 | 1049 | assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); |
mbed_official | 130:1dec54e4aec3 | 1050 | assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); |
mbed_official | 130:1dec54e4aec3 | 1051 | /* Disable the Channel 2: Reset the CC4E Bit */ |
mbed_official | 130:1dec54e4aec3 | 1052 | TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E)); |
mbed_official | 130:1dec54e4aec3 | 1053 | |
mbed_official | 130:1dec54e4aec3 | 1054 | /* Get the TIMx CCER register value */ |
mbed_official | 130:1dec54e4aec3 | 1055 | tmpccer = TIMx->CCER; |
mbed_official | 130:1dec54e4aec3 | 1056 | /* Get the TIMx CR2 register value */ |
mbed_official | 130:1dec54e4aec3 | 1057 | tmpcr2 = TIMx->CR2; |
mbed_official | 130:1dec54e4aec3 | 1058 | |
mbed_official | 130:1dec54e4aec3 | 1059 | /* Get the TIMx CCMR2 register value */ |
mbed_official | 130:1dec54e4aec3 | 1060 | tmpccmrx = TIMx->CCMR2; |
mbed_official | 130:1dec54e4aec3 | 1061 | |
mbed_official | 130:1dec54e4aec3 | 1062 | /* Reset the Output Compare mode and Capture/Compare selection Bits */ |
mbed_official | 130:1dec54e4aec3 | 1063 | tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M)); |
mbed_official | 130:1dec54e4aec3 | 1064 | tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S)); |
mbed_official | 130:1dec54e4aec3 | 1065 | |
mbed_official | 130:1dec54e4aec3 | 1066 | /* Select the Output Compare Mode */ |
mbed_official | 130:1dec54e4aec3 | 1067 | tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); |
mbed_official | 130:1dec54e4aec3 | 1068 | |
mbed_official | 130:1dec54e4aec3 | 1069 | /* Reset the Output Polarity level */ |
mbed_official | 130:1dec54e4aec3 | 1070 | tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P)); |
mbed_official | 130:1dec54e4aec3 | 1071 | /* Set the Output Compare Polarity */ |
mbed_official | 130:1dec54e4aec3 | 1072 | tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); |
mbed_official | 130:1dec54e4aec3 | 1073 | |
mbed_official | 130:1dec54e4aec3 | 1074 | /* Set the Output State */ |
mbed_official | 130:1dec54e4aec3 | 1075 | tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); |
mbed_official | 130:1dec54e4aec3 | 1076 | |
mbed_official | 130:1dec54e4aec3 | 1077 | if(TIMx == TIM1) |
mbed_official | 130:1dec54e4aec3 | 1078 | { |
mbed_official | 130:1dec54e4aec3 | 1079 | assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); |
mbed_official | 130:1dec54e4aec3 | 1080 | /* Reset the Ouput Compare IDLE State */ |
mbed_official | 130:1dec54e4aec3 | 1081 | tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4)); |
mbed_official | 130:1dec54e4aec3 | 1082 | /* Set the Output Idle state */ |
mbed_official | 130:1dec54e4aec3 | 1083 | tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); |
mbed_official | 130:1dec54e4aec3 | 1084 | } |
mbed_official | 130:1dec54e4aec3 | 1085 | /* Write to TIMx CR2 */ |
mbed_official | 130:1dec54e4aec3 | 1086 | TIMx->CR2 = tmpcr2; |
mbed_official | 130:1dec54e4aec3 | 1087 | |
mbed_official | 130:1dec54e4aec3 | 1088 | /* Write to TIMx CCMR2 */ |
mbed_official | 130:1dec54e4aec3 | 1089 | TIMx->CCMR2 = tmpccmrx; |
mbed_official | 130:1dec54e4aec3 | 1090 | |
mbed_official | 130:1dec54e4aec3 | 1091 | /* Set the Capture Compare Register value */ |
mbed_official | 130:1dec54e4aec3 | 1092 | TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; |
mbed_official | 130:1dec54e4aec3 | 1093 | |
mbed_official | 130:1dec54e4aec3 | 1094 | /* Write to TIMx CCER */ |
mbed_official | 130:1dec54e4aec3 | 1095 | TIMx->CCER = tmpccer; |
mbed_official | 130:1dec54e4aec3 | 1096 | } |
mbed_official | 130:1dec54e4aec3 | 1097 | |
mbed_official | 130:1dec54e4aec3 | 1098 | /** |
mbed_official | 130:1dec54e4aec3 | 1099 | * @brief Fills each TIM_OCInitStruct member with its default value. |
mbed_official | 130:1dec54e4aec3 | 1100 | * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will |
mbed_official | 130:1dec54e4aec3 | 1101 | * be initialized. |
mbed_official | 130:1dec54e4aec3 | 1102 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1103 | */ |
mbed_official | 130:1dec54e4aec3 | 1104 | void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) |
mbed_official | 130:1dec54e4aec3 | 1105 | { |
mbed_official | 130:1dec54e4aec3 | 1106 | /* Set the default configuration */ |
mbed_official | 130:1dec54e4aec3 | 1107 | TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; |
mbed_official | 130:1dec54e4aec3 | 1108 | TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; |
mbed_official | 130:1dec54e4aec3 | 1109 | TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; |
mbed_official | 130:1dec54e4aec3 | 1110 | TIM_OCInitStruct->TIM_Pulse = 0x0000000; |
mbed_official | 130:1dec54e4aec3 | 1111 | TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; |
mbed_official | 130:1dec54e4aec3 | 1112 | TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; |
mbed_official | 130:1dec54e4aec3 | 1113 | TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; |
mbed_official | 130:1dec54e4aec3 | 1114 | TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; |
mbed_official | 130:1dec54e4aec3 | 1115 | } |
mbed_official | 130:1dec54e4aec3 | 1116 | |
mbed_official | 130:1dec54e4aec3 | 1117 | /** |
mbed_official | 130:1dec54e4aec3 | 1118 | * @brief Selects the TIM Output Compare Mode. |
mbed_official | 130:1dec54e4aec3 | 1119 | * @note This function disables the selected channel before changing the Output |
mbed_official | 130:1dec54e4aec3 | 1120 | * Compare Mode. |
mbed_official | 130:1dec54e4aec3 | 1121 | * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. |
mbed_official | 130:1dec54e4aec3 | 1122 | * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1123 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1124 | * @param TIM_Channel: specifies the TIM Channel |
mbed_official | 130:1dec54e4aec3 | 1125 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1126 | * @arg TIM_Channel_1: TIM Channel 1 |
mbed_official | 130:1dec54e4aec3 | 1127 | * @arg TIM_Channel_2: TIM Channel 2 |
mbed_official | 130:1dec54e4aec3 | 1128 | * @arg TIM_Channel_3: TIM Channel 3 |
mbed_official | 130:1dec54e4aec3 | 1129 | * @arg TIM_Channel_4: TIM Channel 4 |
mbed_official | 130:1dec54e4aec3 | 1130 | * @param TIM_OCMode: specifies the TIM Output Compare Mode. |
mbed_official | 130:1dec54e4aec3 | 1131 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1132 | * @arg TIM_OCMode_Timing |
mbed_official | 130:1dec54e4aec3 | 1133 | * @arg TIM_OCMode_Active |
mbed_official | 130:1dec54e4aec3 | 1134 | * @arg TIM_OCMode_Toggle |
mbed_official | 130:1dec54e4aec3 | 1135 | * @arg TIM_OCMode_PWM1 |
mbed_official | 130:1dec54e4aec3 | 1136 | * @arg TIM_OCMode_PWM2 |
mbed_official | 130:1dec54e4aec3 | 1137 | * @arg TIM_ForcedAction_Active |
mbed_official | 130:1dec54e4aec3 | 1138 | * @arg TIM_ForcedAction_InActive |
mbed_official | 130:1dec54e4aec3 | 1139 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1140 | */ |
mbed_official | 130:1dec54e4aec3 | 1141 | void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) |
mbed_official | 130:1dec54e4aec3 | 1142 | { |
mbed_official | 130:1dec54e4aec3 | 1143 | uint32_t tmp = 0; |
mbed_official | 130:1dec54e4aec3 | 1144 | uint16_t tmp1 = 0; |
mbed_official | 130:1dec54e4aec3 | 1145 | |
mbed_official | 130:1dec54e4aec3 | 1146 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1147 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1148 | assert_param(IS_TIM_OCM(TIM_OCMode)); |
mbed_official | 130:1dec54e4aec3 | 1149 | |
mbed_official | 130:1dec54e4aec3 | 1150 | tmp = (uint32_t) TIMx; |
mbed_official | 130:1dec54e4aec3 | 1151 | tmp += CCMR_OFFSET; |
mbed_official | 130:1dec54e4aec3 | 1152 | |
mbed_official | 130:1dec54e4aec3 | 1153 | tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel; |
mbed_official | 130:1dec54e4aec3 | 1154 | |
mbed_official | 130:1dec54e4aec3 | 1155 | /* Disable the Channel: Reset the CCxE Bit */ |
mbed_official | 130:1dec54e4aec3 | 1156 | TIMx->CCER &= (uint16_t) ~tmp1; |
mbed_official | 130:1dec54e4aec3 | 1157 | |
mbed_official | 130:1dec54e4aec3 | 1158 | if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) |
mbed_official | 130:1dec54e4aec3 | 1159 | { |
mbed_official | 130:1dec54e4aec3 | 1160 | tmp += (TIM_Channel>>1); |
mbed_official | 130:1dec54e4aec3 | 1161 | |
mbed_official | 130:1dec54e4aec3 | 1162 | /* Reset the OCxM bits in the CCMRx register */ |
mbed_official | 130:1dec54e4aec3 | 1163 | *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); |
mbed_official | 130:1dec54e4aec3 | 1164 | |
mbed_official | 130:1dec54e4aec3 | 1165 | /* Configure the OCxM bits in the CCMRx register */ |
mbed_official | 130:1dec54e4aec3 | 1166 | *(__IO uint32_t *) tmp |= TIM_OCMode; |
mbed_official | 130:1dec54e4aec3 | 1167 | } |
mbed_official | 130:1dec54e4aec3 | 1168 | else |
mbed_official | 130:1dec54e4aec3 | 1169 | { |
mbed_official | 130:1dec54e4aec3 | 1170 | tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; |
mbed_official | 130:1dec54e4aec3 | 1171 | |
mbed_official | 130:1dec54e4aec3 | 1172 | /* Reset the OCxM bits in the CCMRx register */ |
mbed_official | 130:1dec54e4aec3 | 1173 | *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M); |
mbed_official | 130:1dec54e4aec3 | 1174 | |
mbed_official | 130:1dec54e4aec3 | 1175 | /* Configure the OCxM bits in the CCMRx register */ |
mbed_official | 130:1dec54e4aec3 | 1176 | *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); |
mbed_official | 130:1dec54e4aec3 | 1177 | } |
mbed_official | 130:1dec54e4aec3 | 1178 | } |
mbed_official | 130:1dec54e4aec3 | 1179 | |
mbed_official | 130:1dec54e4aec3 | 1180 | /** |
mbed_official | 130:1dec54e4aec3 | 1181 | * @brief Sets the TIMx Capture Compare1 Register value |
mbed_official | 130:1dec54e4aec3 | 1182 | * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1183 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1184 | * @param Compare1: specifies the Capture Compare1 register new value. |
mbed_official | 130:1dec54e4aec3 | 1185 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1186 | */ |
mbed_official | 130:1dec54e4aec3 | 1187 | void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) |
mbed_official | 130:1dec54e4aec3 | 1188 | { |
mbed_official | 130:1dec54e4aec3 | 1189 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1190 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1191 | |
mbed_official | 130:1dec54e4aec3 | 1192 | /* Set the Capture Compare1 Register value */ |
mbed_official | 130:1dec54e4aec3 | 1193 | TIMx->CCR1 = Compare1; |
mbed_official | 130:1dec54e4aec3 | 1194 | } |
mbed_official | 130:1dec54e4aec3 | 1195 | |
mbed_official | 130:1dec54e4aec3 | 1196 | /** |
mbed_official | 130:1dec54e4aec3 | 1197 | * @brief Sets the TIMx Capture Compare2 Register value |
mbed_official | 130:1dec54e4aec3 | 1198 | * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1199 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1200 | * @param Compare2: specifies the Capture Compare2 register new value. |
mbed_official | 130:1dec54e4aec3 | 1201 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1202 | */ |
mbed_official | 130:1dec54e4aec3 | 1203 | void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2) |
mbed_official | 130:1dec54e4aec3 | 1204 | { |
mbed_official | 130:1dec54e4aec3 | 1205 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1206 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1207 | |
mbed_official | 130:1dec54e4aec3 | 1208 | /* Set the Capture Compare2 Register value */ |
mbed_official | 130:1dec54e4aec3 | 1209 | TIMx->CCR2 = Compare2; |
mbed_official | 130:1dec54e4aec3 | 1210 | } |
mbed_official | 130:1dec54e4aec3 | 1211 | |
mbed_official | 130:1dec54e4aec3 | 1212 | /** |
mbed_official | 130:1dec54e4aec3 | 1213 | * @brief Sets the TIMx Capture Compare3 Register value |
mbed_official | 130:1dec54e4aec3 | 1214 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1215 | * @param Compare3: specifies the Capture Compare3 register new value. |
mbed_official | 130:1dec54e4aec3 | 1216 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1217 | */ |
mbed_official | 130:1dec54e4aec3 | 1218 | void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3) |
mbed_official | 130:1dec54e4aec3 | 1219 | { |
mbed_official | 130:1dec54e4aec3 | 1220 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1221 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1222 | |
mbed_official | 130:1dec54e4aec3 | 1223 | /* Set the Capture Compare3 Register value */ |
mbed_official | 130:1dec54e4aec3 | 1224 | TIMx->CCR3 = Compare3; |
mbed_official | 130:1dec54e4aec3 | 1225 | } |
mbed_official | 130:1dec54e4aec3 | 1226 | |
mbed_official | 130:1dec54e4aec3 | 1227 | /** |
mbed_official | 130:1dec54e4aec3 | 1228 | * @brief Sets the TIMx Capture Compare4 Register value |
mbed_official | 130:1dec54e4aec3 | 1229 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1230 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1231 | * @param Compare4: specifies the Capture Compare4 register new value. |
mbed_official | 130:1dec54e4aec3 | 1232 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1233 | */ |
mbed_official | 130:1dec54e4aec3 | 1234 | void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4) |
mbed_official | 130:1dec54e4aec3 | 1235 | { |
mbed_official | 130:1dec54e4aec3 | 1236 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1237 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1238 | |
mbed_official | 130:1dec54e4aec3 | 1239 | /* Set the Capture Compare4 Register value */ |
mbed_official | 130:1dec54e4aec3 | 1240 | TIMx->CCR4 = Compare4; |
mbed_official | 130:1dec54e4aec3 | 1241 | } |
mbed_official | 130:1dec54e4aec3 | 1242 | |
mbed_official | 130:1dec54e4aec3 | 1243 | /** |
mbed_official | 130:1dec54e4aec3 | 1244 | * @brief Forces the TIMx output 1 waveform to active or inactive level. |
mbed_official | 130:1dec54e4aec3 | 1245 | * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1246 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1247 | * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. |
mbed_official | 130:1dec54e4aec3 | 1248 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1249 | * @arg TIM_ForcedAction_Active: Force active level on OC1REF |
mbed_official | 130:1dec54e4aec3 | 1250 | * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. |
mbed_official | 130:1dec54e4aec3 | 1251 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1252 | */ |
mbed_official | 130:1dec54e4aec3 | 1253 | void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) |
mbed_official | 130:1dec54e4aec3 | 1254 | { |
mbed_official | 130:1dec54e4aec3 | 1255 | uint16_t tmpccmr1 = 0; |
mbed_official | 130:1dec54e4aec3 | 1256 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1257 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1258 | assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); |
mbed_official | 130:1dec54e4aec3 | 1259 | tmpccmr1 = TIMx->CCMR1; |
mbed_official | 130:1dec54e4aec3 | 1260 | /* Reset the OC1M Bits */ |
mbed_official | 130:1dec54e4aec3 | 1261 | tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M); |
mbed_official | 130:1dec54e4aec3 | 1262 | /* Configure The Forced output Mode */ |
mbed_official | 130:1dec54e4aec3 | 1263 | tmpccmr1 |= TIM_ForcedAction; |
mbed_official | 130:1dec54e4aec3 | 1264 | /* Write to TIMx CCMR1 register */ |
mbed_official | 130:1dec54e4aec3 | 1265 | TIMx->CCMR1 = tmpccmr1; |
mbed_official | 130:1dec54e4aec3 | 1266 | } |
mbed_official | 130:1dec54e4aec3 | 1267 | |
mbed_official | 130:1dec54e4aec3 | 1268 | /** |
mbed_official | 130:1dec54e4aec3 | 1269 | * @brief Forces the TIMx output 2 waveform to active or inactive level. |
mbed_official | 130:1dec54e4aec3 | 1270 | * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1271 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1272 | * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. |
mbed_official | 130:1dec54e4aec3 | 1273 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1274 | * @arg TIM_ForcedAction_Active: Force active level on OC2REF |
mbed_official | 130:1dec54e4aec3 | 1275 | * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. |
mbed_official | 130:1dec54e4aec3 | 1276 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1277 | */ |
mbed_official | 130:1dec54e4aec3 | 1278 | void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) |
mbed_official | 130:1dec54e4aec3 | 1279 | { |
mbed_official | 130:1dec54e4aec3 | 1280 | uint16_t tmpccmr1 = 0; |
mbed_official | 130:1dec54e4aec3 | 1281 | |
mbed_official | 130:1dec54e4aec3 | 1282 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1283 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1284 | assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); |
mbed_official | 130:1dec54e4aec3 | 1285 | |
mbed_official | 130:1dec54e4aec3 | 1286 | tmpccmr1 = TIMx->CCMR1; |
mbed_official | 130:1dec54e4aec3 | 1287 | /* Reset the OC2M Bits */ |
mbed_official | 130:1dec54e4aec3 | 1288 | tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M); |
mbed_official | 130:1dec54e4aec3 | 1289 | /* Configure The Forced output Mode */ |
mbed_official | 130:1dec54e4aec3 | 1290 | tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); |
mbed_official | 130:1dec54e4aec3 | 1291 | /* Write to TIMx CCMR1 register */ |
mbed_official | 130:1dec54e4aec3 | 1292 | TIMx->CCMR1 = tmpccmr1; |
mbed_official | 130:1dec54e4aec3 | 1293 | } |
mbed_official | 130:1dec54e4aec3 | 1294 | |
mbed_official | 130:1dec54e4aec3 | 1295 | /** |
mbed_official | 130:1dec54e4aec3 | 1296 | * @brief Forces the TIMx output 3 waveform to active or inactive level. |
mbed_official | 130:1dec54e4aec3 | 1297 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1298 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1299 | * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. |
mbed_official | 130:1dec54e4aec3 | 1300 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1301 | * @arg TIM_ForcedAction_Active: Force active level on OC3REF |
mbed_official | 130:1dec54e4aec3 | 1302 | * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. |
mbed_official | 130:1dec54e4aec3 | 1303 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1304 | */ |
mbed_official | 130:1dec54e4aec3 | 1305 | void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) |
mbed_official | 130:1dec54e4aec3 | 1306 | { |
mbed_official | 130:1dec54e4aec3 | 1307 | uint16_t tmpccmr2 = 0; |
mbed_official | 130:1dec54e4aec3 | 1308 | |
mbed_official | 130:1dec54e4aec3 | 1309 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1310 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1311 | assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); |
mbed_official | 130:1dec54e4aec3 | 1312 | |
mbed_official | 130:1dec54e4aec3 | 1313 | tmpccmr2 = TIMx->CCMR2; |
mbed_official | 130:1dec54e4aec3 | 1314 | /* Reset the OC1M Bits */ |
mbed_official | 130:1dec54e4aec3 | 1315 | tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M); |
mbed_official | 130:1dec54e4aec3 | 1316 | /* Configure The Forced output Mode */ |
mbed_official | 130:1dec54e4aec3 | 1317 | tmpccmr2 |= TIM_ForcedAction; |
mbed_official | 130:1dec54e4aec3 | 1318 | /* Write to TIMx CCMR2 register */ |
mbed_official | 130:1dec54e4aec3 | 1319 | TIMx->CCMR2 = tmpccmr2; |
mbed_official | 130:1dec54e4aec3 | 1320 | } |
mbed_official | 130:1dec54e4aec3 | 1321 | |
mbed_official | 130:1dec54e4aec3 | 1322 | /** |
mbed_official | 130:1dec54e4aec3 | 1323 | * @brief Forces the TIMx output 4 waveform to active or inactive level. |
mbed_official | 130:1dec54e4aec3 | 1324 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1325 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1326 | * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. |
mbed_official | 130:1dec54e4aec3 | 1327 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1328 | * @arg TIM_ForcedAction_Active: Force active level on OC4REF |
mbed_official | 130:1dec54e4aec3 | 1329 | * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. |
mbed_official | 130:1dec54e4aec3 | 1330 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1331 | */ |
mbed_official | 130:1dec54e4aec3 | 1332 | void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) |
mbed_official | 130:1dec54e4aec3 | 1333 | { |
mbed_official | 130:1dec54e4aec3 | 1334 | uint16_t tmpccmr2 = 0; |
mbed_official | 130:1dec54e4aec3 | 1335 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1336 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1337 | assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); |
mbed_official | 130:1dec54e4aec3 | 1338 | |
mbed_official | 130:1dec54e4aec3 | 1339 | tmpccmr2 = TIMx->CCMR2; |
mbed_official | 130:1dec54e4aec3 | 1340 | /* Reset the OC2M Bits */ |
mbed_official | 130:1dec54e4aec3 | 1341 | tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M); |
mbed_official | 130:1dec54e4aec3 | 1342 | /* Configure The Forced output Mode */ |
mbed_official | 130:1dec54e4aec3 | 1343 | tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); |
mbed_official | 130:1dec54e4aec3 | 1344 | /* Write to TIMx CCMR2 register */ |
mbed_official | 130:1dec54e4aec3 | 1345 | TIMx->CCMR2 = tmpccmr2; |
mbed_official | 130:1dec54e4aec3 | 1346 | } |
mbed_official | 130:1dec54e4aec3 | 1347 | |
mbed_official | 130:1dec54e4aec3 | 1348 | /** |
mbed_official | 130:1dec54e4aec3 | 1349 | * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. |
mbed_official | 130:1dec54e4aec3 | 1350 | * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIMx peripheral |
mbed_official | 130:1dec54e4aec3 | 1351 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1352 | * @param NewState: new state of the Capture Compare Preload Control bit |
mbed_official | 130:1dec54e4aec3 | 1353 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 130:1dec54e4aec3 | 1354 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1355 | */ |
mbed_official | 130:1dec54e4aec3 | 1356 | void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) |
mbed_official | 130:1dec54e4aec3 | 1357 | { |
mbed_official | 130:1dec54e4aec3 | 1358 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1359 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1360 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 130:1dec54e4aec3 | 1361 | if (NewState != DISABLE) |
mbed_official | 130:1dec54e4aec3 | 1362 | { |
mbed_official | 130:1dec54e4aec3 | 1363 | /* Set the CCPC Bit */ |
mbed_official | 130:1dec54e4aec3 | 1364 | TIMx->CR2 |= TIM_CR2_CCPC; |
mbed_official | 130:1dec54e4aec3 | 1365 | } |
mbed_official | 130:1dec54e4aec3 | 1366 | else |
mbed_official | 130:1dec54e4aec3 | 1367 | { |
mbed_official | 130:1dec54e4aec3 | 1368 | /* Reset the CCPC Bit */ |
mbed_official | 130:1dec54e4aec3 | 1369 | TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC); |
mbed_official | 130:1dec54e4aec3 | 1370 | } |
mbed_official | 130:1dec54e4aec3 | 1371 | } |
mbed_official | 130:1dec54e4aec3 | 1372 | |
mbed_official | 130:1dec54e4aec3 | 1373 | |
mbed_official | 130:1dec54e4aec3 | 1374 | /** |
mbed_official | 130:1dec54e4aec3 | 1375 | * @brief Enables or disables the TIMx peripheral Preload register on CCR1. |
mbed_official | 130:1dec54e4aec3 | 1376 | * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1377 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1378 | * @param TIM_OCPreload: new state of the TIMx peripheral Preload register |
mbed_official | 130:1dec54e4aec3 | 1379 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1380 | * @arg TIM_OCPreload_Enable |
mbed_official | 130:1dec54e4aec3 | 1381 | * @arg TIM_OCPreload_Disable |
mbed_official | 130:1dec54e4aec3 | 1382 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1383 | */ |
mbed_official | 130:1dec54e4aec3 | 1384 | void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) |
mbed_official | 130:1dec54e4aec3 | 1385 | { |
mbed_official | 130:1dec54e4aec3 | 1386 | uint16_t tmpccmr1 = 0; |
mbed_official | 130:1dec54e4aec3 | 1387 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1388 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1389 | assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); |
mbed_official | 130:1dec54e4aec3 | 1390 | |
mbed_official | 130:1dec54e4aec3 | 1391 | tmpccmr1 = TIMx->CCMR1; |
mbed_official | 130:1dec54e4aec3 | 1392 | /* Reset the OC1PE Bit */ |
mbed_official | 130:1dec54e4aec3 | 1393 | tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE); |
mbed_official | 130:1dec54e4aec3 | 1394 | /* Enable or Disable the Output Compare Preload feature */ |
mbed_official | 130:1dec54e4aec3 | 1395 | tmpccmr1 |= TIM_OCPreload; |
mbed_official | 130:1dec54e4aec3 | 1396 | /* Write to TIMx CCMR1 register */ |
mbed_official | 130:1dec54e4aec3 | 1397 | TIMx->CCMR1 = tmpccmr1; |
mbed_official | 130:1dec54e4aec3 | 1398 | } |
mbed_official | 130:1dec54e4aec3 | 1399 | |
mbed_official | 130:1dec54e4aec3 | 1400 | /** |
mbed_official | 130:1dec54e4aec3 | 1401 | * @brief Enables or disables the TIMx peripheral Preload register on CCR2. |
mbed_official | 130:1dec54e4aec3 | 1402 | * @param TIMx: where x can be 1, 2, 3 and 15 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1403 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1404 | * @param TIM_OCPreload: new state of the TIMx peripheral Preload register |
mbed_official | 130:1dec54e4aec3 | 1405 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1406 | * @arg TIM_OCPreload_Enable |
mbed_official | 130:1dec54e4aec3 | 1407 | * @arg TIM_OCPreload_Disable |
mbed_official | 130:1dec54e4aec3 | 1408 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1409 | */ |
mbed_official | 130:1dec54e4aec3 | 1410 | void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) |
mbed_official | 130:1dec54e4aec3 | 1411 | { |
mbed_official | 130:1dec54e4aec3 | 1412 | uint16_t tmpccmr1 = 0; |
mbed_official | 130:1dec54e4aec3 | 1413 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1414 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1415 | assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); |
mbed_official | 130:1dec54e4aec3 | 1416 | |
mbed_official | 130:1dec54e4aec3 | 1417 | tmpccmr1 = TIMx->CCMR1; |
mbed_official | 130:1dec54e4aec3 | 1418 | /* Reset the OC2PE Bit */ |
mbed_official | 130:1dec54e4aec3 | 1419 | tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE); |
mbed_official | 130:1dec54e4aec3 | 1420 | /* Enable or Disable the Output Compare Preload feature */ |
mbed_official | 130:1dec54e4aec3 | 1421 | tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); |
mbed_official | 130:1dec54e4aec3 | 1422 | /* Write to TIMx CCMR1 register */ |
mbed_official | 130:1dec54e4aec3 | 1423 | TIMx->CCMR1 = tmpccmr1; |
mbed_official | 130:1dec54e4aec3 | 1424 | } |
mbed_official | 130:1dec54e4aec3 | 1425 | |
mbed_official | 130:1dec54e4aec3 | 1426 | /** |
mbed_official | 130:1dec54e4aec3 | 1427 | * @brief Enables or disables the TIMx peripheral Preload register on CCR3. |
mbed_official | 130:1dec54e4aec3 | 1428 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1429 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1430 | * @param TIM_OCPreload: new state of the TIMx peripheral Preload register |
mbed_official | 130:1dec54e4aec3 | 1431 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1432 | * @arg TIM_OCPreload_Enable |
mbed_official | 130:1dec54e4aec3 | 1433 | * @arg TIM_OCPreload_Disable |
mbed_official | 130:1dec54e4aec3 | 1434 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1435 | */ |
mbed_official | 130:1dec54e4aec3 | 1436 | void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) |
mbed_official | 130:1dec54e4aec3 | 1437 | { |
mbed_official | 130:1dec54e4aec3 | 1438 | uint16_t tmpccmr2 = 0; |
mbed_official | 130:1dec54e4aec3 | 1439 | |
mbed_official | 130:1dec54e4aec3 | 1440 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1441 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1442 | assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); |
mbed_official | 130:1dec54e4aec3 | 1443 | |
mbed_official | 130:1dec54e4aec3 | 1444 | tmpccmr2 = TIMx->CCMR2; |
mbed_official | 130:1dec54e4aec3 | 1445 | /* Reset the OC3PE Bit */ |
mbed_official | 130:1dec54e4aec3 | 1446 | tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE); |
mbed_official | 130:1dec54e4aec3 | 1447 | /* Enable or Disable the Output Compare Preload feature */ |
mbed_official | 130:1dec54e4aec3 | 1448 | tmpccmr2 |= TIM_OCPreload; |
mbed_official | 130:1dec54e4aec3 | 1449 | /* Write to TIMx CCMR2 register */ |
mbed_official | 130:1dec54e4aec3 | 1450 | TIMx->CCMR2 = tmpccmr2; |
mbed_official | 130:1dec54e4aec3 | 1451 | } |
mbed_official | 130:1dec54e4aec3 | 1452 | |
mbed_official | 130:1dec54e4aec3 | 1453 | /** |
mbed_official | 130:1dec54e4aec3 | 1454 | * @brief Enables or disables the TIMx peripheral Preload register on CCR4. |
mbed_official | 130:1dec54e4aec3 | 1455 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1456 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1457 | * @param TIM_OCPreload: new state of the TIMx peripheral Preload register |
mbed_official | 130:1dec54e4aec3 | 1458 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1459 | * @arg TIM_OCPreload_Enable |
mbed_official | 130:1dec54e4aec3 | 1460 | * @arg TIM_OCPreload_Disable |
mbed_official | 130:1dec54e4aec3 | 1461 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1462 | */ |
mbed_official | 130:1dec54e4aec3 | 1463 | void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) |
mbed_official | 130:1dec54e4aec3 | 1464 | { |
mbed_official | 130:1dec54e4aec3 | 1465 | uint16_t tmpccmr2 = 0; |
mbed_official | 130:1dec54e4aec3 | 1466 | |
mbed_official | 130:1dec54e4aec3 | 1467 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1468 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1469 | assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); |
mbed_official | 130:1dec54e4aec3 | 1470 | |
mbed_official | 130:1dec54e4aec3 | 1471 | tmpccmr2 = TIMx->CCMR2; |
mbed_official | 130:1dec54e4aec3 | 1472 | /* Reset the OC4PE Bit */ |
mbed_official | 130:1dec54e4aec3 | 1473 | tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE); |
mbed_official | 130:1dec54e4aec3 | 1474 | /* Enable or Disable the Output Compare Preload feature */ |
mbed_official | 130:1dec54e4aec3 | 1475 | tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); |
mbed_official | 130:1dec54e4aec3 | 1476 | /* Write to TIMx CCMR2 register */ |
mbed_official | 130:1dec54e4aec3 | 1477 | TIMx->CCMR2 = tmpccmr2; |
mbed_official | 130:1dec54e4aec3 | 1478 | } |
mbed_official | 130:1dec54e4aec3 | 1479 | |
mbed_official | 130:1dec54e4aec3 | 1480 | /** |
mbed_official | 130:1dec54e4aec3 | 1481 | * @brief Configures the TIMx Output Compare 1 Fast feature. |
mbed_official | 130:1dec54e4aec3 | 1482 | * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1483 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1484 | * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. |
mbed_official | 130:1dec54e4aec3 | 1485 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1486 | * @arg TIM_OCFast_Enable: TIM output compare fast enable |
mbed_official | 130:1dec54e4aec3 | 1487 | * @arg TIM_OCFast_Disable: TIM output compare fast disable |
mbed_official | 130:1dec54e4aec3 | 1488 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1489 | */ |
mbed_official | 130:1dec54e4aec3 | 1490 | void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) |
mbed_official | 130:1dec54e4aec3 | 1491 | { |
mbed_official | 130:1dec54e4aec3 | 1492 | uint16_t tmpccmr1 = 0; |
mbed_official | 130:1dec54e4aec3 | 1493 | |
mbed_official | 130:1dec54e4aec3 | 1494 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1495 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1496 | assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); |
mbed_official | 130:1dec54e4aec3 | 1497 | |
mbed_official | 130:1dec54e4aec3 | 1498 | /* Get the TIMx CCMR1 register value */ |
mbed_official | 130:1dec54e4aec3 | 1499 | tmpccmr1 = TIMx->CCMR1; |
mbed_official | 130:1dec54e4aec3 | 1500 | /* Reset the OC1FE Bit */ |
mbed_official | 130:1dec54e4aec3 | 1501 | tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE); |
mbed_official | 130:1dec54e4aec3 | 1502 | /* Enable or Disable the Output Compare Fast Bit */ |
mbed_official | 130:1dec54e4aec3 | 1503 | tmpccmr1 |= TIM_OCFast; |
mbed_official | 130:1dec54e4aec3 | 1504 | /* Write to TIMx CCMR1 */ |
mbed_official | 130:1dec54e4aec3 | 1505 | TIMx->CCMR1 = tmpccmr1; |
mbed_official | 130:1dec54e4aec3 | 1506 | } |
mbed_official | 130:1dec54e4aec3 | 1507 | |
mbed_official | 130:1dec54e4aec3 | 1508 | /** |
mbed_official | 130:1dec54e4aec3 | 1509 | * @brief Configures the TIMx Output Compare 2 Fast feature. |
mbed_official | 130:1dec54e4aec3 | 1510 | * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1511 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1512 | * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. |
mbed_official | 130:1dec54e4aec3 | 1513 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1514 | * @arg TIM_OCFast_Enable: TIM output compare fast enable |
mbed_official | 130:1dec54e4aec3 | 1515 | * @arg TIM_OCFast_Disable: TIM output compare fast disable |
mbed_official | 130:1dec54e4aec3 | 1516 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1517 | */ |
mbed_official | 130:1dec54e4aec3 | 1518 | void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) |
mbed_official | 130:1dec54e4aec3 | 1519 | { |
mbed_official | 130:1dec54e4aec3 | 1520 | uint16_t tmpccmr1 = 0; |
mbed_official | 130:1dec54e4aec3 | 1521 | |
mbed_official | 130:1dec54e4aec3 | 1522 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1523 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1524 | assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); |
mbed_official | 130:1dec54e4aec3 | 1525 | |
mbed_official | 130:1dec54e4aec3 | 1526 | /* Get the TIMx CCMR1 register value */ |
mbed_official | 130:1dec54e4aec3 | 1527 | tmpccmr1 = TIMx->CCMR1; |
mbed_official | 130:1dec54e4aec3 | 1528 | /* Reset the OC2FE Bit */ |
mbed_official | 130:1dec54e4aec3 | 1529 | tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE); |
mbed_official | 130:1dec54e4aec3 | 1530 | /* Enable or Disable the Output Compare Fast Bit */ |
mbed_official | 130:1dec54e4aec3 | 1531 | tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); |
mbed_official | 130:1dec54e4aec3 | 1532 | /* Write to TIMx CCMR1 */ |
mbed_official | 130:1dec54e4aec3 | 1533 | TIMx->CCMR1 = tmpccmr1; |
mbed_official | 130:1dec54e4aec3 | 1534 | } |
mbed_official | 130:1dec54e4aec3 | 1535 | |
mbed_official | 130:1dec54e4aec3 | 1536 | /** |
mbed_official | 130:1dec54e4aec3 | 1537 | * @brief Configures the TIMx Output Compare 3 Fast feature. |
mbed_official | 130:1dec54e4aec3 | 1538 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1539 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1540 | * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. |
mbed_official | 130:1dec54e4aec3 | 1541 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1542 | * @arg TIM_OCFast_Enable: TIM output compare fast enable |
mbed_official | 130:1dec54e4aec3 | 1543 | * @arg TIM_OCFast_Disable: TIM output compare fast disable |
mbed_official | 130:1dec54e4aec3 | 1544 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1545 | */ |
mbed_official | 130:1dec54e4aec3 | 1546 | void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) |
mbed_official | 130:1dec54e4aec3 | 1547 | { |
mbed_official | 130:1dec54e4aec3 | 1548 | uint16_t tmpccmr2 = 0; |
mbed_official | 130:1dec54e4aec3 | 1549 | |
mbed_official | 130:1dec54e4aec3 | 1550 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1551 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1552 | assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); |
mbed_official | 130:1dec54e4aec3 | 1553 | |
mbed_official | 130:1dec54e4aec3 | 1554 | /* Get the TIMx CCMR2 register value */ |
mbed_official | 130:1dec54e4aec3 | 1555 | tmpccmr2 = TIMx->CCMR2; |
mbed_official | 130:1dec54e4aec3 | 1556 | /* Reset the OC3FE Bit */ |
mbed_official | 130:1dec54e4aec3 | 1557 | tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE); |
mbed_official | 130:1dec54e4aec3 | 1558 | /* Enable or Disable the Output Compare Fast Bit */ |
mbed_official | 130:1dec54e4aec3 | 1559 | tmpccmr2 |= TIM_OCFast; |
mbed_official | 130:1dec54e4aec3 | 1560 | /* Write to TIMx CCMR2 */ |
mbed_official | 130:1dec54e4aec3 | 1561 | TIMx->CCMR2 = tmpccmr2; |
mbed_official | 130:1dec54e4aec3 | 1562 | } |
mbed_official | 130:1dec54e4aec3 | 1563 | |
mbed_official | 130:1dec54e4aec3 | 1564 | /** |
mbed_official | 130:1dec54e4aec3 | 1565 | * @brief Configures the TIMx Output Compare 4 Fast feature. |
mbed_official | 130:1dec54e4aec3 | 1566 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1567 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1568 | * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. |
mbed_official | 130:1dec54e4aec3 | 1569 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1570 | * @arg TIM_OCFast_Enable: TIM output compare fast enable |
mbed_official | 130:1dec54e4aec3 | 1571 | * @arg TIM_OCFast_Disable: TIM output compare fast disable |
mbed_official | 130:1dec54e4aec3 | 1572 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1573 | */ |
mbed_official | 130:1dec54e4aec3 | 1574 | void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) |
mbed_official | 130:1dec54e4aec3 | 1575 | { |
mbed_official | 130:1dec54e4aec3 | 1576 | uint16_t tmpccmr2 = 0; |
mbed_official | 130:1dec54e4aec3 | 1577 | |
mbed_official | 130:1dec54e4aec3 | 1578 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1579 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1580 | assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); |
mbed_official | 130:1dec54e4aec3 | 1581 | |
mbed_official | 130:1dec54e4aec3 | 1582 | /* Get the TIMx CCMR2 register value */ |
mbed_official | 130:1dec54e4aec3 | 1583 | tmpccmr2 = TIMx->CCMR2; |
mbed_official | 130:1dec54e4aec3 | 1584 | /* Reset the OC4FE Bit */ |
mbed_official | 130:1dec54e4aec3 | 1585 | tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE); |
mbed_official | 130:1dec54e4aec3 | 1586 | /* Enable or Disable the Output Compare Fast Bit */ |
mbed_official | 130:1dec54e4aec3 | 1587 | tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); |
mbed_official | 130:1dec54e4aec3 | 1588 | /* Write to TIMx CCMR2 */ |
mbed_official | 130:1dec54e4aec3 | 1589 | TIMx->CCMR2 = tmpccmr2; |
mbed_official | 130:1dec54e4aec3 | 1590 | } |
mbed_official | 130:1dec54e4aec3 | 1591 | |
mbed_official | 130:1dec54e4aec3 | 1592 | /** |
mbed_official | 130:1dec54e4aec3 | 1593 | * @brief Clears or safeguards the OCREF1 signal on an external event |
mbed_official | 130:1dec54e4aec3 | 1594 | * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1595 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1596 | * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. |
mbed_official | 130:1dec54e4aec3 | 1597 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1598 | * @arg TIM_OCClear_Enable: TIM Output clear enable |
mbed_official | 130:1dec54e4aec3 | 1599 | * @arg TIM_OCClear_Disable: TIM Output clear disable |
mbed_official | 130:1dec54e4aec3 | 1600 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1601 | */ |
mbed_official | 130:1dec54e4aec3 | 1602 | void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) |
mbed_official | 130:1dec54e4aec3 | 1603 | { |
mbed_official | 130:1dec54e4aec3 | 1604 | uint16_t tmpccmr1 = 0; |
mbed_official | 130:1dec54e4aec3 | 1605 | |
mbed_official | 130:1dec54e4aec3 | 1606 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1607 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1608 | assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); |
mbed_official | 130:1dec54e4aec3 | 1609 | |
mbed_official | 130:1dec54e4aec3 | 1610 | tmpccmr1 = TIMx->CCMR1; |
mbed_official | 130:1dec54e4aec3 | 1611 | /* Reset the OC1CE Bit */ |
mbed_official | 130:1dec54e4aec3 | 1612 | tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE); |
mbed_official | 130:1dec54e4aec3 | 1613 | /* Enable or Disable the Output Compare Clear Bit */ |
mbed_official | 130:1dec54e4aec3 | 1614 | tmpccmr1 |= TIM_OCClear; |
mbed_official | 130:1dec54e4aec3 | 1615 | /* Write to TIMx CCMR1 register */ |
mbed_official | 130:1dec54e4aec3 | 1616 | TIMx->CCMR1 = tmpccmr1; |
mbed_official | 130:1dec54e4aec3 | 1617 | } |
mbed_official | 130:1dec54e4aec3 | 1618 | |
mbed_official | 130:1dec54e4aec3 | 1619 | /** |
mbed_official | 130:1dec54e4aec3 | 1620 | * @brief Clears or safeguards the OCREF2 signal on an external event |
mbed_official | 130:1dec54e4aec3 | 1621 | * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1622 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1623 | * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. |
mbed_official | 130:1dec54e4aec3 | 1624 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1625 | * @arg TIM_OCClear_Enable: TIM Output clear enable |
mbed_official | 130:1dec54e4aec3 | 1626 | * @arg TIM_OCClear_Disable: TIM Output clear disable |
mbed_official | 130:1dec54e4aec3 | 1627 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1628 | */ |
mbed_official | 130:1dec54e4aec3 | 1629 | void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) |
mbed_official | 130:1dec54e4aec3 | 1630 | { |
mbed_official | 130:1dec54e4aec3 | 1631 | uint16_t tmpccmr1 = 0; |
mbed_official | 130:1dec54e4aec3 | 1632 | |
mbed_official | 130:1dec54e4aec3 | 1633 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1634 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1635 | assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); |
mbed_official | 130:1dec54e4aec3 | 1636 | |
mbed_official | 130:1dec54e4aec3 | 1637 | tmpccmr1 = TIMx->CCMR1; |
mbed_official | 130:1dec54e4aec3 | 1638 | /* Reset the OC2CE Bit */ |
mbed_official | 130:1dec54e4aec3 | 1639 | tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE); |
mbed_official | 130:1dec54e4aec3 | 1640 | /* Enable or Disable the Output Compare Clear Bit */ |
mbed_official | 130:1dec54e4aec3 | 1641 | tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); |
mbed_official | 130:1dec54e4aec3 | 1642 | /* Write to TIMx CCMR1 register */ |
mbed_official | 130:1dec54e4aec3 | 1643 | TIMx->CCMR1 = tmpccmr1; |
mbed_official | 130:1dec54e4aec3 | 1644 | } |
mbed_official | 130:1dec54e4aec3 | 1645 | |
mbed_official | 130:1dec54e4aec3 | 1646 | /** |
mbed_official | 130:1dec54e4aec3 | 1647 | * @brief Clears or safeguards the OCREF3 signal on an external event |
mbed_official | 130:1dec54e4aec3 | 1648 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1649 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1650 | * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. |
mbed_official | 130:1dec54e4aec3 | 1651 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1652 | * @arg TIM_OCClear_Enable: TIM Output clear enable |
mbed_official | 130:1dec54e4aec3 | 1653 | * @arg TIM_OCClear_Disable: TIM Output clear disable |
mbed_official | 130:1dec54e4aec3 | 1654 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1655 | */ |
mbed_official | 130:1dec54e4aec3 | 1656 | void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) |
mbed_official | 130:1dec54e4aec3 | 1657 | { |
mbed_official | 130:1dec54e4aec3 | 1658 | uint16_t tmpccmr2 = 0; |
mbed_official | 130:1dec54e4aec3 | 1659 | |
mbed_official | 130:1dec54e4aec3 | 1660 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1661 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1662 | assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); |
mbed_official | 130:1dec54e4aec3 | 1663 | |
mbed_official | 130:1dec54e4aec3 | 1664 | tmpccmr2 = TIMx->CCMR2; |
mbed_official | 130:1dec54e4aec3 | 1665 | /* Reset the OC3CE Bit */ |
mbed_official | 130:1dec54e4aec3 | 1666 | tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE); |
mbed_official | 130:1dec54e4aec3 | 1667 | /* Enable or Disable the Output Compare Clear Bit */ |
mbed_official | 130:1dec54e4aec3 | 1668 | tmpccmr2 |= TIM_OCClear; |
mbed_official | 130:1dec54e4aec3 | 1669 | /* Write to TIMx CCMR2 register */ |
mbed_official | 130:1dec54e4aec3 | 1670 | TIMx->CCMR2 = tmpccmr2; |
mbed_official | 130:1dec54e4aec3 | 1671 | } |
mbed_official | 130:1dec54e4aec3 | 1672 | |
mbed_official | 130:1dec54e4aec3 | 1673 | /** |
mbed_official | 130:1dec54e4aec3 | 1674 | * @brief Clears or safeguards the OCREF4 signal on an external event |
mbed_official | 130:1dec54e4aec3 | 1675 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1676 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1677 | * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. |
mbed_official | 130:1dec54e4aec3 | 1678 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1679 | * @arg TIM_OCClear_Enable: TIM Output clear enable |
mbed_official | 130:1dec54e4aec3 | 1680 | * @arg TIM_OCClear_Disable: TIM Output clear disable |
mbed_official | 130:1dec54e4aec3 | 1681 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1682 | */ |
mbed_official | 130:1dec54e4aec3 | 1683 | void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) |
mbed_official | 130:1dec54e4aec3 | 1684 | { |
mbed_official | 130:1dec54e4aec3 | 1685 | uint16_t tmpccmr2 = 0; |
mbed_official | 130:1dec54e4aec3 | 1686 | |
mbed_official | 130:1dec54e4aec3 | 1687 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1688 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1689 | assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); |
mbed_official | 130:1dec54e4aec3 | 1690 | |
mbed_official | 130:1dec54e4aec3 | 1691 | tmpccmr2 = TIMx->CCMR2; |
mbed_official | 130:1dec54e4aec3 | 1692 | /* Reset the OC4CE Bit */ |
mbed_official | 130:1dec54e4aec3 | 1693 | tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE); |
mbed_official | 130:1dec54e4aec3 | 1694 | /* Enable or Disable the Output Compare Clear Bit */ |
mbed_official | 130:1dec54e4aec3 | 1695 | tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); |
mbed_official | 130:1dec54e4aec3 | 1696 | /* Write to TIMx CCMR2 register */ |
mbed_official | 130:1dec54e4aec3 | 1697 | TIMx->CCMR2 = tmpccmr2; |
mbed_official | 130:1dec54e4aec3 | 1698 | } |
mbed_official | 130:1dec54e4aec3 | 1699 | |
mbed_official | 130:1dec54e4aec3 | 1700 | /** |
mbed_official | 130:1dec54e4aec3 | 1701 | * @brief Configures the TIMx channel 1 polarity. |
mbed_official | 130:1dec54e4aec3 | 1702 | * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1703 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1704 | * @param TIM_OCPolarity: specifies the OC1 Polarity |
mbed_official | 130:1dec54e4aec3 | 1705 | * This parmeter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1706 | * @arg TIM_OCPolarity_High: Output Compare active high |
mbed_official | 130:1dec54e4aec3 | 1707 | * @arg TIM_OCPolarity_Low: Output Compare active low |
mbed_official | 130:1dec54e4aec3 | 1708 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1709 | */ |
mbed_official | 130:1dec54e4aec3 | 1710 | void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) |
mbed_official | 130:1dec54e4aec3 | 1711 | { |
mbed_official | 130:1dec54e4aec3 | 1712 | uint16_t tmpccer = 0; |
mbed_official | 130:1dec54e4aec3 | 1713 | |
mbed_official | 130:1dec54e4aec3 | 1714 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1715 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1716 | assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); |
mbed_official | 130:1dec54e4aec3 | 1717 | |
mbed_official | 130:1dec54e4aec3 | 1718 | tmpccer = TIMx->CCER; |
mbed_official | 130:1dec54e4aec3 | 1719 | /* Set or Reset the CC1P Bit */ |
mbed_official | 130:1dec54e4aec3 | 1720 | tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P); |
mbed_official | 130:1dec54e4aec3 | 1721 | tmpccer |= TIM_OCPolarity; |
mbed_official | 130:1dec54e4aec3 | 1722 | /* Write to TIMx CCER register */ |
mbed_official | 130:1dec54e4aec3 | 1723 | TIMx->CCER = tmpccer; |
mbed_official | 130:1dec54e4aec3 | 1724 | } |
mbed_official | 130:1dec54e4aec3 | 1725 | |
mbed_official | 130:1dec54e4aec3 | 1726 | /** |
mbed_official | 130:1dec54e4aec3 | 1727 | * @brief Configures the TIMx Channel 1N polarity. |
mbed_official | 130:1dec54e4aec3 | 1728 | * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1729 | * @param TIM_OCNPolarity: specifies the OC1N Polarity |
mbed_official | 130:1dec54e4aec3 | 1730 | * This parmeter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1731 | * @arg TIM_OCNPolarity_High: Output Compare active high |
mbed_official | 130:1dec54e4aec3 | 1732 | * @arg TIM_OCNPolarity_Low: Output Compare active low |
mbed_official | 130:1dec54e4aec3 | 1733 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1734 | */ |
mbed_official | 130:1dec54e4aec3 | 1735 | void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) |
mbed_official | 130:1dec54e4aec3 | 1736 | { |
mbed_official | 130:1dec54e4aec3 | 1737 | uint16_t tmpccer = 0; |
mbed_official | 130:1dec54e4aec3 | 1738 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1739 | assert_param(IS_TIM_LIST2_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1740 | assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); |
mbed_official | 130:1dec54e4aec3 | 1741 | |
mbed_official | 130:1dec54e4aec3 | 1742 | tmpccer = TIMx->CCER; |
mbed_official | 130:1dec54e4aec3 | 1743 | /* Set or Reset the CC1NP Bit */ |
mbed_official | 130:1dec54e4aec3 | 1744 | tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP); |
mbed_official | 130:1dec54e4aec3 | 1745 | tmpccer |= TIM_OCNPolarity; |
mbed_official | 130:1dec54e4aec3 | 1746 | /* Write to TIMx CCER register */ |
mbed_official | 130:1dec54e4aec3 | 1747 | TIMx->CCER = tmpccer; |
mbed_official | 130:1dec54e4aec3 | 1748 | } |
mbed_official | 130:1dec54e4aec3 | 1749 | |
mbed_official | 130:1dec54e4aec3 | 1750 | /** |
mbed_official | 130:1dec54e4aec3 | 1751 | * @brief Configures the TIMx channel 2 polarity. |
mbed_official | 130:1dec54e4aec3 | 1752 | * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1753 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1754 | * @param TIM_OCPolarity: specifies the OC2 Polarity |
mbed_official | 130:1dec54e4aec3 | 1755 | * This parmeter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1756 | * @arg TIM_OCPolarity_High: Output Compare active high |
mbed_official | 130:1dec54e4aec3 | 1757 | * @arg TIM_OCPolarity_Low: Output Compare active low |
mbed_official | 130:1dec54e4aec3 | 1758 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1759 | */ |
mbed_official | 130:1dec54e4aec3 | 1760 | void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) |
mbed_official | 130:1dec54e4aec3 | 1761 | { |
mbed_official | 130:1dec54e4aec3 | 1762 | uint16_t tmpccer = 0; |
mbed_official | 130:1dec54e4aec3 | 1763 | |
mbed_official | 130:1dec54e4aec3 | 1764 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1765 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1766 | assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); |
mbed_official | 130:1dec54e4aec3 | 1767 | |
mbed_official | 130:1dec54e4aec3 | 1768 | tmpccer = TIMx->CCER; |
mbed_official | 130:1dec54e4aec3 | 1769 | /* Set or Reset the CC2P Bit */ |
mbed_official | 130:1dec54e4aec3 | 1770 | tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P); |
mbed_official | 130:1dec54e4aec3 | 1771 | tmpccer |= (uint16_t)(TIM_OCPolarity << 4); |
mbed_official | 130:1dec54e4aec3 | 1772 | /* Write to TIMx CCER register */ |
mbed_official | 130:1dec54e4aec3 | 1773 | TIMx->CCER = tmpccer; |
mbed_official | 130:1dec54e4aec3 | 1774 | } |
mbed_official | 130:1dec54e4aec3 | 1775 | |
mbed_official | 130:1dec54e4aec3 | 1776 | /** |
mbed_official | 130:1dec54e4aec3 | 1777 | * @brief Configures the TIMx Channel 2N polarity. |
mbed_official | 130:1dec54e4aec3 | 1778 | * @param TIMx: where x can be 1 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1779 | * @param TIM_OCNPolarity: specifies the OC2N Polarity |
mbed_official | 130:1dec54e4aec3 | 1780 | * This parmeter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1781 | * @arg TIM_OCNPolarity_High: Output Compare active high |
mbed_official | 130:1dec54e4aec3 | 1782 | * @arg TIM_OCNPolarity_Low: Output Compare active low |
mbed_official | 130:1dec54e4aec3 | 1783 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1784 | */ |
mbed_official | 130:1dec54e4aec3 | 1785 | void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) |
mbed_official | 130:1dec54e4aec3 | 1786 | { |
mbed_official | 130:1dec54e4aec3 | 1787 | uint16_t tmpccer = 0; |
mbed_official | 130:1dec54e4aec3 | 1788 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1789 | assert_param(IS_TIM_LIST1_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1790 | assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); |
mbed_official | 130:1dec54e4aec3 | 1791 | |
mbed_official | 130:1dec54e4aec3 | 1792 | tmpccer = TIMx->CCER; |
mbed_official | 130:1dec54e4aec3 | 1793 | /* Set or Reset the CC2NP Bit */ |
mbed_official | 130:1dec54e4aec3 | 1794 | tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP); |
mbed_official | 130:1dec54e4aec3 | 1795 | tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); |
mbed_official | 130:1dec54e4aec3 | 1796 | /* Write to TIMx CCER register */ |
mbed_official | 130:1dec54e4aec3 | 1797 | TIMx->CCER = tmpccer; |
mbed_official | 130:1dec54e4aec3 | 1798 | } |
mbed_official | 130:1dec54e4aec3 | 1799 | |
mbed_official | 130:1dec54e4aec3 | 1800 | /** |
mbed_official | 130:1dec54e4aec3 | 1801 | * @brief Configures the TIMx channel 3 polarity. |
mbed_official | 130:1dec54e4aec3 | 1802 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1803 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1804 | * @param TIM_OCPolarity: specifies the OC3 Polarity |
mbed_official | 130:1dec54e4aec3 | 1805 | * This parmeter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1806 | * @arg TIM_OCPolarity_High: Output Compare active high |
mbed_official | 130:1dec54e4aec3 | 1807 | * @arg TIM_OCPolarity_Low: Output Compare active low |
mbed_official | 130:1dec54e4aec3 | 1808 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1809 | */ |
mbed_official | 130:1dec54e4aec3 | 1810 | void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) |
mbed_official | 130:1dec54e4aec3 | 1811 | { |
mbed_official | 130:1dec54e4aec3 | 1812 | uint16_t tmpccer = 0; |
mbed_official | 130:1dec54e4aec3 | 1813 | |
mbed_official | 130:1dec54e4aec3 | 1814 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1815 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1816 | assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); |
mbed_official | 130:1dec54e4aec3 | 1817 | |
mbed_official | 130:1dec54e4aec3 | 1818 | tmpccer = TIMx->CCER; |
mbed_official | 130:1dec54e4aec3 | 1819 | /* Set or Reset the CC3P Bit */ |
mbed_official | 130:1dec54e4aec3 | 1820 | tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P); |
mbed_official | 130:1dec54e4aec3 | 1821 | tmpccer |= (uint16_t)(TIM_OCPolarity << 8); |
mbed_official | 130:1dec54e4aec3 | 1822 | /* Write to TIMx CCER register */ |
mbed_official | 130:1dec54e4aec3 | 1823 | TIMx->CCER = tmpccer; |
mbed_official | 130:1dec54e4aec3 | 1824 | } |
mbed_official | 130:1dec54e4aec3 | 1825 | |
mbed_official | 130:1dec54e4aec3 | 1826 | /** |
mbed_official | 130:1dec54e4aec3 | 1827 | * @brief Configures the TIMx Channel 3N polarity. |
mbed_official | 130:1dec54e4aec3 | 1828 | * @param TIMx: where x can be 1 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1829 | * @param TIM_OCNPolarity: specifies the OC3N Polarity |
mbed_official | 130:1dec54e4aec3 | 1830 | * This parmeter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1831 | * @arg TIM_OCNPolarity_High: Output Compare active high |
mbed_official | 130:1dec54e4aec3 | 1832 | * @arg TIM_OCNPolarity_Low: Output Compare active low |
mbed_official | 130:1dec54e4aec3 | 1833 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1834 | */ |
mbed_official | 130:1dec54e4aec3 | 1835 | void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) |
mbed_official | 130:1dec54e4aec3 | 1836 | { |
mbed_official | 130:1dec54e4aec3 | 1837 | uint16_t tmpccer = 0; |
mbed_official | 130:1dec54e4aec3 | 1838 | |
mbed_official | 130:1dec54e4aec3 | 1839 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1840 | assert_param(IS_TIM_LIST1_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1841 | assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); |
mbed_official | 130:1dec54e4aec3 | 1842 | |
mbed_official | 130:1dec54e4aec3 | 1843 | tmpccer = TIMx->CCER; |
mbed_official | 130:1dec54e4aec3 | 1844 | /* Set or Reset the CC3NP Bit */ |
mbed_official | 130:1dec54e4aec3 | 1845 | tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP); |
mbed_official | 130:1dec54e4aec3 | 1846 | tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); |
mbed_official | 130:1dec54e4aec3 | 1847 | /* Write to TIMx CCER register */ |
mbed_official | 130:1dec54e4aec3 | 1848 | TIMx->CCER = tmpccer; |
mbed_official | 130:1dec54e4aec3 | 1849 | } |
mbed_official | 130:1dec54e4aec3 | 1850 | |
mbed_official | 130:1dec54e4aec3 | 1851 | /** |
mbed_official | 130:1dec54e4aec3 | 1852 | * @brief Configures the TIMx channel 4 polarity. |
mbed_official | 130:1dec54e4aec3 | 1853 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1854 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1855 | * @param TIM_OCPolarity: specifies the OC4 Polarity |
mbed_official | 130:1dec54e4aec3 | 1856 | * This parmeter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1857 | * @arg TIM_OCPolarity_High: Output Compare active high |
mbed_official | 130:1dec54e4aec3 | 1858 | * @arg TIM_OCPolarity_Low: Output Compare active low |
mbed_official | 130:1dec54e4aec3 | 1859 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1860 | */ |
mbed_official | 130:1dec54e4aec3 | 1861 | void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) |
mbed_official | 130:1dec54e4aec3 | 1862 | { |
mbed_official | 130:1dec54e4aec3 | 1863 | uint16_t tmpccer = 0; |
mbed_official | 130:1dec54e4aec3 | 1864 | |
mbed_official | 130:1dec54e4aec3 | 1865 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1866 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1867 | assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); |
mbed_official | 130:1dec54e4aec3 | 1868 | |
mbed_official | 130:1dec54e4aec3 | 1869 | tmpccer = TIMx->CCER; |
mbed_official | 130:1dec54e4aec3 | 1870 | /* Set or Reset the CC4P Bit */ |
mbed_official | 130:1dec54e4aec3 | 1871 | tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P); |
mbed_official | 130:1dec54e4aec3 | 1872 | tmpccer |= (uint16_t)(TIM_OCPolarity << 12); |
mbed_official | 130:1dec54e4aec3 | 1873 | /* Write to TIMx CCER register */ |
mbed_official | 130:1dec54e4aec3 | 1874 | TIMx->CCER = tmpccer; |
mbed_official | 130:1dec54e4aec3 | 1875 | } |
mbed_official | 130:1dec54e4aec3 | 1876 | |
mbed_official | 130:1dec54e4aec3 | 1877 | /** |
mbed_official | 130:1dec54e4aec3 | 1878 | * @brief Selects the OCReference Clear source. |
mbed_official | 130:1dec54e4aec3 | 1879 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1880 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1881 | * @param TIM_OCReferenceClear: specifies the OCReference Clear source. |
mbed_official | 130:1dec54e4aec3 | 1882 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1883 | * @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF. |
mbed_official | 130:1dec54e4aec3 | 1884 | * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input. |
mbed_official | 130:1dec54e4aec3 | 1885 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1886 | */ |
mbed_official | 130:1dec54e4aec3 | 1887 | void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear) |
mbed_official | 130:1dec54e4aec3 | 1888 | { |
mbed_official | 130:1dec54e4aec3 | 1889 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1890 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1891 | assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear)); |
mbed_official | 130:1dec54e4aec3 | 1892 | |
mbed_official | 130:1dec54e4aec3 | 1893 | /* Set the TIM_OCReferenceClear source */ |
mbed_official | 130:1dec54e4aec3 | 1894 | TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS); |
mbed_official | 130:1dec54e4aec3 | 1895 | TIMx->SMCR |= TIM_OCReferenceClear; |
mbed_official | 130:1dec54e4aec3 | 1896 | } |
mbed_official | 130:1dec54e4aec3 | 1897 | |
mbed_official | 130:1dec54e4aec3 | 1898 | /** |
mbed_official | 130:1dec54e4aec3 | 1899 | * @brief Enables or disables the TIM Capture Compare Channel x. |
mbed_official | 130:1dec54e4aec3 | 1900 | * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1901 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 1902 | * @param TIM_Channel: specifies the TIM Channel |
mbed_official | 130:1dec54e4aec3 | 1903 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1904 | * @arg TIM_Channel_1: TIM Channel 1 |
mbed_official | 130:1dec54e4aec3 | 1905 | * @arg TIM_Channel_2: TIM Channel 2 |
mbed_official | 130:1dec54e4aec3 | 1906 | * @arg TIM_Channel_3: TIM Channel 3 |
mbed_official | 130:1dec54e4aec3 | 1907 | * @arg TIM_Channel_4: TIM Channel 4 |
mbed_official | 130:1dec54e4aec3 | 1908 | * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. |
mbed_official | 130:1dec54e4aec3 | 1909 | * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. |
mbed_official | 130:1dec54e4aec3 | 1910 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1911 | */ |
mbed_official | 130:1dec54e4aec3 | 1912 | void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) |
mbed_official | 130:1dec54e4aec3 | 1913 | { |
mbed_official | 130:1dec54e4aec3 | 1914 | uint16_t tmp = 0; |
mbed_official | 130:1dec54e4aec3 | 1915 | |
mbed_official | 130:1dec54e4aec3 | 1916 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1917 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1918 | assert_param(IS_TIM_CCX(TIM_CCx)); |
mbed_official | 130:1dec54e4aec3 | 1919 | |
mbed_official | 130:1dec54e4aec3 | 1920 | tmp = CCER_CCE_SET << TIM_Channel; |
mbed_official | 130:1dec54e4aec3 | 1921 | |
mbed_official | 130:1dec54e4aec3 | 1922 | /* Reset the CCxE Bit */ |
mbed_official | 130:1dec54e4aec3 | 1923 | TIMx->CCER &= (uint16_t)~ tmp; |
mbed_official | 130:1dec54e4aec3 | 1924 | |
mbed_official | 130:1dec54e4aec3 | 1925 | /* Set or reset the CCxE Bit */ |
mbed_official | 130:1dec54e4aec3 | 1926 | TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); |
mbed_official | 130:1dec54e4aec3 | 1927 | } |
mbed_official | 130:1dec54e4aec3 | 1928 | |
mbed_official | 130:1dec54e4aec3 | 1929 | /** |
mbed_official | 130:1dec54e4aec3 | 1930 | * @brief Enables or disables the TIM Capture Compare Channel xN. |
mbed_official | 130:1dec54e4aec3 | 1931 | * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 1932 | * @param TIM_Channel: specifies the TIM Channel |
mbed_official | 130:1dec54e4aec3 | 1933 | * This parmeter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 1934 | * @arg TIM_Channel_1: TIM Channel 1 |
mbed_official | 130:1dec54e4aec3 | 1935 | * @arg TIM_Channel_2: TIM Channel 2 |
mbed_official | 130:1dec54e4aec3 | 1936 | * @arg TIM_Channel_3: TIM Channel 3 |
mbed_official | 130:1dec54e4aec3 | 1937 | * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. |
mbed_official | 130:1dec54e4aec3 | 1938 | * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. |
mbed_official | 130:1dec54e4aec3 | 1939 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1940 | */ |
mbed_official | 130:1dec54e4aec3 | 1941 | void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) |
mbed_official | 130:1dec54e4aec3 | 1942 | { |
mbed_official | 130:1dec54e4aec3 | 1943 | uint16_t tmp = 0; |
mbed_official | 130:1dec54e4aec3 | 1944 | |
mbed_official | 130:1dec54e4aec3 | 1945 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1946 | assert_param(IS_TIM_LIST2_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1947 | assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); |
mbed_official | 130:1dec54e4aec3 | 1948 | assert_param(IS_TIM_CCXN(TIM_CCxN)); |
mbed_official | 130:1dec54e4aec3 | 1949 | |
mbed_official | 130:1dec54e4aec3 | 1950 | tmp = CCER_CCNE_SET << TIM_Channel; |
mbed_official | 130:1dec54e4aec3 | 1951 | |
mbed_official | 130:1dec54e4aec3 | 1952 | /* Reset the CCxNE Bit */ |
mbed_official | 130:1dec54e4aec3 | 1953 | TIMx->CCER &= (uint16_t) ~tmp; |
mbed_official | 130:1dec54e4aec3 | 1954 | |
mbed_official | 130:1dec54e4aec3 | 1955 | /* Set or reset the CCxNE Bit */ |
mbed_official | 130:1dec54e4aec3 | 1956 | TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); |
mbed_official | 130:1dec54e4aec3 | 1957 | } |
mbed_official | 130:1dec54e4aec3 | 1958 | |
mbed_official | 130:1dec54e4aec3 | 1959 | /** |
mbed_official | 130:1dec54e4aec3 | 1960 | * @brief Selects the TIM peripheral Commutation event. |
mbed_official | 130:1dec54e4aec3 | 1961 | * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIMx peripheral |
mbed_official | 130:1dec54e4aec3 | 1962 | * @param NewState: new state of the Commutation event. |
mbed_official | 130:1dec54e4aec3 | 1963 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 130:1dec54e4aec3 | 1964 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 1965 | */ |
mbed_official | 130:1dec54e4aec3 | 1966 | void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) |
mbed_official | 130:1dec54e4aec3 | 1967 | { |
mbed_official | 130:1dec54e4aec3 | 1968 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 1969 | assert_param(IS_TIM_LIST2_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 1970 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 130:1dec54e4aec3 | 1971 | if (NewState != DISABLE) |
mbed_official | 130:1dec54e4aec3 | 1972 | { |
mbed_official | 130:1dec54e4aec3 | 1973 | /* Set the COM Bit */ |
mbed_official | 130:1dec54e4aec3 | 1974 | TIMx->CR2 |= TIM_CR2_CCUS; |
mbed_official | 130:1dec54e4aec3 | 1975 | } |
mbed_official | 130:1dec54e4aec3 | 1976 | else |
mbed_official | 130:1dec54e4aec3 | 1977 | { |
mbed_official | 130:1dec54e4aec3 | 1978 | /* Reset the COM Bit */ |
mbed_official | 130:1dec54e4aec3 | 1979 | TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS); |
mbed_official | 130:1dec54e4aec3 | 1980 | } |
mbed_official | 130:1dec54e4aec3 | 1981 | } |
mbed_official | 130:1dec54e4aec3 | 1982 | |
mbed_official | 130:1dec54e4aec3 | 1983 | /** |
mbed_official | 130:1dec54e4aec3 | 1984 | * @} |
mbed_official | 130:1dec54e4aec3 | 1985 | */ |
mbed_official | 130:1dec54e4aec3 | 1986 | |
mbed_official | 130:1dec54e4aec3 | 1987 | /** @defgroup TIM_Group4 Input Capture management functions |
mbed_official | 130:1dec54e4aec3 | 1988 | * @brief Input Capture management functions |
mbed_official | 130:1dec54e4aec3 | 1989 | * |
mbed_official | 130:1dec54e4aec3 | 1990 | @verbatim |
mbed_official | 130:1dec54e4aec3 | 1991 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 1992 | ##### Input Capture management functions ##### |
mbed_official | 130:1dec54e4aec3 | 1993 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 1994 | |
mbed_official | 130:1dec54e4aec3 | 1995 | *** TIM Driver: how to use it in Input Capture Mode *** |
mbed_official | 130:1dec54e4aec3 | 1996 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 1997 | [..] To use the Timer in Input Capture mode, the following steps are mandatory: |
mbed_official | 130:1dec54e4aec3 | 1998 | (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) |
mbed_official | 130:1dec54e4aec3 | 1999 | function. |
mbed_official | 130:1dec54e4aec3 | 2000 | (#) Configure the TIM pins by configuring the corresponding GPIO pins. |
mbed_official | 130:1dec54e4aec3 | 2001 | (#) Configure the Time base unit as described in the first part of this |
mbed_official | 130:1dec54e4aec3 | 2002 | driver, if needed, else the Timer will run with the default configuration: |
mbed_official | 130:1dec54e4aec3 | 2003 | (++) Autoreload value = 0xFFFF. |
mbed_official | 130:1dec54e4aec3 | 2004 | (++) Prescaler value = 0x0000. |
mbed_official | 130:1dec54e4aec3 | 2005 | (++) Counter mode = Up counting. |
mbed_official | 130:1dec54e4aec3 | 2006 | (++) Clock Division = TIM_CKD_DIV1. |
mbed_official | 130:1dec54e4aec3 | 2007 | (#) Fill the TIM_ICInitStruct with the desired parameters including: |
mbed_official | 130:1dec54e4aec3 | 2008 | (++) TIM Channel: TIM_Channel. |
mbed_official | 130:1dec54e4aec3 | 2009 | (++) TIM Input Capture polarity: TIM_ICPolarity. |
mbed_official | 130:1dec54e4aec3 | 2010 | (++) TIM Input Capture selection: TIM_ICSelection. |
mbed_official | 130:1dec54e4aec3 | 2011 | (++) TIM Input Capture Prescaler: TIM_ICPrescaler. |
mbed_official | 130:1dec54e4aec3 | 2012 | (++) TIM Input CApture filter value: TIM_ICFilter. |
mbed_official | 130:1dec54e4aec3 | 2013 | (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired |
mbed_official | 130:1dec54e4aec3 | 2014 | channel with the corresponding configuration and to measure only |
mbed_official | 130:1dec54e4aec3 | 2015 | frequency or duty cycle of the input signal,or, Call |
mbed_official | 130:1dec54e4aec3 | 2016 | TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired |
mbed_official | 130:1dec54e4aec3 | 2017 | channels with the corresponding configuration and to measure the |
mbed_official | 130:1dec54e4aec3 | 2018 | frequency and the duty cycle of the input signal. |
mbed_official | 130:1dec54e4aec3 | 2019 | (#) Enable the NVIC or the DMA to read the measured frequency. |
mbed_official | 130:1dec54e4aec3 | 2020 | (#) Enable the corresponding interrupt (or DMA request) to read |
mbed_official | 130:1dec54e4aec3 | 2021 | the Captured value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx) |
mbed_official | 130:1dec54e4aec3 | 2022 | (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)). |
mbed_official | 130:1dec54e4aec3 | 2023 | (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. |
mbed_official | 130:1dec54e4aec3 | 2024 | (#) Use TIM_GetCapturex(TIMx); to read the captured value. |
mbed_official | 130:1dec54e4aec3 | 2025 | [..] |
mbed_official | 130:1dec54e4aec3 | 2026 | (@) All other functions can be used separately to modify, if needed, |
mbed_official | 130:1dec54e4aec3 | 2027 | a specific feature of the Timer. |
mbed_official | 130:1dec54e4aec3 | 2028 | |
mbed_official | 130:1dec54e4aec3 | 2029 | @endverbatim |
mbed_official | 130:1dec54e4aec3 | 2030 | * @{ |
mbed_official | 130:1dec54e4aec3 | 2031 | */ |
mbed_official | 130:1dec54e4aec3 | 2032 | |
mbed_official | 130:1dec54e4aec3 | 2033 | /** |
mbed_official | 130:1dec54e4aec3 | 2034 | * @brief Initializes the TIM peripheral according to the specified |
mbed_official | 130:1dec54e4aec3 | 2035 | * parameters in the TIM_ICInitStruct. |
mbed_official | 130:1dec54e4aec3 | 2036 | * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2037 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2038 | * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure |
mbed_official | 130:1dec54e4aec3 | 2039 | * that contains the configuration information for the specified TIM |
mbed_official | 130:1dec54e4aec3 | 2040 | * peripheral. |
mbed_official | 130:1dec54e4aec3 | 2041 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 2042 | */ |
mbed_official | 130:1dec54e4aec3 | 2043 | void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) |
mbed_official | 130:1dec54e4aec3 | 2044 | { |
mbed_official | 130:1dec54e4aec3 | 2045 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2046 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2047 | assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); |
mbed_official | 130:1dec54e4aec3 | 2048 | assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); |
mbed_official | 130:1dec54e4aec3 | 2049 | assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); |
mbed_official | 130:1dec54e4aec3 | 2050 | assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); |
mbed_official | 130:1dec54e4aec3 | 2051 | assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); |
mbed_official | 130:1dec54e4aec3 | 2052 | |
mbed_official | 130:1dec54e4aec3 | 2053 | if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) |
mbed_official | 130:1dec54e4aec3 | 2054 | { |
mbed_official | 130:1dec54e4aec3 | 2055 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2056 | /* TI1 Configuration */ |
mbed_official | 130:1dec54e4aec3 | 2057 | TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, |
mbed_official | 130:1dec54e4aec3 | 2058 | TIM_ICInitStruct->TIM_ICSelection, |
mbed_official | 130:1dec54e4aec3 | 2059 | TIM_ICInitStruct->TIM_ICFilter); |
mbed_official | 130:1dec54e4aec3 | 2060 | /* Set the Input Capture Prescaler value */ |
mbed_official | 130:1dec54e4aec3 | 2061 | TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); |
mbed_official | 130:1dec54e4aec3 | 2062 | } |
mbed_official | 130:1dec54e4aec3 | 2063 | else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) |
mbed_official | 130:1dec54e4aec3 | 2064 | { |
mbed_official | 130:1dec54e4aec3 | 2065 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2066 | /* TI2 Configuration */ |
mbed_official | 130:1dec54e4aec3 | 2067 | TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, |
mbed_official | 130:1dec54e4aec3 | 2068 | TIM_ICInitStruct->TIM_ICSelection, |
mbed_official | 130:1dec54e4aec3 | 2069 | TIM_ICInitStruct->TIM_ICFilter); |
mbed_official | 130:1dec54e4aec3 | 2070 | /* Set the Input Capture Prescaler value */ |
mbed_official | 130:1dec54e4aec3 | 2071 | TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); |
mbed_official | 130:1dec54e4aec3 | 2072 | } |
mbed_official | 130:1dec54e4aec3 | 2073 | else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) |
mbed_official | 130:1dec54e4aec3 | 2074 | { |
mbed_official | 130:1dec54e4aec3 | 2075 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2076 | /* TI3 Configuration */ |
mbed_official | 130:1dec54e4aec3 | 2077 | TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, |
mbed_official | 130:1dec54e4aec3 | 2078 | TIM_ICInitStruct->TIM_ICSelection, |
mbed_official | 130:1dec54e4aec3 | 2079 | TIM_ICInitStruct->TIM_ICFilter); |
mbed_official | 130:1dec54e4aec3 | 2080 | /* Set the Input Capture Prescaler value */ |
mbed_official | 130:1dec54e4aec3 | 2081 | TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); |
mbed_official | 130:1dec54e4aec3 | 2082 | } |
mbed_official | 130:1dec54e4aec3 | 2083 | else |
mbed_official | 130:1dec54e4aec3 | 2084 | { |
mbed_official | 130:1dec54e4aec3 | 2085 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2086 | /* TI4 Configuration */ |
mbed_official | 130:1dec54e4aec3 | 2087 | TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, |
mbed_official | 130:1dec54e4aec3 | 2088 | TIM_ICInitStruct->TIM_ICSelection, |
mbed_official | 130:1dec54e4aec3 | 2089 | TIM_ICInitStruct->TIM_ICFilter); |
mbed_official | 130:1dec54e4aec3 | 2090 | /* Set the Input Capture Prescaler value */ |
mbed_official | 130:1dec54e4aec3 | 2091 | TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); |
mbed_official | 130:1dec54e4aec3 | 2092 | } |
mbed_official | 130:1dec54e4aec3 | 2093 | } |
mbed_official | 130:1dec54e4aec3 | 2094 | |
mbed_official | 130:1dec54e4aec3 | 2095 | /** |
mbed_official | 130:1dec54e4aec3 | 2096 | * @brief Fills each TIM_ICInitStruct member with its default value. |
mbed_official | 130:1dec54e4aec3 | 2097 | * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will |
mbed_official | 130:1dec54e4aec3 | 2098 | * be initialized. |
mbed_official | 130:1dec54e4aec3 | 2099 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 2100 | */ |
mbed_official | 130:1dec54e4aec3 | 2101 | void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) |
mbed_official | 130:1dec54e4aec3 | 2102 | { |
mbed_official | 130:1dec54e4aec3 | 2103 | /* Set the default configuration */ |
mbed_official | 130:1dec54e4aec3 | 2104 | TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; |
mbed_official | 130:1dec54e4aec3 | 2105 | TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; |
mbed_official | 130:1dec54e4aec3 | 2106 | TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; |
mbed_official | 130:1dec54e4aec3 | 2107 | TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; |
mbed_official | 130:1dec54e4aec3 | 2108 | TIM_ICInitStruct->TIM_ICFilter = 0x00; |
mbed_official | 130:1dec54e4aec3 | 2109 | } |
mbed_official | 130:1dec54e4aec3 | 2110 | |
mbed_official | 130:1dec54e4aec3 | 2111 | /** |
mbed_official | 130:1dec54e4aec3 | 2112 | * @brief Configures the TIM peripheral according to the specified |
mbed_official | 130:1dec54e4aec3 | 2113 | * parameters in the TIM_ICInitStruct to measure an external PWM signal. |
mbed_official | 130:1dec54e4aec3 | 2114 | * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2115 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2116 | * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure |
mbed_official | 130:1dec54e4aec3 | 2117 | * that contains the configuration information for the specified TIM |
mbed_official | 130:1dec54e4aec3 | 2118 | * peripheral. |
mbed_official | 130:1dec54e4aec3 | 2119 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 2120 | */ |
mbed_official | 130:1dec54e4aec3 | 2121 | void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) |
mbed_official | 130:1dec54e4aec3 | 2122 | { |
mbed_official | 130:1dec54e4aec3 | 2123 | uint16_t icoppositepolarity = TIM_ICPolarity_Rising; |
mbed_official | 130:1dec54e4aec3 | 2124 | uint16_t icoppositeselection = TIM_ICSelection_DirectTI; |
mbed_official | 130:1dec54e4aec3 | 2125 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2126 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2127 | /* Select the Opposite Input Polarity */ |
mbed_official | 130:1dec54e4aec3 | 2128 | if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) |
mbed_official | 130:1dec54e4aec3 | 2129 | { |
mbed_official | 130:1dec54e4aec3 | 2130 | icoppositepolarity = TIM_ICPolarity_Falling; |
mbed_official | 130:1dec54e4aec3 | 2131 | } |
mbed_official | 130:1dec54e4aec3 | 2132 | else |
mbed_official | 130:1dec54e4aec3 | 2133 | { |
mbed_official | 130:1dec54e4aec3 | 2134 | icoppositepolarity = TIM_ICPolarity_Rising; |
mbed_official | 130:1dec54e4aec3 | 2135 | } |
mbed_official | 130:1dec54e4aec3 | 2136 | /* Select the Opposite Input */ |
mbed_official | 130:1dec54e4aec3 | 2137 | if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) |
mbed_official | 130:1dec54e4aec3 | 2138 | { |
mbed_official | 130:1dec54e4aec3 | 2139 | icoppositeselection = TIM_ICSelection_IndirectTI; |
mbed_official | 130:1dec54e4aec3 | 2140 | } |
mbed_official | 130:1dec54e4aec3 | 2141 | else |
mbed_official | 130:1dec54e4aec3 | 2142 | { |
mbed_official | 130:1dec54e4aec3 | 2143 | icoppositeselection = TIM_ICSelection_DirectTI; |
mbed_official | 130:1dec54e4aec3 | 2144 | } |
mbed_official | 130:1dec54e4aec3 | 2145 | if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) |
mbed_official | 130:1dec54e4aec3 | 2146 | { |
mbed_official | 130:1dec54e4aec3 | 2147 | /* TI1 Configuration */ |
mbed_official | 130:1dec54e4aec3 | 2148 | TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, |
mbed_official | 130:1dec54e4aec3 | 2149 | TIM_ICInitStruct->TIM_ICFilter); |
mbed_official | 130:1dec54e4aec3 | 2150 | /* Set the Input Capture Prescaler value */ |
mbed_official | 130:1dec54e4aec3 | 2151 | TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); |
mbed_official | 130:1dec54e4aec3 | 2152 | /* TI2 Configuration */ |
mbed_official | 130:1dec54e4aec3 | 2153 | TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); |
mbed_official | 130:1dec54e4aec3 | 2154 | /* Set the Input Capture Prescaler value */ |
mbed_official | 130:1dec54e4aec3 | 2155 | TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); |
mbed_official | 130:1dec54e4aec3 | 2156 | } |
mbed_official | 130:1dec54e4aec3 | 2157 | else |
mbed_official | 130:1dec54e4aec3 | 2158 | { |
mbed_official | 130:1dec54e4aec3 | 2159 | /* TI2 Configuration */ |
mbed_official | 130:1dec54e4aec3 | 2160 | TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, |
mbed_official | 130:1dec54e4aec3 | 2161 | TIM_ICInitStruct->TIM_ICFilter); |
mbed_official | 130:1dec54e4aec3 | 2162 | /* Set the Input Capture Prescaler value */ |
mbed_official | 130:1dec54e4aec3 | 2163 | TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); |
mbed_official | 130:1dec54e4aec3 | 2164 | /* TI1 Configuration */ |
mbed_official | 130:1dec54e4aec3 | 2165 | TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); |
mbed_official | 130:1dec54e4aec3 | 2166 | /* Set the Input Capture Prescaler value */ |
mbed_official | 130:1dec54e4aec3 | 2167 | TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); |
mbed_official | 130:1dec54e4aec3 | 2168 | } |
mbed_official | 130:1dec54e4aec3 | 2169 | } |
mbed_official | 130:1dec54e4aec3 | 2170 | |
mbed_official | 130:1dec54e4aec3 | 2171 | /** |
mbed_official | 130:1dec54e4aec3 | 2172 | * @brief Gets the TIMx Input Capture 1 value. |
mbed_official | 130:1dec54e4aec3 | 2173 | * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2174 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2175 | * @retval Capture Compare 1 Register value. |
mbed_official | 130:1dec54e4aec3 | 2176 | */ |
mbed_official | 130:1dec54e4aec3 | 2177 | uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx) |
mbed_official | 130:1dec54e4aec3 | 2178 | { |
mbed_official | 130:1dec54e4aec3 | 2179 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2180 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2181 | |
mbed_official | 130:1dec54e4aec3 | 2182 | /* Get the Capture 1 Register value */ |
mbed_official | 130:1dec54e4aec3 | 2183 | return TIMx->CCR1; |
mbed_official | 130:1dec54e4aec3 | 2184 | } |
mbed_official | 130:1dec54e4aec3 | 2185 | |
mbed_official | 130:1dec54e4aec3 | 2186 | /** |
mbed_official | 130:1dec54e4aec3 | 2187 | * @brief Gets the TIMx Input Capture 2 value. |
mbed_official | 130:1dec54e4aec3 | 2188 | * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2189 | * @retval Capture Compare 2 Register value. |
mbed_official | 130:1dec54e4aec3 | 2190 | */ |
mbed_official | 130:1dec54e4aec3 | 2191 | uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx) |
mbed_official | 130:1dec54e4aec3 | 2192 | { |
mbed_official | 130:1dec54e4aec3 | 2193 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2194 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2195 | |
mbed_official | 130:1dec54e4aec3 | 2196 | /* Get the Capture 2 Register value */ |
mbed_official | 130:1dec54e4aec3 | 2197 | return TIMx->CCR2; |
mbed_official | 130:1dec54e4aec3 | 2198 | } |
mbed_official | 130:1dec54e4aec3 | 2199 | |
mbed_official | 130:1dec54e4aec3 | 2200 | /** |
mbed_official | 130:1dec54e4aec3 | 2201 | * @brief Gets the TIMx Input Capture 3 value. |
mbed_official | 130:1dec54e4aec3 | 2202 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2203 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2204 | * @retval Capture Compare 3 Register value. |
mbed_official | 130:1dec54e4aec3 | 2205 | */ |
mbed_official | 130:1dec54e4aec3 | 2206 | uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx) |
mbed_official | 130:1dec54e4aec3 | 2207 | { |
mbed_official | 130:1dec54e4aec3 | 2208 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2209 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2210 | |
mbed_official | 130:1dec54e4aec3 | 2211 | /* Get the Capture 3 Register value */ |
mbed_official | 130:1dec54e4aec3 | 2212 | return TIMx->CCR3; |
mbed_official | 130:1dec54e4aec3 | 2213 | } |
mbed_official | 130:1dec54e4aec3 | 2214 | |
mbed_official | 130:1dec54e4aec3 | 2215 | /** |
mbed_official | 130:1dec54e4aec3 | 2216 | * @brief Gets the TIMx Input Capture 4 value. |
mbed_official | 130:1dec54e4aec3 | 2217 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2218 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2219 | * @retval Capture Compare 4 Register value. |
mbed_official | 130:1dec54e4aec3 | 2220 | */ |
mbed_official | 130:1dec54e4aec3 | 2221 | uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx) |
mbed_official | 130:1dec54e4aec3 | 2222 | { |
mbed_official | 130:1dec54e4aec3 | 2223 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2224 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2225 | |
mbed_official | 130:1dec54e4aec3 | 2226 | /* Get the Capture 4 Register value */ |
mbed_official | 130:1dec54e4aec3 | 2227 | return TIMx->CCR4; |
mbed_official | 130:1dec54e4aec3 | 2228 | } |
mbed_official | 130:1dec54e4aec3 | 2229 | |
mbed_official | 130:1dec54e4aec3 | 2230 | /** |
mbed_official | 130:1dec54e4aec3 | 2231 | * @brief Sets the TIMx Input Capture 1 prescaler. |
mbed_official | 130:1dec54e4aec3 | 2232 | * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2233 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2234 | * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. |
mbed_official | 130:1dec54e4aec3 | 2235 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 2236 | * @arg TIM_ICPSC_DIV1: no prescaler |
mbed_official | 130:1dec54e4aec3 | 2237 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
mbed_official | 130:1dec54e4aec3 | 2238 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
mbed_official | 130:1dec54e4aec3 | 2239 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
mbed_official | 130:1dec54e4aec3 | 2240 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 2241 | */ |
mbed_official | 130:1dec54e4aec3 | 2242 | void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) |
mbed_official | 130:1dec54e4aec3 | 2243 | { |
mbed_official | 130:1dec54e4aec3 | 2244 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2245 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2246 | assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); |
mbed_official | 130:1dec54e4aec3 | 2247 | |
mbed_official | 130:1dec54e4aec3 | 2248 | /* Reset the IC1PSC Bits */ |
mbed_official | 130:1dec54e4aec3 | 2249 | TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC); |
mbed_official | 130:1dec54e4aec3 | 2250 | /* Set the IC1PSC value */ |
mbed_official | 130:1dec54e4aec3 | 2251 | TIMx->CCMR1 |= TIM_ICPSC; |
mbed_official | 130:1dec54e4aec3 | 2252 | } |
mbed_official | 130:1dec54e4aec3 | 2253 | |
mbed_official | 130:1dec54e4aec3 | 2254 | /** |
mbed_official | 130:1dec54e4aec3 | 2255 | * @brief Sets the TIMx Input Capture 2 prescaler. |
mbed_official | 130:1dec54e4aec3 | 2256 | * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2257 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2258 | * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. |
mbed_official | 130:1dec54e4aec3 | 2259 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 2260 | * @arg TIM_ICPSC_DIV1: no prescaler |
mbed_official | 130:1dec54e4aec3 | 2261 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
mbed_official | 130:1dec54e4aec3 | 2262 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
mbed_official | 130:1dec54e4aec3 | 2263 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
mbed_official | 130:1dec54e4aec3 | 2264 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 2265 | */ |
mbed_official | 130:1dec54e4aec3 | 2266 | void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) |
mbed_official | 130:1dec54e4aec3 | 2267 | { |
mbed_official | 130:1dec54e4aec3 | 2268 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2269 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2270 | assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); |
mbed_official | 130:1dec54e4aec3 | 2271 | |
mbed_official | 130:1dec54e4aec3 | 2272 | /* Reset the IC2PSC Bits */ |
mbed_official | 130:1dec54e4aec3 | 2273 | TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC); |
mbed_official | 130:1dec54e4aec3 | 2274 | /* Set the IC2PSC value */ |
mbed_official | 130:1dec54e4aec3 | 2275 | TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); |
mbed_official | 130:1dec54e4aec3 | 2276 | } |
mbed_official | 130:1dec54e4aec3 | 2277 | |
mbed_official | 130:1dec54e4aec3 | 2278 | /** |
mbed_official | 130:1dec54e4aec3 | 2279 | * @brief Sets the TIMx Input Capture 3 prescaler. |
mbed_official | 130:1dec54e4aec3 | 2280 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2281 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2282 | * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. |
mbed_official | 130:1dec54e4aec3 | 2283 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 2284 | * @arg TIM_ICPSC_DIV1: no prescaler |
mbed_official | 130:1dec54e4aec3 | 2285 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
mbed_official | 130:1dec54e4aec3 | 2286 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
mbed_official | 130:1dec54e4aec3 | 2287 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
mbed_official | 130:1dec54e4aec3 | 2288 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 2289 | */ |
mbed_official | 130:1dec54e4aec3 | 2290 | void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) |
mbed_official | 130:1dec54e4aec3 | 2291 | { |
mbed_official | 130:1dec54e4aec3 | 2292 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2293 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2294 | assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); |
mbed_official | 130:1dec54e4aec3 | 2295 | |
mbed_official | 130:1dec54e4aec3 | 2296 | /* Reset the IC3PSC Bits */ |
mbed_official | 130:1dec54e4aec3 | 2297 | TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC); |
mbed_official | 130:1dec54e4aec3 | 2298 | /* Set the IC3PSC value */ |
mbed_official | 130:1dec54e4aec3 | 2299 | TIMx->CCMR2 |= TIM_ICPSC; |
mbed_official | 130:1dec54e4aec3 | 2300 | } |
mbed_official | 130:1dec54e4aec3 | 2301 | |
mbed_official | 130:1dec54e4aec3 | 2302 | /** |
mbed_official | 130:1dec54e4aec3 | 2303 | * @brief Sets the TIMx Input Capture 4 prescaler. |
mbed_official | 130:1dec54e4aec3 | 2304 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2305 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2306 | * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. |
mbed_official | 130:1dec54e4aec3 | 2307 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 2308 | * @arg TIM_ICPSC_DIV1: no prescaler |
mbed_official | 130:1dec54e4aec3 | 2309 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
mbed_official | 130:1dec54e4aec3 | 2310 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
mbed_official | 130:1dec54e4aec3 | 2311 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
mbed_official | 130:1dec54e4aec3 | 2312 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 2313 | */ |
mbed_official | 130:1dec54e4aec3 | 2314 | void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) |
mbed_official | 130:1dec54e4aec3 | 2315 | { |
mbed_official | 130:1dec54e4aec3 | 2316 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2317 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2318 | assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); |
mbed_official | 130:1dec54e4aec3 | 2319 | |
mbed_official | 130:1dec54e4aec3 | 2320 | /* Reset the IC4PSC Bits */ |
mbed_official | 130:1dec54e4aec3 | 2321 | TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC); |
mbed_official | 130:1dec54e4aec3 | 2322 | /* Set the IC4PSC value */ |
mbed_official | 130:1dec54e4aec3 | 2323 | TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); |
mbed_official | 130:1dec54e4aec3 | 2324 | } |
mbed_official | 130:1dec54e4aec3 | 2325 | |
mbed_official | 130:1dec54e4aec3 | 2326 | /** |
mbed_official | 130:1dec54e4aec3 | 2327 | * @} |
mbed_official | 130:1dec54e4aec3 | 2328 | */ |
mbed_official | 130:1dec54e4aec3 | 2329 | |
mbed_official | 130:1dec54e4aec3 | 2330 | /** @defgroup TIM_Group5 Interrupts DMA and flags management functions |
mbed_official | 130:1dec54e4aec3 | 2331 | * @brief Interrupts, DMA and flags management functions |
mbed_official | 130:1dec54e4aec3 | 2332 | * |
mbed_official | 130:1dec54e4aec3 | 2333 | @verbatim |
mbed_official | 130:1dec54e4aec3 | 2334 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 2335 | ##### Interrupts, DMA and flags management functions ##### |
mbed_official | 130:1dec54e4aec3 | 2336 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 2337 | |
mbed_official | 130:1dec54e4aec3 | 2338 | @endverbatim |
mbed_official | 130:1dec54e4aec3 | 2339 | * @{ |
mbed_official | 130:1dec54e4aec3 | 2340 | */ |
mbed_official | 130:1dec54e4aec3 | 2341 | |
mbed_official | 130:1dec54e4aec3 | 2342 | /** |
mbed_official | 130:1dec54e4aec3 | 2343 | * @brief Enables or disables the specified TIM interrupts. |
mbed_official | 130:1dec54e4aec3 | 2344 | * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIMx peripheral. |
mbed_official | 130:1dec54e4aec3 | 2345 | * @note TIM7 is applicable only for STM32F072 devices |
mbed_official | 130:1dec54e4aec3 | 2346 | * @note TIM6 is not applivable for STM32F031 devices. |
mbed_official | 130:1dec54e4aec3 | 2347 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2348 | * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. |
mbed_official | 130:1dec54e4aec3 | 2349 | * This parameter can be any combination of the following values: |
mbed_official | 130:1dec54e4aec3 | 2350 | * @arg TIM_IT_Update: TIM update Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2351 | * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2352 | * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2353 | * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2354 | * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2355 | * @arg TIM_IT_COM: TIM Commutation Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2356 | * @arg TIM_IT_Trigger: TIM Trigger Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2357 | * @arg TIM_IT_Break: TIM Break Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2358 | * |
mbed_official | 130:1dec54e4aec3 | 2359 | * @note TIM6 and TIM7 can only generate an update interrupt. |
mbed_official | 130:1dec54e4aec3 | 2360 | * @note TIM15 can have only TIM_IT_Update, TIM_IT_CC1,TIM_IT_CC2 or TIM_IT_Trigger. |
mbed_official | 130:1dec54e4aec3 | 2361 | * @note TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. |
mbed_official | 130:1dec54e4aec3 | 2362 | * @note TIM_IT_Break is used only with TIM1 and TIM15. |
mbed_official | 130:1dec54e4aec3 | 2363 | * @note TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17. |
mbed_official | 130:1dec54e4aec3 | 2364 | * |
mbed_official | 130:1dec54e4aec3 | 2365 | * @param NewState: new state of the TIM interrupts. |
mbed_official | 130:1dec54e4aec3 | 2366 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 130:1dec54e4aec3 | 2367 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 2368 | */ |
mbed_official | 130:1dec54e4aec3 | 2369 | void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) |
mbed_official | 130:1dec54e4aec3 | 2370 | { |
mbed_official | 130:1dec54e4aec3 | 2371 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2372 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2373 | assert_param(IS_TIM_IT(TIM_IT)); |
mbed_official | 130:1dec54e4aec3 | 2374 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 130:1dec54e4aec3 | 2375 | |
mbed_official | 130:1dec54e4aec3 | 2376 | if (NewState != DISABLE) |
mbed_official | 130:1dec54e4aec3 | 2377 | { |
mbed_official | 130:1dec54e4aec3 | 2378 | /* Enable the Interrupt sources */ |
mbed_official | 130:1dec54e4aec3 | 2379 | TIMx->DIER |= TIM_IT; |
mbed_official | 130:1dec54e4aec3 | 2380 | } |
mbed_official | 130:1dec54e4aec3 | 2381 | else |
mbed_official | 130:1dec54e4aec3 | 2382 | { |
mbed_official | 130:1dec54e4aec3 | 2383 | /* Disable the Interrupt sources */ |
mbed_official | 130:1dec54e4aec3 | 2384 | TIMx->DIER &= (uint16_t)~TIM_IT; |
mbed_official | 130:1dec54e4aec3 | 2385 | } |
mbed_official | 130:1dec54e4aec3 | 2386 | } |
mbed_official | 130:1dec54e4aec3 | 2387 | |
mbed_official | 130:1dec54e4aec3 | 2388 | /** |
mbed_official | 130:1dec54e4aec3 | 2389 | * @brief Configures the TIMx event to be generate by software. |
mbed_official | 130:1dec54e4aec3 | 2390 | * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the |
mbed_official | 130:1dec54e4aec3 | 2391 | * TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2392 | * @note TIM7 is applicable only for STM32F072 devices |
mbed_official | 130:1dec54e4aec3 | 2393 | * @note TIM6 is not applivable for STM32F031 devices. |
mbed_official | 130:1dec54e4aec3 | 2394 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2395 | * @param TIM_EventSource: specifies the event source. |
mbed_official | 130:1dec54e4aec3 | 2396 | * This parameter can be one or more of the following values: |
mbed_official | 130:1dec54e4aec3 | 2397 | * @arg TIM_EventSource_Update: Timer update Event source |
mbed_official | 130:1dec54e4aec3 | 2398 | * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source |
mbed_official | 130:1dec54e4aec3 | 2399 | * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source |
mbed_official | 130:1dec54e4aec3 | 2400 | * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source |
mbed_official | 130:1dec54e4aec3 | 2401 | * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source |
mbed_official | 130:1dec54e4aec3 | 2402 | * @arg TIM_EventSource_COM: Timer COM event source |
mbed_official | 130:1dec54e4aec3 | 2403 | * @arg TIM_EventSource_Trigger: Timer Trigger Event source |
mbed_official | 130:1dec54e4aec3 | 2404 | * @arg TIM_EventSource_Break: Timer Break event source |
mbed_official | 130:1dec54e4aec3 | 2405 | * |
mbed_official | 130:1dec54e4aec3 | 2406 | * @note TIM6 and TIM7 can only generate an update event. |
mbed_official | 130:1dec54e4aec3 | 2407 | * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1. |
mbed_official | 130:1dec54e4aec3 | 2408 | * |
mbed_official | 130:1dec54e4aec3 | 2409 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 2410 | */ |
mbed_official | 130:1dec54e4aec3 | 2411 | void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) |
mbed_official | 130:1dec54e4aec3 | 2412 | { |
mbed_official | 130:1dec54e4aec3 | 2413 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2414 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2415 | assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); |
mbed_official | 130:1dec54e4aec3 | 2416 | /* Set the event sources */ |
mbed_official | 130:1dec54e4aec3 | 2417 | TIMx->EGR = TIM_EventSource; |
mbed_official | 130:1dec54e4aec3 | 2418 | } |
mbed_official | 130:1dec54e4aec3 | 2419 | |
mbed_official | 130:1dec54e4aec3 | 2420 | /** |
mbed_official | 130:1dec54e4aec3 | 2421 | * @brief Checks whether the specified TIM flag is set or not. |
mbed_official | 130:1dec54e4aec3 | 2422 | * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2423 | * @note TIM7 is applicable only for STM32F072 devices |
mbed_official | 130:1dec54e4aec3 | 2424 | * @note TIM6 is not applivable for STM32F031 devices. |
mbed_official | 130:1dec54e4aec3 | 2425 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2426 | * @param TIM_FLAG: specifies the flag to check. |
mbed_official | 130:1dec54e4aec3 | 2427 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 2428 | * @arg TIM_FLAG_Update: TIM update Flag |
mbed_official | 130:1dec54e4aec3 | 2429 | * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag |
mbed_official | 130:1dec54e4aec3 | 2430 | * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag |
mbed_official | 130:1dec54e4aec3 | 2431 | * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag |
mbed_official | 130:1dec54e4aec3 | 2432 | * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag |
mbed_official | 130:1dec54e4aec3 | 2433 | * @arg TIM_FLAG_COM: TIM Commutation Flag |
mbed_official | 130:1dec54e4aec3 | 2434 | * @arg TIM_FLAG_Trigger: TIM Trigger Flag |
mbed_official | 130:1dec54e4aec3 | 2435 | * @arg TIM_FLAG_Break: TIM Break Flag |
mbed_official | 130:1dec54e4aec3 | 2436 | * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag |
mbed_official | 130:1dec54e4aec3 | 2437 | * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag |
mbed_official | 130:1dec54e4aec3 | 2438 | * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag |
mbed_official | 130:1dec54e4aec3 | 2439 | * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag |
mbed_official | 130:1dec54e4aec3 | 2440 | * |
mbed_official | 130:1dec54e4aec3 | 2441 | * @note TIM6 and TIM7 can have only one update flag. |
mbed_official | 130:1dec54e4aec3 | 2442 | * @note TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, TIM_FLAG_CC2 or TIM_FLAG_Trigger. |
mbed_official | 130:1dec54e4aec3 | 2443 | * @note TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. |
mbed_official | 130:1dec54e4aec3 | 2444 | * @note TIM_FLAG_Break is used only with TIM1 and TIM15. |
mbed_official | 130:1dec54e4aec3 | 2445 | * @note TIM_FLAG_COM is used only with TIM1 TIM15, TIM16 and TIM17. |
mbed_official | 130:1dec54e4aec3 | 2446 | * |
mbed_official | 130:1dec54e4aec3 | 2447 | * @retval The new state of TIM_FLAG (SET or RESET). |
mbed_official | 130:1dec54e4aec3 | 2448 | */ |
mbed_official | 130:1dec54e4aec3 | 2449 | FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) |
mbed_official | 130:1dec54e4aec3 | 2450 | { |
mbed_official | 130:1dec54e4aec3 | 2451 | ITStatus bitstatus = RESET; |
mbed_official | 130:1dec54e4aec3 | 2452 | |
mbed_official | 130:1dec54e4aec3 | 2453 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2454 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2455 | assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); |
mbed_official | 130:1dec54e4aec3 | 2456 | |
mbed_official | 130:1dec54e4aec3 | 2457 | if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) |
mbed_official | 130:1dec54e4aec3 | 2458 | { |
mbed_official | 130:1dec54e4aec3 | 2459 | bitstatus = SET; |
mbed_official | 130:1dec54e4aec3 | 2460 | } |
mbed_official | 130:1dec54e4aec3 | 2461 | else |
mbed_official | 130:1dec54e4aec3 | 2462 | { |
mbed_official | 130:1dec54e4aec3 | 2463 | bitstatus = RESET; |
mbed_official | 130:1dec54e4aec3 | 2464 | } |
mbed_official | 130:1dec54e4aec3 | 2465 | return bitstatus; |
mbed_official | 130:1dec54e4aec3 | 2466 | } |
mbed_official | 130:1dec54e4aec3 | 2467 | |
mbed_official | 130:1dec54e4aec3 | 2468 | /** |
mbed_official | 130:1dec54e4aec3 | 2469 | * @brief Clears the TIMx's pending flags. |
mbed_official | 130:1dec54e4aec3 | 2470 | * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2471 | * @note TIM7 is applicable only for STM32F072 devices |
mbed_official | 130:1dec54e4aec3 | 2472 | * @note TIM6 is not applivable for STM32F031 devices. |
mbed_official | 130:1dec54e4aec3 | 2473 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2474 | * @param TIM_FLAG: specifies the flag bit to clear. |
mbed_official | 130:1dec54e4aec3 | 2475 | * This parameter can be any combination of the following values: |
mbed_official | 130:1dec54e4aec3 | 2476 | * @arg TIM_FLAG_Update: TIM update Flag |
mbed_official | 130:1dec54e4aec3 | 2477 | * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag |
mbed_official | 130:1dec54e4aec3 | 2478 | * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag |
mbed_official | 130:1dec54e4aec3 | 2479 | * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag |
mbed_official | 130:1dec54e4aec3 | 2480 | * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag |
mbed_official | 130:1dec54e4aec3 | 2481 | * @arg TIM_FLAG_COM: TIM Commutation Flag |
mbed_official | 130:1dec54e4aec3 | 2482 | * @arg TIM_FLAG_Trigger: TIM Trigger Flag |
mbed_official | 130:1dec54e4aec3 | 2483 | * @arg TIM_FLAG_Break: TIM Break Flag |
mbed_official | 130:1dec54e4aec3 | 2484 | * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag |
mbed_official | 130:1dec54e4aec3 | 2485 | * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag |
mbed_official | 130:1dec54e4aec3 | 2486 | * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag |
mbed_official | 130:1dec54e4aec3 | 2487 | * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag |
mbed_official | 130:1dec54e4aec3 | 2488 | * |
mbed_official | 130:1dec54e4aec3 | 2489 | * @note TIM6 and TIM7 can have only one update flag. |
mbed_official | 130:1dec54e4aec3 | 2490 | * @note TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,TIM_FLAG_CC2 or |
mbed_official | 130:1dec54e4aec3 | 2491 | * TIM_FLAG_Trigger. |
mbed_official | 130:1dec54e4aec3 | 2492 | * @note TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. |
mbed_official | 130:1dec54e4aec3 | 2493 | * @note TIM_FLAG_Break is used only with TIM1 and TIM15. |
mbed_official | 130:1dec54e4aec3 | 2494 | * @note TIM_FLAG_COM is used only with TIM1, TIM15, TIM16 and TIM17. |
mbed_official | 130:1dec54e4aec3 | 2495 | * |
mbed_official | 130:1dec54e4aec3 | 2496 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 2497 | */ |
mbed_official | 130:1dec54e4aec3 | 2498 | void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) |
mbed_official | 130:1dec54e4aec3 | 2499 | { |
mbed_official | 130:1dec54e4aec3 | 2500 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2501 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2502 | assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG)); |
mbed_official | 130:1dec54e4aec3 | 2503 | |
mbed_official | 130:1dec54e4aec3 | 2504 | /* Clear the flags */ |
mbed_official | 130:1dec54e4aec3 | 2505 | TIMx->SR = (uint16_t)~TIM_FLAG; |
mbed_official | 130:1dec54e4aec3 | 2506 | } |
mbed_official | 130:1dec54e4aec3 | 2507 | |
mbed_official | 130:1dec54e4aec3 | 2508 | /** |
mbed_official | 130:1dec54e4aec3 | 2509 | * @brief Checks whether the TIM interrupt has occurred or not. |
mbed_official | 130:1dec54e4aec3 | 2510 | * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2511 | * @note TIM7 is applicable only for STM32F072 devices |
mbed_official | 130:1dec54e4aec3 | 2512 | * @note TIM6 is not applivable for STM32F031 devices. |
mbed_official | 130:1dec54e4aec3 | 2513 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2514 | * @param TIM_IT: specifies the TIM interrupt source to check. |
mbed_official | 130:1dec54e4aec3 | 2515 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 2516 | * @arg TIM_IT_Update: TIM update Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2517 | * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2518 | * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2519 | * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2520 | * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2521 | * @arg TIM_IT_COM: TIM Commutation Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2522 | * @arg TIM_IT_Trigger: TIM Trigger Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2523 | * @arg TIM_IT_Break: TIM Break Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2524 | * |
mbed_official | 130:1dec54e4aec3 | 2525 | * @note TIM6 and TIM7 can generate only an update interrupt. |
mbed_official | 130:1dec54e4aec3 | 2526 | * @note TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. |
mbed_official | 130:1dec54e4aec3 | 2527 | * @note TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. |
mbed_official | 130:1dec54e4aec3 | 2528 | * @note TIM_IT_Break is used only with TIM1 and TIM15. |
mbed_official | 130:1dec54e4aec3 | 2529 | * @note TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17. |
mbed_official | 130:1dec54e4aec3 | 2530 | * |
mbed_official | 130:1dec54e4aec3 | 2531 | * @retval The new state of the TIM_IT(SET or RESET). |
mbed_official | 130:1dec54e4aec3 | 2532 | */ |
mbed_official | 130:1dec54e4aec3 | 2533 | ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) |
mbed_official | 130:1dec54e4aec3 | 2534 | { |
mbed_official | 130:1dec54e4aec3 | 2535 | ITStatus bitstatus = RESET; |
mbed_official | 130:1dec54e4aec3 | 2536 | uint16_t itstatus = 0x0, itenable = 0x0; |
mbed_official | 130:1dec54e4aec3 | 2537 | |
mbed_official | 130:1dec54e4aec3 | 2538 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2539 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2540 | assert_param(IS_TIM_GET_IT(TIM_IT)); |
mbed_official | 130:1dec54e4aec3 | 2541 | |
mbed_official | 130:1dec54e4aec3 | 2542 | itstatus = TIMx->SR & TIM_IT; |
mbed_official | 130:1dec54e4aec3 | 2543 | |
mbed_official | 130:1dec54e4aec3 | 2544 | itenable = TIMx->DIER & TIM_IT; |
mbed_official | 130:1dec54e4aec3 | 2545 | if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) |
mbed_official | 130:1dec54e4aec3 | 2546 | { |
mbed_official | 130:1dec54e4aec3 | 2547 | bitstatus = SET; |
mbed_official | 130:1dec54e4aec3 | 2548 | } |
mbed_official | 130:1dec54e4aec3 | 2549 | else |
mbed_official | 130:1dec54e4aec3 | 2550 | { |
mbed_official | 130:1dec54e4aec3 | 2551 | bitstatus = RESET; |
mbed_official | 130:1dec54e4aec3 | 2552 | } |
mbed_official | 130:1dec54e4aec3 | 2553 | return bitstatus; |
mbed_official | 130:1dec54e4aec3 | 2554 | } |
mbed_official | 130:1dec54e4aec3 | 2555 | |
mbed_official | 130:1dec54e4aec3 | 2556 | /** |
mbed_official | 130:1dec54e4aec3 | 2557 | * @brief Clears the TIMx's interrupt pending bits. |
mbed_official | 130:1dec54e4aec3 | 2558 | * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2559 | * @note TIM7 is applicable only for STM32F072 devices |
mbed_official | 130:1dec54e4aec3 | 2560 | * @note TIM6 is not applivable for STM32F031 devices. |
mbed_official | 130:1dec54e4aec3 | 2561 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2562 | * @param TIM_IT: specifies the pending bit to clear. |
mbed_official | 130:1dec54e4aec3 | 2563 | * This parameter can be any combination of the following values: |
mbed_official | 130:1dec54e4aec3 | 2564 | * @arg TIM_IT_Update: TIM1 update Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2565 | * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2566 | * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2567 | * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2568 | * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2569 | * @arg TIM_IT_COM: TIM Commutation Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2570 | * @arg TIM_IT_Trigger: TIM Trigger Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2571 | * @arg TIM_IT_Break: TIM Break Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2572 | * |
mbed_official | 130:1dec54e4aec3 | 2573 | * @note TIM6 and TIM7 can generate only an update interrupt. |
mbed_official | 130:1dec54e4aec3 | 2574 | * @note TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. |
mbed_official | 130:1dec54e4aec3 | 2575 | * @note TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. |
mbed_official | 130:1dec54e4aec3 | 2576 | * @note TIM_IT_Break is used only with TIM1 and TIM15. |
mbed_official | 130:1dec54e4aec3 | 2577 | * @note TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17. |
mbed_official | 130:1dec54e4aec3 | 2578 | * |
mbed_official | 130:1dec54e4aec3 | 2579 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 2580 | */ |
mbed_official | 130:1dec54e4aec3 | 2581 | void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) |
mbed_official | 130:1dec54e4aec3 | 2582 | { |
mbed_official | 130:1dec54e4aec3 | 2583 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2584 | assert_param(IS_TIM_ALL_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2585 | assert_param(IS_TIM_IT(TIM_IT)); |
mbed_official | 130:1dec54e4aec3 | 2586 | |
mbed_official | 130:1dec54e4aec3 | 2587 | /* Clear the IT pending Bit */ |
mbed_official | 130:1dec54e4aec3 | 2588 | TIMx->SR = (uint16_t)~TIM_IT; |
mbed_official | 130:1dec54e4aec3 | 2589 | } |
mbed_official | 130:1dec54e4aec3 | 2590 | |
mbed_official | 130:1dec54e4aec3 | 2591 | /** |
mbed_official | 130:1dec54e4aec3 | 2592 | * @brief Configures the TIMx's DMA interface. |
mbed_official | 130:1dec54e4aec3 | 2593 | * @param TIMx: where x can be 1, 2, 3, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2594 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2595 | * @param TIM_DMABase: DMA Base address. |
mbed_official | 130:1dec54e4aec3 | 2596 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 2597 | * @arg TIM_DMABase_CR1 |
mbed_official | 130:1dec54e4aec3 | 2598 | * @arg TIM_DMABase_CR2 |
mbed_official | 130:1dec54e4aec3 | 2599 | * @arg TIM_DMABase_SMCR |
mbed_official | 130:1dec54e4aec3 | 2600 | * @arg TIM_DMABase_DIER |
mbed_official | 130:1dec54e4aec3 | 2601 | * @arg TIM_DMABase_SR |
mbed_official | 130:1dec54e4aec3 | 2602 | * @arg TIM_DMABase_EGR |
mbed_official | 130:1dec54e4aec3 | 2603 | * @arg TIM_DMABase_CCMR1 |
mbed_official | 130:1dec54e4aec3 | 2604 | * @arg TIM_DMABase_CCMR2 |
mbed_official | 130:1dec54e4aec3 | 2605 | * @arg TIM_DMABase_CCER |
mbed_official | 130:1dec54e4aec3 | 2606 | * @arg TIM_DMABase_CNT |
mbed_official | 130:1dec54e4aec3 | 2607 | * @arg TIM_DMABase_PSC |
mbed_official | 130:1dec54e4aec3 | 2608 | * @arg TIM_DMABase_ARR |
mbed_official | 130:1dec54e4aec3 | 2609 | * @arg TIM_DMABase_CCR1 |
mbed_official | 130:1dec54e4aec3 | 2610 | * @arg TIM_DMABase_CCR2 |
mbed_official | 130:1dec54e4aec3 | 2611 | * @arg TIM_DMABase_CCR3 |
mbed_official | 130:1dec54e4aec3 | 2612 | * @arg TIM_DMABase_CCR4 |
mbed_official | 130:1dec54e4aec3 | 2613 | * @arg TIM_DMABase_DCR |
mbed_official | 130:1dec54e4aec3 | 2614 | * @arg TIM_DMABase_OR |
mbed_official | 130:1dec54e4aec3 | 2615 | * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value |
mbed_official | 130:1dec54e4aec3 | 2616 | * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. |
mbed_official | 130:1dec54e4aec3 | 2617 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 2618 | */ |
mbed_official | 130:1dec54e4aec3 | 2619 | void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) |
mbed_official | 130:1dec54e4aec3 | 2620 | { |
mbed_official | 130:1dec54e4aec3 | 2621 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2622 | assert_param(IS_TIM_LIST4_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2623 | assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); |
mbed_official | 130:1dec54e4aec3 | 2624 | assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); |
mbed_official | 130:1dec54e4aec3 | 2625 | /* Set the DMA Base and the DMA Burst Length */ |
mbed_official | 130:1dec54e4aec3 | 2626 | TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; |
mbed_official | 130:1dec54e4aec3 | 2627 | } |
mbed_official | 130:1dec54e4aec3 | 2628 | |
mbed_official | 130:1dec54e4aec3 | 2629 | /** |
mbed_official | 130:1dec54e4aec3 | 2630 | * @brief Enables or disables the TIMx's DMA Requests. |
mbed_official | 130:1dec54e4aec3 | 2631 | * @param TIMx: where x can be 1, 2, 3, 6, 7, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2632 | * @note TIM7 is applicable only for STM32F072 devices |
mbed_official | 130:1dec54e4aec3 | 2633 | * @note TIM6 is not applivable for STM32F031 devices. |
mbed_official | 130:1dec54e4aec3 | 2634 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2635 | * @param TIM_DMASource: specifies the DMA Request sources. |
mbed_official | 130:1dec54e4aec3 | 2636 | * This parameter can be any combination of the following values: |
mbed_official | 130:1dec54e4aec3 | 2637 | * @arg TIM_DMA_Update: TIM update Interrupt source |
mbed_official | 130:1dec54e4aec3 | 2638 | * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source |
mbed_official | 130:1dec54e4aec3 | 2639 | * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source |
mbed_official | 130:1dec54e4aec3 | 2640 | * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source |
mbed_official | 130:1dec54e4aec3 | 2641 | * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source |
mbed_official | 130:1dec54e4aec3 | 2642 | * @arg TIM_DMA_COM: TIM Commutation DMA source |
mbed_official | 130:1dec54e4aec3 | 2643 | * @arg TIM_DMA_Trigger: TIM Trigger DMA source |
mbed_official | 130:1dec54e4aec3 | 2644 | * @param NewState: new state of the DMA Request sources. |
mbed_official | 130:1dec54e4aec3 | 2645 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 130:1dec54e4aec3 | 2646 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 2647 | */ |
mbed_official | 130:1dec54e4aec3 | 2648 | void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) |
mbed_official | 130:1dec54e4aec3 | 2649 | { |
mbed_official | 130:1dec54e4aec3 | 2650 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2651 | assert_param(IS_TIM_LIST10_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2652 | assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); |
mbed_official | 130:1dec54e4aec3 | 2653 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 130:1dec54e4aec3 | 2654 | |
mbed_official | 130:1dec54e4aec3 | 2655 | if (NewState != DISABLE) |
mbed_official | 130:1dec54e4aec3 | 2656 | { |
mbed_official | 130:1dec54e4aec3 | 2657 | /* Enable the DMA sources */ |
mbed_official | 130:1dec54e4aec3 | 2658 | TIMx->DIER |= TIM_DMASource; |
mbed_official | 130:1dec54e4aec3 | 2659 | } |
mbed_official | 130:1dec54e4aec3 | 2660 | else |
mbed_official | 130:1dec54e4aec3 | 2661 | { |
mbed_official | 130:1dec54e4aec3 | 2662 | /* Disable the DMA sources */ |
mbed_official | 130:1dec54e4aec3 | 2663 | TIMx->DIER &= (uint16_t)~TIM_DMASource; |
mbed_official | 130:1dec54e4aec3 | 2664 | } |
mbed_official | 130:1dec54e4aec3 | 2665 | } |
mbed_official | 130:1dec54e4aec3 | 2666 | |
mbed_official | 130:1dec54e4aec3 | 2667 | /** |
mbed_official | 130:1dec54e4aec3 | 2668 | * @brief Selects the TIMx peripheral Capture Compare DMA source. |
mbed_official | 130:1dec54e4aec3 | 2669 | * @param TIMx: where x can be 1, 2, 3, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2670 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2671 | * @param NewState: new state of the Capture Compare DMA source |
mbed_official | 130:1dec54e4aec3 | 2672 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 130:1dec54e4aec3 | 2673 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 2674 | */ |
mbed_official | 130:1dec54e4aec3 | 2675 | void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) |
mbed_official | 130:1dec54e4aec3 | 2676 | { |
mbed_official | 130:1dec54e4aec3 | 2677 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2678 | assert_param(IS_TIM_LIST5_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2679 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 130:1dec54e4aec3 | 2680 | |
mbed_official | 130:1dec54e4aec3 | 2681 | if (NewState != DISABLE) |
mbed_official | 130:1dec54e4aec3 | 2682 | { |
mbed_official | 130:1dec54e4aec3 | 2683 | /* Set the CCDS Bit */ |
mbed_official | 130:1dec54e4aec3 | 2684 | TIMx->CR2 |= TIM_CR2_CCDS; |
mbed_official | 130:1dec54e4aec3 | 2685 | } |
mbed_official | 130:1dec54e4aec3 | 2686 | else |
mbed_official | 130:1dec54e4aec3 | 2687 | { |
mbed_official | 130:1dec54e4aec3 | 2688 | /* Reset the CCDS Bit */ |
mbed_official | 130:1dec54e4aec3 | 2689 | TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS); |
mbed_official | 130:1dec54e4aec3 | 2690 | } |
mbed_official | 130:1dec54e4aec3 | 2691 | } |
mbed_official | 130:1dec54e4aec3 | 2692 | |
mbed_official | 130:1dec54e4aec3 | 2693 | /** |
mbed_official | 130:1dec54e4aec3 | 2694 | * @} |
mbed_official | 130:1dec54e4aec3 | 2695 | */ |
mbed_official | 130:1dec54e4aec3 | 2696 | |
mbed_official | 130:1dec54e4aec3 | 2697 | /** @defgroup TIM_Group6 Clocks management functions |
mbed_official | 130:1dec54e4aec3 | 2698 | * @brief Clocks management functions |
mbed_official | 130:1dec54e4aec3 | 2699 | * |
mbed_official | 130:1dec54e4aec3 | 2700 | @verbatim |
mbed_official | 130:1dec54e4aec3 | 2701 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 2702 | ##### Clocks management functions ##### |
mbed_official | 130:1dec54e4aec3 | 2703 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 2704 | |
mbed_official | 130:1dec54e4aec3 | 2705 | @endverbatim |
mbed_official | 130:1dec54e4aec3 | 2706 | * @{ |
mbed_official | 130:1dec54e4aec3 | 2707 | */ |
mbed_official | 130:1dec54e4aec3 | 2708 | |
mbed_official | 130:1dec54e4aec3 | 2709 | /** |
mbed_official | 130:1dec54e4aec3 | 2710 | * @brief Configures the TIMx internal Clock |
mbed_official | 130:1dec54e4aec3 | 2711 | * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2712 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2713 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 2714 | */ |
mbed_official | 130:1dec54e4aec3 | 2715 | void TIM_InternalClockConfig(TIM_TypeDef* TIMx) |
mbed_official | 130:1dec54e4aec3 | 2716 | { |
mbed_official | 130:1dec54e4aec3 | 2717 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2718 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2719 | /* Disable slave mode to clock the prescaler directly with the internal clock */ |
mbed_official | 130:1dec54e4aec3 | 2720 | TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); |
mbed_official | 130:1dec54e4aec3 | 2721 | } |
mbed_official | 130:1dec54e4aec3 | 2722 | |
mbed_official | 130:1dec54e4aec3 | 2723 | /** |
mbed_official | 130:1dec54e4aec3 | 2724 | * @brief Configures the TIMx Internal Trigger as External Clock |
mbed_official | 130:1dec54e4aec3 | 2725 | * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2726 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2727 | * @param TIM_ITRSource: Trigger source. |
mbed_official | 130:1dec54e4aec3 | 2728 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 2729 | * @arg TIM_TS_ITR0: Internal Trigger 0 |
mbed_official | 130:1dec54e4aec3 | 2730 | * @arg TIM_TS_ITR1: Internal Trigger 1 |
mbed_official | 130:1dec54e4aec3 | 2731 | * @arg TIM_TS_ITR2: Internal Trigger 2 |
mbed_official | 130:1dec54e4aec3 | 2732 | * @arg TIM_TS_ITR3: Internal Trigger 3 |
mbed_official | 130:1dec54e4aec3 | 2733 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 2734 | */ |
mbed_official | 130:1dec54e4aec3 | 2735 | void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) |
mbed_official | 130:1dec54e4aec3 | 2736 | { |
mbed_official | 130:1dec54e4aec3 | 2737 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2738 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2739 | assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); |
mbed_official | 130:1dec54e4aec3 | 2740 | /* Select the Internal Trigger */ |
mbed_official | 130:1dec54e4aec3 | 2741 | TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); |
mbed_official | 130:1dec54e4aec3 | 2742 | /* Select the External clock mode1 */ |
mbed_official | 130:1dec54e4aec3 | 2743 | TIMx->SMCR |= TIM_SlaveMode_External1; |
mbed_official | 130:1dec54e4aec3 | 2744 | } |
mbed_official | 130:1dec54e4aec3 | 2745 | |
mbed_official | 130:1dec54e4aec3 | 2746 | /** |
mbed_official | 130:1dec54e4aec3 | 2747 | * @brief Configures the TIMx Trigger as External Clock |
mbed_official | 130:1dec54e4aec3 | 2748 | * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2749 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2750 | * @param TIM_TIxExternalCLKSource: Trigger source. |
mbed_official | 130:1dec54e4aec3 | 2751 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 2752 | * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector |
mbed_official | 130:1dec54e4aec3 | 2753 | * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 |
mbed_official | 130:1dec54e4aec3 | 2754 | * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 |
mbed_official | 130:1dec54e4aec3 | 2755 | * @param TIM_ICPolarity: specifies the TIx Polarity. |
mbed_official | 130:1dec54e4aec3 | 2756 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 2757 | * @arg TIM_ICPolarity_Rising |
mbed_official | 130:1dec54e4aec3 | 2758 | * @arg TIM_ICPolarity_Falling |
mbed_official | 130:1dec54e4aec3 | 2759 | * @param ICFilter: specifies the filter value. |
mbed_official | 130:1dec54e4aec3 | 2760 | * This parameter must be a value between 0x0 and 0xF. |
mbed_official | 130:1dec54e4aec3 | 2761 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 2762 | */ |
mbed_official | 130:1dec54e4aec3 | 2763 | void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, |
mbed_official | 130:1dec54e4aec3 | 2764 | uint16_t TIM_ICPolarity, uint16_t ICFilter) |
mbed_official | 130:1dec54e4aec3 | 2765 | { |
mbed_official | 130:1dec54e4aec3 | 2766 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2767 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2768 | assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); |
mbed_official | 130:1dec54e4aec3 | 2769 | assert_param(IS_TIM_IC_FILTER(ICFilter)); |
mbed_official | 130:1dec54e4aec3 | 2770 | |
mbed_official | 130:1dec54e4aec3 | 2771 | /* Configure the Timer Input Clock Source */ |
mbed_official | 130:1dec54e4aec3 | 2772 | if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) |
mbed_official | 130:1dec54e4aec3 | 2773 | { |
mbed_official | 130:1dec54e4aec3 | 2774 | TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); |
mbed_official | 130:1dec54e4aec3 | 2775 | } |
mbed_official | 130:1dec54e4aec3 | 2776 | else |
mbed_official | 130:1dec54e4aec3 | 2777 | { |
mbed_official | 130:1dec54e4aec3 | 2778 | TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); |
mbed_official | 130:1dec54e4aec3 | 2779 | } |
mbed_official | 130:1dec54e4aec3 | 2780 | /* Select the Trigger source */ |
mbed_official | 130:1dec54e4aec3 | 2781 | TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); |
mbed_official | 130:1dec54e4aec3 | 2782 | /* Select the External clock mode1 */ |
mbed_official | 130:1dec54e4aec3 | 2783 | TIMx->SMCR |= TIM_SlaveMode_External1; |
mbed_official | 130:1dec54e4aec3 | 2784 | } |
mbed_official | 130:1dec54e4aec3 | 2785 | |
mbed_official | 130:1dec54e4aec3 | 2786 | /** |
mbed_official | 130:1dec54e4aec3 | 2787 | * @brief Configures the External clock Mode1 |
mbed_official | 130:1dec54e4aec3 | 2788 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2789 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2790 | * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. |
mbed_official | 130:1dec54e4aec3 | 2791 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 2792 | * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. |
mbed_official | 130:1dec54e4aec3 | 2793 | * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. |
mbed_official | 130:1dec54e4aec3 | 2794 | * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. |
mbed_official | 130:1dec54e4aec3 | 2795 | * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. |
mbed_official | 130:1dec54e4aec3 | 2796 | * @param TIM_ExtTRGPolarity: The external Trigger Polarity. |
mbed_official | 130:1dec54e4aec3 | 2797 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 2798 | * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. |
mbed_official | 130:1dec54e4aec3 | 2799 | * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. |
mbed_official | 130:1dec54e4aec3 | 2800 | * @param ExtTRGFilter: External Trigger Filter. |
mbed_official | 130:1dec54e4aec3 | 2801 | * This parameter must be a value between 0x00 and 0x0F |
mbed_official | 130:1dec54e4aec3 | 2802 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 2803 | */ |
mbed_official | 130:1dec54e4aec3 | 2804 | void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, |
mbed_official | 130:1dec54e4aec3 | 2805 | uint16_t ExtTRGFilter) |
mbed_official | 130:1dec54e4aec3 | 2806 | { |
mbed_official | 130:1dec54e4aec3 | 2807 | uint16_t tmpsmcr = 0; |
mbed_official | 130:1dec54e4aec3 | 2808 | |
mbed_official | 130:1dec54e4aec3 | 2809 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2810 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2811 | assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); |
mbed_official | 130:1dec54e4aec3 | 2812 | assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); |
mbed_official | 130:1dec54e4aec3 | 2813 | assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); |
mbed_official | 130:1dec54e4aec3 | 2814 | |
mbed_official | 130:1dec54e4aec3 | 2815 | /* Configure the ETR Clock source */ |
mbed_official | 130:1dec54e4aec3 | 2816 | TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); |
mbed_official | 130:1dec54e4aec3 | 2817 | |
mbed_official | 130:1dec54e4aec3 | 2818 | /* Get the TIMx SMCR register value */ |
mbed_official | 130:1dec54e4aec3 | 2819 | tmpsmcr = TIMx->SMCR; |
mbed_official | 130:1dec54e4aec3 | 2820 | /* Reset the SMS Bits */ |
mbed_official | 130:1dec54e4aec3 | 2821 | tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); |
mbed_official | 130:1dec54e4aec3 | 2822 | /* Select the External clock mode1 */ |
mbed_official | 130:1dec54e4aec3 | 2823 | tmpsmcr |= TIM_SlaveMode_External1; |
mbed_official | 130:1dec54e4aec3 | 2824 | /* Select the Trigger selection : ETRF */ |
mbed_official | 130:1dec54e4aec3 | 2825 | tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); |
mbed_official | 130:1dec54e4aec3 | 2826 | tmpsmcr |= TIM_TS_ETRF; |
mbed_official | 130:1dec54e4aec3 | 2827 | /* Write to TIMx SMCR */ |
mbed_official | 130:1dec54e4aec3 | 2828 | TIMx->SMCR = tmpsmcr; |
mbed_official | 130:1dec54e4aec3 | 2829 | } |
mbed_official | 130:1dec54e4aec3 | 2830 | |
mbed_official | 130:1dec54e4aec3 | 2831 | /** |
mbed_official | 130:1dec54e4aec3 | 2832 | * @brief Configures the External clock Mode2 |
mbed_official | 130:1dec54e4aec3 | 2833 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2834 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2835 | * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. |
mbed_official | 130:1dec54e4aec3 | 2836 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 2837 | * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. |
mbed_official | 130:1dec54e4aec3 | 2838 | * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. |
mbed_official | 130:1dec54e4aec3 | 2839 | * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. |
mbed_official | 130:1dec54e4aec3 | 2840 | * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. |
mbed_official | 130:1dec54e4aec3 | 2841 | * @param TIM_ExtTRGPolarity: The external Trigger Polarity. |
mbed_official | 130:1dec54e4aec3 | 2842 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 2843 | * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. |
mbed_official | 130:1dec54e4aec3 | 2844 | * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. |
mbed_official | 130:1dec54e4aec3 | 2845 | * @param ExtTRGFilter: External Trigger Filter. |
mbed_official | 130:1dec54e4aec3 | 2846 | * This parameter must be a value between 0x00 and 0x0F |
mbed_official | 130:1dec54e4aec3 | 2847 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 2848 | */ |
mbed_official | 130:1dec54e4aec3 | 2849 | void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, |
mbed_official | 130:1dec54e4aec3 | 2850 | uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) |
mbed_official | 130:1dec54e4aec3 | 2851 | { |
mbed_official | 130:1dec54e4aec3 | 2852 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2853 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2854 | assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); |
mbed_official | 130:1dec54e4aec3 | 2855 | assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); |
mbed_official | 130:1dec54e4aec3 | 2856 | assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); |
mbed_official | 130:1dec54e4aec3 | 2857 | |
mbed_official | 130:1dec54e4aec3 | 2858 | /* Configure the ETR Clock source */ |
mbed_official | 130:1dec54e4aec3 | 2859 | TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); |
mbed_official | 130:1dec54e4aec3 | 2860 | /* Enable the External clock mode2 */ |
mbed_official | 130:1dec54e4aec3 | 2861 | TIMx->SMCR |= TIM_SMCR_ECE; |
mbed_official | 130:1dec54e4aec3 | 2862 | } |
mbed_official | 130:1dec54e4aec3 | 2863 | |
mbed_official | 130:1dec54e4aec3 | 2864 | /** |
mbed_official | 130:1dec54e4aec3 | 2865 | * @} |
mbed_official | 130:1dec54e4aec3 | 2866 | */ |
mbed_official | 130:1dec54e4aec3 | 2867 | |
mbed_official | 130:1dec54e4aec3 | 2868 | /** @defgroup TIM_Group7 Synchronization management functions |
mbed_official | 130:1dec54e4aec3 | 2869 | * @brief Synchronization management functions |
mbed_official | 130:1dec54e4aec3 | 2870 | * |
mbed_official | 130:1dec54e4aec3 | 2871 | @verbatim |
mbed_official | 130:1dec54e4aec3 | 2872 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 2873 | ##### Synchronization management functions ##### |
mbed_official | 130:1dec54e4aec3 | 2874 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 2875 | *** TIM Driver: how to use it in synchronization Mode *** |
mbed_official | 130:1dec54e4aec3 | 2876 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 2877 | [..] Case of two/several Timers |
mbed_official | 130:1dec54e4aec3 | 2878 | (#) Configure the Master Timers using the following functions: |
mbed_official | 130:1dec54e4aec3 | 2879 | (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, |
mbed_official | 130:1dec54e4aec3 | 2880 | uint16_t TIM_TRGOSource). |
mbed_official | 130:1dec54e4aec3 | 2881 | (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, |
mbed_official | 130:1dec54e4aec3 | 2882 | uint16_t TIM_MasterSlaveMode); |
mbed_official | 130:1dec54e4aec3 | 2883 | (#) Configure the Slave Timers using the following functions: |
mbed_official | 130:1dec54e4aec3 | 2884 | (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, |
mbed_official | 130:1dec54e4aec3 | 2885 | uint16_t TIM_InputTriggerSource); |
mbed_official | 130:1dec54e4aec3 | 2886 | (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); |
mbed_official | 130:1dec54e4aec3 | 2887 | [..] Case of Timers and external trigger(ETR pin) |
mbed_official | 130:1dec54e4aec3 | 2888 | (#) Configure the Etrenal trigger using this function: |
mbed_official | 130:1dec54e4aec3 | 2889 | (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, |
mbed_official | 130:1dec54e4aec3 | 2890 | uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); |
mbed_official | 130:1dec54e4aec3 | 2891 | (#) Configure the Slave Timers using the following functions: |
mbed_official | 130:1dec54e4aec3 | 2892 | (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, |
mbed_official | 130:1dec54e4aec3 | 2893 | uint16_t TIM_InputTriggerSource); |
mbed_official | 130:1dec54e4aec3 | 2894 | (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); |
mbed_official | 130:1dec54e4aec3 | 2895 | |
mbed_official | 130:1dec54e4aec3 | 2896 | @endverbatim |
mbed_official | 130:1dec54e4aec3 | 2897 | * @{ |
mbed_official | 130:1dec54e4aec3 | 2898 | */ |
mbed_official | 130:1dec54e4aec3 | 2899 | /** |
mbed_official | 130:1dec54e4aec3 | 2900 | * @brief Selects the Input Trigger source |
mbed_official | 130:1dec54e4aec3 | 2901 | * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2902 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2903 | * @param TIM_InputTriggerSource: The Input Trigger source. |
mbed_official | 130:1dec54e4aec3 | 2904 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 2905 | * @arg TIM_TS_ITR0: Internal Trigger 0 |
mbed_official | 130:1dec54e4aec3 | 2906 | * @arg TIM_TS_ITR1: Internal Trigger 1 |
mbed_official | 130:1dec54e4aec3 | 2907 | * @arg TIM_TS_ITR2: Internal Trigger 2 |
mbed_official | 130:1dec54e4aec3 | 2908 | * @arg TIM_TS_ITR3: Internal Trigger 3 |
mbed_official | 130:1dec54e4aec3 | 2909 | * @arg TIM_TS_TI1F_ED: TI1 Edge Detector |
mbed_official | 130:1dec54e4aec3 | 2910 | * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 |
mbed_official | 130:1dec54e4aec3 | 2911 | * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 |
mbed_official | 130:1dec54e4aec3 | 2912 | * @arg TIM_TS_ETRF: External Trigger input |
mbed_official | 130:1dec54e4aec3 | 2913 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 2914 | */ |
mbed_official | 130:1dec54e4aec3 | 2915 | void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) |
mbed_official | 130:1dec54e4aec3 | 2916 | { |
mbed_official | 130:1dec54e4aec3 | 2917 | uint16_t tmpsmcr = 0; |
mbed_official | 130:1dec54e4aec3 | 2918 | |
mbed_official | 130:1dec54e4aec3 | 2919 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2920 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2921 | assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); |
mbed_official | 130:1dec54e4aec3 | 2922 | |
mbed_official | 130:1dec54e4aec3 | 2923 | /* Get the TIMx SMCR register value */ |
mbed_official | 130:1dec54e4aec3 | 2924 | tmpsmcr = TIMx->SMCR; |
mbed_official | 130:1dec54e4aec3 | 2925 | /* Reset the TS Bits */ |
mbed_official | 130:1dec54e4aec3 | 2926 | tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); |
mbed_official | 130:1dec54e4aec3 | 2927 | /* Set the Input Trigger source */ |
mbed_official | 130:1dec54e4aec3 | 2928 | tmpsmcr |= TIM_InputTriggerSource; |
mbed_official | 130:1dec54e4aec3 | 2929 | /* Write to TIMx SMCR */ |
mbed_official | 130:1dec54e4aec3 | 2930 | TIMx->SMCR = tmpsmcr; |
mbed_official | 130:1dec54e4aec3 | 2931 | } |
mbed_official | 130:1dec54e4aec3 | 2932 | |
mbed_official | 130:1dec54e4aec3 | 2933 | /** |
mbed_official | 130:1dec54e4aec3 | 2934 | * @brief Selects the TIMx Trigger Output Mode. |
mbed_official | 130:1dec54e4aec3 | 2935 | * @param TIMx: where x can be 1, 2, 3, 6, 7, or 15 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2936 | * @note TIM7 is applicable only for STM32F072 devices |
mbed_official | 130:1dec54e4aec3 | 2937 | * @note TIM6 is not applivable for STM32F031 devices. |
mbed_official | 130:1dec54e4aec3 | 2938 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2939 | * @param TIM_TRGOSource: specifies the Trigger Output source. |
mbed_official | 130:1dec54e4aec3 | 2940 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 2941 | * |
mbed_official | 130:1dec54e4aec3 | 2942 | * - For all TIMx |
mbed_official | 130:1dec54e4aec3 | 2943 | * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO). |
mbed_official | 130:1dec54e4aec3 | 2944 | * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO). |
mbed_official | 130:1dec54e4aec3 | 2945 | * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO). |
mbed_official | 130:1dec54e4aec3 | 2946 | * |
mbed_official | 130:1dec54e4aec3 | 2947 | * - For all TIMx except TIM6 and TIM7 |
mbed_official | 130:1dec54e4aec3 | 2948 | * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag |
mbed_official | 130:1dec54e4aec3 | 2949 | * is to be set, as soon as a capture or compare match occurs (TRGO). |
mbed_official | 130:1dec54e4aec3 | 2950 | * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO). |
mbed_official | 130:1dec54e4aec3 | 2951 | * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO). |
mbed_official | 130:1dec54e4aec3 | 2952 | * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO). |
mbed_official | 130:1dec54e4aec3 | 2953 | * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO). |
mbed_official | 130:1dec54e4aec3 | 2954 | * |
mbed_official | 130:1dec54e4aec3 | 2955 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 2956 | */ |
mbed_official | 130:1dec54e4aec3 | 2957 | void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) |
mbed_official | 130:1dec54e4aec3 | 2958 | { |
mbed_official | 130:1dec54e4aec3 | 2959 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2960 | assert_param(IS_TIM_LIST9_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2961 | assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); |
mbed_official | 130:1dec54e4aec3 | 2962 | |
mbed_official | 130:1dec54e4aec3 | 2963 | /* Reset the MMS Bits */ |
mbed_official | 130:1dec54e4aec3 | 2964 | TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS); |
mbed_official | 130:1dec54e4aec3 | 2965 | /* Select the TRGO source */ |
mbed_official | 130:1dec54e4aec3 | 2966 | TIMx->CR2 |= TIM_TRGOSource; |
mbed_official | 130:1dec54e4aec3 | 2967 | } |
mbed_official | 130:1dec54e4aec3 | 2968 | |
mbed_official | 130:1dec54e4aec3 | 2969 | /** |
mbed_official | 130:1dec54e4aec3 | 2970 | * @brief Selects the TIMx Slave Mode. |
mbed_official | 130:1dec54e4aec3 | 2971 | * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2972 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2973 | * @param TIM_SlaveMode: specifies the Timer Slave Mode. |
mbed_official | 130:1dec54e4aec3 | 2974 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 2975 | * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes |
mbed_official | 130:1dec54e4aec3 | 2976 | * the counter and triggers an update of the registers. |
mbed_official | 130:1dec54e4aec3 | 2977 | * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high. |
mbed_official | 130:1dec54e4aec3 | 2978 | * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI. |
mbed_official | 130:1dec54e4aec3 | 2979 | * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. |
mbed_official | 130:1dec54e4aec3 | 2980 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 2981 | */ |
mbed_official | 130:1dec54e4aec3 | 2982 | void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) |
mbed_official | 130:1dec54e4aec3 | 2983 | { |
mbed_official | 130:1dec54e4aec3 | 2984 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 2985 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 2986 | assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); |
mbed_official | 130:1dec54e4aec3 | 2987 | |
mbed_official | 130:1dec54e4aec3 | 2988 | /* Reset the SMS Bits */ |
mbed_official | 130:1dec54e4aec3 | 2989 | TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS); |
mbed_official | 130:1dec54e4aec3 | 2990 | /* Select the Slave Mode */ |
mbed_official | 130:1dec54e4aec3 | 2991 | TIMx->SMCR |= TIM_SlaveMode; |
mbed_official | 130:1dec54e4aec3 | 2992 | } |
mbed_official | 130:1dec54e4aec3 | 2993 | |
mbed_official | 130:1dec54e4aec3 | 2994 | /** |
mbed_official | 130:1dec54e4aec3 | 2995 | * @brief Sets or Resets the TIMx Master/Slave Mode. |
mbed_official | 130:1dec54e4aec3 | 2996 | * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 2997 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 2998 | * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. |
mbed_official | 130:1dec54e4aec3 | 2999 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 3000 | * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer |
mbed_official | 130:1dec54e4aec3 | 3001 | * and its slaves (through TRGO). |
mbed_official | 130:1dec54e4aec3 | 3002 | * @arg TIM_MasterSlaveMode_Disable: No action |
mbed_official | 130:1dec54e4aec3 | 3003 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 3004 | */ |
mbed_official | 130:1dec54e4aec3 | 3005 | void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) |
mbed_official | 130:1dec54e4aec3 | 3006 | { |
mbed_official | 130:1dec54e4aec3 | 3007 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 3008 | assert_param(IS_TIM_LIST6_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 3009 | assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); |
mbed_official | 130:1dec54e4aec3 | 3010 | |
mbed_official | 130:1dec54e4aec3 | 3011 | /* Reset the MSM Bit */ |
mbed_official | 130:1dec54e4aec3 | 3012 | TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM); |
mbed_official | 130:1dec54e4aec3 | 3013 | |
mbed_official | 130:1dec54e4aec3 | 3014 | /* Set or Reset the MSM Bit */ |
mbed_official | 130:1dec54e4aec3 | 3015 | TIMx->SMCR |= TIM_MasterSlaveMode; |
mbed_official | 130:1dec54e4aec3 | 3016 | } |
mbed_official | 130:1dec54e4aec3 | 3017 | |
mbed_official | 130:1dec54e4aec3 | 3018 | /** |
mbed_official | 130:1dec54e4aec3 | 3019 | * @brief Configures the TIMx External Trigger (ETR). |
mbed_official | 130:1dec54e4aec3 | 3020 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 3021 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 3022 | * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. |
mbed_official | 130:1dec54e4aec3 | 3023 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 3024 | * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. |
mbed_official | 130:1dec54e4aec3 | 3025 | * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. |
mbed_official | 130:1dec54e4aec3 | 3026 | * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. |
mbed_official | 130:1dec54e4aec3 | 3027 | * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. |
mbed_official | 130:1dec54e4aec3 | 3028 | * @param TIM_ExtTRGPolarity: The external Trigger Polarity. |
mbed_official | 130:1dec54e4aec3 | 3029 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 3030 | * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. |
mbed_official | 130:1dec54e4aec3 | 3031 | * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. |
mbed_official | 130:1dec54e4aec3 | 3032 | * @param ExtTRGFilter: External Trigger Filter. |
mbed_official | 130:1dec54e4aec3 | 3033 | * This parameter must be a value between 0x00 and 0x0F |
mbed_official | 130:1dec54e4aec3 | 3034 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 3035 | */ |
mbed_official | 130:1dec54e4aec3 | 3036 | void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, |
mbed_official | 130:1dec54e4aec3 | 3037 | uint16_t ExtTRGFilter) |
mbed_official | 130:1dec54e4aec3 | 3038 | { |
mbed_official | 130:1dec54e4aec3 | 3039 | uint16_t tmpsmcr = 0; |
mbed_official | 130:1dec54e4aec3 | 3040 | |
mbed_official | 130:1dec54e4aec3 | 3041 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 3042 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 3043 | assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); |
mbed_official | 130:1dec54e4aec3 | 3044 | assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); |
mbed_official | 130:1dec54e4aec3 | 3045 | assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); |
mbed_official | 130:1dec54e4aec3 | 3046 | |
mbed_official | 130:1dec54e4aec3 | 3047 | tmpsmcr = TIMx->SMCR; |
mbed_official | 130:1dec54e4aec3 | 3048 | /* Reset the ETR Bits */ |
mbed_official | 130:1dec54e4aec3 | 3049 | tmpsmcr &= SMCR_ETR_MASK; |
mbed_official | 130:1dec54e4aec3 | 3050 | /* Set the Prescaler, the Filter value and the Polarity */ |
mbed_official | 130:1dec54e4aec3 | 3051 | tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); |
mbed_official | 130:1dec54e4aec3 | 3052 | /* Write to TIMx SMCR */ |
mbed_official | 130:1dec54e4aec3 | 3053 | TIMx->SMCR = tmpsmcr; |
mbed_official | 130:1dec54e4aec3 | 3054 | } |
mbed_official | 130:1dec54e4aec3 | 3055 | |
mbed_official | 130:1dec54e4aec3 | 3056 | /** |
mbed_official | 130:1dec54e4aec3 | 3057 | * @} |
mbed_official | 130:1dec54e4aec3 | 3058 | */ |
mbed_official | 130:1dec54e4aec3 | 3059 | |
mbed_official | 130:1dec54e4aec3 | 3060 | /** @defgroup TIM_Group8 Specific interface management functions |
mbed_official | 130:1dec54e4aec3 | 3061 | * @brief Specific interface management functions |
mbed_official | 130:1dec54e4aec3 | 3062 | * |
mbed_official | 130:1dec54e4aec3 | 3063 | @verbatim |
mbed_official | 130:1dec54e4aec3 | 3064 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 3065 | ##### Specific interface management functions ##### |
mbed_official | 130:1dec54e4aec3 | 3066 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 3067 | |
mbed_official | 130:1dec54e4aec3 | 3068 | @endverbatim |
mbed_official | 130:1dec54e4aec3 | 3069 | * @{ |
mbed_official | 130:1dec54e4aec3 | 3070 | */ |
mbed_official | 130:1dec54e4aec3 | 3071 | |
mbed_official | 130:1dec54e4aec3 | 3072 | /** |
mbed_official | 130:1dec54e4aec3 | 3073 | * @brief Configures the TIMx Encoder Interface. |
mbed_official | 130:1dec54e4aec3 | 3074 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 3075 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 3076 | * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. |
mbed_official | 130:1dec54e4aec3 | 3077 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 3078 | * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. |
mbed_official | 130:1dec54e4aec3 | 3079 | * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. |
mbed_official | 130:1dec54e4aec3 | 3080 | * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending |
mbed_official | 130:1dec54e4aec3 | 3081 | * on the level of the other input. |
mbed_official | 130:1dec54e4aec3 | 3082 | * @param TIM_IC1Polarity: specifies the IC1 Polarity |
mbed_official | 130:1dec54e4aec3 | 3083 | * This parmeter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 3084 | * @arg TIM_ICPolarity_Falling: IC Falling edge. |
mbed_official | 130:1dec54e4aec3 | 3085 | * @arg TIM_ICPolarity_Rising: IC Rising edge. |
mbed_official | 130:1dec54e4aec3 | 3086 | * @param TIM_IC2Polarity: specifies the IC2 Polarity |
mbed_official | 130:1dec54e4aec3 | 3087 | * This parmeter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 3088 | * @arg TIM_ICPolarity_Falling: IC Falling edge. |
mbed_official | 130:1dec54e4aec3 | 3089 | * @arg TIM_ICPolarity_Rising: IC Rising edge. |
mbed_official | 130:1dec54e4aec3 | 3090 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 3091 | */ |
mbed_official | 130:1dec54e4aec3 | 3092 | void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, |
mbed_official | 130:1dec54e4aec3 | 3093 | uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) |
mbed_official | 130:1dec54e4aec3 | 3094 | { |
mbed_official | 130:1dec54e4aec3 | 3095 | uint16_t tmpsmcr = 0; |
mbed_official | 130:1dec54e4aec3 | 3096 | uint16_t tmpccmr1 = 0; |
mbed_official | 130:1dec54e4aec3 | 3097 | uint16_t tmpccer = 0; |
mbed_official | 130:1dec54e4aec3 | 3098 | |
mbed_official | 130:1dec54e4aec3 | 3099 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 3100 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 3101 | assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); |
mbed_official | 130:1dec54e4aec3 | 3102 | assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); |
mbed_official | 130:1dec54e4aec3 | 3103 | assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); |
mbed_official | 130:1dec54e4aec3 | 3104 | |
mbed_official | 130:1dec54e4aec3 | 3105 | /* Get the TIMx SMCR register value */ |
mbed_official | 130:1dec54e4aec3 | 3106 | tmpsmcr = TIMx->SMCR; |
mbed_official | 130:1dec54e4aec3 | 3107 | /* Get the TIMx CCMR1 register value */ |
mbed_official | 130:1dec54e4aec3 | 3108 | tmpccmr1 = TIMx->CCMR1; |
mbed_official | 130:1dec54e4aec3 | 3109 | /* Get the TIMx CCER register value */ |
mbed_official | 130:1dec54e4aec3 | 3110 | tmpccer = TIMx->CCER; |
mbed_official | 130:1dec54e4aec3 | 3111 | /* Set the encoder Mode */ |
mbed_official | 130:1dec54e4aec3 | 3112 | tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); |
mbed_official | 130:1dec54e4aec3 | 3113 | tmpsmcr |= TIM_EncoderMode; |
mbed_official | 130:1dec54e4aec3 | 3114 | /* Select the Capture Compare 1 and the Capture Compare 2 as input */ |
mbed_official | 130:1dec54e4aec3 | 3115 | tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S))); |
mbed_official | 130:1dec54e4aec3 | 3116 | tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; |
mbed_official | 130:1dec54e4aec3 | 3117 | /* Set the TI1 and the TI2 Polarities */ |
mbed_official | 130:1dec54e4aec3 | 3118 | tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)) & (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); |
mbed_official | 130:1dec54e4aec3 | 3119 | tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); |
mbed_official | 130:1dec54e4aec3 | 3120 | /* Write to TIMx SMCR */ |
mbed_official | 130:1dec54e4aec3 | 3121 | TIMx->SMCR = tmpsmcr; |
mbed_official | 130:1dec54e4aec3 | 3122 | /* Write to TIMx CCMR1 */ |
mbed_official | 130:1dec54e4aec3 | 3123 | TIMx->CCMR1 = tmpccmr1; |
mbed_official | 130:1dec54e4aec3 | 3124 | /* Write to TIMx CCER */ |
mbed_official | 130:1dec54e4aec3 | 3125 | TIMx->CCER = tmpccer; |
mbed_official | 130:1dec54e4aec3 | 3126 | } |
mbed_official | 130:1dec54e4aec3 | 3127 | |
mbed_official | 130:1dec54e4aec3 | 3128 | /** |
mbed_official | 130:1dec54e4aec3 | 3129 | * @brief Enables or disables the TIMx's Hall sensor interface. |
mbed_official | 130:1dec54e4aec3 | 3130 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 3131 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 3132 | * @param NewState: new state of the TIMx Hall sensor interface. |
mbed_official | 130:1dec54e4aec3 | 3133 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 130:1dec54e4aec3 | 3134 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 3135 | */ |
mbed_official | 130:1dec54e4aec3 | 3136 | void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) |
mbed_official | 130:1dec54e4aec3 | 3137 | { |
mbed_official | 130:1dec54e4aec3 | 3138 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 3139 | assert_param(IS_TIM_LIST3_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 3140 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 130:1dec54e4aec3 | 3141 | |
mbed_official | 130:1dec54e4aec3 | 3142 | if (NewState != DISABLE) |
mbed_official | 130:1dec54e4aec3 | 3143 | { |
mbed_official | 130:1dec54e4aec3 | 3144 | /* Set the TI1S Bit */ |
mbed_official | 130:1dec54e4aec3 | 3145 | TIMx->CR2 |= TIM_CR2_TI1S; |
mbed_official | 130:1dec54e4aec3 | 3146 | } |
mbed_official | 130:1dec54e4aec3 | 3147 | else |
mbed_official | 130:1dec54e4aec3 | 3148 | { |
mbed_official | 130:1dec54e4aec3 | 3149 | /* Reset the TI1S Bit */ |
mbed_official | 130:1dec54e4aec3 | 3150 | TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S); |
mbed_official | 130:1dec54e4aec3 | 3151 | } |
mbed_official | 130:1dec54e4aec3 | 3152 | } |
mbed_official | 130:1dec54e4aec3 | 3153 | |
mbed_official | 130:1dec54e4aec3 | 3154 | /** |
mbed_official | 130:1dec54e4aec3 | 3155 | * @} |
mbed_official | 130:1dec54e4aec3 | 3156 | */ |
mbed_official | 130:1dec54e4aec3 | 3157 | |
mbed_official | 130:1dec54e4aec3 | 3158 | /** @defgroup TIM_Group9 Specific remapping management function |
mbed_official | 130:1dec54e4aec3 | 3159 | * @brief Specific remapping management function |
mbed_official | 130:1dec54e4aec3 | 3160 | * |
mbed_official | 130:1dec54e4aec3 | 3161 | @verbatim |
mbed_official | 130:1dec54e4aec3 | 3162 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 3163 | ##### Specific remapping management function ##### |
mbed_official | 130:1dec54e4aec3 | 3164 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 3165 | |
mbed_official | 130:1dec54e4aec3 | 3166 | @endverbatim |
mbed_official | 130:1dec54e4aec3 | 3167 | * @{ |
mbed_official | 130:1dec54e4aec3 | 3168 | */ |
mbed_official | 130:1dec54e4aec3 | 3169 | /** |
mbed_official | 130:1dec54e4aec3 | 3170 | * @brief Configures the TIM14 Remapping input Capabilities. |
mbed_official | 130:1dec54e4aec3 | 3171 | * @param TIMx: where x can be 14 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 3172 | * @param TIM_Remap: specifies the TIM input reampping source. |
mbed_official | 130:1dec54e4aec3 | 3173 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 3174 | * @arg TIM14_GPIO: TIM14 Channel 1 is connected to GPIO. |
mbed_official | 130:1dec54e4aec3 | 3175 | * @arg TIM14_RTC_CLK: TIM14 Channel 1 is connected to RTC input clock. |
mbed_official | 130:1dec54e4aec3 | 3176 | * RTC input clock can be LSE, LSI or HSE/div128. |
mbed_official | 130:1dec54e4aec3 | 3177 | * @arg TIM14_HSE_DIV32: TIM14 Channel 1 is connected to HSE/32 clock. |
mbed_official | 130:1dec54e4aec3 | 3178 | * @arg TIM14_MCO: TIM14 Channel 1 is connected to MCO clock. |
mbed_official | 130:1dec54e4aec3 | 3179 | * MCO clock can be HSI14, SYSCLK, HSI, HSE or PLL/2. |
mbed_official | 130:1dec54e4aec3 | 3180 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 3181 | */ |
mbed_official | 130:1dec54e4aec3 | 3182 | void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap) |
mbed_official | 130:1dec54e4aec3 | 3183 | { |
mbed_official | 130:1dec54e4aec3 | 3184 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 3185 | assert_param(IS_TIM_LIST11_PERIPH(TIMx)); |
mbed_official | 130:1dec54e4aec3 | 3186 | assert_param(IS_TIM_REMAP(TIM_Remap)); |
mbed_official | 130:1dec54e4aec3 | 3187 | |
mbed_official | 130:1dec54e4aec3 | 3188 | /* Set the Timer remapping configuration */ |
mbed_official | 130:1dec54e4aec3 | 3189 | TIMx->OR = TIM_Remap; |
mbed_official | 130:1dec54e4aec3 | 3190 | } |
mbed_official | 130:1dec54e4aec3 | 3191 | |
mbed_official | 130:1dec54e4aec3 | 3192 | /** |
mbed_official | 130:1dec54e4aec3 | 3193 | * @} |
mbed_official | 130:1dec54e4aec3 | 3194 | */ |
mbed_official | 130:1dec54e4aec3 | 3195 | |
mbed_official | 130:1dec54e4aec3 | 3196 | /** |
mbed_official | 130:1dec54e4aec3 | 3197 | * @brief Configure the TI1 as Input. |
mbed_official | 130:1dec54e4aec3 | 3198 | * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 3199 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 3200 | * @param TIM_ICPolarity: The Input Polarity. |
mbed_official | 130:1dec54e4aec3 | 3201 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 3202 | * @arg TIM_ICPolarity_Rising |
mbed_official | 130:1dec54e4aec3 | 3203 | * @arg TIM_ICPolarity_Falling |
mbed_official | 130:1dec54e4aec3 | 3204 | * @param TIM_ICSelection: specifies the input to be used. |
mbed_official | 130:1dec54e4aec3 | 3205 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 3206 | * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. |
mbed_official | 130:1dec54e4aec3 | 3207 | * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. |
mbed_official | 130:1dec54e4aec3 | 3208 | * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. |
mbed_official | 130:1dec54e4aec3 | 3209 | * @param TIM_ICFilter: Specifies the Input Capture Filter. |
mbed_official | 130:1dec54e4aec3 | 3210 | * This parameter must be a value between 0x00 and 0x0F. |
mbed_official | 130:1dec54e4aec3 | 3211 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 3212 | */ |
mbed_official | 130:1dec54e4aec3 | 3213 | static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, |
mbed_official | 130:1dec54e4aec3 | 3214 | uint16_t TIM_ICFilter) |
mbed_official | 130:1dec54e4aec3 | 3215 | { |
mbed_official | 130:1dec54e4aec3 | 3216 | uint16_t tmpccmr1 = 0, tmpccer = 0; |
mbed_official | 130:1dec54e4aec3 | 3217 | /* Disable the Channel 1: Reset the CC1E Bit */ |
mbed_official | 130:1dec54e4aec3 | 3218 | TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E); |
mbed_official | 130:1dec54e4aec3 | 3219 | tmpccmr1 = TIMx->CCMR1; |
mbed_official | 130:1dec54e4aec3 | 3220 | tmpccer = TIMx->CCER; |
mbed_official | 130:1dec54e4aec3 | 3221 | /* Select the Input and set the filter */ |
mbed_official | 130:1dec54e4aec3 | 3222 | tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F))); |
mbed_official | 130:1dec54e4aec3 | 3223 | tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); |
mbed_official | 130:1dec54e4aec3 | 3224 | |
mbed_official | 130:1dec54e4aec3 | 3225 | /* Select the Polarity and set the CC1E Bit */ |
mbed_official | 130:1dec54e4aec3 | 3226 | tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)); |
mbed_official | 130:1dec54e4aec3 | 3227 | tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); |
mbed_official | 130:1dec54e4aec3 | 3228 | /* Write to TIMx CCMR1 and CCER registers */ |
mbed_official | 130:1dec54e4aec3 | 3229 | TIMx->CCMR1 = tmpccmr1; |
mbed_official | 130:1dec54e4aec3 | 3230 | TIMx->CCER = tmpccer; |
mbed_official | 130:1dec54e4aec3 | 3231 | } |
mbed_official | 130:1dec54e4aec3 | 3232 | |
mbed_official | 130:1dec54e4aec3 | 3233 | /** |
mbed_official | 130:1dec54e4aec3 | 3234 | * @brief Configure the TI2 as Input. |
mbed_official | 130:1dec54e4aec3 | 3235 | * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 3236 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 3237 | * @param TIM_ICPolarity: The Input Polarity. |
mbed_official | 130:1dec54e4aec3 | 3238 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 3239 | * @arg TIM_ICPolarity_Rising |
mbed_official | 130:1dec54e4aec3 | 3240 | * @arg TIM_ICPolarity_Falling |
mbed_official | 130:1dec54e4aec3 | 3241 | * @param TIM_ICSelection: specifies the input to be used. |
mbed_official | 130:1dec54e4aec3 | 3242 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 3243 | * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. |
mbed_official | 130:1dec54e4aec3 | 3244 | * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. |
mbed_official | 130:1dec54e4aec3 | 3245 | * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. |
mbed_official | 130:1dec54e4aec3 | 3246 | * @param TIM_ICFilter: Specifies the Input Capture Filter. |
mbed_official | 130:1dec54e4aec3 | 3247 | * This parameter must be a value between 0x00 and 0x0F. |
mbed_official | 130:1dec54e4aec3 | 3248 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 3249 | */ |
mbed_official | 130:1dec54e4aec3 | 3250 | static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, |
mbed_official | 130:1dec54e4aec3 | 3251 | uint16_t TIM_ICFilter) |
mbed_official | 130:1dec54e4aec3 | 3252 | { |
mbed_official | 130:1dec54e4aec3 | 3253 | uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; |
mbed_official | 130:1dec54e4aec3 | 3254 | /* Disable the Channel 2: Reset the CC2E Bit */ |
mbed_official | 130:1dec54e4aec3 | 3255 | TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E); |
mbed_official | 130:1dec54e4aec3 | 3256 | tmpccmr1 = TIMx->CCMR1; |
mbed_official | 130:1dec54e4aec3 | 3257 | tmpccer = TIMx->CCER; |
mbed_official | 130:1dec54e4aec3 | 3258 | tmp = (uint16_t)(TIM_ICPolarity << 4); |
mbed_official | 130:1dec54e4aec3 | 3259 | /* Select the Input and set the filter */ |
mbed_official | 130:1dec54e4aec3 | 3260 | tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F))); |
mbed_official | 130:1dec54e4aec3 | 3261 | tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); |
mbed_official | 130:1dec54e4aec3 | 3262 | tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); |
mbed_official | 130:1dec54e4aec3 | 3263 | /* Select the Polarity and set the CC2E Bit */ |
mbed_official | 130:1dec54e4aec3 | 3264 | tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); |
mbed_official | 130:1dec54e4aec3 | 3265 | tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); |
mbed_official | 130:1dec54e4aec3 | 3266 | /* Write to TIMx CCMR1 and CCER registers */ |
mbed_official | 130:1dec54e4aec3 | 3267 | TIMx->CCMR1 = tmpccmr1 ; |
mbed_official | 130:1dec54e4aec3 | 3268 | TIMx->CCER = tmpccer; |
mbed_official | 130:1dec54e4aec3 | 3269 | } |
mbed_official | 130:1dec54e4aec3 | 3270 | |
mbed_official | 130:1dec54e4aec3 | 3271 | /** |
mbed_official | 130:1dec54e4aec3 | 3272 | * @brief Configure the TI3 as Input. |
mbed_official | 130:1dec54e4aec3 | 3273 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 3274 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 3275 | * @param TIM_ICPolarity: The Input Polarity. |
mbed_official | 130:1dec54e4aec3 | 3276 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 3277 | * @arg TIM_ICPolarity_Rising |
mbed_official | 130:1dec54e4aec3 | 3278 | * @arg TIM_ICPolarity_Falling |
mbed_official | 130:1dec54e4aec3 | 3279 | * @param TIM_ICSelection: specifies the input to be used. |
mbed_official | 130:1dec54e4aec3 | 3280 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 3281 | * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. |
mbed_official | 130:1dec54e4aec3 | 3282 | * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. |
mbed_official | 130:1dec54e4aec3 | 3283 | * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. |
mbed_official | 130:1dec54e4aec3 | 3284 | * @param TIM_ICFilter: Specifies the Input Capture Filter. |
mbed_official | 130:1dec54e4aec3 | 3285 | * This parameter must be a value between 0x00 and 0x0F. |
mbed_official | 130:1dec54e4aec3 | 3286 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 3287 | */ |
mbed_official | 130:1dec54e4aec3 | 3288 | static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, |
mbed_official | 130:1dec54e4aec3 | 3289 | uint16_t TIM_ICFilter) |
mbed_official | 130:1dec54e4aec3 | 3290 | { |
mbed_official | 130:1dec54e4aec3 | 3291 | uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; |
mbed_official | 130:1dec54e4aec3 | 3292 | /* Disable the Channel 3: Reset the CC3E Bit */ |
mbed_official | 130:1dec54e4aec3 | 3293 | TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E); |
mbed_official | 130:1dec54e4aec3 | 3294 | tmpccmr2 = TIMx->CCMR2; |
mbed_official | 130:1dec54e4aec3 | 3295 | tmpccer = TIMx->CCER; |
mbed_official | 130:1dec54e4aec3 | 3296 | tmp = (uint16_t)(TIM_ICPolarity << 8); |
mbed_official | 130:1dec54e4aec3 | 3297 | /* Select the Input and set the filter */ |
mbed_official | 130:1dec54e4aec3 | 3298 | tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F))); |
mbed_official | 130:1dec54e4aec3 | 3299 | tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); |
mbed_official | 130:1dec54e4aec3 | 3300 | /* Select the Polarity and set the CC3E Bit */ |
mbed_official | 130:1dec54e4aec3 | 3301 | tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP)); |
mbed_official | 130:1dec54e4aec3 | 3302 | tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); |
mbed_official | 130:1dec54e4aec3 | 3303 | /* Write to TIMx CCMR2 and CCER registers */ |
mbed_official | 130:1dec54e4aec3 | 3304 | TIMx->CCMR2 = tmpccmr2; |
mbed_official | 130:1dec54e4aec3 | 3305 | TIMx->CCER = tmpccer; |
mbed_official | 130:1dec54e4aec3 | 3306 | } |
mbed_official | 130:1dec54e4aec3 | 3307 | |
mbed_official | 130:1dec54e4aec3 | 3308 | /** |
mbed_official | 130:1dec54e4aec3 | 3309 | * @brief Configure the TI4 as Input. |
mbed_official | 130:1dec54e4aec3 | 3310 | * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral. |
mbed_official | 130:1dec54e4aec3 | 3311 | * @note TIM2 is not applicable for STM32F030 devices. |
mbed_official | 130:1dec54e4aec3 | 3312 | * @param TIM_ICPolarity: The Input Polarity. |
mbed_official | 130:1dec54e4aec3 | 3313 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 3314 | * @arg TIM_ICPolarity_Rising |
mbed_official | 130:1dec54e4aec3 | 3315 | * @arg TIM_ICPolarity_Falling |
mbed_official | 130:1dec54e4aec3 | 3316 | * @param TIM_ICSelection: specifies the input to be used. |
mbed_official | 130:1dec54e4aec3 | 3317 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 3318 | * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. |
mbed_official | 130:1dec54e4aec3 | 3319 | * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. |
mbed_official | 130:1dec54e4aec3 | 3320 | * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. |
mbed_official | 130:1dec54e4aec3 | 3321 | * @param TIM_ICFilter: Specifies the Input Capture Filter. |
mbed_official | 130:1dec54e4aec3 | 3322 | * This parameter must be a value between 0x00 and 0x0F. |
mbed_official | 130:1dec54e4aec3 | 3323 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 3324 | */ |
mbed_official | 130:1dec54e4aec3 | 3325 | static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, |
mbed_official | 130:1dec54e4aec3 | 3326 | uint16_t TIM_ICFilter) |
mbed_official | 130:1dec54e4aec3 | 3327 | { |
mbed_official | 130:1dec54e4aec3 | 3328 | uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; |
mbed_official | 130:1dec54e4aec3 | 3329 | |
mbed_official | 130:1dec54e4aec3 | 3330 | /* Disable the Channel 4: Reset the CC4E Bit */ |
mbed_official | 130:1dec54e4aec3 | 3331 | TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E); |
mbed_official | 130:1dec54e4aec3 | 3332 | tmpccmr2 = TIMx->CCMR2; |
mbed_official | 130:1dec54e4aec3 | 3333 | tmpccer = TIMx->CCER; |
mbed_official | 130:1dec54e4aec3 | 3334 | tmp = (uint16_t)(TIM_ICPolarity << 12); |
mbed_official | 130:1dec54e4aec3 | 3335 | /* Select the Input and set the filter */ |
mbed_official | 130:1dec54e4aec3 | 3336 | tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F))); |
mbed_official | 130:1dec54e4aec3 | 3337 | tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); |
mbed_official | 130:1dec54e4aec3 | 3338 | tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); |
mbed_official | 130:1dec54e4aec3 | 3339 | /* Select the Polarity and set the CC4E Bit */ |
mbed_official | 130:1dec54e4aec3 | 3340 | tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P | TIM_CCER_CC4NP)); |
mbed_official | 130:1dec54e4aec3 | 3341 | tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); |
mbed_official | 130:1dec54e4aec3 | 3342 | /* Write to TIMx CCMR2 and CCER registers */ |
mbed_official | 130:1dec54e4aec3 | 3343 | TIMx->CCMR2 = tmpccmr2; |
mbed_official | 130:1dec54e4aec3 | 3344 | TIMx->CCER = tmpccer; |
mbed_official | 130:1dec54e4aec3 | 3345 | } |
mbed_official | 130:1dec54e4aec3 | 3346 | |
mbed_official | 130:1dec54e4aec3 | 3347 | /** |
mbed_official | 130:1dec54e4aec3 | 3348 | * @} |
mbed_official | 130:1dec54e4aec3 | 3349 | */ |
mbed_official | 130:1dec54e4aec3 | 3350 | |
mbed_official | 130:1dec54e4aec3 | 3351 | /** |
mbed_official | 130:1dec54e4aec3 | 3352 | * @} |
mbed_official | 130:1dec54e4aec3 | 3353 | */ |
mbed_official | 130:1dec54e4aec3 | 3354 | |
mbed_official | 130:1dec54e4aec3 | 3355 | /** |
mbed_official | 130:1dec54e4aec3 | 3356 | * @} |
mbed_official | 130:1dec54e4aec3 | 3357 | */ |
mbed_official | 130:1dec54e4aec3 | 3358 | |
mbed_official | 130:1dec54e4aec3 | 3359 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |