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targets/cmsis/TARGET_STM/TARGET_DISCO_F051R8/stm32f0xx_dma.c@308:59cc78a25982, 2014-09-05 (annotated)
- Committer:
- todotani
- Date:
- Fri Sep 05 14:20:33 2014 +0000
- Revision:
- 308:59cc78a25982
- Parent:
- 130:1dec54e4aec3
BLE_Health_Thermometer for mbed HRM1017 with BLE library 0.1.0
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mbed_official | 130:1dec54e4aec3 | 1 | /** |
mbed_official | 130:1dec54e4aec3 | 2 | ****************************************************************************** |
mbed_official | 130:1dec54e4aec3 | 3 | * @file stm32f0xx_dma.c |
mbed_official | 130:1dec54e4aec3 | 4 | * @author MCD Application Team |
mbed_official | 130:1dec54e4aec3 | 5 | * @version V1.3.0 |
mbed_official | 130:1dec54e4aec3 | 6 | * @date 16-January-2014 |
mbed_official | 130:1dec54e4aec3 | 7 | * @brief This file provides firmware functions to manage the following |
mbed_official | 130:1dec54e4aec3 | 8 | * functionalities of the Direct Memory Access controller (DMA): |
mbed_official | 130:1dec54e4aec3 | 9 | * + Initialization and Configuration |
mbed_official | 130:1dec54e4aec3 | 10 | * + Data Counter |
mbed_official | 130:1dec54e4aec3 | 11 | * + Interrupts and flags management |
mbed_official | 130:1dec54e4aec3 | 12 | * |
mbed_official | 130:1dec54e4aec3 | 13 | * @verbatim |
mbed_official | 130:1dec54e4aec3 | 14 | ============================================================================== |
mbed_official | 130:1dec54e4aec3 | 15 | ##### How to use this driver ##### |
mbed_official | 130:1dec54e4aec3 | 16 | ============================================================================== |
mbed_official | 130:1dec54e4aec3 | 17 | [..] |
mbed_official | 130:1dec54e4aec3 | 18 | (#) Enable The DMA controller clock using |
mbed_official | 130:1dec54e4aec3 | 19 | RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1. |
mbed_official | 130:1dec54e4aec3 | 20 | (#) Enable and configure the peripheral to be connected to the DMA channel |
mbed_official | 130:1dec54e4aec3 | 21 | (except for internal SRAM / FLASH memories: no initialization is necessary). |
mbed_official | 130:1dec54e4aec3 | 22 | (#) For a given Channel, program the Source and Destination addresses, |
mbed_official | 130:1dec54e4aec3 | 23 | the transfer Direction, the Buffer Size, the Peripheral and Memory |
mbed_official | 130:1dec54e4aec3 | 24 | Incrementation mode and Data Size, the Circular or Normal mode, |
mbed_official | 130:1dec54e4aec3 | 25 | the channel transfer Priority and the Memory-to-Memory transfer |
mbed_official | 130:1dec54e4aec3 | 26 | mode (if needed) using the DMA_Init() function. |
mbed_official | 130:1dec54e4aec3 | 27 | (#) Enable the NVIC and the corresponding interrupt(s) using the function |
mbed_official | 130:1dec54e4aec3 | 28 | DMA_ITConfig() if you need to use DMA interrupts. |
mbed_official | 130:1dec54e4aec3 | 29 | (#) Enable the DMA channel using the DMA_Cmd() function. |
mbed_official | 130:1dec54e4aec3 | 30 | (#) Activate the needed channel Request using PPP_DMACmd() function for |
mbed_official | 130:1dec54e4aec3 | 31 | any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) |
mbed_official | 130:1dec54e4aec3 | 32 | The function allowing this operation is provided in each PPP peripheral |
mbed_official | 130:1dec54e4aec3 | 33 | driver (ie. SPI_DMACmd for SPI peripheral). |
mbed_official | 130:1dec54e4aec3 | 34 | (#) Optionally, you can configure the number of data to be transferred |
mbed_official | 130:1dec54e4aec3 | 35 | when the channel is disabled (ie. after each Transfer Complete event |
mbed_official | 130:1dec54e4aec3 | 36 | or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter(). |
mbed_official | 130:1dec54e4aec3 | 37 | And you can get the number of remaining data to be transferred using |
mbed_official | 130:1dec54e4aec3 | 38 | the function DMA_GetCurrDataCounter() at run time (when the DMA channel is |
mbed_official | 130:1dec54e4aec3 | 39 | enabled and running). |
mbed_official | 130:1dec54e4aec3 | 40 | (#) To control DMA events you can use one of the following two methods: |
mbed_official | 130:1dec54e4aec3 | 41 | (##) Check on DMA channel flags using the function DMA_GetFlagStatus(). |
mbed_official | 130:1dec54e4aec3 | 42 | (##) Use DMA interrupts through the function DMA_ITConfig() at initialization |
mbed_official | 130:1dec54e4aec3 | 43 | phase and DMA_GetITStatus() function into interrupt routines in |
mbed_official | 130:1dec54e4aec3 | 44 | communication phase. |
mbed_official | 130:1dec54e4aec3 | 45 | After checking on a flag you should clear it using DMA_ClearFlag() |
mbed_official | 130:1dec54e4aec3 | 46 | function. And after checking on an interrupt event you should |
mbed_official | 130:1dec54e4aec3 | 47 | clear it using DMA_ClearITPendingBit() function. |
mbed_official | 130:1dec54e4aec3 | 48 | @endverbatim |
mbed_official | 130:1dec54e4aec3 | 49 | * |
mbed_official | 130:1dec54e4aec3 | 50 | ****************************************************************************** |
mbed_official | 130:1dec54e4aec3 | 51 | * @attention |
mbed_official | 130:1dec54e4aec3 | 52 | * |
mbed_official | 130:1dec54e4aec3 | 53 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 130:1dec54e4aec3 | 54 | * |
mbed_official | 130:1dec54e4aec3 | 55 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 130:1dec54e4aec3 | 56 | * are permitted provided that the following conditions are met: |
mbed_official | 130:1dec54e4aec3 | 57 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 130:1dec54e4aec3 | 58 | * this list of conditions and the following disclaimer. |
mbed_official | 130:1dec54e4aec3 | 59 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 130:1dec54e4aec3 | 60 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 130:1dec54e4aec3 | 61 | * and/or other materials provided with the distribution. |
mbed_official | 130:1dec54e4aec3 | 62 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 130:1dec54e4aec3 | 63 | * may be used to endorse or promote products derived from this software |
mbed_official | 130:1dec54e4aec3 | 64 | * without specific prior written permission. |
mbed_official | 130:1dec54e4aec3 | 65 | * |
mbed_official | 130:1dec54e4aec3 | 66 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 130:1dec54e4aec3 | 67 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 130:1dec54e4aec3 | 68 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 130:1dec54e4aec3 | 69 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 130:1dec54e4aec3 | 70 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 130:1dec54e4aec3 | 71 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 130:1dec54e4aec3 | 72 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 130:1dec54e4aec3 | 73 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 130:1dec54e4aec3 | 74 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 130:1dec54e4aec3 | 75 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 130:1dec54e4aec3 | 76 | * |
mbed_official | 130:1dec54e4aec3 | 77 | ****************************************************************************** |
mbed_official | 130:1dec54e4aec3 | 78 | */ |
mbed_official | 130:1dec54e4aec3 | 79 | |
mbed_official | 130:1dec54e4aec3 | 80 | /* Includes ------------------------------------------------------------------*/ |
mbed_official | 130:1dec54e4aec3 | 81 | #include "stm32f0xx_dma.h" |
mbed_official | 130:1dec54e4aec3 | 82 | |
mbed_official | 130:1dec54e4aec3 | 83 | /** @addtogroup STM32F0xx_StdPeriph_Driver |
mbed_official | 130:1dec54e4aec3 | 84 | * @{ |
mbed_official | 130:1dec54e4aec3 | 85 | */ |
mbed_official | 130:1dec54e4aec3 | 86 | |
mbed_official | 130:1dec54e4aec3 | 87 | /** @defgroup DMA |
mbed_official | 130:1dec54e4aec3 | 88 | * @brief DMA driver modules |
mbed_official | 130:1dec54e4aec3 | 89 | * @{ |
mbed_official | 130:1dec54e4aec3 | 90 | */ |
mbed_official | 130:1dec54e4aec3 | 91 | |
mbed_official | 130:1dec54e4aec3 | 92 | /* Private typedef -----------------------------------------------------------*/ |
mbed_official | 130:1dec54e4aec3 | 93 | /* Private define ------------------------------------------------------------*/ |
mbed_official | 130:1dec54e4aec3 | 94 | #define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */ |
mbed_official | 130:1dec54e4aec3 | 95 | |
mbed_official | 130:1dec54e4aec3 | 96 | /* DMA1 Channelx interrupt pending bit masks */ |
mbed_official | 130:1dec54e4aec3 | 97 | #define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1)) |
mbed_official | 130:1dec54e4aec3 | 98 | #define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2)) |
mbed_official | 130:1dec54e4aec3 | 99 | #define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3)) |
mbed_official | 130:1dec54e4aec3 | 100 | #define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4)) |
mbed_official | 130:1dec54e4aec3 | 101 | #define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5)) |
mbed_official | 130:1dec54e4aec3 | 102 | #define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6)) /*!< Only applicable for STM32F072 devices */ |
mbed_official | 130:1dec54e4aec3 | 103 | #define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7)) /*!< Only applicable for STM32F072 devices */ |
mbed_official | 130:1dec54e4aec3 | 104 | |
mbed_official | 130:1dec54e4aec3 | 105 | /* Private macro -------------------------------------------------------------*/ |
mbed_official | 130:1dec54e4aec3 | 106 | /* Private variables ---------------------------------------------------------*/ |
mbed_official | 130:1dec54e4aec3 | 107 | /* Private function prototypes -----------------------------------------------*/ |
mbed_official | 130:1dec54e4aec3 | 108 | /* Private functions ---------------------------------------------------------*/ |
mbed_official | 130:1dec54e4aec3 | 109 | |
mbed_official | 130:1dec54e4aec3 | 110 | /** @defgroup DMA_Private_Functions |
mbed_official | 130:1dec54e4aec3 | 111 | * @{ |
mbed_official | 130:1dec54e4aec3 | 112 | */ |
mbed_official | 130:1dec54e4aec3 | 113 | |
mbed_official | 130:1dec54e4aec3 | 114 | /** @defgroup DMA_Group1 Initialization and Configuration functions |
mbed_official | 130:1dec54e4aec3 | 115 | * @brief Initialization and Configuration functions |
mbed_official | 130:1dec54e4aec3 | 116 | * |
mbed_official | 130:1dec54e4aec3 | 117 | @verbatim |
mbed_official | 130:1dec54e4aec3 | 118 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 119 | ##### Initialization and Configuration functions ##### |
mbed_official | 130:1dec54e4aec3 | 120 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 121 | [..] This subsection provides functions allowing to initialize the DMA channel |
mbed_official | 130:1dec54e4aec3 | 122 | source and destination addresses, incrementation and data sizes, transfer |
mbed_official | 130:1dec54e4aec3 | 123 | direction, buffer size, circular/normal mode selection, memory-to-memory |
mbed_official | 130:1dec54e4aec3 | 124 | mode selection and channel priority value. |
mbed_official | 130:1dec54e4aec3 | 125 | [..] The DMA_Init() function follows the DMA configuration procedures as described |
mbed_official | 130:1dec54e4aec3 | 126 | in reference manual (RM0091). |
mbed_official | 130:1dec54e4aec3 | 127 | @endverbatim |
mbed_official | 130:1dec54e4aec3 | 128 | * @{ |
mbed_official | 130:1dec54e4aec3 | 129 | */ |
mbed_official | 130:1dec54e4aec3 | 130 | |
mbed_official | 130:1dec54e4aec3 | 131 | /** |
mbed_official | 130:1dec54e4aec3 | 132 | * @brief Deinitializes the DMAy Channelx registers to their default reset |
mbed_official | 130:1dec54e4aec3 | 133 | * values. |
mbed_official | 130:1dec54e4aec3 | 134 | * @param DMAy_Channelx: where y can be 1 to select the DMA and |
mbed_official | 130:1dec54e4aec3 | 135 | * x can be 1 to 7 for DMA1 to select the DMA Channel. |
mbed_official | 130:1dec54e4aec3 | 136 | * @note Channel 6 and 7 are available only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 137 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 138 | */ |
mbed_official | 130:1dec54e4aec3 | 139 | void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) |
mbed_official | 130:1dec54e4aec3 | 140 | { |
mbed_official | 130:1dec54e4aec3 | 141 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 142 | assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
mbed_official | 130:1dec54e4aec3 | 143 | |
mbed_official | 130:1dec54e4aec3 | 144 | /* Disable the selected DMAy Channelx */ |
mbed_official | 130:1dec54e4aec3 | 145 | DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN); |
mbed_official | 130:1dec54e4aec3 | 146 | |
mbed_official | 130:1dec54e4aec3 | 147 | /* Reset DMAy Channelx control register */ |
mbed_official | 130:1dec54e4aec3 | 148 | DMAy_Channelx->CCR = 0; |
mbed_official | 130:1dec54e4aec3 | 149 | |
mbed_official | 130:1dec54e4aec3 | 150 | /* Reset DMAy Channelx remaining bytes register */ |
mbed_official | 130:1dec54e4aec3 | 151 | DMAy_Channelx->CNDTR = 0; |
mbed_official | 130:1dec54e4aec3 | 152 | |
mbed_official | 130:1dec54e4aec3 | 153 | /* Reset DMAy Channelx peripheral address register */ |
mbed_official | 130:1dec54e4aec3 | 154 | DMAy_Channelx->CPAR = 0; |
mbed_official | 130:1dec54e4aec3 | 155 | |
mbed_official | 130:1dec54e4aec3 | 156 | /* Reset DMAy Channelx memory address register */ |
mbed_official | 130:1dec54e4aec3 | 157 | DMAy_Channelx->CMAR = 0; |
mbed_official | 130:1dec54e4aec3 | 158 | |
mbed_official | 130:1dec54e4aec3 | 159 | if (DMAy_Channelx == DMA1_Channel1) |
mbed_official | 130:1dec54e4aec3 | 160 | { |
mbed_official | 130:1dec54e4aec3 | 161 | /* Reset interrupt pending bits for DMA1 Channel1 */ |
mbed_official | 130:1dec54e4aec3 | 162 | DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK; |
mbed_official | 130:1dec54e4aec3 | 163 | } |
mbed_official | 130:1dec54e4aec3 | 164 | else if (DMAy_Channelx == DMA1_Channel2) |
mbed_official | 130:1dec54e4aec3 | 165 | { |
mbed_official | 130:1dec54e4aec3 | 166 | /* Reset interrupt pending bits for DMA1 Channel2 */ |
mbed_official | 130:1dec54e4aec3 | 167 | DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK; |
mbed_official | 130:1dec54e4aec3 | 168 | } |
mbed_official | 130:1dec54e4aec3 | 169 | else if (DMAy_Channelx == DMA1_Channel3) |
mbed_official | 130:1dec54e4aec3 | 170 | { |
mbed_official | 130:1dec54e4aec3 | 171 | /* Reset interrupt pending bits for DMA1 Channel3 */ |
mbed_official | 130:1dec54e4aec3 | 172 | DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK; |
mbed_official | 130:1dec54e4aec3 | 173 | } |
mbed_official | 130:1dec54e4aec3 | 174 | else if (DMAy_Channelx == DMA1_Channel4) |
mbed_official | 130:1dec54e4aec3 | 175 | { |
mbed_official | 130:1dec54e4aec3 | 176 | /* Reset interrupt pending bits for DMA1 Channel4 */ |
mbed_official | 130:1dec54e4aec3 | 177 | DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK; |
mbed_official | 130:1dec54e4aec3 | 178 | } |
mbed_official | 130:1dec54e4aec3 | 179 | else if (DMAy_Channelx == DMA1_Channel5) |
mbed_official | 130:1dec54e4aec3 | 180 | { |
mbed_official | 130:1dec54e4aec3 | 181 | /* Reset interrupt pending bits for DMA1 Channel5 */ |
mbed_official | 130:1dec54e4aec3 | 182 | DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK; |
mbed_official | 130:1dec54e4aec3 | 183 | } |
mbed_official | 130:1dec54e4aec3 | 184 | else if (DMAy_Channelx == DMA1_Channel6) |
mbed_official | 130:1dec54e4aec3 | 185 | { |
mbed_official | 130:1dec54e4aec3 | 186 | /* Reset interrupt pending bits for DMA1 Channel6 */ |
mbed_official | 130:1dec54e4aec3 | 187 | DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK; |
mbed_official | 130:1dec54e4aec3 | 188 | } |
mbed_official | 130:1dec54e4aec3 | 189 | else |
mbed_official | 130:1dec54e4aec3 | 190 | { |
mbed_official | 130:1dec54e4aec3 | 191 | if (DMAy_Channelx == DMA1_Channel7) |
mbed_official | 130:1dec54e4aec3 | 192 | { |
mbed_official | 130:1dec54e4aec3 | 193 | /* Reset interrupt pending bits for DMA1 Channel7 */ |
mbed_official | 130:1dec54e4aec3 | 194 | DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK; |
mbed_official | 130:1dec54e4aec3 | 195 | } |
mbed_official | 130:1dec54e4aec3 | 196 | } |
mbed_official | 130:1dec54e4aec3 | 197 | } |
mbed_official | 130:1dec54e4aec3 | 198 | |
mbed_official | 130:1dec54e4aec3 | 199 | /** |
mbed_official | 130:1dec54e4aec3 | 200 | * @brief Initializes the DMAy Channelx according to the specified parameters |
mbed_official | 130:1dec54e4aec3 | 201 | * in the DMA_InitStruct. |
mbed_official | 130:1dec54e4aec3 | 202 | * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7 |
mbed_official | 130:1dec54e4aec3 | 203 | * for DMA1 to select the DMA Channel. |
mbed_official | 130:1dec54e4aec3 | 204 | * @note Channel 6 and 7 are available only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 205 | * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains |
mbed_official | 130:1dec54e4aec3 | 206 | * the configuration information for the specified DMA Channel. |
mbed_official | 130:1dec54e4aec3 | 207 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 208 | */ |
mbed_official | 130:1dec54e4aec3 | 209 | void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct) |
mbed_official | 130:1dec54e4aec3 | 210 | { |
mbed_official | 130:1dec54e4aec3 | 211 | uint32_t tmpreg = 0; |
mbed_official | 130:1dec54e4aec3 | 212 | |
mbed_official | 130:1dec54e4aec3 | 213 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 214 | assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
mbed_official | 130:1dec54e4aec3 | 215 | assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR)); |
mbed_official | 130:1dec54e4aec3 | 216 | assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); |
mbed_official | 130:1dec54e4aec3 | 217 | assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); |
mbed_official | 130:1dec54e4aec3 | 218 | assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); |
mbed_official | 130:1dec54e4aec3 | 219 | assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); |
mbed_official | 130:1dec54e4aec3 | 220 | assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); |
mbed_official | 130:1dec54e4aec3 | 221 | assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); |
mbed_official | 130:1dec54e4aec3 | 222 | assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); |
mbed_official | 130:1dec54e4aec3 | 223 | assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M)); |
mbed_official | 130:1dec54e4aec3 | 224 | |
mbed_official | 130:1dec54e4aec3 | 225 | /*--------------------------- DMAy Channelx CCR Configuration ----------------*/ |
mbed_official | 130:1dec54e4aec3 | 226 | /* Get the DMAy_Channelx CCR value */ |
mbed_official | 130:1dec54e4aec3 | 227 | tmpreg = DMAy_Channelx->CCR; |
mbed_official | 130:1dec54e4aec3 | 228 | |
mbed_official | 130:1dec54e4aec3 | 229 | /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ |
mbed_official | 130:1dec54e4aec3 | 230 | tmpreg &= CCR_CLEAR_MASK; |
mbed_official | 130:1dec54e4aec3 | 231 | |
mbed_official | 130:1dec54e4aec3 | 232 | /* Configure DMAy Channelx: data transfer, data size, priority level and mode */ |
mbed_official | 130:1dec54e4aec3 | 233 | /* Set DIR bit according to DMA_DIR value */ |
mbed_official | 130:1dec54e4aec3 | 234 | /* Set CIRC bit according to DMA_Mode value */ |
mbed_official | 130:1dec54e4aec3 | 235 | /* Set PINC bit according to DMA_PeripheralInc value */ |
mbed_official | 130:1dec54e4aec3 | 236 | /* Set MINC bit according to DMA_MemoryInc value */ |
mbed_official | 130:1dec54e4aec3 | 237 | /* Set PSIZE bits according to DMA_PeripheralDataSize value */ |
mbed_official | 130:1dec54e4aec3 | 238 | /* Set MSIZE bits according to DMA_MemoryDataSize value */ |
mbed_official | 130:1dec54e4aec3 | 239 | /* Set PL bits according to DMA_Priority value */ |
mbed_official | 130:1dec54e4aec3 | 240 | /* Set the MEM2MEM bit according to DMA_M2M value */ |
mbed_official | 130:1dec54e4aec3 | 241 | tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | |
mbed_official | 130:1dec54e4aec3 | 242 | DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | |
mbed_official | 130:1dec54e4aec3 | 243 | DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | |
mbed_official | 130:1dec54e4aec3 | 244 | DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; |
mbed_official | 130:1dec54e4aec3 | 245 | |
mbed_official | 130:1dec54e4aec3 | 246 | /* Write to DMAy Channelx CCR */ |
mbed_official | 130:1dec54e4aec3 | 247 | DMAy_Channelx->CCR = tmpreg; |
mbed_official | 130:1dec54e4aec3 | 248 | |
mbed_official | 130:1dec54e4aec3 | 249 | /*--------------------------- DMAy Channelx CNDTR Configuration --------------*/ |
mbed_official | 130:1dec54e4aec3 | 250 | /* Write to DMAy Channelx CNDTR */ |
mbed_official | 130:1dec54e4aec3 | 251 | DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize; |
mbed_official | 130:1dec54e4aec3 | 252 | |
mbed_official | 130:1dec54e4aec3 | 253 | /*--------------------------- DMAy Channelx CPAR Configuration ---------------*/ |
mbed_official | 130:1dec54e4aec3 | 254 | /* Write to DMAy Channelx CPAR */ |
mbed_official | 130:1dec54e4aec3 | 255 | DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr; |
mbed_official | 130:1dec54e4aec3 | 256 | |
mbed_official | 130:1dec54e4aec3 | 257 | /*--------------------------- DMAy Channelx CMAR Configuration ---------------*/ |
mbed_official | 130:1dec54e4aec3 | 258 | /* Write to DMAy Channelx CMAR */ |
mbed_official | 130:1dec54e4aec3 | 259 | DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr; |
mbed_official | 130:1dec54e4aec3 | 260 | } |
mbed_official | 130:1dec54e4aec3 | 261 | |
mbed_official | 130:1dec54e4aec3 | 262 | /** |
mbed_official | 130:1dec54e4aec3 | 263 | * @brief Fills each DMA_InitStruct member with its default value. |
mbed_official | 130:1dec54e4aec3 | 264 | * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will |
mbed_official | 130:1dec54e4aec3 | 265 | * be initialized. |
mbed_official | 130:1dec54e4aec3 | 266 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 267 | */ |
mbed_official | 130:1dec54e4aec3 | 268 | void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) |
mbed_official | 130:1dec54e4aec3 | 269 | { |
mbed_official | 130:1dec54e4aec3 | 270 | /*-------------- Reset DMA init structure parameters values ------------------*/ |
mbed_official | 130:1dec54e4aec3 | 271 | /* Initialize the DMA_PeripheralBaseAddr member */ |
mbed_official | 130:1dec54e4aec3 | 272 | DMA_InitStruct->DMA_PeripheralBaseAddr = 0; |
mbed_official | 130:1dec54e4aec3 | 273 | /* Initialize the DMA_MemoryBaseAddr member */ |
mbed_official | 130:1dec54e4aec3 | 274 | DMA_InitStruct->DMA_MemoryBaseAddr = 0; |
mbed_official | 130:1dec54e4aec3 | 275 | /* Initialize the DMA_DIR member */ |
mbed_official | 130:1dec54e4aec3 | 276 | DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; |
mbed_official | 130:1dec54e4aec3 | 277 | /* Initialize the DMA_BufferSize member */ |
mbed_official | 130:1dec54e4aec3 | 278 | DMA_InitStruct->DMA_BufferSize = 0; |
mbed_official | 130:1dec54e4aec3 | 279 | /* Initialize the DMA_PeripheralInc member */ |
mbed_official | 130:1dec54e4aec3 | 280 | DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; |
mbed_official | 130:1dec54e4aec3 | 281 | /* Initialize the DMA_MemoryInc member */ |
mbed_official | 130:1dec54e4aec3 | 282 | DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; |
mbed_official | 130:1dec54e4aec3 | 283 | /* Initialize the DMA_PeripheralDataSize member */ |
mbed_official | 130:1dec54e4aec3 | 284 | DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; |
mbed_official | 130:1dec54e4aec3 | 285 | /* Initialize the DMA_MemoryDataSize member */ |
mbed_official | 130:1dec54e4aec3 | 286 | DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; |
mbed_official | 130:1dec54e4aec3 | 287 | /* Initialize the DMA_Mode member */ |
mbed_official | 130:1dec54e4aec3 | 288 | DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; |
mbed_official | 130:1dec54e4aec3 | 289 | /* Initialize the DMA_Priority member */ |
mbed_official | 130:1dec54e4aec3 | 290 | DMA_InitStruct->DMA_Priority = DMA_Priority_Low; |
mbed_official | 130:1dec54e4aec3 | 291 | /* Initialize the DMA_M2M member */ |
mbed_official | 130:1dec54e4aec3 | 292 | DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; |
mbed_official | 130:1dec54e4aec3 | 293 | } |
mbed_official | 130:1dec54e4aec3 | 294 | |
mbed_official | 130:1dec54e4aec3 | 295 | /** |
mbed_official | 130:1dec54e4aec3 | 296 | * @brief Enables or disables the specified DMAy Channelx. |
mbed_official | 130:1dec54e4aec3 | 297 | * @param DMAy_Channelx: where y can be 1 to select the DMA and |
mbed_official | 130:1dec54e4aec3 | 298 | * x can be 1 to 7 for DMA1 to select the DMA Channel. |
mbed_official | 130:1dec54e4aec3 | 299 | * @note Channel 6 and 7 are available only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 300 | * @param NewState: new state of the DMAy Channelx. |
mbed_official | 130:1dec54e4aec3 | 301 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 130:1dec54e4aec3 | 302 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 303 | */ |
mbed_official | 130:1dec54e4aec3 | 304 | void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) |
mbed_official | 130:1dec54e4aec3 | 305 | { |
mbed_official | 130:1dec54e4aec3 | 306 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 307 | assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
mbed_official | 130:1dec54e4aec3 | 308 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 130:1dec54e4aec3 | 309 | |
mbed_official | 130:1dec54e4aec3 | 310 | if (NewState != DISABLE) |
mbed_official | 130:1dec54e4aec3 | 311 | { |
mbed_official | 130:1dec54e4aec3 | 312 | /* Enable the selected DMAy Channelx */ |
mbed_official | 130:1dec54e4aec3 | 313 | DMAy_Channelx->CCR |= DMA_CCR_EN; |
mbed_official | 130:1dec54e4aec3 | 314 | } |
mbed_official | 130:1dec54e4aec3 | 315 | else |
mbed_official | 130:1dec54e4aec3 | 316 | { |
mbed_official | 130:1dec54e4aec3 | 317 | /* Disable the selected DMAy Channelx */ |
mbed_official | 130:1dec54e4aec3 | 318 | DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN); |
mbed_official | 130:1dec54e4aec3 | 319 | } |
mbed_official | 130:1dec54e4aec3 | 320 | } |
mbed_official | 130:1dec54e4aec3 | 321 | |
mbed_official | 130:1dec54e4aec3 | 322 | /** |
mbed_official | 130:1dec54e4aec3 | 323 | * @} |
mbed_official | 130:1dec54e4aec3 | 324 | */ |
mbed_official | 130:1dec54e4aec3 | 325 | |
mbed_official | 130:1dec54e4aec3 | 326 | /** @defgroup DMA_Group2 Data Counter functions |
mbed_official | 130:1dec54e4aec3 | 327 | * @brief Data Counter functions |
mbed_official | 130:1dec54e4aec3 | 328 | * |
mbed_official | 130:1dec54e4aec3 | 329 | @verbatim |
mbed_official | 130:1dec54e4aec3 | 330 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 331 | ##### Data Counter functions ##### |
mbed_official | 130:1dec54e4aec3 | 332 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 333 | [..] This subsection provides function allowing to configure and read the buffer |
mbed_official | 130:1dec54e4aec3 | 334 | size (number of data to be transferred).The DMA data counter can be written |
mbed_official | 130:1dec54e4aec3 | 335 | only when the DMA channel is disabled (ie. after transfer complete event). |
mbed_official | 130:1dec54e4aec3 | 336 | [..] The following function can be used to write the Channel data counter value: |
mbed_official | 130:1dec54e4aec3 | 337 | (+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t |
mbed_official | 130:1dec54e4aec3 | 338 | DataNumber). |
mbed_official | 130:1dec54e4aec3 | 339 | -@- It is advised to use this function rather than DMA_Init() in situations |
mbed_official | 130:1dec54e4aec3 | 340 | where only the Data buffer needs to be reloaded. |
mbed_official | 130:1dec54e4aec3 | 341 | [..] The DMA data counter can be read to indicate the number of remaining transfers |
mbed_official | 130:1dec54e4aec3 | 342 | for the relative DMA channel. This counter is decremented at the end of each |
mbed_official | 130:1dec54e4aec3 | 343 | data transfer and when the transfer is complete: |
mbed_official | 130:1dec54e4aec3 | 344 | (+) If Normal mode is selected: the counter is set to 0. |
mbed_official | 130:1dec54e4aec3 | 345 | (+) If Circular mode is selected: the counter is reloaded with the initial |
mbed_official | 130:1dec54e4aec3 | 346 | value(configured before enabling the DMA channel). |
mbed_official | 130:1dec54e4aec3 | 347 | [..] The following function can be used to read the Channel data counter value: |
mbed_official | 130:1dec54e4aec3 | 348 | (+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx). |
mbed_official | 130:1dec54e4aec3 | 349 | |
mbed_official | 130:1dec54e4aec3 | 350 | @endverbatim |
mbed_official | 130:1dec54e4aec3 | 351 | * @{ |
mbed_official | 130:1dec54e4aec3 | 352 | */ |
mbed_official | 130:1dec54e4aec3 | 353 | |
mbed_official | 130:1dec54e4aec3 | 354 | /** |
mbed_official | 130:1dec54e4aec3 | 355 | * @brief Sets the number of data units in the current DMAy Channelx transfer. |
mbed_official | 130:1dec54e4aec3 | 356 | * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be |
mbed_official | 130:1dec54e4aec3 | 357 | * 1 to 7 for DMA1 to select the DMA Channel. |
mbed_official | 130:1dec54e4aec3 | 358 | * @note Channel 6 and 7 are available only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 359 | * @param DataNumber: The number of data units in the current DMAy Channelx |
mbed_official | 130:1dec54e4aec3 | 360 | * transfer. |
mbed_official | 130:1dec54e4aec3 | 361 | * @note This function can only be used when the DMAy_Channelx is disabled. |
mbed_official | 130:1dec54e4aec3 | 362 | * @retval None. |
mbed_official | 130:1dec54e4aec3 | 363 | */ |
mbed_official | 130:1dec54e4aec3 | 364 | void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber) |
mbed_official | 130:1dec54e4aec3 | 365 | { |
mbed_official | 130:1dec54e4aec3 | 366 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 367 | assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
mbed_official | 130:1dec54e4aec3 | 368 | |
mbed_official | 130:1dec54e4aec3 | 369 | /*--------------------------- DMAy Channelx CNDTR Configuration --------------*/ |
mbed_official | 130:1dec54e4aec3 | 370 | /* Write to DMAy Channelx CNDTR */ |
mbed_official | 130:1dec54e4aec3 | 371 | DMAy_Channelx->CNDTR = DataNumber; |
mbed_official | 130:1dec54e4aec3 | 372 | } |
mbed_official | 130:1dec54e4aec3 | 373 | |
mbed_official | 130:1dec54e4aec3 | 374 | /** |
mbed_official | 130:1dec54e4aec3 | 375 | * @brief Returns the number of remaining data units in the current |
mbed_official | 130:1dec54e4aec3 | 376 | * DMAy Channelx transfer. |
mbed_official | 130:1dec54e4aec3 | 377 | * @param DMAy_Channelx: where y can be 1 to select the DMA and |
mbed_official | 130:1dec54e4aec3 | 378 | * x can be 1 to 7 for DMA1 to select the DMA Channel. |
mbed_official | 130:1dec54e4aec3 | 379 | * @note Channel 6 and 7 are available only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 380 | * @retval The number of remaining data units in the current DMAy Channelx |
mbed_official | 130:1dec54e4aec3 | 381 | * transfer. |
mbed_official | 130:1dec54e4aec3 | 382 | */ |
mbed_official | 130:1dec54e4aec3 | 383 | uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) |
mbed_official | 130:1dec54e4aec3 | 384 | { |
mbed_official | 130:1dec54e4aec3 | 385 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 386 | assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
mbed_official | 130:1dec54e4aec3 | 387 | /* Return the number of remaining data units for DMAy Channelx */ |
mbed_official | 130:1dec54e4aec3 | 388 | return ((uint16_t)(DMAy_Channelx->CNDTR)); |
mbed_official | 130:1dec54e4aec3 | 389 | } |
mbed_official | 130:1dec54e4aec3 | 390 | |
mbed_official | 130:1dec54e4aec3 | 391 | /** |
mbed_official | 130:1dec54e4aec3 | 392 | * @} |
mbed_official | 130:1dec54e4aec3 | 393 | */ |
mbed_official | 130:1dec54e4aec3 | 394 | |
mbed_official | 130:1dec54e4aec3 | 395 | /** @defgroup DMA_Group3 Interrupts and flags management functions |
mbed_official | 130:1dec54e4aec3 | 396 | * @brief Interrupts and flags management functions |
mbed_official | 130:1dec54e4aec3 | 397 | * |
mbed_official | 130:1dec54e4aec3 | 398 | @verbatim |
mbed_official | 130:1dec54e4aec3 | 399 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 400 | ##### Interrupts and flags management functions ##### |
mbed_official | 130:1dec54e4aec3 | 401 | =============================================================================== |
mbed_official | 130:1dec54e4aec3 | 402 | [..] This subsection provides functions allowing to configure the DMA Interrupts |
mbed_official | 130:1dec54e4aec3 | 403 | sources and check or clear the flags or pending bits status. |
mbed_official | 130:1dec54e4aec3 | 404 | The user should identify which mode will be used in his application to manage |
mbed_official | 130:1dec54e4aec3 | 405 | the DMA controller events: Polling mode or Interrupt mode. |
mbed_official | 130:1dec54e4aec3 | 406 | *** Polling Mode *** |
mbed_official | 130:1dec54e4aec3 | 407 | ==================== |
mbed_official | 130:1dec54e4aec3 | 408 | [..] Each DMA channel can be managed through 4 event Flags:(y : DMA Controller |
mbed_official | 130:1dec54e4aec3 | 409 | number x : DMA channel number ). |
mbed_official | 130:1dec54e4aec3 | 410 | (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred. |
mbed_official | 130:1dec54e4aec3 | 411 | (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred. |
mbed_official | 130:1dec54e4aec3 | 412 | (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred. |
mbed_official | 130:1dec54e4aec3 | 413 | (#) DMAy_FLAG_GLx : to indicate that at least one of the events described |
mbed_official | 130:1dec54e4aec3 | 414 | above occurred. |
mbed_official | 130:1dec54e4aec3 | 415 | -@- Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the |
mbed_official | 130:1dec54e4aec3 | 416 | same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). |
mbed_official | 130:1dec54e4aec3 | 417 | [..]In this Mode it is advised to use the following functions: |
mbed_official | 130:1dec54e4aec3 | 418 | (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG); |
mbed_official | 130:1dec54e4aec3 | 419 | (+) void DMA_ClearFlag(uint32_t DMA_FLAG); |
mbed_official | 130:1dec54e4aec3 | 420 | |
mbed_official | 130:1dec54e4aec3 | 421 | *** Interrupt Mode *** |
mbed_official | 130:1dec54e4aec3 | 422 | ====================== |
mbed_official | 130:1dec54e4aec3 | 423 | [..] Each DMA channel can be managed through 4 Interrupts: |
mbed_official | 130:1dec54e4aec3 | 424 | (+) Interrupt Source |
mbed_official | 130:1dec54e4aec3 | 425 | (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete |
mbed_official | 130:1dec54e4aec3 | 426 | event. |
mbed_official | 130:1dec54e4aec3 | 427 | (##) DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete |
mbed_official | 130:1dec54e4aec3 | 428 | event. |
mbed_official | 130:1dec54e4aec3 | 429 | (##) DMA_IT_TE : specifies the interrupt source for the transfer errors event. |
mbed_official | 130:1dec54e4aec3 | 430 | (##) DMA_IT_GL : to indicate that at least one of the interrupts described |
mbed_official | 130:1dec54e4aec3 | 431 | above occurred. |
mbed_official | 130:1dec54e4aec3 | 432 | -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of |
mbed_official | 130:1dec54e4aec3 | 433 | the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE). |
mbed_official | 130:1dec54e4aec3 | 434 | [..]In this Mode it is advised to use the following functions: |
mbed_official | 130:1dec54e4aec3 | 435 | (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, |
mbed_official | 130:1dec54e4aec3 | 436 | FunctionalState NewState); |
mbed_official | 130:1dec54e4aec3 | 437 | (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT); |
mbed_official | 130:1dec54e4aec3 | 438 | (+) void DMA_ClearITPendingBit(uint32_t DMA_IT); |
mbed_official | 130:1dec54e4aec3 | 439 | |
mbed_official | 130:1dec54e4aec3 | 440 | @endverbatim |
mbed_official | 130:1dec54e4aec3 | 441 | * @{ |
mbed_official | 130:1dec54e4aec3 | 442 | */ |
mbed_official | 130:1dec54e4aec3 | 443 | |
mbed_official | 130:1dec54e4aec3 | 444 | /** |
mbed_official | 130:1dec54e4aec3 | 445 | * @brief Enables or disables the specified DMAy Channelx interrupts. |
mbed_official | 130:1dec54e4aec3 | 446 | * @param DMAy_Channelx: where y can be 1 to select the DMA and |
mbed_official | 130:1dec54e4aec3 | 447 | * x can be 1 to 7 for DMA1 to select the DMA Channel. |
mbed_official | 130:1dec54e4aec3 | 448 | * @note Channel 6 and 7 are available only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 449 | * @param DMA_IT: specifies the DMA interrupts sources to be enabled |
mbed_official | 130:1dec54e4aec3 | 450 | * or disabled. |
mbed_official | 130:1dec54e4aec3 | 451 | * This parameter can be any combination of the following values: |
mbed_official | 130:1dec54e4aec3 | 452 | * @arg DMA_IT_TC: Transfer complete interrupt mask |
mbed_official | 130:1dec54e4aec3 | 453 | * @arg DMA_IT_HT: Half transfer interrupt mask |
mbed_official | 130:1dec54e4aec3 | 454 | * @arg DMA_IT_TE: Transfer error interrupt mask |
mbed_official | 130:1dec54e4aec3 | 455 | * @param NewState: new state of the specified DMA interrupts. |
mbed_official | 130:1dec54e4aec3 | 456 | * This parameter can be: ENABLE or DISABLE. |
mbed_official | 130:1dec54e4aec3 | 457 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 458 | */ |
mbed_official | 130:1dec54e4aec3 | 459 | void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) |
mbed_official | 130:1dec54e4aec3 | 460 | { |
mbed_official | 130:1dec54e4aec3 | 461 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 462 | assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx)); |
mbed_official | 130:1dec54e4aec3 | 463 | assert_param(IS_DMA_CONFIG_IT(DMA_IT)); |
mbed_official | 130:1dec54e4aec3 | 464 | assert_param(IS_FUNCTIONAL_STATE(NewState)); |
mbed_official | 130:1dec54e4aec3 | 465 | |
mbed_official | 130:1dec54e4aec3 | 466 | if (NewState != DISABLE) |
mbed_official | 130:1dec54e4aec3 | 467 | { |
mbed_official | 130:1dec54e4aec3 | 468 | /* Enable the selected DMA interrupts */ |
mbed_official | 130:1dec54e4aec3 | 469 | DMAy_Channelx->CCR |= DMA_IT; |
mbed_official | 130:1dec54e4aec3 | 470 | } |
mbed_official | 130:1dec54e4aec3 | 471 | else |
mbed_official | 130:1dec54e4aec3 | 472 | { |
mbed_official | 130:1dec54e4aec3 | 473 | /* Disable the selected DMA interrupts */ |
mbed_official | 130:1dec54e4aec3 | 474 | DMAy_Channelx->CCR &= ~DMA_IT; |
mbed_official | 130:1dec54e4aec3 | 475 | } |
mbed_official | 130:1dec54e4aec3 | 476 | } |
mbed_official | 130:1dec54e4aec3 | 477 | |
mbed_official | 130:1dec54e4aec3 | 478 | /** |
mbed_official | 130:1dec54e4aec3 | 479 | * @brief Checks whether the specified DMAy Channelx flag is set or not. |
mbed_official | 130:1dec54e4aec3 | 480 | * @param DMA_FLAG: specifies the flag to check. |
mbed_official | 130:1dec54e4aec3 | 481 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 482 | * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. |
mbed_official | 130:1dec54e4aec3 | 483 | * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. |
mbed_official | 130:1dec54e4aec3 | 484 | * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. |
mbed_official | 130:1dec54e4aec3 | 485 | * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. |
mbed_official | 130:1dec54e4aec3 | 486 | * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. |
mbed_official | 130:1dec54e4aec3 | 487 | * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. |
mbed_official | 130:1dec54e4aec3 | 488 | * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. |
mbed_official | 130:1dec54e4aec3 | 489 | * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. |
mbed_official | 130:1dec54e4aec3 | 490 | * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. |
mbed_official | 130:1dec54e4aec3 | 491 | * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. |
mbed_official | 130:1dec54e4aec3 | 492 | * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. |
mbed_official | 130:1dec54e4aec3 | 493 | * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. |
mbed_official | 130:1dec54e4aec3 | 494 | * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. |
mbed_official | 130:1dec54e4aec3 | 495 | * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. |
mbed_official | 130:1dec54e4aec3 | 496 | * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. |
mbed_official | 130:1dec54e4aec3 | 497 | * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. |
mbed_official | 130:1dec54e4aec3 | 498 | * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. |
mbed_official | 130:1dec54e4aec3 | 499 | * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. |
mbed_official | 130:1dec54e4aec3 | 500 | * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. |
mbed_official | 130:1dec54e4aec3 | 501 | * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. |
mbed_official | 130:1dec54e4aec3 | 502 | * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 503 | * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 504 | * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 505 | * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 506 | * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 507 | * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 508 | * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 509 | * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 510 | * @note The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags |
mbed_official | 130:1dec54e4aec3 | 511 | * relative to the same channel is set (Transfer Complete, Half-transfer |
mbed_official | 130:1dec54e4aec3 | 512 | * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or |
mbed_official | 130:1dec54e4aec3 | 513 | * DMAy_FLAG_TEx). |
mbed_official | 130:1dec54e4aec3 | 514 | * |
mbed_official | 130:1dec54e4aec3 | 515 | * @retval The new state of DMA_FLAG (SET or RESET). |
mbed_official | 130:1dec54e4aec3 | 516 | */ |
mbed_official | 130:1dec54e4aec3 | 517 | FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG) |
mbed_official | 130:1dec54e4aec3 | 518 | { |
mbed_official | 130:1dec54e4aec3 | 519 | FlagStatus bitstatus = RESET; |
mbed_official | 130:1dec54e4aec3 | 520 | |
mbed_official | 130:1dec54e4aec3 | 521 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 522 | assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); |
mbed_official | 130:1dec54e4aec3 | 523 | |
mbed_official | 130:1dec54e4aec3 | 524 | /* Check the status of the specified DMA flag */ |
mbed_official | 130:1dec54e4aec3 | 525 | if ((DMA1->ISR & DMA_FLAG) != (uint32_t)RESET) |
mbed_official | 130:1dec54e4aec3 | 526 | { |
mbed_official | 130:1dec54e4aec3 | 527 | /* DMA_FLAG is set */ |
mbed_official | 130:1dec54e4aec3 | 528 | bitstatus = SET; |
mbed_official | 130:1dec54e4aec3 | 529 | } |
mbed_official | 130:1dec54e4aec3 | 530 | else |
mbed_official | 130:1dec54e4aec3 | 531 | { |
mbed_official | 130:1dec54e4aec3 | 532 | /* DMA_FLAG is reset */ |
mbed_official | 130:1dec54e4aec3 | 533 | bitstatus = RESET; |
mbed_official | 130:1dec54e4aec3 | 534 | } |
mbed_official | 130:1dec54e4aec3 | 535 | |
mbed_official | 130:1dec54e4aec3 | 536 | /* Return the DMA_FLAG status */ |
mbed_official | 130:1dec54e4aec3 | 537 | return bitstatus; |
mbed_official | 130:1dec54e4aec3 | 538 | } |
mbed_official | 130:1dec54e4aec3 | 539 | |
mbed_official | 130:1dec54e4aec3 | 540 | /** |
mbed_official | 130:1dec54e4aec3 | 541 | * @brief Clears the DMAy Channelx's pending flags. |
mbed_official | 130:1dec54e4aec3 | 542 | * @param DMA_FLAG: specifies the flag to clear. |
mbed_official | 130:1dec54e4aec3 | 543 | * This parameter can be any combination (for the same DMA) of the following values: |
mbed_official | 130:1dec54e4aec3 | 544 | * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag. |
mbed_official | 130:1dec54e4aec3 | 545 | * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag. |
mbed_official | 130:1dec54e4aec3 | 546 | * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag. |
mbed_official | 130:1dec54e4aec3 | 547 | * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag. |
mbed_official | 130:1dec54e4aec3 | 548 | * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag. |
mbed_official | 130:1dec54e4aec3 | 549 | * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag. |
mbed_official | 130:1dec54e4aec3 | 550 | * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag. |
mbed_official | 130:1dec54e4aec3 | 551 | * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag. |
mbed_official | 130:1dec54e4aec3 | 552 | * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag. |
mbed_official | 130:1dec54e4aec3 | 553 | * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag. |
mbed_official | 130:1dec54e4aec3 | 554 | * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag. |
mbed_official | 130:1dec54e4aec3 | 555 | * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag. |
mbed_official | 130:1dec54e4aec3 | 556 | * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag. |
mbed_official | 130:1dec54e4aec3 | 557 | * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag. |
mbed_official | 130:1dec54e4aec3 | 558 | * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag. |
mbed_official | 130:1dec54e4aec3 | 559 | * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag. |
mbed_official | 130:1dec54e4aec3 | 560 | * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag. |
mbed_official | 130:1dec54e4aec3 | 561 | * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag. |
mbed_official | 130:1dec54e4aec3 | 562 | * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag. |
mbed_official | 130:1dec54e4aec3 | 563 | * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag. |
mbed_official | 130:1dec54e4aec3 | 564 | * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 565 | * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 566 | * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 567 | * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 568 | * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 569 | * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 570 | * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 571 | * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 572 | * |
mbed_official | 130:1dec54e4aec3 | 573 | * @note Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags |
mbed_official | 130:1dec54e4aec3 | 574 | * relative to the same channel (Transfer Complete, Half-transfer Complete and |
mbed_official | 130:1dec54e4aec3 | 575 | * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx). |
mbed_official | 130:1dec54e4aec3 | 576 | * |
mbed_official | 130:1dec54e4aec3 | 577 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 578 | */ |
mbed_official | 130:1dec54e4aec3 | 579 | void DMA_ClearFlag(uint32_t DMA_FLAG) |
mbed_official | 130:1dec54e4aec3 | 580 | { |
mbed_official | 130:1dec54e4aec3 | 581 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 582 | assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); |
mbed_official | 130:1dec54e4aec3 | 583 | |
mbed_official | 130:1dec54e4aec3 | 584 | /* Clear the selected DMA flags */ |
mbed_official | 130:1dec54e4aec3 | 585 | DMA1->IFCR = DMA_FLAG; |
mbed_official | 130:1dec54e4aec3 | 586 | } |
mbed_official | 130:1dec54e4aec3 | 587 | |
mbed_official | 130:1dec54e4aec3 | 588 | /** |
mbed_official | 130:1dec54e4aec3 | 589 | * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. |
mbed_official | 130:1dec54e4aec3 | 590 | * @param DMA_IT: specifies the DMA interrupt source to check. |
mbed_official | 130:1dec54e4aec3 | 591 | * This parameter can be one of the following values: |
mbed_official | 130:1dec54e4aec3 | 592 | * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. |
mbed_official | 130:1dec54e4aec3 | 593 | * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. |
mbed_official | 130:1dec54e4aec3 | 594 | * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. |
mbed_official | 130:1dec54e4aec3 | 595 | * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. |
mbed_official | 130:1dec54e4aec3 | 596 | * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. |
mbed_official | 130:1dec54e4aec3 | 597 | * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. |
mbed_official | 130:1dec54e4aec3 | 598 | * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. |
mbed_official | 130:1dec54e4aec3 | 599 | * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. |
mbed_official | 130:1dec54e4aec3 | 600 | * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. |
mbed_official | 130:1dec54e4aec3 | 601 | * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. |
mbed_official | 130:1dec54e4aec3 | 602 | * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. |
mbed_official | 130:1dec54e4aec3 | 603 | * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. |
mbed_official | 130:1dec54e4aec3 | 604 | * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. |
mbed_official | 130:1dec54e4aec3 | 605 | * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. |
mbed_official | 130:1dec54e4aec3 | 606 | * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. |
mbed_official | 130:1dec54e4aec3 | 607 | * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. |
mbed_official | 130:1dec54e4aec3 | 608 | * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. |
mbed_official | 130:1dec54e4aec3 | 609 | * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. |
mbed_official | 130:1dec54e4aec3 | 610 | * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. |
mbed_official | 130:1dec54e4aec3 | 611 | * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. |
mbed_official | 130:1dec54e4aec3 | 612 | * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 613 | * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 614 | * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 615 | * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 616 | * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 617 | * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 618 | * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 619 | * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 620 | * |
mbed_official | 130:1dec54e4aec3 | 621 | * @note The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other |
mbed_official | 130:1dec54e4aec3 | 622 | * interrupts relative to the same channel is set (Transfer Complete, |
mbed_official | 130:1dec54e4aec3 | 623 | * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx, |
mbed_official | 130:1dec54e4aec3 | 624 | * DMAy_IT_HTx or DMAy_IT_TEx). |
mbed_official | 130:1dec54e4aec3 | 625 | * |
mbed_official | 130:1dec54e4aec3 | 626 | * @retval The new state of DMA_IT (SET or RESET). |
mbed_official | 130:1dec54e4aec3 | 627 | */ |
mbed_official | 130:1dec54e4aec3 | 628 | ITStatus DMA_GetITStatus(uint32_t DMA_IT) |
mbed_official | 130:1dec54e4aec3 | 629 | { |
mbed_official | 130:1dec54e4aec3 | 630 | ITStatus bitstatus = RESET; |
mbed_official | 130:1dec54e4aec3 | 631 | |
mbed_official | 130:1dec54e4aec3 | 632 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 633 | assert_param(IS_DMA_GET_IT(DMA_IT)); |
mbed_official | 130:1dec54e4aec3 | 634 | |
mbed_official | 130:1dec54e4aec3 | 635 | /* Check the status of the specified DMA interrupt */ |
mbed_official | 130:1dec54e4aec3 | 636 | if ((DMA1->ISR & DMA_IT) != (uint32_t)RESET) |
mbed_official | 130:1dec54e4aec3 | 637 | { |
mbed_official | 130:1dec54e4aec3 | 638 | /* DMA_IT is set */ |
mbed_official | 130:1dec54e4aec3 | 639 | bitstatus = SET; |
mbed_official | 130:1dec54e4aec3 | 640 | } |
mbed_official | 130:1dec54e4aec3 | 641 | else |
mbed_official | 130:1dec54e4aec3 | 642 | { |
mbed_official | 130:1dec54e4aec3 | 643 | /* DMA_IT is reset */ |
mbed_official | 130:1dec54e4aec3 | 644 | bitstatus = RESET; |
mbed_official | 130:1dec54e4aec3 | 645 | } |
mbed_official | 130:1dec54e4aec3 | 646 | /* Return the DMA_IT status */ |
mbed_official | 130:1dec54e4aec3 | 647 | return bitstatus; |
mbed_official | 130:1dec54e4aec3 | 648 | } |
mbed_official | 130:1dec54e4aec3 | 649 | |
mbed_official | 130:1dec54e4aec3 | 650 | /** |
mbed_official | 130:1dec54e4aec3 | 651 | * @brief Clears the DMAy Channelx's interrupt pending bits. |
mbed_official | 130:1dec54e4aec3 | 652 | * @param DMA_IT: specifies the DMA interrupt pending bit to clear. |
mbed_official | 130:1dec54e4aec3 | 653 | * This parameter can be any combination (for the same DMA) of the following values: |
mbed_official | 130:1dec54e4aec3 | 654 | * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt. |
mbed_official | 130:1dec54e4aec3 | 655 | * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt. |
mbed_official | 130:1dec54e4aec3 | 656 | * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt. |
mbed_official | 130:1dec54e4aec3 | 657 | * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt. |
mbed_official | 130:1dec54e4aec3 | 658 | * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt. |
mbed_official | 130:1dec54e4aec3 | 659 | * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt. |
mbed_official | 130:1dec54e4aec3 | 660 | * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt. |
mbed_official | 130:1dec54e4aec3 | 661 | * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt. |
mbed_official | 130:1dec54e4aec3 | 662 | * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt. |
mbed_official | 130:1dec54e4aec3 | 663 | * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt. |
mbed_official | 130:1dec54e4aec3 | 664 | * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt. |
mbed_official | 130:1dec54e4aec3 | 665 | * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt. |
mbed_official | 130:1dec54e4aec3 | 666 | * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt. |
mbed_official | 130:1dec54e4aec3 | 667 | * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt. |
mbed_official | 130:1dec54e4aec3 | 668 | * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt. |
mbed_official | 130:1dec54e4aec3 | 669 | * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt. |
mbed_official | 130:1dec54e4aec3 | 670 | * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt. |
mbed_official | 130:1dec54e4aec3 | 671 | * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt. |
mbed_official | 130:1dec54e4aec3 | 672 | * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt. |
mbed_official | 130:1dec54e4aec3 | 673 | * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt. |
mbed_official | 130:1dec54e4aec3 | 674 | * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 675 | * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 676 | * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 677 | * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 678 | * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 679 | * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 680 | * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 681 | * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt, applicable only for STM32F072 devices. |
mbed_official | 130:1dec54e4aec3 | 682 | * |
mbed_official | 130:1dec54e4aec3 | 683 | * @note Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other |
mbed_official | 130:1dec54e4aec3 | 684 | * interrupts relative to the same channel (Transfer Complete, Half-transfer |
mbed_official | 130:1dec54e4aec3 | 685 | * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and |
mbed_official | 130:1dec54e4aec3 | 686 | * DMAy_IT_TEx). |
mbed_official | 130:1dec54e4aec3 | 687 | * |
mbed_official | 130:1dec54e4aec3 | 688 | * @retval None |
mbed_official | 130:1dec54e4aec3 | 689 | */ |
mbed_official | 130:1dec54e4aec3 | 690 | void DMA_ClearITPendingBit(uint32_t DMA_IT) |
mbed_official | 130:1dec54e4aec3 | 691 | { |
mbed_official | 130:1dec54e4aec3 | 692 | /* Check the parameters */ |
mbed_official | 130:1dec54e4aec3 | 693 | assert_param(IS_DMA_CLEAR_IT(DMA_IT)); |
mbed_official | 130:1dec54e4aec3 | 694 | |
mbed_official | 130:1dec54e4aec3 | 695 | /* Clear the selected DMA interrupt pending bits */ |
mbed_official | 130:1dec54e4aec3 | 696 | DMA1->IFCR = DMA_IT; |
mbed_official | 130:1dec54e4aec3 | 697 | } |
mbed_official | 130:1dec54e4aec3 | 698 | |
mbed_official | 130:1dec54e4aec3 | 699 | /** |
mbed_official | 130:1dec54e4aec3 | 700 | * @} |
mbed_official | 130:1dec54e4aec3 | 701 | */ |
mbed_official | 130:1dec54e4aec3 | 702 | |
mbed_official | 130:1dec54e4aec3 | 703 | /** |
mbed_official | 130:1dec54e4aec3 | 704 | * @} |
mbed_official | 130:1dec54e4aec3 | 705 | */ |
mbed_official | 130:1dec54e4aec3 | 706 | |
mbed_official | 130:1dec54e4aec3 | 707 | /** |
mbed_official | 130:1dec54e4aec3 | 708 | * @} |
mbed_official | 130:1dec54e4aec3 | 709 | */ |
mbed_official | 130:1dec54e4aec3 | 710 | |
mbed_official | 130:1dec54e4aec3 | 711 | /** |
mbed_official | 130:1dec54e4aec3 | 712 | * @} |
mbed_official | 130:1dec54e4aec3 | 713 | */ |
mbed_official | 130:1dec54e4aec3 | 714 | |
mbed_official | 130:1dec54e4aec3 | 715 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |