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targets/cmsis/TARGET_NXP/TARGET_LPC408X/LPC407x_8x_177x_8x.h@308:59cc78a25982, 2014-09-05 (annotated)
- Committer:
- todotani
- Date:
- Fri Sep 05 14:20:33 2014 +0000
- Revision:
- 308:59cc78a25982
- Parent:
- 29:6ac4027eff2b
BLE_Health_Thermometer for mbed HRM1017 with BLE library 0.1.0
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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bogdanm | 15:4892fe388435 | 1 | /****************************************************************************************************//** |
bogdanm | 15:4892fe388435 | 2 | * $Id$ LPC407x_8x_177x_8x.h 2012-04-25 |
bogdanm | 15:4892fe388435 | 3 | *//** |
bogdanm | 15:4892fe388435 | 4 | * @file LPC407x_8x_177x_8x.h |
bogdanm | 15:4892fe388435 | 5 | * |
bogdanm | 15:4892fe388435 | 6 | * @brief CMSIS Cortex-M4 Cortex-M3 Peripheral Access Layer Header File for |
bogdanm | 15:4892fe388435 | 7 | * NXP LPC407x_8x_177x_8x. |
bogdanm | 15:4892fe388435 | 8 | * @version V0.7 |
bogdanm | 15:4892fe388435 | 9 | * @date 20. June 2012 |
bogdanm | 15:4892fe388435 | 10 | * @author NXP MCU SW Application Team |
bogdanm | 15:4892fe388435 | 11 | * |
bogdanm | 15:4892fe388435 | 12 | * Copyright(C) 2012, NXP Semiconductor |
bogdanm | 15:4892fe388435 | 13 | * All rights reserved. |
bogdanm | 15:4892fe388435 | 14 | * |
bogdanm | 15:4892fe388435 | 15 | *********************************************************************** |
bogdanm | 15:4892fe388435 | 16 | * Software that is described herein is for illustrative purposes only |
bogdanm | 15:4892fe388435 | 17 | * which provides customers with programming information regarding the |
bogdanm | 15:4892fe388435 | 18 | * products. This software is supplied "AS IS" without any warranties. |
bogdanm | 15:4892fe388435 | 19 | * NXP Semiconductors assumes no responsibility or liability for the |
bogdanm | 15:4892fe388435 | 20 | * use of the software, conveys no license or title under any patent, |
bogdanm | 15:4892fe388435 | 21 | * copyright, or mask work right to the product. NXP Semiconductors |
bogdanm | 15:4892fe388435 | 22 | * reserves the right to make changes in the software without |
bogdanm | 15:4892fe388435 | 23 | * notification. NXP Semiconductors also make no representation or |
bogdanm | 15:4892fe388435 | 24 | * warranty that such application will be suitable for the specified |
bogdanm | 15:4892fe388435 | 25 | * use without further testing or modification. |
bogdanm | 15:4892fe388435 | 26 | * Permission to use, copy, modify, and distribute this software and its |
bogdanm | 15:4892fe388435 | 27 | * documentation is hereby granted, under NXP Semiconductors' |
bogdanm | 15:4892fe388435 | 28 | * relevant copyright in the software, without fee, provided that it |
bogdanm | 15:4892fe388435 | 29 | * is used in conjunction with NXP Semiconductors microcontrollers. This |
bogdanm | 15:4892fe388435 | 30 | * copyright, permission, and disclaimer notice must appear in all copies of |
bogdanm | 15:4892fe388435 | 31 | * this code. |
bogdanm | 15:4892fe388435 | 32 | **********************************************************************/ |
bogdanm | 15:4892fe388435 | 33 | |
bogdanm | 15:4892fe388435 | 34 | #ifndef __LPC407x_8x_177x_8x_H__ |
bogdanm | 15:4892fe388435 | 35 | #define __LPC407x_8x_177x_8x_H__ |
bogdanm | 15:4892fe388435 | 36 | |
mbed_official | 29:6ac4027eff2b | 37 | #if defined(__CORTEX_M4) && !defined(CORE_M4) |
mbed_official | 29:6ac4027eff2b | 38 | #define CORE_M4 |
mbed_official | 29:6ac4027eff2b | 39 | #endif |
bogdanm | 15:4892fe388435 | 40 | |
bogdanm | 15:4892fe388435 | 41 | // ################## |
bogdanm | 15:4892fe388435 | 42 | // Code Red - excluded extern "C" as unrequired |
bogdanm | 15:4892fe388435 | 43 | // ################## |
bogdanm | 15:4892fe388435 | 44 | #if 0 |
bogdanm | 15:4892fe388435 | 45 | #ifdef __cplusplus |
bogdanm | 15:4892fe388435 | 46 | extern "C" { |
bogdanm | 15:4892fe388435 | 47 | #endif |
bogdanm | 15:4892fe388435 | 48 | #endif |
bogdanm | 15:4892fe388435 | 49 | |
bogdanm | 15:4892fe388435 | 50 | |
bogdanm | 15:4892fe388435 | 51 | /* ------------------------- Interrupt Number Definition ------------------------ */ |
bogdanm | 15:4892fe388435 | 52 | |
bogdanm | 15:4892fe388435 | 53 | typedef enum IRQn |
bogdanm | 15:4892fe388435 | 54 | { |
bogdanm | 15:4892fe388435 | 55 | /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ |
bogdanm | 15:4892fe388435 | 56 | Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ |
bogdanm | 15:4892fe388435 | 57 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
bogdanm | 15:4892fe388435 | 58 | HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ |
bogdanm | 15:4892fe388435 | 59 | MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ |
bogdanm | 15:4892fe388435 | 60 | BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ |
bogdanm | 15:4892fe388435 | 61 | UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ |
bogdanm | 15:4892fe388435 | 62 | SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ |
bogdanm | 15:4892fe388435 | 63 | DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ |
bogdanm | 15:4892fe388435 | 64 | PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ |
bogdanm | 15:4892fe388435 | 65 | SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ |
bogdanm | 15:4892fe388435 | 66 | |
bogdanm | 15:4892fe388435 | 67 | /****** LPC407x_8x_177x_8x Specific Interrupt Numbers *******************************************************/ |
bogdanm | 15:4892fe388435 | 68 | WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */ |
bogdanm | 15:4892fe388435 | 69 | TIMER0_IRQn = 1, /*!< Timer0 Interrupt */ |
bogdanm | 15:4892fe388435 | 70 | TIMER1_IRQn = 2, /*!< Timer1 Interrupt */ |
bogdanm | 15:4892fe388435 | 71 | TIMER2_IRQn = 3, /*!< Timer2 Interrupt */ |
bogdanm | 15:4892fe388435 | 72 | TIMER3_IRQn = 4, /*!< Timer3 Interrupt */ |
bogdanm | 15:4892fe388435 | 73 | UART0_IRQn = 5, /*!< UART0 Interrupt */ |
bogdanm | 15:4892fe388435 | 74 | UART1_IRQn = 6, /*!< UART1 Interrupt */ |
bogdanm | 15:4892fe388435 | 75 | UART2_IRQn = 7, /*!< UART2 Interrupt */ |
bogdanm | 15:4892fe388435 | 76 | UART3_IRQn = 8, /*!< UART3 Interrupt */ |
bogdanm | 15:4892fe388435 | 77 | PWM1_IRQn = 9, /*!< PWM1 Interrupt */ |
bogdanm | 15:4892fe388435 | 78 | I2C0_IRQn = 10, /*!< I2C0 Interrupt */ |
bogdanm | 15:4892fe388435 | 79 | I2C1_IRQn = 11, /*!< I2C1 Interrupt */ |
bogdanm | 15:4892fe388435 | 80 | I2C2_IRQn = 12, /*!< I2C2 Interrupt */ |
bogdanm | 15:4892fe388435 | 81 | Reserved0_IRQn = 13, /*!< Reserved */ |
bogdanm | 15:4892fe388435 | 82 | SSP0_IRQn = 14, /*!< SSP0 Interrupt */ |
bogdanm | 15:4892fe388435 | 83 | SSP1_IRQn = 15, /*!< SSP1 Interrupt */ |
bogdanm | 15:4892fe388435 | 84 | PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */ |
bogdanm | 15:4892fe388435 | 85 | RTC_IRQn = 17, /*!< Real Time Clock Interrupt */ |
bogdanm | 15:4892fe388435 | 86 | EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */ |
bogdanm | 15:4892fe388435 | 87 | EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */ |
bogdanm | 15:4892fe388435 | 88 | EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */ |
bogdanm | 15:4892fe388435 | 89 | EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */ |
bogdanm | 15:4892fe388435 | 90 | ADC_IRQn = 22, /*!< A/D Converter Interrupt */ |
bogdanm | 15:4892fe388435 | 91 | BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */ |
bogdanm | 15:4892fe388435 | 92 | USB_IRQn = 24, /*!< USB Interrupt */ |
bogdanm | 15:4892fe388435 | 93 | CAN_IRQn = 25, /*!< CAN Interrupt */ |
bogdanm | 15:4892fe388435 | 94 | DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */ |
bogdanm | 15:4892fe388435 | 95 | I2S_IRQn = 27, /*!< I2S Interrupt */ |
bogdanm | 15:4892fe388435 | 96 | ENET_IRQn = 28, /*!< Ethernet Interrupt */ |
bogdanm | 15:4892fe388435 | 97 | MCI_IRQn = 29, /*!< SD/MMC card I/F Interrupt */ |
bogdanm | 15:4892fe388435 | 98 | MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */ |
bogdanm | 15:4892fe388435 | 99 | QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */ |
bogdanm | 15:4892fe388435 | 100 | PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */ |
bogdanm | 15:4892fe388435 | 101 | USBActivity_IRQn = 33, /*!< USB Activity interrupt */ |
bogdanm | 15:4892fe388435 | 102 | CANActivity_IRQn = 34, /*!< CAN Activity interrupt */ |
bogdanm | 15:4892fe388435 | 103 | UART4_IRQn = 35, /*!< UART4 Interrupt */ |
bogdanm | 15:4892fe388435 | 104 | SSP2_IRQn = 36, /*!< SSP2 Interrupt */ |
bogdanm | 15:4892fe388435 | 105 | LCD_IRQn = 37, /*!< LCD Interrupt */ |
bogdanm | 15:4892fe388435 | 106 | GPIO_IRQn = 38, /*!< GPIO Interrupt */ |
bogdanm | 15:4892fe388435 | 107 | PWM0_IRQn = 39, /*!< 39 PWM0 */ |
bogdanm | 15:4892fe388435 | 108 | EEPROM_IRQn = 40, /*!< 40 EEPROM */ |
bogdanm | 15:4892fe388435 | 109 | CMP0_IRQn = 41, /*!< 41 CMP0 */ |
bogdanm | 15:4892fe388435 | 110 | CMP1_IRQn = 42 /*!< 42 CMP1 */ |
bogdanm | 15:4892fe388435 | 111 | } IRQn_Type; |
bogdanm | 15:4892fe388435 | 112 | |
bogdanm | 15:4892fe388435 | 113 | /* ================================================================================ */ |
bogdanm | 15:4892fe388435 | 114 | /* ================ Processor and Core Peripheral Section ================ */ |
bogdanm | 15:4892fe388435 | 115 | /* ================================================================================ */ |
bogdanm | 15:4892fe388435 | 116 | #ifdef CORE_M4 |
bogdanm | 15:4892fe388435 | 117 | /* ----------------Configuration of the cm4 Processor and Core Peripherals---------------- */ |
bogdanm | 15:4892fe388435 | 118 | #define __CM4_REV 0x0000 /*!< Cortex-M4 Core Revision */ |
bogdanm | 15:4892fe388435 | 119 | #define __MPU_PRESENT 1 /*!< MPU present or not */ |
bogdanm | 15:4892fe388435 | 120 | #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ |
bogdanm | 15:4892fe388435 | 121 | #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ |
bogdanm | 15:4892fe388435 | 122 | #define __FPU_PRESENT 1 /*!< FPU present or not */ |
bogdanm | 15:4892fe388435 | 123 | |
bogdanm | 15:4892fe388435 | 124 | |
bogdanm | 15:4892fe388435 | 125 | #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */ |
bogdanm | 15:4892fe388435 | 126 | #else |
bogdanm | 15:4892fe388435 | 127 | /* Configuration of the Cortex-M3 Processor and Core Peripherals */ |
bogdanm | 15:4892fe388435 | 128 | #define __MPU_PRESENT 1 /*!< MPU present or not */ |
bogdanm | 15:4892fe388435 | 129 | #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */ |
bogdanm | 15:4892fe388435 | 130 | #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ |
bogdanm | 15:4892fe388435 | 131 | |
bogdanm | 15:4892fe388435 | 132 | |
bogdanm | 15:4892fe388435 | 133 | #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */ |
bogdanm | 15:4892fe388435 | 134 | |
bogdanm | 15:4892fe388435 | 135 | #endif |
bogdanm | 15:4892fe388435 | 136 | |
bogdanm | 15:4892fe388435 | 137 | #include "system_LPC407x_8x_177x_8x.h" /*!< LPC408x_7x System */ |
bogdanm | 15:4892fe388435 | 138 | |
bogdanm | 15:4892fe388435 | 139 | |
bogdanm | 15:4892fe388435 | 140 | |
bogdanm | 15:4892fe388435 | 141 | |
bogdanm | 15:4892fe388435 | 142 | |
bogdanm | 15:4892fe388435 | 143 | |
bogdanm | 15:4892fe388435 | 144 | /* ================================================================================ */ |
bogdanm | 15:4892fe388435 | 145 | /* ================ Device Specific Peripheral Section ================ */ |
bogdanm | 15:4892fe388435 | 146 | /* ================================================================================ */ |
bogdanm | 15:4892fe388435 | 147 | |
bogdanm | 15:4892fe388435 | 148 | #if defined ( __CC_ARM ) |
bogdanm | 15:4892fe388435 | 149 | #pragma anon_unions |
bogdanm | 15:4892fe388435 | 150 | #endif |
bogdanm | 15:4892fe388435 | 151 | |
bogdanm | 15:4892fe388435 | 152 | /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ |
bogdanm | 15:4892fe388435 | 153 | typedef struct /* Common Registers */ |
bogdanm | 15:4892fe388435 | 154 | { |
bogdanm | 15:4892fe388435 | 155 | __I uint32_t IntStat; |
bogdanm | 15:4892fe388435 | 156 | __I uint32_t IntTCStat; |
bogdanm | 15:4892fe388435 | 157 | __O uint32_t IntTCClear; |
bogdanm | 15:4892fe388435 | 158 | __I uint32_t IntErrStat; |
bogdanm | 15:4892fe388435 | 159 | __O uint32_t IntErrClr; |
bogdanm | 15:4892fe388435 | 160 | __I uint32_t RawIntTCStat; |
bogdanm | 15:4892fe388435 | 161 | __I uint32_t RawIntErrStat; |
bogdanm | 15:4892fe388435 | 162 | __I uint32_t EnbldChns; |
bogdanm | 15:4892fe388435 | 163 | __IO uint32_t SoftBReq; |
bogdanm | 15:4892fe388435 | 164 | __IO uint32_t SoftSReq; |
bogdanm | 15:4892fe388435 | 165 | __IO uint32_t SoftLBReq; |
bogdanm | 15:4892fe388435 | 166 | __IO uint32_t SoftLSReq; |
bogdanm | 15:4892fe388435 | 167 | __IO uint32_t Config; |
bogdanm | 15:4892fe388435 | 168 | __IO uint32_t Sync; |
bogdanm | 15:4892fe388435 | 169 | } LPC_GPDMA_TypeDef; |
bogdanm | 15:4892fe388435 | 170 | |
bogdanm | 15:4892fe388435 | 171 | typedef struct /* Channel Registers */ |
bogdanm | 15:4892fe388435 | 172 | { |
bogdanm | 15:4892fe388435 | 173 | __IO uint32_t CSrcAddr; |
bogdanm | 15:4892fe388435 | 174 | __IO uint32_t CDestAddr; |
bogdanm | 15:4892fe388435 | 175 | __IO uint32_t CLLI; |
bogdanm | 15:4892fe388435 | 176 | __IO uint32_t CControl; |
bogdanm | 15:4892fe388435 | 177 | __IO uint32_t CConfig; |
bogdanm | 15:4892fe388435 | 178 | } LPC_GPDMACH_TypeDef; |
bogdanm | 15:4892fe388435 | 179 | |
bogdanm | 15:4892fe388435 | 180 | /*------------- System Control (SC) ------------------------------------------*/ |
bogdanm | 15:4892fe388435 | 181 | typedef struct |
bogdanm | 15:4892fe388435 | 182 | { |
bogdanm | 15:4892fe388435 | 183 | __IO uint32_t FLASHCFG; /*!< Offset: 0x000 (R/W) Flash Accelerator Configuration Register */ |
bogdanm | 15:4892fe388435 | 184 | uint32_t RESERVED0[31]; |
bogdanm | 15:4892fe388435 | 185 | __IO uint32_t PLL0CON; /*!< Offset: 0x080 (R/W) PLL0 Control Register */ |
bogdanm | 15:4892fe388435 | 186 | __IO uint32_t PLL0CFG; /*!< Offset: 0x084 (R/W) PLL0 Configuration Register */ |
bogdanm | 15:4892fe388435 | 187 | __I uint32_t PLL0STAT; /*!< Offset: 0x088 (R/ ) PLL0 Status Register */ |
bogdanm | 15:4892fe388435 | 188 | __O uint32_t PLL0FEED; /*!< Offset: 0x08C ( /W) PLL0 Feed Register */ |
bogdanm | 15:4892fe388435 | 189 | uint32_t RESERVED1[4]; |
bogdanm | 15:4892fe388435 | 190 | __IO uint32_t PLL1CON; /*!< Offset: 0x0A0 (R/W) PLL1 Control Register */ |
bogdanm | 15:4892fe388435 | 191 | __IO uint32_t PLL1CFG; /*!< Offset: 0x0A4 (R/W) PLL1 Configuration Register */ |
bogdanm | 15:4892fe388435 | 192 | __I uint32_t PLL1STAT; /*!< Offset: 0x0A8 (R/ ) PLL1 Status Register */ |
bogdanm | 15:4892fe388435 | 193 | __O uint32_t PLL1FEED; /*!< Offset: 0x0AC ( /W) PLL1 Feed Register */ |
bogdanm | 15:4892fe388435 | 194 | uint32_t RESERVED2[4]; |
bogdanm | 15:4892fe388435 | 195 | __IO uint32_t PCON; /*!< Offset: 0x0C0 (R/W) Power Control Register */ |
bogdanm | 15:4892fe388435 | 196 | __IO uint32_t PCONP; /*!< Offset: 0x0C4 (R/W) Power Control for Peripherals Register */ |
bogdanm | 15:4892fe388435 | 197 | __IO uint32_t PCONP1; /*!< Offset: 0x0C8 (R/W) Power Control for Peripherals Register */ |
bogdanm | 15:4892fe388435 | 198 | uint32_t RESERVED3[13]; |
bogdanm | 15:4892fe388435 | 199 | __IO uint32_t EMCCLKSEL; /*!< Offset: 0x100 (R/W) External Memory Controller Clock Selection Register */ |
bogdanm | 15:4892fe388435 | 200 | __IO uint32_t CCLKSEL; /*!< Offset: 0x104 (R/W) CPU Clock Selection Register */ |
bogdanm | 15:4892fe388435 | 201 | __IO uint32_t USBCLKSEL; /*!< Offset: 0x108 (R/W) USB Clock Selection Register */ |
bogdanm | 15:4892fe388435 | 202 | __IO uint32_t CLKSRCSEL; /*!< Offset: 0x10C (R/W) Clock Source Select Register */ |
bogdanm | 15:4892fe388435 | 203 | __IO uint32_t CANSLEEPCLR; /*!< Offset: 0x110 (R/W) CAN Sleep Clear Register */ |
bogdanm | 15:4892fe388435 | 204 | __IO uint32_t CANWAKEFLAGS; /*!< Offset: 0x114 (R/W) CAN Wake-up Flags Register */ |
bogdanm | 15:4892fe388435 | 205 | uint32_t RESERVED4[10]; |
bogdanm | 15:4892fe388435 | 206 | __IO uint32_t EXTINT; /*!< Offset: 0x140 (R/W) External Interrupt Flag Register */ |
bogdanm | 15:4892fe388435 | 207 | uint32_t RESERVED5[1]; |
bogdanm | 15:4892fe388435 | 208 | __IO uint32_t EXTMODE; /*!< Offset: 0x148 (R/W) External Interrupt Mode Register */ |
bogdanm | 15:4892fe388435 | 209 | __IO uint32_t EXTPOLAR; /*!< Offset: 0x14C (R/W) External Interrupt Polarity Register */ |
bogdanm | 15:4892fe388435 | 210 | uint32_t RESERVED6[12]; |
bogdanm | 15:4892fe388435 | 211 | __IO uint32_t RSID; /*!< Offset: 0x180 (R/W) Reset Source Identification Register */ |
bogdanm | 15:4892fe388435 | 212 | uint32_t RESERVED7[7]; |
bogdanm | 15:4892fe388435 | 213 | __IO uint32_t SCS; /*!< Offset: 0x1A0 (R/W) System Controls and Status Register */ |
bogdanm | 15:4892fe388435 | 214 | __IO uint32_t IRCTRIM; /*!< Offset: 0x1A4 (R/W) Clock Dividers */ |
bogdanm | 15:4892fe388435 | 215 | __IO uint32_t PCLKSEL; /*!< Offset: 0x1A8 (R/W) Peripheral Clock Selection Register */ |
bogdanm | 15:4892fe388435 | 216 | uint32_t RESERVED8; |
bogdanm | 15:4892fe388435 | 217 | __IO uint32_t PBOOST; /*!< Offset: 0x1B0 (R/W) Power Boost control register */ |
bogdanm | 15:4892fe388435 | 218 | __IO uint32_t SPIFICLKSEL; |
bogdanm | 15:4892fe388435 | 219 | __IO uint32_t LCD_CFG; /*!< Offset: 0x1B8 (R/W) LCD Configuration and clocking control Register */ |
bogdanm | 15:4892fe388435 | 220 | uint32_t RESERVED10[1]; |
bogdanm | 15:4892fe388435 | 221 | __IO uint32_t USBIntSt; /*!< Offset: 0x1C0 (R/W) USB Interrupt Status Register */ |
bogdanm | 15:4892fe388435 | 222 | __IO uint32_t DMAREQSEL; /*!< Offset: 0x1C4 (R/W) DMA Request Select Register */ |
bogdanm | 15:4892fe388435 | 223 | __IO uint32_t CLKOUTCFG; /*!< Offset: 0x1C8 (R/W) Clock Output Configuration Register */ |
bogdanm | 15:4892fe388435 | 224 | __IO uint32_t RSTCON0; /*!< Offset: 0x1CC (R/W) RESET Control0 Register */ |
bogdanm | 15:4892fe388435 | 225 | __IO uint32_t RSTCON1; /*!< Offset: 0x1D0 (R/W) RESET Control1 Register */ |
bogdanm | 15:4892fe388435 | 226 | uint32_t RESERVED11[2]; |
bogdanm | 15:4892fe388435 | 227 | __IO uint32_t EMCDLYCTL; /*!< Offset: 0x1DC (R/W) SDRAM programmable delays */ |
bogdanm | 15:4892fe388435 | 228 | __IO uint32_t EMCCAL; /*!< Offset: 0x1E0 (R/W) Calibration of programmable delays */ |
bogdanm | 15:4892fe388435 | 229 | } LPC_SC_TypeDef; |
bogdanm | 15:4892fe388435 | 230 | /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ |
bogdanm | 15:4892fe388435 | 231 | typedef struct |
bogdanm | 15:4892fe388435 | 232 | { |
bogdanm | 15:4892fe388435 | 233 | __IO uint32_t MAC1; /* MAC Registers */ |
bogdanm | 15:4892fe388435 | 234 | __IO uint32_t MAC2; |
bogdanm | 15:4892fe388435 | 235 | __IO uint32_t IPGT; |
bogdanm | 15:4892fe388435 | 236 | __IO uint32_t IPGR; |
bogdanm | 15:4892fe388435 | 237 | __IO uint32_t CLRT; |
bogdanm | 15:4892fe388435 | 238 | __IO uint32_t MAXF; |
bogdanm | 15:4892fe388435 | 239 | __IO uint32_t SUPP; |
bogdanm | 15:4892fe388435 | 240 | __IO uint32_t TEST; |
bogdanm | 15:4892fe388435 | 241 | __IO uint32_t MCFG; |
bogdanm | 15:4892fe388435 | 242 | __IO uint32_t MCMD; |
bogdanm | 15:4892fe388435 | 243 | __IO uint32_t MADR; |
bogdanm | 15:4892fe388435 | 244 | __O uint32_t MWTD; |
bogdanm | 15:4892fe388435 | 245 | __I uint32_t MRDD; |
bogdanm | 15:4892fe388435 | 246 | __I uint32_t MIND; |
bogdanm | 15:4892fe388435 | 247 | uint32_t RESERVED0[2]; |
bogdanm | 15:4892fe388435 | 248 | __IO uint32_t SA0; |
bogdanm | 15:4892fe388435 | 249 | __IO uint32_t SA1; |
bogdanm | 15:4892fe388435 | 250 | __IO uint32_t SA2; |
bogdanm | 15:4892fe388435 | 251 | uint32_t RESERVED1[45]; |
bogdanm | 15:4892fe388435 | 252 | __IO uint32_t Command; /* Control Registers */ |
bogdanm | 15:4892fe388435 | 253 | __I uint32_t Status; |
bogdanm | 15:4892fe388435 | 254 | __IO uint32_t RxDescriptor; |
bogdanm | 15:4892fe388435 | 255 | __IO uint32_t RxStatus; |
bogdanm | 15:4892fe388435 | 256 | __IO uint32_t RxDescriptorNumber; |
bogdanm | 15:4892fe388435 | 257 | __I uint32_t RxProduceIndex; |
bogdanm | 15:4892fe388435 | 258 | __IO uint32_t RxConsumeIndex; |
bogdanm | 15:4892fe388435 | 259 | __IO uint32_t TxDescriptor; |
bogdanm | 15:4892fe388435 | 260 | __IO uint32_t TxStatus; |
bogdanm | 15:4892fe388435 | 261 | __IO uint32_t TxDescriptorNumber; |
bogdanm | 15:4892fe388435 | 262 | __IO uint32_t TxProduceIndex; |
bogdanm | 15:4892fe388435 | 263 | __I uint32_t TxConsumeIndex; |
bogdanm | 15:4892fe388435 | 264 | uint32_t RESERVED2[10]; |
bogdanm | 15:4892fe388435 | 265 | __I uint32_t TSV0; |
bogdanm | 15:4892fe388435 | 266 | __I uint32_t TSV1; |
bogdanm | 15:4892fe388435 | 267 | __I uint32_t RSV; |
bogdanm | 15:4892fe388435 | 268 | uint32_t RESERVED3[3]; |
bogdanm | 15:4892fe388435 | 269 | __IO uint32_t FlowControlCounter; |
bogdanm | 15:4892fe388435 | 270 | __I uint32_t FlowControlStatus; |
bogdanm | 15:4892fe388435 | 271 | uint32_t RESERVED4[34]; |
bogdanm | 15:4892fe388435 | 272 | __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ |
bogdanm | 15:4892fe388435 | 273 | __I uint32_t RxFilterWoLStatus; |
bogdanm | 15:4892fe388435 | 274 | __O uint32_t RxFilterWoLClear; |
bogdanm | 15:4892fe388435 | 275 | uint32_t RESERVED5; |
bogdanm | 15:4892fe388435 | 276 | __IO uint32_t HashFilterL; |
bogdanm | 15:4892fe388435 | 277 | __IO uint32_t HashFilterH; |
bogdanm | 15:4892fe388435 | 278 | uint32_t RESERVED6[882]; |
bogdanm | 15:4892fe388435 | 279 | __I uint32_t IntStatus; /* Module Control Registers */ |
bogdanm | 15:4892fe388435 | 280 | __IO uint32_t IntEnable; |
bogdanm | 15:4892fe388435 | 281 | __O uint32_t IntClear; |
bogdanm | 15:4892fe388435 | 282 | __O uint32_t IntSet; |
bogdanm | 15:4892fe388435 | 283 | uint32_t RESERVED7; |
bogdanm | 15:4892fe388435 | 284 | __IO uint32_t PowerDown; |
bogdanm | 15:4892fe388435 | 285 | uint32_t RESERVED8; |
bogdanm | 15:4892fe388435 | 286 | __IO uint32_t Module_ID; |
bogdanm | 15:4892fe388435 | 287 | } LPC_EMAC_TypeDef; |
bogdanm | 15:4892fe388435 | 288 | |
bogdanm | 15:4892fe388435 | 289 | /*------------- LCD controller (LCD) -----------------------------------------*/ |
bogdanm | 15:4892fe388435 | 290 | typedef struct |
bogdanm | 15:4892fe388435 | 291 | { |
bogdanm | 15:4892fe388435 | 292 | __IO uint32_t TIMH; /* LCD Registers */ |
bogdanm | 15:4892fe388435 | 293 | __IO uint32_t TIMV; |
bogdanm | 15:4892fe388435 | 294 | __IO uint32_t POL; |
bogdanm | 15:4892fe388435 | 295 | __IO uint32_t LE; |
bogdanm | 15:4892fe388435 | 296 | __IO uint32_t UPBASE; |
bogdanm | 15:4892fe388435 | 297 | __IO uint32_t LPBASE; |
bogdanm | 15:4892fe388435 | 298 | __IO uint32_t CTRL; |
bogdanm | 15:4892fe388435 | 299 | __IO uint32_t INTMSK; |
bogdanm | 15:4892fe388435 | 300 | __I uint32_t INTRAW; |
bogdanm | 15:4892fe388435 | 301 | __I uint32_t INTSTAT; |
bogdanm | 15:4892fe388435 | 302 | __O uint32_t INTCLR; |
bogdanm | 15:4892fe388435 | 303 | __I uint32_t UPCURR; |
bogdanm | 15:4892fe388435 | 304 | __I uint32_t LPCURR; |
bogdanm | 15:4892fe388435 | 305 | uint32_t RESERVED0[115]; |
bogdanm | 15:4892fe388435 | 306 | __IO uint32_t PAL[128]; |
bogdanm | 15:4892fe388435 | 307 | uint32_t RESERVED1[256]; |
bogdanm | 15:4892fe388435 | 308 | __IO uint32_t CRSR_IMG[256]; |
bogdanm | 15:4892fe388435 | 309 | __IO uint32_t CRSR_CTRL; |
bogdanm | 15:4892fe388435 | 310 | __IO uint32_t CRSR_CFG; |
bogdanm | 15:4892fe388435 | 311 | __IO uint32_t CRSR_PAL0; |
bogdanm | 15:4892fe388435 | 312 | __IO uint32_t CRSR_PAL1; |
bogdanm | 15:4892fe388435 | 313 | __IO uint32_t CRSR_XY; |
bogdanm | 15:4892fe388435 | 314 | __IO uint32_t CRSR_CLIP; |
bogdanm | 15:4892fe388435 | 315 | uint32_t RESERVED2[2]; |
bogdanm | 15:4892fe388435 | 316 | __IO uint32_t CRSR_INTMSK; |
bogdanm | 15:4892fe388435 | 317 | __O uint32_t CRSR_INTCLR; |
bogdanm | 15:4892fe388435 | 318 | __I uint32_t CRSR_INTRAW; |
bogdanm | 15:4892fe388435 | 319 | __I uint32_t CRSR_INTSTAT; |
bogdanm | 15:4892fe388435 | 320 | } LPC_LCD_TypeDef; |
bogdanm | 15:4892fe388435 | 321 | |
bogdanm | 15:4892fe388435 | 322 | /*------------- Universal Serial Bus (USB) -----------------------------------*/ |
bogdanm | 15:4892fe388435 | 323 | typedef struct |
bogdanm | 15:4892fe388435 | 324 | { |
bogdanm | 15:4892fe388435 | 325 | __I uint32_t Revision; /* USB Host Registers */ |
bogdanm | 15:4892fe388435 | 326 | __IO uint32_t Control; |
bogdanm | 15:4892fe388435 | 327 | __IO uint32_t CommandStatus; |
bogdanm | 15:4892fe388435 | 328 | __IO uint32_t InterruptStatus; |
bogdanm | 15:4892fe388435 | 329 | __IO uint32_t InterruptEnable; |
bogdanm | 15:4892fe388435 | 330 | __IO uint32_t InterruptDisable; |
bogdanm | 15:4892fe388435 | 331 | __IO uint32_t HCCA; |
bogdanm | 15:4892fe388435 | 332 | __I uint32_t PeriodCurrentED; |
bogdanm | 15:4892fe388435 | 333 | __IO uint32_t ControlHeadED; |
bogdanm | 15:4892fe388435 | 334 | __IO uint32_t ControlCurrentED; |
bogdanm | 15:4892fe388435 | 335 | __IO uint32_t BulkHeadED; |
bogdanm | 15:4892fe388435 | 336 | __IO uint32_t BulkCurrentED; |
bogdanm | 15:4892fe388435 | 337 | __I uint32_t DoneHead; |
bogdanm | 15:4892fe388435 | 338 | __IO uint32_t FmInterval; |
bogdanm | 15:4892fe388435 | 339 | __I uint32_t FmRemaining; |
bogdanm | 15:4892fe388435 | 340 | __I uint32_t FmNumber; |
bogdanm | 15:4892fe388435 | 341 | __IO uint32_t PeriodicStart; |
bogdanm | 15:4892fe388435 | 342 | __IO uint32_t LSTreshold; |
bogdanm | 15:4892fe388435 | 343 | __IO uint32_t RhDescriptorA; |
bogdanm | 15:4892fe388435 | 344 | __IO uint32_t RhDescriptorB; |
bogdanm | 15:4892fe388435 | 345 | __IO uint32_t RhStatus; |
bogdanm | 15:4892fe388435 | 346 | __IO uint32_t RhPortStatus1; |
bogdanm | 15:4892fe388435 | 347 | __IO uint32_t RhPortStatus2; |
bogdanm | 15:4892fe388435 | 348 | uint32_t RESERVED0[40]; |
bogdanm | 15:4892fe388435 | 349 | __I uint32_t Module_ID; |
bogdanm | 15:4892fe388435 | 350 | |
bogdanm | 15:4892fe388435 | 351 | __I uint32_t IntSt; /* USB On-The-Go Registers */ |
bogdanm | 15:4892fe388435 | 352 | __IO uint32_t IntEn; |
bogdanm | 15:4892fe388435 | 353 | __O uint32_t IntSet; |
bogdanm | 15:4892fe388435 | 354 | __O uint32_t IntClr; |
bogdanm | 15:4892fe388435 | 355 | __IO uint32_t StCtrl; |
bogdanm | 15:4892fe388435 | 356 | __IO uint32_t Tmr; |
bogdanm | 15:4892fe388435 | 357 | uint32_t RESERVED1[58]; |
bogdanm | 15:4892fe388435 | 358 | |
bogdanm | 15:4892fe388435 | 359 | __I uint32_t DevIntSt; /* USB Device Interrupt Registers */ |
bogdanm | 15:4892fe388435 | 360 | __IO uint32_t DevIntEn; |
bogdanm | 15:4892fe388435 | 361 | __O uint32_t DevIntClr; |
bogdanm | 15:4892fe388435 | 362 | __O uint32_t DevIntSet; |
bogdanm | 15:4892fe388435 | 363 | |
bogdanm | 15:4892fe388435 | 364 | __O uint32_t CmdCode; /* USB Device SIE Command Registers */ |
bogdanm | 15:4892fe388435 | 365 | __I uint32_t CmdData; |
bogdanm | 15:4892fe388435 | 366 | |
bogdanm | 15:4892fe388435 | 367 | __I uint32_t RxData; /* USB Device Transfer Registers */ |
bogdanm | 15:4892fe388435 | 368 | __O uint32_t TxData; |
bogdanm | 15:4892fe388435 | 369 | __I uint32_t RxPLen; |
bogdanm | 15:4892fe388435 | 370 | __O uint32_t TxPLen; |
bogdanm | 15:4892fe388435 | 371 | __IO uint32_t Ctrl; |
bogdanm | 15:4892fe388435 | 372 | __O uint32_t DevIntPri; |
bogdanm | 15:4892fe388435 | 373 | |
bogdanm | 15:4892fe388435 | 374 | __I uint32_t EpIntSt; /* USB Device Endpoint Interrupt Regs */ |
bogdanm | 15:4892fe388435 | 375 | __IO uint32_t EpIntEn; |
bogdanm | 15:4892fe388435 | 376 | __O uint32_t EpIntClr; |
bogdanm | 15:4892fe388435 | 377 | __O uint32_t EpIntSet; |
bogdanm | 15:4892fe388435 | 378 | __O uint32_t EpIntPri; |
bogdanm | 15:4892fe388435 | 379 | |
bogdanm | 15:4892fe388435 | 380 | __IO uint32_t ReEp; /* USB Device Endpoint Realization Reg*/ |
bogdanm | 15:4892fe388435 | 381 | __O uint32_t EpInd; |
bogdanm | 15:4892fe388435 | 382 | __IO uint32_t MaxPSize; |
bogdanm | 15:4892fe388435 | 383 | |
bogdanm | 15:4892fe388435 | 384 | __I uint32_t DMARSt; /* USB Device DMA Registers */ |
bogdanm | 15:4892fe388435 | 385 | __O uint32_t DMARClr; |
bogdanm | 15:4892fe388435 | 386 | __O uint32_t DMARSet; |
bogdanm | 15:4892fe388435 | 387 | uint32_t RESERVED2[9]; |
bogdanm | 15:4892fe388435 | 388 | __IO uint32_t UDCAH; |
bogdanm | 15:4892fe388435 | 389 | __I uint32_t EpDMASt; |
bogdanm | 15:4892fe388435 | 390 | __O uint32_t EpDMAEn; |
bogdanm | 15:4892fe388435 | 391 | __O uint32_t EpDMADis; |
bogdanm | 15:4892fe388435 | 392 | __I uint32_t DMAIntSt; |
bogdanm | 15:4892fe388435 | 393 | __IO uint32_t DMAIntEn; |
bogdanm | 15:4892fe388435 | 394 | uint32_t RESERVED3[2]; |
bogdanm | 15:4892fe388435 | 395 | __I uint32_t EoTIntSt; |
bogdanm | 15:4892fe388435 | 396 | __O uint32_t EoTIntClr; |
bogdanm | 15:4892fe388435 | 397 | __O uint32_t EoTIntSet; |
bogdanm | 15:4892fe388435 | 398 | __I uint32_t NDDRIntSt; |
bogdanm | 15:4892fe388435 | 399 | __O uint32_t NDDRIntClr; |
bogdanm | 15:4892fe388435 | 400 | __O uint32_t NDDRIntSet; |
bogdanm | 15:4892fe388435 | 401 | __I uint32_t SysErrIntSt; |
bogdanm | 15:4892fe388435 | 402 | __O uint32_t SysErrIntClr; |
bogdanm | 15:4892fe388435 | 403 | __O uint32_t SysErrIntSet; |
bogdanm | 15:4892fe388435 | 404 | uint32_t RESERVED4[15]; |
bogdanm | 15:4892fe388435 | 405 | |
bogdanm | 15:4892fe388435 | 406 | union { |
bogdanm | 15:4892fe388435 | 407 | __I uint32_t I2C_RX; /* USB OTG I2C Registers */ |
bogdanm | 15:4892fe388435 | 408 | __O uint32_t I2C_TX; |
bogdanm | 15:4892fe388435 | 409 | }; |
bogdanm | 15:4892fe388435 | 410 | __IO uint32_t I2C_STS; |
bogdanm | 15:4892fe388435 | 411 | __IO uint32_t I2C_CTL; |
bogdanm | 15:4892fe388435 | 412 | __IO uint32_t I2C_CLKHI; |
bogdanm | 15:4892fe388435 | 413 | __O uint32_t I2C_CLKLO; |
bogdanm | 15:4892fe388435 | 414 | uint32_t RESERVED5[824]; |
bogdanm | 15:4892fe388435 | 415 | |
bogdanm | 15:4892fe388435 | 416 | union { |
bogdanm | 15:4892fe388435 | 417 | __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ |
bogdanm | 15:4892fe388435 | 418 | __IO uint32_t OTGClkCtrl; |
bogdanm | 15:4892fe388435 | 419 | }; |
bogdanm | 15:4892fe388435 | 420 | union { |
bogdanm | 15:4892fe388435 | 421 | __I uint32_t USBClkSt; |
bogdanm | 15:4892fe388435 | 422 | __I uint32_t OTGClkSt; |
bogdanm | 15:4892fe388435 | 423 | }; |
bogdanm | 15:4892fe388435 | 424 | } LPC_USB_TypeDef; |
bogdanm | 15:4892fe388435 | 425 | |
bogdanm | 15:4892fe388435 | 426 | /*------------- CRC Engine (CRC) -----------------------------------------*/ |
bogdanm | 15:4892fe388435 | 427 | typedef struct |
bogdanm | 15:4892fe388435 | 428 | { |
bogdanm | 15:4892fe388435 | 429 | __IO uint32_t MODE; |
bogdanm | 15:4892fe388435 | 430 | __IO uint32_t SEED; |
bogdanm | 15:4892fe388435 | 431 | union { |
bogdanm | 15:4892fe388435 | 432 | __I uint32_t SUM; |
bogdanm | 15:4892fe388435 | 433 | struct { |
bogdanm | 15:4892fe388435 | 434 | __O uint32_t DATA; |
bogdanm | 15:4892fe388435 | 435 | } WR_DATA_DWORD; |
bogdanm | 15:4892fe388435 | 436 | |
bogdanm | 15:4892fe388435 | 437 | struct { |
bogdanm | 15:4892fe388435 | 438 | __O uint16_t DATA; |
bogdanm | 15:4892fe388435 | 439 | uint16_t RESERVED; |
bogdanm | 15:4892fe388435 | 440 | }WR_DATA_WORD; |
bogdanm | 15:4892fe388435 | 441 | |
bogdanm | 15:4892fe388435 | 442 | struct { |
bogdanm | 15:4892fe388435 | 443 | __O uint8_t DATA; |
bogdanm | 15:4892fe388435 | 444 | uint8_t RESERVED[3]; |
bogdanm | 15:4892fe388435 | 445 | }WR_DATA_BYTE; |
bogdanm | 15:4892fe388435 | 446 | }; |
bogdanm | 15:4892fe388435 | 447 | } LPC_CRC_TypeDef; |
bogdanm | 15:4892fe388435 | 448 | /*------------- General Purpose Input/Output (GPIO) --------------------------*/ |
bogdanm | 15:4892fe388435 | 449 | typedef struct |
bogdanm | 15:4892fe388435 | 450 | { |
bogdanm | 15:4892fe388435 | 451 | __IO uint32_t DIR; |
bogdanm | 15:4892fe388435 | 452 | uint32_t RESERVED0[3]; |
bogdanm | 15:4892fe388435 | 453 | __IO uint32_t MASK; |
bogdanm | 15:4892fe388435 | 454 | __IO uint32_t PIN; |
bogdanm | 15:4892fe388435 | 455 | __IO uint32_t SET; |
bogdanm | 15:4892fe388435 | 456 | __O uint32_t CLR; |
bogdanm | 15:4892fe388435 | 457 | } LPC_GPIO_TypeDef; |
bogdanm | 15:4892fe388435 | 458 | |
bogdanm | 15:4892fe388435 | 459 | typedef struct |
bogdanm | 15:4892fe388435 | 460 | { |
bogdanm | 15:4892fe388435 | 461 | __I uint32_t IntStatus; |
bogdanm | 15:4892fe388435 | 462 | __I uint32_t IO0IntStatR; |
bogdanm | 15:4892fe388435 | 463 | __I uint32_t IO0IntStatF; |
bogdanm | 15:4892fe388435 | 464 | __O uint32_t IO0IntClr; |
bogdanm | 15:4892fe388435 | 465 | __IO uint32_t IO0IntEnR; |
bogdanm | 15:4892fe388435 | 466 | __IO uint32_t IO0IntEnF; |
bogdanm | 15:4892fe388435 | 467 | uint32_t RESERVED0[3]; |
bogdanm | 15:4892fe388435 | 468 | __I uint32_t IO2IntStatR; |
bogdanm | 15:4892fe388435 | 469 | __I uint32_t IO2IntStatF; |
bogdanm | 15:4892fe388435 | 470 | __O uint32_t IO2IntClr; |
bogdanm | 15:4892fe388435 | 471 | __IO uint32_t IO2IntEnR; |
bogdanm | 15:4892fe388435 | 472 | __IO uint32_t IO2IntEnF; |
bogdanm | 15:4892fe388435 | 473 | } LPC_GPIOINT_TypeDef; |
bogdanm | 15:4892fe388435 | 474 | |
bogdanm | 15:4892fe388435 | 475 | /*------------- External Memory Controller (EMC) -----------------------------*/ |
bogdanm | 15:4892fe388435 | 476 | typedef struct |
bogdanm | 15:4892fe388435 | 477 | { |
bogdanm | 15:4892fe388435 | 478 | __IO uint32_t Control; |
bogdanm | 15:4892fe388435 | 479 | __I uint32_t Status; |
bogdanm | 15:4892fe388435 | 480 | __IO uint32_t Config; |
bogdanm | 15:4892fe388435 | 481 | uint32_t RESERVED0[5]; |
bogdanm | 15:4892fe388435 | 482 | __IO uint32_t DynamicControl; |
bogdanm | 15:4892fe388435 | 483 | __IO uint32_t DynamicRefresh; |
bogdanm | 15:4892fe388435 | 484 | __IO uint32_t DynamicReadConfig; |
bogdanm | 15:4892fe388435 | 485 | uint32_t RESERVED1[1]; |
bogdanm | 15:4892fe388435 | 486 | __IO uint32_t DynamicRP; |
bogdanm | 15:4892fe388435 | 487 | __IO uint32_t DynamicRAS; |
bogdanm | 15:4892fe388435 | 488 | __IO uint32_t DynamicSREX; |
bogdanm | 15:4892fe388435 | 489 | __IO uint32_t DynamicAPR; |
bogdanm | 15:4892fe388435 | 490 | __IO uint32_t DynamicDAL; |
bogdanm | 15:4892fe388435 | 491 | __IO uint32_t DynamicWR; |
bogdanm | 15:4892fe388435 | 492 | __IO uint32_t DynamicRC; |
bogdanm | 15:4892fe388435 | 493 | __IO uint32_t DynamicRFC; |
bogdanm | 15:4892fe388435 | 494 | __IO uint32_t DynamicXSR; |
bogdanm | 15:4892fe388435 | 495 | __IO uint32_t DynamicRRD; |
bogdanm | 15:4892fe388435 | 496 | __IO uint32_t DynamicMRD; |
bogdanm | 15:4892fe388435 | 497 | uint32_t RESERVED2[9]; |
bogdanm | 15:4892fe388435 | 498 | __IO uint32_t StaticExtendedWait; |
bogdanm | 15:4892fe388435 | 499 | uint32_t RESERVED3[31]; |
bogdanm | 15:4892fe388435 | 500 | __IO uint32_t DynamicConfig0; |
bogdanm | 15:4892fe388435 | 501 | __IO uint32_t DynamicRasCas0; |
bogdanm | 15:4892fe388435 | 502 | uint32_t RESERVED4[6]; |
bogdanm | 15:4892fe388435 | 503 | __IO uint32_t DynamicConfig1; |
bogdanm | 15:4892fe388435 | 504 | __IO uint32_t DynamicRasCas1; |
bogdanm | 15:4892fe388435 | 505 | uint32_t RESERVED5[6]; |
bogdanm | 15:4892fe388435 | 506 | __IO uint32_t DynamicConfig2; |
bogdanm | 15:4892fe388435 | 507 | __IO uint32_t DynamicRasCas2; |
bogdanm | 15:4892fe388435 | 508 | uint32_t RESERVED6[6]; |
bogdanm | 15:4892fe388435 | 509 | __IO uint32_t DynamicConfig3; |
bogdanm | 15:4892fe388435 | 510 | __IO uint32_t DynamicRasCas3; |
bogdanm | 15:4892fe388435 | 511 | uint32_t RESERVED7[38]; |
bogdanm | 15:4892fe388435 | 512 | __IO uint32_t StaticConfig0; |
bogdanm | 15:4892fe388435 | 513 | __IO uint32_t StaticWaitWen0; |
bogdanm | 15:4892fe388435 | 514 | __IO uint32_t StaticWaitOen0; |
bogdanm | 15:4892fe388435 | 515 | __IO uint32_t StaticWaitRd0; |
bogdanm | 15:4892fe388435 | 516 | __IO uint32_t StaticWaitPage0; |
bogdanm | 15:4892fe388435 | 517 | __IO uint32_t StaticWaitWr0; |
bogdanm | 15:4892fe388435 | 518 | __IO uint32_t StaticWaitTurn0; |
bogdanm | 15:4892fe388435 | 519 | uint32_t RESERVED8[1]; |
bogdanm | 15:4892fe388435 | 520 | __IO uint32_t StaticConfig1; |
bogdanm | 15:4892fe388435 | 521 | __IO uint32_t StaticWaitWen1; |
bogdanm | 15:4892fe388435 | 522 | __IO uint32_t StaticWaitOen1; |
bogdanm | 15:4892fe388435 | 523 | __IO uint32_t StaticWaitRd1; |
bogdanm | 15:4892fe388435 | 524 | __IO uint32_t StaticWaitPage1; |
bogdanm | 15:4892fe388435 | 525 | __IO uint32_t StaticWaitWr1; |
bogdanm | 15:4892fe388435 | 526 | __IO uint32_t StaticWaitTurn1; |
bogdanm | 15:4892fe388435 | 527 | uint32_t RESERVED9[1]; |
bogdanm | 15:4892fe388435 | 528 | __IO uint32_t StaticConfig2; |
bogdanm | 15:4892fe388435 | 529 | __IO uint32_t StaticWaitWen2; |
bogdanm | 15:4892fe388435 | 530 | __IO uint32_t StaticWaitOen2; |
bogdanm | 15:4892fe388435 | 531 | __IO uint32_t StaticWaitRd2; |
bogdanm | 15:4892fe388435 | 532 | __IO uint32_t StaticWaitPage2; |
bogdanm | 15:4892fe388435 | 533 | __IO uint32_t StaticWaitWr2; |
bogdanm | 15:4892fe388435 | 534 | __IO uint32_t StaticWaitTurn2; |
bogdanm | 15:4892fe388435 | 535 | uint32_t RESERVED10[1]; |
bogdanm | 15:4892fe388435 | 536 | __IO uint32_t StaticConfig3; |
bogdanm | 15:4892fe388435 | 537 | __IO uint32_t StaticWaitWen3; |
bogdanm | 15:4892fe388435 | 538 | __IO uint32_t StaticWaitOen3; |
bogdanm | 15:4892fe388435 | 539 | __IO uint32_t StaticWaitRd3; |
bogdanm | 15:4892fe388435 | 540 | __IO uint32_t StaticWaitPage3; |
bogdanm | 15:4892fe388435 | 541 | __IO uint32_t StaticWaitWr3; |
bogdanm | 15:4892fe388435 | 542 | __IO uint32_t StaticWaitTurn3; |
bogdanm | 15:4892fe388435 | 543 | } LPC_EMC_TypeDef; |
bogdanm | 15:4892fe388435 | 544 | |
bogdanm | 15:4892fe388435 | 545 | /*------------- Watchdog Timer (WDT) -----------------------------------------*/ |
bogdanm | 15:4892fe388435 | 546 | typedef struct |
bogdanm | 15:4892fe388435 | 547 | { |
bogdanm | 15:4892fe388435 | 548 | __IO uint8_t MOD; |
bogdanm | 15:4892fe388435 | 549 | uint8_t RESERVED0[3]; |
bogdanm | 15:4892fe388435 | 550 | __IO uint32_t TC; |
bogdanm | 15:4892fe388435 | 551 | __O uint8_t FEED; |
bogdanm | 15:4892fe388435 | 552 | uint8_t RESERVED1[3]; |
bogdanm | 15:4892fe388435 | 553 | __I uint32_t TV; |
bogdanm | 15:4892fe388435 | 554 | uint32_t RESERVED2; |
bogdanm | 15:4892fe388435 | 555 | __IO uint32_t WARNINT; |
bogdanm | 15:4892fe388435 | 556 | __IO uint32_t WINDOW; |
bogdanm | 15:4892fe388435 | 557 | } LPC_WDT_TypeDef; |
bogdanm | 15:4892fe388435 | 558 | |
bogdanm | 15:4892fe388435 | 559 | /*------------- Timer (TIM) --------------------------------------------------*/ |
bogdanm | 15:4892fe388435 | 560 | typedef struct |
bogdanm | 15:4892fe388435 | 561 | { |
bogdanm | 15:4892fe388435 | 562 | __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */ |
bogdanm | 15:4892fe388435 | 563 | __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */ |
bogdanm | 15:4892fe388435 | 564 | __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */ |
bogdanm | 15:4892fe388435 | 565 | __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */ |
bogdanm | 15:4892fe388435 | 566 | __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */ |
bogdanm | 15:4892fe388435 | 567 | __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */ |
bogdanm | 15:4892fe388435 | 568 | __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */ |
bogdanm | 15:4892fe388435 | 569 | __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */ |
bogdanm | 15:4892fe388435 | 570 | __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */ |
bogdanm | 15:4892fe388435 | 571 | __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */ |
bogdanm | 15:4892fe388435 | 572 | __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */ |
bogdanm | 15:4892fe388435 | 573 | __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */ |
bogdanm | 15:4892fe388435 | 574 | __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */ |
bogdanm | 15:4892fe388435 | 575 | uint32_t RESERVED0[2]; |
bogdanm | 15:4892fe388435 | 576 | __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */ |
bogdanm | 15:4892fe388435 | 577 | uint32_t RESERVED1[12]; |
bogdanm | 15:4892fe388435 | 578 | __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */ |
bogdanm | 15:4892fe388435 | 579 | } LPC_TIM_TypeDef; |
bogdanm | 15:4892fe388435 | 580 | |
bogdanm | 15:4892fe388435 | 581 | |
bogdanm | 15:4892fe388435 | 582 | /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ |
bogdanm | 15:4892fe388435 | 583 | typedef struct |
bogdanm | 15:4892fe388435 | 584 | { |
bogdanm | 15:4892fe388435 | 585 | __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */ |
bogdanm | 15:4892fe388435 | 586 | __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */ |
bogdanm | 15:4892fe388435 | 587 | __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */ |
bogdanm | 15:4892fe388435 | 588 | __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */ |
bogdanm | 15:4892fe388435 | 589 | __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */ |
bogdanm | 15:4892fe388435 | 590 | __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */ |
bogdanm | 15:4892fe388435 | 591 | __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */ |
bogdanm | 15:4892fe388435 | 592 | __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */ |
bogdanm | 15:4892fe388435 | 593 | __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */ |
bogdanm | 15:4892fe388435 | 594 | __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */ |
bogdanm | 15:4892fe388435 | 595 | __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */ |
bogdanm | 15:4892fe388435 | 596 | __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */ |
bogdanm | 15:4892fe388435 | 597 | __I uint32_t CR1; /*!< Offset: 0x030 Capture Register 1 (R/ ) */ |
bogdanm | 15:4892fe388435 | 598 | __I uint32_t CR2; /*!< Offset: 0x034 Capture Register 2 (R/ ) */ |
bogdanm | 15:4892fe388435 | 599 | __I uint32_t CR3; /*!< Offset: 0x038 Capture Register 3 (R/ ) */ |
bogdanm | 15:4892fe388435 | 600 | uint32_t RESERVED0; |
bogdanm | 15:4892fe388435 | 601 | __IO uint32_t MR4; /*!< Offset: 0x040 Match Register 4 (R/W) */ |
bogdanm | 15:4892fe388435 | 602 | __IO uint32_t MR5; /*!< Offset: 0x044 Match Register 5 (R/W) */ |
bogdanm | 15:4892fe388435 | 603 | __IO uint32_t MR6; /*!< Offset: 0x048 Match Register 6 (R/W) */ |
bogdanm | 15:4892fe388435 | 604 | __IO uint32_t PCR; /*!< Offset: 0x04C PWM Control Register (R/W) */ |
bogdanm | 15:4892fe388435 | 605 | __IO uint32_t LER; /*!< Offset: 0x050 Load Enable Register (R/W) */ |
bogdanm | 15:4892fe388435 | 606 | uint32_t RESERVED1[7]; |
bogdanm | 15:4892fe388435 | 607 | __IO uint32_t CTCR; /*!< Offset: 0x070 Counter Control Register (R/W) */ |
bogdanm | 15:4892fe388435 | 608 | } LPC_PWM_TypeDef; |
bogdanm | 15:4892fe388435 | 609 | |
bogdanm | 15:4892fe388435 | 610 | /*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/ |
bogdanm | 15:4892fe388435 | 611 | /* There are three types of UARTs on the chip: |
bogdanm | 15:4892fe388435 | 612 | (1) UART0,UART2, and UART3 are the standard UART. |
bogdanm | 15:4892fe388435 | 613 | (2) UART1 is the standard with modem capability. |
bogdanm | 15:4892fe388435 | 614 | (3) USART(UART4) is the sync/async UART with smart card capability. |
bogdanm | 15:4892fe388435 | 615 | More details can be found on the Users Manual. */ |
bogdanm | 15:4892fe388435 | 616 | |
bogdanm | 15:4892fe388435 | 617 | #if 0 |
bogdanm | 15:4892fe388435 | 618 | typedef struct |
bogdanm | 15:4892fe388435 | 619 | { |
bogdanm | 15:4892fe388435 | 620 | union { |
bogdanm | 15:4892fe388435 | 621 | __I uint8_t RBR; |
bogdanm | 15:4892fe388435 | 622 | __O uint8_t THR; |
bogdanm | 15:4892fe388435 | 623 | __IO uint8_t DLL; |
bogdanm | 15:4892fe388435 | 624 | uint32_t RESERVED0; |
bogdanm | 15:4892fe388435 | 625 | }; |
bogdanm | 15:4892fe388435 | 626 | union { |
bogdanm | 15:4892fe388435 | 627 | __IO uint8_t DLM; |
bogdanm | 15:4892fe388435 | 628 | __IO uint32_t IER; |
bogdanm | 15:4892fe388435 | 629 | }; |
bogdanm | 15:4892fe388435 | 630 | union { |
bogdanm | 15:4892fe388435 | 631 | __I uint32_t IIR; |
bogdanm | 15:4892fe388435 | 632 | __O uint8_t FCR; |
bogdanm | 15:4892fe388435 | 633 | }; |
bogdanm | 15:4892fe388435 | 634 | __IO uint8_t LCR; |
bogdanm | 15:4892fe388435 | 635 | uint8_t RESERVED1[7]; |
bogdanm | 15:4892fe388435 | 636 | __I uint8_t LSR; |
bogdanm | 15:4892fe388435 | 637 | uint8_t RESERVED2[7]; |
bogdanm | 15:4892fe388435 | 638 | __IO uint8_t SCR; |
bogdanm | 15:4892fe388435 | 639 | uint8_t RESERVED3[3]; |
bogdanm | 15:4892fe388435 | 640 | __IO uint32_t ACR; |
bogdanm | 15:4892fe388435 | 641 | __IO uint8_t ICR; |
bogdanm | 15:4892fe388435 | 642 | uint8_t RESERVED4[3]; |
bogdanm | 15:4892fe388435 | 643 | __IO uint8_t FDR; |
bogdanm | 15:4892fe388435 | 644 | uint8_t RESERVED5[7]; |
bogdanm | 15:4892fe388435 | 645 | __IO uint8_t TER; |
bogdanm | 15:4892fe388435 | 646 | uint8_t RESERVED6[39]; |
bogdanm | 15:4892fe388435 | 647 | __I uint8_t FIFOLVL; |
bogdanm | 15:4892fe388435 | 648 | } LPC_UART_TypeDef; |
bogdanm | 15:4892fe388435 | 649 | #else |
bogdanm | 15:4892fe388435 | 650 | typedef struct |
bogdanm | 15:4892fe388435 | 651 | { |
bogdanm | 15:4892fe388435 | 652 | union |
bogdanm | 15:4892fe388435 | 653 | { |
bogdanm | 15:4892fe388435 | 654 | __I uint8_t RBR; |
bogdanm | 15:4892fe388435 | 655 | __O uint8_t THR; |
bogdanm | 15:4892fe388435 | 656 | __IO uint8_t DLL; |
bogdanm | 15:4892fe388435 | 657 | uint32_t RESERVED0; |
bogdanm | 15:4892fe388435 | 658 | }; |
bogdanm | 15:4892fe388435 | 659 | union |
bogdanm | 15:4892fe388435 | 660 | { |
bogdanm | 15:4892fe388435 | 661 | __IO uint8_t DLM; |
bogdanm | 15:4892fe388435 | 662 | __IO uint32_t IER; |
bogdanm | 15:4892fe388435 | 663 | }; |
bogdanm | 15:4892fe388435 | 664 | union |
bogdanm | 15:4892fe388435 | 665 | { |
bogdanm | 15:4892fe388435 | 666 | __I uint32_t IIR; |
bogdanm | 15:4892fe388435 | 667 | __O uint8_t FCR; |
bogdanm | 15:4892fe388435 | 668 | }; |
bogdanm | 15:4892fe388435 | 669 | __IO uint8_t LCR; |
bogdanm | 15:4892fe388435 | 670 | uint8_t RESERVED1[7];//Reserved |
bogdanm | 15:4892fe388435 | 671 | __I uint8_t LSR; |
bogdanm | 15:4892fe388435 | 672 | uint8_t RESERVED2[7];//Reserved |
bogdanm | 15:4892fe388435 | 673 | __IO uint8_t SCR; |
bogdanm | 15:4892fe388435 | 674 | uint8_t RESERVED3[3];//Reserved |
bogdanm | 15:4892fe388435 | 675 | __IO uint32_t ACR; |
bogdanm | 15:4892fe388435 | 676 | __IO uint8_t ICR; |
bogdanm | 15:4892fe388435 | 677 | uint8_t RESERVED4[3];//Reserved |
bogdanm | 15:4892fe388435 | 678 | __IO uint8_t FDR; |
bogdanm | 15:4892fe388435 | 679 | uint8_t RESERVED5[7];//Reserved |
bogdanm | 15:4892fe388435 | 680 | __IO uint8_t TER; |
bogdanm | 15:4892fe388435 | 681 | uint8_t RESERVED8[27];//Reserved |
bogdanm | 15:4892fe388435 | 682 | __IO uint8_t RS485CTRL; |
bogdanm | 15:4892fe388435 | 683 | uint8_t RESERVED9[3];//Reserved |
bogdanm | 15:4892fe388435 | 684 | __IO uint8_t ADRMATCH; |
bogdanm | 15:4892fe388435 | 685 | uint8_t RESERVED10[3];//Reserved |
bogdanm | 15:4892fe388435 | 686 | __IO uint8_t RS485DLY; |
bogdanm | 15:4892fe388435 | 687 | uint8_t RESERVED11[3];//Reserved |
bogdanm | 15:4892fe388435 | 688 | __I uint8_t FIFOLVL; |
bogdanm | 15:4892fe388435 | 689 | }LPC_UART_TypeDef; |
bogdanm | 15:4892fe388435 | 690 | #endif |
bogdanm | 15:4892fe388435 | 691 | |
bogdanm | 15:4892fe388435 | 692 | |
bogdanm | 15:4892fe388435 | 693 | typedef struct |
bogdanm | 15:4892fe388435 | 694 | { |
bogdanm | 15:4892fe388435 | 695 | union { |
bogdanm | 15:4892fe388435 | 696 | __I uint8_t RBR; |
bogdanm | 15:4892fe388435 | 697 | __O uint8_t THR; |
bogdanm | 15:4892fe388435 | 698 | __IO uint8_t DLL; |
bogdanm | 15:4892fe388435 | 699 | uint32_t RESERVED0; |
bogdanm | 15:4892fe388435 | 700 | }; |
bogdanm | 15:4892fe388435 | 701 | union { |
bogdanm | 15:4892fe388435 | 702 | __IO uint8_t DLM; |
bogdanm | 15:4892fe388435 | 703 | __IO uint32_t IER; |
bogdanm | 15:4892fe388435 | 704 | }; |
bogdanm | 15:4892fe388435 | 705 | union { |
bogdanm | 15:4892fe388435 | 706 | __I uint32_t IIR; |
bogdanm | 15:4892fe388435 | 707 | __O uint8_t FCR; |
bogdanm | 15:4892fe388435 | 708 | }; |
bogdanm | 15:4892fe388435 | 709 | __IO uint8_t LCR; |
bogdanm | 15:4892fe388435 | 710 | uint8_t RESERVED1[3]; |
bogdanm | 15:4892fe388435 | 711 | __IO uint8_t MCR; |
bogdanm | 15:4892fe388435 | 712 | uint8_t RESERVED2[3]; |
bogdanm | 15:4892fe388435 | 713 | __I uint8_t LSR; |
bogdanm | 15:4892fe388435 | 714 | uint8_t RESERVED3[3]; |
bogdanm | 15:4892fe388435 | 715 | __I uint8_t MSR; |
bogdanm | 15:4892fe388435 | 716 | uint8_t RESERVED4[3]; |
bogdanm | 15:4892fe388435 | 717 | __IO uint8_t SCR; |
bogdanm | 15:4892fe388435 | 718 | uint8_t RESERVED5[3]; |
bogdanm | 15:4892fe388435 | 719 | __IO uint32_t ACR; |
bogdanm | 15:4892fe388435 | 720 | uint32_t RESERVED6; |
bogdanm | 15:4892fe388435 | 721 | __IO uint32_t FDR; |
bogdanm | 15:4892fe388435 | 722 | uint32_t RESERVED7; |
bogdanm | 15:4892fe388435 | 723 | __IO uint8_t TER; |
bogdanm | 15:4892fe388435 | 724 | uint8_t RESERVED8[27]; |
bogdanm | 15:4892fe388435 | 725 | __IO uint8_t RS485CTRL; |
bogdanm | 15:4892fe388435 | 726 | uint8_t RESERVED9[3]; |
bogdanm | 15:4892fe388435 | 727 | __IO uint8_t ADRMATCH; |
bogdanm | 15:4892fe388435 | 728 | uint8_t RESERVED10[3]; |
bogdanm | 15:4892fe388435 | 729 | __IO uint8_t RS485DLY; |
bogdanm | 15:4892fe388435 | 730 | uint8_t RESERVED11[3]; |
bogdanm | 15:4892fe388435 | 731 | __I uint8_t FIFOLVL; |
bogdanm | 15:4892fe388435 | 732 | } LPC_UART1_TypeDef; |
bogdanm | 15:4892fe388435 | 733 | |
bogdanm | 15:4892fe388435 | 734 | typedef struct |
bogdanm | 15:4892fe388435 | 735 | { |
bogdanm | 15:4892fe388435 | 736 | union { |
bogdanm | 15:4892fe388435 | 737 | __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */ |
bogdanm | 15:4892fe388435 | 738 | __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */ |
bogdanm | 15:4892fe388435 | 739 | __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */ |
bogdanm | 15:4892fe388435 | 740 | }; |
bogdanm | 15:4892fe388435 | 741 | union { |
bogdanm | 15:4892fe388435 | 742 | __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */ |
bogdanm | 15:4892fe388435 | 743 | __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */ |
bogdanm | 15:4892fe388435 | 744 | }; |
bogdanm | 15:4892fe388435 | 745 | union { |
bogdanm | 15:4892fe388435 | 746 | __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */ |
bogdanm | 15:4892fe388435 | 747 | __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */ |
bogdanm | 15:4892fe388435 | 748 | }; |
bogdanm | 15:4892fe388435 | 749 | __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */ |
bogdanm | 15:4892fe388435 | 750 | __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */ |
bogdanm | 15:4892fe388435 | 751 | __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */ |
bogdanm | 15:4892fe388435 | 752 | __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */ |
bogdanm | 15:4892fe388435 | 753 | __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */ |
bogdanm | 15:4892fe388435 | 754 | __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */ |
bogdanm | 15:4892fe388435 | 755 | __IO uint32_t ICR; /*!< Offset: 0x024 irDA Control Register (R/W) */ |
bogdanm | 15:4892fe388435 | 756 | __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */ |
bogdanm | 15:4892fe388435 | 757 | __IO uint32_t OSR; /*!< Offset: 0x02C Over sampling Register (R/W) */ |
bogdanm | 15:4892fe388435 | 758 | __O uint32_t POP; /*!< Offset: 0x030 NHP Pop Register (W) */ |
bogdanm | 15:4892fe388435 | 759 | __IO uint32_t MODE; /*!< Offset: 0x034 NHP Mode selection Register (W) */ |
bogdanm | 15:4892fe388435 | 760 | uint32_t RESERVED0[2]; |
bogdanm | 15:4892fe388435 | 761 | __IO uint32_t HDEN; /*!< Offset: 0x040 Half duplex Enable Register (R/W) */ |
bogdanm | 15:4892fe388435 | 762 | uint32_t RESERVED1; |
bogdanm | 15:4892fe388435 | 763 | __IO uint32_t SCI_CTRL; /*!< Offset: 0x048 Smart card Interface Control Register (R/W) */ |
bogdanm | 15:4892fe388435 | 764 | __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */ |
bogdanm | 15:4892fe388435 | 765 | __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */ |
bogdanm | 15:4892fe388435 | 766 | __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */ |
bogdanm | 15:4892fe388435 | 767 | __IO uint32_t SYNCCTRL; /*!< Offset: 0x058 Synchronous Mode Control Register (R/W ) */ |
bogdanm | 15:4892fe388435 | 768 | __IO uint32_t TER; /*!< Offset: 0x05C Transmit Enable Register (R/W) */ |
bogdanm | 15:4892fe388435 | 769 | uint32_t RESERVED2[989]; |
bogdanm | 15:4892fe388435 | 770 | __I uint32_t CFG; /*!< Offset: 0xFD4 Configuration Register (R) */ |
bogdanm | 15:4892fe388435 | 771 | __O uint32_t INTCE; /*!< Offset: 0xFD8 Interrupt Clear Enable Register (W) */ |
bogdanm | 15:4892fe388435 | 772 | __O uint32_t INTSE; /*!< Offset: 0xFDC Interrupt Set Enable Register (W) */ |
bogdanm | 15:4892fe388435 | 773 | __I uint32_t INTS; /*!< Offset: 0xFE0 Interrupt Status Register (R) */ |
bogdanm | 15:4892fe388435 | 774 | __I uint32_t INTE; /*!< Offset: 0xFE4 Interrupt Enable Register (R) */ |
bogdanm | 15:4892fe388435 | 775 | __O uint32_t INTCS; /*!< Offset: 0xFE8 Interrupt Clear Status Register (W) */ |
bogdanm | 15:4892fe388435 | 776 | __O uint32_t INTSS; /*!< Offset: 0xFEC Interrupt Set Status Register (W) */ |
bogdanm | 15:4892fe388435 | 777 | uint32_t RESERVED3[3]; |
bogdanm | 15:4892fe388435 | 778 | __I uint32_t MID; /*!< Offset: 0xFFC Module Identification Register (R) */ |
bogdanm | 15:4892fe388435 | 779 | } LPC_UART4_TypeDef; |
bogdanm | 15:4892fe388435 | 780 | /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ |
bogdanm | 15:4892fe388435 | 781 | typedef struct |
bogdanm | 15:4892fe388435 | 782 | { |
bogdanm | 15:4892fe388435 | 783 | __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */ |
bogdanm | 15:4892fe388435 | 784 | __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */ |
bogdanm | 15:4892fe388435 | 785 | __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */ |
bogdanm | 15:4892fe388435 | 786 | __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */ |
bogdanm | 15:4892fe388435 | 787 | __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */ |
bogdanm | 15:4892fe388435 | 788 | __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */ |
bogdanm | 15:4892fe388435 | 789 | __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */ |
bogdanm | 15:4892fe388435 | 790 | __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */ |
bogdanm | 15:4892fe388435 | 791 | __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */ |
bogdanm | 15:4892fe388435 | 792 | __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */ |
bogdanm | 15:4892fe388435 | 793 | __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */ |
bogdanm | 15:4892fe388435 | 794 | __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */ |
bogdanm | 15:4892fe388435 | 795 | __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */ |
bogdanm | 15:4892fe388435 | 796 | __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */ |
bogdanm | 15:4892fe388435 | 797 | __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */ |
bogdanm | 15:4892fe388435 | 798 | __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */ |
bogdanm | 15:4892fe388435 | 799 | } LPC_I2C_TypeDef; |
bogdanm | 15:4892fe388435 | 800 | |
bogdanm | 15:4892fe388435 | 801 | /*------------- Real-Time Clock (RTC) ----------------------------------------*/ |
bogdanm | 15:4892fe388435 | 802 | typedef struct |
bogdanm | 15:4892fe388435 | 803 | { |
bogdanm | 15:4892fe388435 | 804 | __IO uint8_t ILR; |
bogdanm | 15:4892fe388435 | 805 | uint8_t RESERVED0[7]; |
bogdanm | 15:4892fe388435 | 806 | __IO uint8_t CCR; |
bogdanm | 15:4892fe388435 | 807 | uint8_t RESERVED1[3]; |
bogdanm | 15:4892fe388435 | 808 | __IO uint8_t CIIR; |
bogdanm | 15:4892fe388435 | 809 | uint8_t RESERVED2[3]; |
bogdanm | 15:4892fe388435 | 810 | __IO uint8_t AMR; |
bogdanm | 15:4892fe388435 | 811 | uint8_t RESERVED3[3]; |
bogdanm | 15:4892fe388435 | 812 | __I uint32_t CTIME0; |
bogdanm | 15:4892fe388435 | 813 | __I uint32_t CTIME1; |
bogdanm | 15:4892fe388435 | 814 | __I uint32_t CTIME2; |
bogdanm | 15:4892fe388435 | 815 | __IO uint8_t SEC; |
bogdanm | 15:4892fe388435 | 816 | uint8_t RESERVED4[3]; |
bogdanm | 15:4892fe388435 | 817 | __IO uint8_t MIN; |
bogdanm | 15:4892fe388435 | 818 | uint8_t RESERVED5[3]; |
bogdanm | 15:4892fe388435 | 819 | __IO uint8_t HOUR; |
bogdanm | 15:4892fe388435 | 820 | uint8_t RESERVED6[3]; |
bogdanm | 15:4892fe388435 | 821 | __IO uint8_t DOM; |
bogdanm | 15:4892fe388435 | 822 | uint8_t RESERVED7[3]; |
bogdanm | 15:4892fe388435 | 823 | __IO uint8_t DOW; |
bogdanm | 15:4892fe388435 | 824 | uint8_t RESERVED8[3]; |
bogdanm | 15:4892fe388435 | 825 | __IO uint16_t DOY; |
bogdanm | 15:4892fe388435 | 826 | uint16_t RESERVED9; |
bogdanm | 15:4892fe388435 | 827 | __IO uint8_t MONTH; |
bogdanm | 15:4892fe388435 | 828 | uint8_t RESERVED10[3]; |
bogdanm | 15:4892fe388435 | 829 | __IO uint16_t YEAR; |
bogdanm | 15:4892fe388435 | 830 | uint16_t RESERVED11; |
bogdanm | 15:4892fe388435 | 831 | __IO uint32_t CALIBRATION; |
bogdanm | 15:4892fe388435 | 832 | __IO uint32_t GPREG0; |
bogdanm | 15:4892fe388435 | 833 | __IO uint32_t GPREG1; |
bogdanm | 15:4892fe388435 | 834 | __IO uint32_t GPREG2; |
bogdanm | 15:4892fe388435 | 835 | __IO uint32_t GPREG3; |
bogdanm | 15:4892fe388435 | 836 | __IO uint32_t GPREG4; |
bogdanm | 15:4892fe388435 | 837 | __IO uint8_t RTC_AUXEN; |
bogdanm | 15:4892fe388435 | 838 | uint8_t RESERVED12[3]; |
bogdanm | 15:4892fe388435 | 839 | __IO uint8_t RTC_AUX; |
bogdanm | 15:4892fe388435 | 840 | uint8_t RESERVED13[3]; |
bogdanm | 15:4892fe388435 | 841 | __IO uint8_t ALSEC; |
bogdanm | 15:4892fe388435 | 842 | uint8_t RESERVED14[3]; |
bogdanm | 15:4892fe388435 | 843 | __IO uint8_t ALMIN; |
bogdanm | 15:4892fe388435 | 844 | uint8_t RESERVED15[3]; |
bogdanm | 15:4892fe388435 | 845 | __IO uint8_t ALHOUR; |
bogdanm | 15:4892fe388435 | 846 | uint8_t RESERVED16[3]; |
bogdanm | 15:4892fe388435 | 847 | __IO uint8_t ALDOM; |
bogdanm | 15:4892fe388435 | 848 | uint8_t RESERVED17[3]; |
bogdanm | 15:4892fe388435 | 849 | __IO uint8_t ALDOW; |
bogdanm | 15:4892fe388435 | 850 | uint8_t RESERVED18[3]; |
bogdanm | 15:4892fe388435 | 851 | __IO uint16_t ALDOY; |
bogdanm | 15:4892fe388435 | 852 | uint16_t RESERVED19; |
bogdanm | 15:4892fe388435 | 853 | __IO uint8_t ALMON; |
bogdanm | 15:4892fe388435 | 854 | uint8_t RESERVED20[3]; |
bogdanm | 15:4892fe388435 | 855 | __IO uint16_t ALYEAR; |
bogdanm | 15:4892fe388435 | 856 | uint16_t RESERVED21; |
bogdanm | 15:4892fe388435 | 857 | __IO uint32_t ERSTATUS; |
bogdanm | 15:4892fe388435 | 858 | __IO uint32_t ERCONTROL; |
bogdanm | 15:4892fe388435 | 859 | __IO uint32_t ERCOUNTERS; |
bogdanm | 15:4892fe388435 | 860 | uint32_t RESERVED22; |
bogdanm | 15:4892fe388435 | 861 | __IO uint32_t ERFIRSTSTAMP0; |
bogdanm | 15:4892fe388435 | 862 | __IO uint32_t ERFIRSTSTAMP1; |
bogdanm | 15:4892fe388435 | 863 | __IO uint32_t ERFIRSTSTAMP2; |
bogdanm | 15:4892fe388435 | 864 | uint32_t RESERVED23; |
bogdanm | 15:4892fe388435 | 865 | __IO uint32_t ERLASTSTAMP0; |
bogdanm | 15:4892fe388435 | 866 | __IO uint32_t ERLASTSTAMP1; |
bogdanm | 15:4892fe388435 | 867 | __IO uint32_t ERLASTSTAMP2; |
bogdanm | 15:4892fe388435 | 868 | } LPC_RTC_TypeDef; |
bogdanm | 15:4892fe388435 | 869 | |
bogdanm | 15:4892fe388435 | 870 | |
bogdanm | 15:4892fe388435 | 871 | |
bogdanm | 15:4892fe388435 | 872 | /*------------- Pin Connect Block (PINCON) -----------------------------------*/ |
bogdanm | 15:4892fe388435 | 873 | typedef struct |
bogdanm | 15:4892fe388435 | 874 | { |
bogdanm | 15:4892fe388435 | 875 | __IO uint32_t P0_0; /* 0x000 */ |
bogdanm | 15:4892fe388435 | 876 | __IO uint32_t P0_1; |
bogdanm | 15:4892fe388435 | 877 | __IO uint32_t P0_2; |
bogdanm | 15:4892fe388435 | 878 | __IO uint32_t P0_3; |
bogdanm | 15:4892fe388435 | 879 | __IO uint32_t P0_4; |
bogdanm | 15:4892fe388435 | 880 | __IO uint32_t P0_5; |
bogdanm | 15:4892fe388435 | 881 | __IO uint32_t P0_6; |
bogdanm | 15:4892fe388435 | 882 | __IO uint32_t P0_7; |
bogdanm | 15:4892fe388435 | 883 | |
bogdanm | 15:4892fe388435 | 884 | __IO uint32_t P0_8; /* 0x020 */ |
bogdanm | 15:4892fe388435 | 885 | __IO uint32_t P0_9; |
bogdanm | 15:4892fe388435 | 886 | __IO uint32_t P0_10; |
bogdanm | 15:4892fe388435 | 887 | __IO uint32_t P0_11; |
bogdanm | 15:4892fe388435 | 888 | __IO uint32_t P0_12; |
bogdanm | 15:4892fe388435 | 889 | __IO uint32_t P0_13; |
bogdanm | 15:4892fe388435 | 890 | __IO uint32_t P0_14; |
bogdanm | 15:4892fe388435 | 891 | __IO uint32_t P0_15; |
bogdanm | 15:4892fe388435 | 892 | |
bogdanm | 15:4892fe388435 | 893 | __IO uint32_t P0_16; /* 0x040 */ |
bogdanm | 15:4892fe388435 | 894 | __IO uint32_t P0_17; |
bogdanm | 15:4892fe388435 | 895 | __IO uint32_t P0_18; |
bogdanm | 15:4892fe388435 | 896 | __IO uint32_t P0_19; |
bogdanm | 15:4892fe388435 | 897 | __IO uint32_t P0_20; |
bogdanm | 15:4892fe388435 | 898 | __IO uint32_t P0_21; |
bogdanm | 15:4892fe388435 | 899 | __IO uint32_t P0_22; |
bogdanm | 15:4892fe388435 | 900 | __IO uint32_t P0_23; |
bogdanm | 15:4892fe388435 | 901 | |
bogdanm | 15:4892fe388435 | 902 | __IO uint32_t P0_24; /* 0x060 */ |
bogdanm | 15:4892fe388435 | 903 | __IO uint32_t P0_25; |
bogdanm | 15:4892fe388435 | 904 | __IO uint32_t P0_26; |
bogdanm | 15:4892fe388435 | 905 | __IO uint32_t P0_27; |
bogdanm | 15:4892fe388435 | 906 | __IO uint32_t P0_28; |
bogdanm | 15:4892fe388435 | 907 | __IO uint32_t P0_29; |
bogdanm | 15:4892fe388435 | 908 | __IO uint32_t P0_30; |
bogdanm | 15:4892fe388435 | 909 | __IO uint32_t P0_31; |
bogdanm | 15:4892fe388435 | 910 | |
bogdanm | 15:4892fe388435 | 911 | __IO uint32_t P1_0; /* 0x080 */ |
bogdanm | 15:4892fe388435 | 912 | __IO uint32_t P1_1; |
bogdanm | 15:4892fe388435 | 913 | __IO uint32_t P1_2; |
bogdanm | 15:4892fe388435 | 914 | __IO uint32_t P1_3; |
bogdanm | 15:4892fe388435 | 915 | __IO uint32_t P1_4; |
bogdanm | 15:4892fe388435 | 916 | __IO uint32_t P1_5; |
bogdanm | 15:4892fe388435 | 917 | __IO uint32_t P1_6; |
bogdanm | 15:4892fe388435 | 918 | __IO uint32_t P1_7; |
bogdanm | 15:4892fe388435 | 919 | |
bogdanm | 15:4892fe388435 | 920 | __IO uint32_t P1_8; /* 0x0A0 */ |
bogdanm | 15:4892fe388435 | 921 | __IO uint32_t P1_9; |
bogdanm | 15:4892fe388435 | 922 | __IO uint32_t P1_10; |
bogdanm | 15:4892fe388435 | 923 | __IO uint32_t P1_11; |
bogdanm | 15:4892fe388435 | 924 | __IO uint32_t P1_12; |
bogdanm | 15:4892fe388435 | 925 | __IO uint32_t P1_13; |
bogdanm | 15:4892fe388435 | 926 | __IO uint32_t P1_14; |
bogdanm | 15:4892fe388435 | 927 | __IO uint32_t P1_15; |
bogdanm | 15:4892fe388435 | 928 | |
bogdanm | 15:4892fe388435 | 929 | __IO uint32_t P1_16; /* 0x0C0 */ |
bogdanm | 15:4892fe388435 | 930 | __IO uint32_t P1_17; |
bogdanm | 15:4892fe388435 | 931 | __IO uint32_t P1_18; |
bogdanm | 15:4892fe388435 | 932 | __IO uint32_t P1_19; |
bogdanm | 15:4892fe388435 | 933 | __IO uint32_t P1_20; |
bogdanm | 15:4892fe388435 | 934 | __IO uint32_t P1_21; |
bogdanm | 15:4892fe388435 | 935 | __IO uint32_t P1_22; |
bogdanm | 15:4892fe388435 | 936 | __IO uint32_t P1_23; |
bogdanm | 15:4892fe388435 | 937 | |
bogdanm | 15:4892fe388435 | 938 | __IO uint32_t P1_24; /* 0x0E0 */ |
bogdanm | 15:4892fe388435 | 939 | __IO uint32_t P1_25; |
bogdanm | 15:4892fe388435 | 940 | __IO uint32_t P1_26; |
bogdanm | 15:4892fe388435 | 941 | __IO uint32_t P1_27; |
bogdanm | 15:4892fe388435 | 942 | __IO uint32_t P1_28; |
bogdanm | 15:4892fe388435 | 943 | __IO uint32_t P1_29; |
bogdanm | 15:4892fe388435 | 944 | __IO uint32_t P1_30; |
bogdanm | 15:4892fe388435 | 945 | __IO uint32_t P1_31; |
bogdanm | 15:4892fe388435 | 946 | |
bogdanm | 15:4892fe388435 | 947 | __IO uint32_t P2_0; /* 0x100 */ |
bogdanm | 15:4892fe388435 | 948 | __IO uint32_t P2_1; |
bogdanm | 15:4892fe388435 | 949 | __IO uint32_t P2_2; |
bogdanm | 15:4892fe388435 | 950 | __IO uint32_t P2_3; |
bogdanm | 15:4892fe388435 | 951 | __IO uint32_t P2_4; |
bogdanm | 15:4892fe388435 | 952 | __IO uint32_t P2_5; |
bogdanm | 15:4892fe388435 | 953 | __IO uint32_t P2_6; |
bogdanm | 15:4892fe388435 | 954 | __IO uint32_t P2_7; |
bogdanm | 15:4892fe388435 | 955 | |
bogdanm | 15:4892fe388435 | 956 | __IO uint32_t P2_8; /* 0x120 */ |
bogdanm | 15:4892fe388435 | 957 | __IO uint32_t P2_9; |
bogdanm | 15:4892fe388435 | 958 | __IO uint32_t P2_10; |
bogdanm | 15:4892fe388435 | 959 | __IO uint32_t P2_11; |
bogdanm | 15:4892fe388435 | 960 | __IO uint32_t P2_12; |
bogdanm | 15:4892fe388435 | 961 | __IO uint32_t P2_13; |
bogdanm | 15:4892fe388435 | 962 | __IO uint32_t P2_14; |
bogdanm | 15:4892fe388435 | 963 | __IO uint32_t P2_15; |
bogdanm | 15:4892fe388435 | 964 | |
bogdanm | 15:4892fe388435 | 965 | __IO uint32_t P2_16; /* 0x140 */ |
bogdanm | 15:4892fe388435 | 966 | __IO uint32_t P2_17; |
bogdanm | 15:4892fe388435 | 967 | __IO uint32_t P2_18; |
bogdanm | 15:4892fe388435 | 968 | __IO uint32_t P2_19; |
bogdanm | 15:4892fe388435 | 969 | __IO uint32_t P2_20; |
bogdanm | 15:4892fe388435 | 970 | __IO uint32_t P2_21; |
bogdanm | 15:4892fe388435 | 971 | __IO uint32_t P2_22; |
bogdanm | 15:4892fe388435 | 972 | __IO uint32_t P2_23; |
bogdanm | 15:4892fe388435 | 973 | |
bogdanm | 15:4892fe388435 | 974 | __IO uint32_t P2_24; /* 0x160 */ |
bogdanm | 15:4892fe388435 | 975 | __IO uint32_t P2_25; |
bogdanm | 15:4892fe388435 | 976 | __IO uint32_t P2_26; |
bogdanm | 15:4892fe388435 | 977 | __IO uint32_t P2_27; |
bogdanm | 15:4892fe388435 | 978 | __IO uint32_t P2_28; |
bogdanm | 15:4892fe388435 | 979 | __IO uint32_t P2_29; |
bogdanm | 15:4892fe388435 | 980 | __IO uint32_t P2_30; |
bogdanm | 15:4892fe388435 | 981 | __IO uint32_t P2_31; |
bogdanm | 15:4892fe388435 | 982 | |
bogdanm | 15:4892fe388435 | 983 | __IO uint32_t P3_0; /* 0x180 */ |
bogdanm | 15:4892fe388435 | 984 | __IO uint32_t P3_1; |
bogdanm | 15:4892fe388435 | 985 | __IO uint32_t P3_2; |
bogdanm | 15:4892fe388435 | 986 | __IO uint32_t P3_3; |
bogdanm | 15:4892fe388435 | 987 | __IO uint32_t P3_4; |
bogdanm | 15:4892fe388435 | 988 | __IO uint32_t P3_5; |
bogdanm | 15:4892fe388435 | 989 | __IO uint32_t P3_6; |
bogdanm | 15:4892fe388435 | 990 | __IO uint32_t P3_7; |
bogdanm | 15:4892fe388435 | 991 | |
bogdanm | 15:4892fe388435 | 992 | __IO uint32_t P3_8; /* 0x1A0 */ |
bogdanm | 15:4892fe388435 | 993 | __IO uint32_t P3_9; |
bogdanm | 15:4892fe388435 | 994 | __IO uint32_t P3_10; |
bogdanm | 15:4892fe388435 | 995 | __IO uint32_t P3_11; |
bogdanm | 15:4892fe388435 | 996 | __IO uint32_t P3_12; |
bogdanm | 15:4892fe388435 | 997 | __IO uint32_t P3_13; |
bogdanm | 15:4892fe388435 | 998 | __IO uint32_t P3_14; |
bogdanm | 15:4892fe388435 | 999 | __IO uint32_t P3_15; |
bogdanm | 15:4892fe388435 | 1000 | |
bogdanm | 15:4892fe388435 | 1001 | __IO uint32_t P3_16; /* 0x1C0 */ |
bogdanm | 15:4892fe388435 | 1002 | __IO uint32_t P3_17; |
bogdanm | 15:4892fe388435 | 1003 | __IO uint32_t P3_18; |
bogdanm | 15:4892fe388435 | 1004 | __IO uint32_t P3_19; |
bogdanm | 15:4892fe388435 | 1005 | __IO uint32_t P3_20; |
bogdanm | 15:4892fe388435 | 1006 | __IO uint32_t P3_21; |
bogdanm | 15:4892fe388435 | 1007 | __IO uint32_t P3_22; |
bogdanm | 15:4892fe388435 | 1008 | __IO uint32_t P3_23; |
bogdanm | 15:4892fe388435 | 1009 | |
bogdanm | 15:4892fe388435 | 1010 | __IO uint32_t P3_24; /* 0x1E0 */ |
bogdanm | 15:4892fe388435 | 1011 | __IO uint32_t P3_25; |
bogdanm | 15:4892fe388435 | 1012 | __IO uint32_t P3_26; |
bogdanm | 15:4892fe388435 | 1013 | __IO uint32_t P3_27; |
bogdanm | 15:4892fe388435 | 1014 | __IO uint32_t P3_28; |
bogdanm | 15:4892fe388435 | 1015 | __IO uint32_t P3_29; |
bogdanm | 15:4892fe388435 | 1016 | __IO uint32_t P3_30; |
bogdanm | 15:4892fe388435 | 1017 | __IO uint32_t P3_31; |
bogdanm | 15:4892fe388435 | 1018 | |
bogdanm | 15:4892fe388435 | 1019 | __IO uint32_t P4_0; /* 0x200 */ |
bogdanm | 15:4892fe388435 | 1020 | __IO uint32_t P4_1; |
bogdanm | 15:4892fe388435 | 1021 | __IO uint32_t P4_2; |
bogdanm | 15:4892fe388435 | 1022 | __IO uint32_t P4_3; |
bogdanm | 15:4892fe388435 | 1023 | __IO uint32_t P4_4; |
bogdanm | 15:4892fe388435 | 1024 | __IO uint32_t P4_5; |
bogdanm | 15:4892fe388435 | 1025 | __IO uint32_t P4_6; |
bogdanm | 15:4892fe388435 | 1026 | __IO uint32_t P4_7; |
bogdanm | 15:4892fe388435 | 1027 | |
bogdanm | 15:4892fe388435 | 1028 | __IO uint32_t P4_8; /* 0x220 */ |
bogdanm | 15:4892fe388435 | 1029 | __IO uint32_t P4_9; |
bogdanm | 15:4892fe388435 | 1030 | __IO uint32_t P4_10; |
bogdanm | 15:4892fe388435 | 1031 | __IO uint32_t P4_11; |
bogdanm | 15:4892fe388435 | 1032 | __IO uint32_t P4_12; |
bogdanm | 15:4892fe388435 | 1033 | __IO uint32_t P4_13; |
bogdanm | 15:4892fe388435 | 1034 | __IO uint32_t P4_14; |
bogdanm | 15:4892fe388435 | 1035 | __IO uint32_t P4_15; |
bogdanm | 15:4892fe388435 | 1036 | |
bogdanm | 15:4892fe388435 | 1037 | __IO uint32_t P4_16; /* 0x240 */ |
bogdanm | 15:4892fe388435 | 1038 | __IO uint32_t P4_17; |
bogdanm | 15:4892fe388435 | 1039 | __IO uint32_t P4_18; |
bogdanm | 15:4892fe388435 | 1040 | __IO uint32_t P4_19; |
bogdanm | 15:4892fe388435 | 1041 | __IO uint32_t P4_20; |
bogdanm | 15:4892fe388435 | 1042 | __IO uint32_t P4_21; |
bogdanm | 15:4892fe388435 | 1043 | __IO uint32_t P4_22; |
bogdanm | 15:4892fe388435 | 1044 | __IO uint32_t P4_23; |
bogdanm | 15:4892fe388435 | 1045 | |
bogdanm | 15:4892fe388435 | 1046 | __IO uint32_t P4_24; /* 0x260 */ |
bogdanm | 15:4892fe388435 | 1047 | __IO uint32_t P4_25; |
bogdanm | 15:4892fe388435 | 1048 | __IO uint32_t P4_26; |
bogdanm | 15:4892fe388435 | 1049 | __IO uint32_t P4_27; |
bogdanm | 15:4892fe388435 | 1050 | __IO uint32_t P4_28; |
bogdanm | 15:4892fe388435 | 1051 | __IO uint32_t P4_29; |
bogdanm | 15:4892fe388435 | 1052 | __IO uint32_t P4_30; |
bogdanm | 15:4892fe388435 | 1053 | __IO uint32_t P4_31; |
bogdanm | 15:4892fe388435 | 1054 | |
bogdanm | 15:4892fe388435 | 1055 | __IO uint32_t P5_0; /* 0x280 */ |
bogdanm | 15:4892fe388435 | 1056 | __IO uint32_t P5_1; |
bogdanm | 15:4892fe388435 | 1057 | __IO uint32_t P5_2; |
bogdanm | 15:4892fe388435 | 1058 | __IO uint32_t P5_3; |
bogdanm | 15:4892fe388435 | 1059 | __IO uint32_t P5_4; /* 0x290 */ |
bogdanm | 15:4892fe388435 | 1060 | } LPC_IOCON_TypeDef; |
bogdanm | 15:4892fe388435 | 1061 | |
bogdanm | 15:4892fe388435 | 1062 | |
bogdanm | 15:4892fe388435 | 1063 | |
bogdanm | 15:4892fe388435 | 1064 | |
bogdanm | 15:4892fe388435 | 1065 | |
bogdanm | 15:4892fe388435 | 1066 | |
bogdanm | 15:4892fe388435 | 1067 | /*------------- Synchronous Serial Communication (SSP) -----------------------*/ |
bogdanm | 15:4892fe388435 | 1068 | typedef struct |
bogdanm | 15:4892fe388435 | 1069 | { |
bogdanm | 15:4892fe388435 | 1070 | __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */ |
bogdanm | 15:4892fe388435 | 1071 | __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */ |
bogdanm | 15:4892fe388435 | 1072 | __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */ |
bogdanm | 15:4892fe388435 | 1073 | __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */ |
bogdanm | 15:4892fe388435 | 1074 | __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */ |
bogdanm | 15:4892fe388435 | 1075 | __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */ |
bogdanm | 15:4892fe388435 | 1076 | __IO uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */ |
bogdanm | 15:4892fe388435 | 1077 | __IO uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */ |
bogdanm | 15:4892fe388435 | 1078 | __IO uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */ |
bogdanm | 15:4892fe388435 | 1079 | __IO uint32_t DMACR; |
bogdanm | 15:4892fe388435 | 1080 | } LPC_SSP_TypeDef; |
bogdanm | 15:4892fe388435 | 1081 | |
bogdanm | 15:4892fe388435 | 1082 | /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ |
bogdanm | 15:4892fe388435 | 1083 | typedef struct |
bogdanm | 15:4892fe388435 | 1084 | { |
bogdanm | 15:4892fe388435 | 1085 | __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */ |
bogdanm | 15:4892fe388435 | 1086 | __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */ |
bogdanm | 15:4892fe388435 | 1087 | uint32_t RESERVED0; |
bogdanm | 15:4892fe388435 | 1088 | __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */ |
bogdanm | 15:4892fe388435 | 1089 | __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */ |
bogdanm | 15:4892fe388435 | 1090 | __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */ |
bogdanm | 15:4892fe388435 | 1091 | __IO uint32_t ADTRM; |
bogdanm | 15:4892fe388435 | 1092 | } LPC_ADC_TypeDef; |
bogdanm | 15:4892fe388435 | 1093 | |
bogdanm | 15:4892fe388435 | 1094 | /*------------- Controller Area Network (CAN) --------------------------------*/ |
bogdanm | 15:4892fe388435 | 1095 | typedef struct |
bogdanm | 15:4892fe388435 | 1096 | { |
bogdanm | 15:4892fe388435 | 1097 | __IO uint32_t mask[512]; /* ID Masks */ |
bogdanm | 15:4892fe388435 | 1098 | } LPC_CANAF_RAM_TypeDef; |
bogdanm | 15:4892fe388435 | 1099 | |
bogdanm | 15:4892fe388435 | 1100 | typedef struct /* Acceptance Filter Registers */ |
bogdanm | 15:4892fe388435 | 1101 | { |
bogdanm | 15:4892fe388435 | 1102 | ///Offset: 0x00000000 - Acceptance Filter Register |
bogdanm | 15:4892fe388435 | 1103 | __IO uint32_t AFMR; |
bogdanm | 15:4892fe388435 | 1104 | |
bogdanm | 15:4892fe388435 | 1105 | ///Offset: 0x00000004 - Standard Frame Individual Start Address Register |
bogdanm | 15:4892fe388435 | 1106 | __IO uint32_t SFF_sa; |
bogdanm | 15:4892fe388435 | 1107 | |
bogdanm | 15:4892fe388435 | 1108 | ///Offset: 0x00000008 - Standard Frame Group Start Address Register |
bogdanm | 15:4892fe388435 | 1109 | __IO uint32_t SFF_GRP_sa; |
bogdanm | 15:4892fe388435 | 1110 | |
bogdanm | 15:4892fe388435 | 1111 | ///Offset: 0x0000000C - Extended Frame Start Address Register |
bogdanm | 15:4892fe388435 | 1112 | __IO uint32_t EFF_sa; |
bogdanm | 15:4892fe388435 | 1113 | |
bogdanm | 15:4892fe388435 | 1114 | ///Offset: 0x00000010 - Extended Frame Group Start Address Register |
bogdanm | 15:4892fe388435 | 1115 | __IO uint32_t EFF_GRP_sa; |
bogdanm | 15:4892fe388435 | 1116 | |
bogdanm | 15:4892fe388435 | 1117 | ///Offset: 0x00000014 - End of AF Tables register |
bogdanm | 15:4892fe388435 | 1118 | __IO uint32_t ENDofTable; |
bogdanm | 15:4892fe388435 | 1119 | |
bogdanm | 15:4892fe388435 | 1120 | ///Offset: 0x00000018 - LUT Error Address register |
bogdanm | 15:4892fe388435 | 1121 | __I uint32_t LUTerrAd; |
bogdanm | 15:4892fe388435 | 1122 | |
bogdanm | 15:4892fe388435 | 1123 | ///Offset: 0x0000001C - LUT Error Register |
bogdanm | 15:4892fe388435 | 1124 | __I uint32_t LUTerr; |
bogdanm | 15:4892fe388435 | 1125 | |
bogdanm | 15:4892fe388435 | 1126 | ///Offset: 0x00000020 - CAN Central Transmit Status Register |
bogdanm | 15:4892fe388435 | 1127 | __IO uint32_t FCANIE; |
bogdanm | 15:4892fe388435 | 1128 | |
bogdanm | 15:4892fe388435 | 1129 | ///Offset: 0x00000024 - FullCAN Interrupt and Capture registers 0 |
bogdanm | 15:4892fe388435 | 1130 | __IO uint32_t FCANIC0; |
bogdanm | 15:4892fe388435 | 1131 | |
bogdanm | 15:4892fe388435 | 1132 | ///Offset: 0x00000028 - FullCAN Interrupt and Capture registers 1 |
bogdanm | 15:4892fe388435 | 1133 | __IO uint32_t FCANIC1; |
bogdanm | 15:4892fe388435 | 1134 | } LPC_CANAF_TypeDef; |
bogdanm | 15:4892fe388435 | 1135 | |
bogdanm | 15:4892fe388435 | 1136 | typedef struct /* Central Registers */ |
bogdanm | 15:4892fe388435 | 1137 | { |
bogdanm | 15:4892fe388435 | 1138 | __I uint32_t TxSR; |
bogdanm | 15:4892fe388435 | 1139 | __I uint32_t RxSR; |
bogdanm | 15:4892fe388435 | 1140 | __I uint32_t MSR; |
bogdanm | 15:4892fe388435 | 1141 | } LPC_CANCR_TypeDef; |
bogdanm | 15:4892fe388435 | 1142 | |
bogdanm | 15:4892fe388435 | 1143 | typedef struct /* Controller Registers */ |
bogdanm | 15:4892fe388435 | 1144 | { |
bogdanm | 15:4892fe388435 | 1145 | ///Offset: 0x00000000 - Controls the operating mode of the CAN Controller |
bogdanm | 15:4892fe388435 | 1146 | __IO uint32_t MOD; |
bogdanm | 15:4892fe388435 | 1147 | |
bogdanm | 15:4892fe388435 | 1148 | ///Offset: 0x00000004 - Command bits that affect the state |
bogdanm | 15:4892fe388435 | 1149 | __O uint32_t CMR; |
bogdanm | 15:4892fe388435 | 1150 | |
bogdanm | 15:4892fe388435 | 1151 | ///Offset: 0x00000008 - Global Controller Status and Error Counters |
bogdanm | 15:4892fe388435 | 1152 | __IO uint32_t GSR; |
bogdanm | 15:4892fe388435 | 1153 | |
bogdanm | 15:4892fe388435 | 1154 | ///Offset: 0x0000000C - Interrupt status, Arbitration Lost Capture, Error Code Capture |
bogdanm | 15:4892fe388435 | 1155 | __I uint32_t ICR; |
bogdanm | 15:4892fe388435 | 1156 | |
bogdanm | 15:4892fe388435 | 1157 | ///Offset: 0x00000010 - Interrupt Enable Register |
bogdanm | 15:4892fe388435 | 1158 | __IO uint32_t IER; |
bogdanm | 15:4892fe388435 | 1159 | |
bogdanm | 15:4892fe388435 | 1160 | ///Offset: 0x00000014 - Bus Timing Register |
bogdanm | 15:4892fe388435 | 1161 | __IO uint32_t BTR; |
bogdanm | 15:4892fe388435 | 1162 | |
bogdanm | 15:4892fe388435 | 1163 | ///Offset: 0x00000018 - Error Warning Limit |
bogdanm | 15:4892fe388435 | 1164 | __IO uint32_t EWL; |
bogdanm | 15:4892fe388435 | 1165 | |
bogdanm | 15:4892fe388435 | 1166 | ///Offset: 0x0000001C - Status Register |
bogdanm | 15:4892fe388435 | 1167 | __I uint32_t SR; |
bogdanm | 15:4892fe388435 | 1168 | |
bogdanm | 15:4892fe388435 | 1169 | ///Offset: 0x00000020 - Receive frame status |
bogdanm | 15:4892fe388435 | 1170 | __IO uint32_t RFS; |
bogdanm | 15:4892fe388435 | 1171 | |
bogdanm | 15:4892fe388435 | 1172 | ///Offset: 0x00000024 - Received Identifier |
bogdanm | 15:4892fe388435 | 1173 | __IO uint32_t RID; |
bogdanm | 15:4892fe388435 | 1174 | |
bogdanm | 15:4892fe388435 | 1175 | ///Offset: 0x00000028 - Received data bytes 1-4 |
bogdanm | 15:4892fe388435 | 1176 | __IO uint32_t RDA; |
bogdanm | 15:4892fe388435 | 1177 | |
bogdanm | 15:4892fe388435 | 1178 | ///Offset: 0x0000002C - Received data bytes 5-8 |
bogdanm | 15:4892fe388435 | 1179 | __IO uint32_t RDB; |
bogdanm | 15:4892fe388435 | 1180 | |
bogdanm | 15:4892fe388435 | 1181 | ///Offset: 0x00000030 - Transmit frame info (Tx Buffer 1) |
bogdanm | 15:4892fe388435 | 1182 | __IO uint32_t TFI1; |
bogdanm | 15:4892fe388435 | 1183 | |
bogdanm | 15:4892fe388435 | 1184 | ///Offset: 0x00000034 - Transmit Identifier (Tx Buffer 1) |
bogdanm | 15:4892fe388435 | 1185 | __IO uint32_t TID1; |
bogdanm | 15:4892fe388435 | 1186 | |
bogdanm | 15:4892fe388435 | 1187 | ///Offset: 0x00000038 - Transmit data bytes 1-4 (Tx Buffer 1) |
bogdanm | 15:4892fe388435 | 1188 | __IO uint32_t TDA1; |
bogdanm | 15:4892fe388435 | 1189 | |
bogdanm | 15:4892fe388435 | 1190 | ///Offset: 0x0000003C - Transmit data bytes 5-8 (Tx Buffer 1) |
bogdanm | 15:4892fe388435 | 1191 | __IO uint32_t TDB1; |
bogdanm | 15:4892fe388435 | 1192 | |
bogdanm | 15:4892fe388435 | 1193 | ///Offset: 0x00000040 - Transmit frame info (Tx Buffer 2) |
bogdanm | 15:4892fe388435 | 1194 | __IO uint32_t TFI2; |
bogdanm | 15:4892fe388435 | 1195 | |
bogdanm | 15:4892fe388435 | 1196 | ///Offset: 0x00000044 - Transmit Identifier (Tx Buffer 2) |
bogdanm | 15:4892fe388435 | 1197 | __IO uint32_t TID2; |
bogdanm | 15:4892fe388435 | 1198 | |
bogdanm | 15:4892fe388435 | 1199 | ///Offset: 0x00000048 - Transmit data bytes 1-4 (Tx Buffer 2) |
bogdanm | 15:4892fe388435 | 1200 | __IO uint32_t TDA2; |
bogdanm | 15:4892fe388435 | 1201 | |
bogdanm | 15:4892fe388435 | 1202 | ///Offset: 0x0000004C - Transmit data bytes 5-8 (Tx Buffer 2) |
bogdanm | 15:4892fe388435 | 1203 | __IO uint32_t TDB2; |
bogdanm | 15:4892fe388435 | 1204 | |
bogdanm | 15:4892fe388435 | 1205 | ///Offset: 0x00000050 - Transmit frame info (Tx Buffer 3) |
bogdanm | 15:4892fe388435 | 1206 | __IO uint32_t TFI3; |
bogdanm | 15:4892fe388435 | 1207 | |
bogdanm | 15:4892fe388435 | 1208 | ///Offset: 0x00000054 - Transmit Identifier (Tx Buffer 3) |
bogdanm | 15:4892fe388435 | 1209 | __IO uint32_t TID3; |
bogdanm | 15:4892fe388435 | 1210 | |
bogdanm | 15:4892fe388435 | 1211 | ///Offset: 0x00000058 - Transmit data bytes 1-4 (Tx Buffer 3) |
bogdanm | 15:4892fe388435 | 1212 | __IO uint32_t TDA3; |
bogdanm | 15:4892fe388435 | 1213 | |
bogdanm | 15:4892fe388435 | 1214 | ///Offset: 0x0000005C - Transmit data bytes 5-8 (Tx Buffer 3) |
bogdanm | 15:4892fe388435 | 1215 | __IO uint32_t TDB3; |
bogdanm | 15:4892fe388435 | 1216 | } LPC_CAN_TypeDef; |
bogdanm | 15:4892fe388435 | 1217 | |
bogdanm | 15:4892fe388435 | 1218 | /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ |
bogdanm | 15:4892fe388435 | 1219 | typedef struct |
bogdanm | 15:4892fe388435 | 1220 | { |
bogdanm | 15:4892fe388435 | 1221 | __IO uint32_t CR; |
bogdanm | 15:4892fe388435 | 1222 | __IO uint32_t CTRL; |
bogdanm | 15:4892fe388435 | 1223 | __IO uint32_t CNTVAL; |
bogdanm | 15:4892fe388435 | 1224 | } LPC_DAC_TypeDef; |
bogdanm | 15:4892fe388435 | 1225 | |
bogdanm | 15:4892fe388435 | 1226 | |
bogdanm | 15:4892fe388435 | 1227 | /*------------- Inter IC Sound (I2S) -----------------------------------------*/ |
bogdanm | 15:4892fe388435 | 1228 | typedef struct |
bogdanm | 15:4892fe388435 | 1229 | { |
bogdanm | 15:4892fe388435 | 1230 | __IO uint32_t DAO; |
bogdanm | 15:4892fe388435 | 1231 | __IO uint32_t DAI; |
bogdanm | 15:4892fe388435 | 1232 | __O uint32_t TXFIFO; |
bogdanm | 15:4892fe388435 | 1233 | __I uint32_t RXFIFO; |
bogdanm | 15:4892fe388435 | 1234 | __I uint32_t STATE; |
bogdanm | 15:4892fe388435 | 1235 | __IO uint32_t DMA1; |
bogdanm | 15:4892fe388435 | 1236 | __IO uint32_t DMA2; |
bogdanm | 15:4892fe388435 | 1237 | __IO uint32_t IRQ; |
bogdanm | 15:4892fe388435 | 1238 | __IO uint32_t TXRATE; |
bogdanm | 15:4892fe388435 | 1239 | __IO uint32_t RXRATE; |
bogdanm | 15:4892fe388435 | 1240 | __IO uint32_t TXBITRATE; |
bogdanm | 15:4892fe388435 | 1241 | __IO uint32_t RXBITRATE; |
bogdanm | 15:4892fe388435 | 1242 | __IO uint32_t TXMODE; |
bogdanm | 15:4892fe388435 | 1243 | __IO uint32_t RXMODE; |
bogdanm | 15:4892fe388435 | 1244 | } LPC_I2S_TypeDef; |
bogdanm | 15:4892fe388435 | 1245 | |
bogdanm | 15:4892fe388435 | 1246 | |
bogdanm | 15:4892fe388435 | 1247 | |
bogdanm | 15:4892fe388435 | 1248 | |
bogdanm | 15:4892fe388435 | 1249 | |
bogdanm | 15:4892fe388435 | 1250 | |
bogdanm | 15:4892fe388435 | 1251 | /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ |
bogdanm | 15:4892fe388435 | 1252 | typedef struct |
bogdanm | 15:4892fe388435 | 1253 | { |
bogdanm | 15:4892fe388435 | 1254 | __I uint32_t CON; |
bogdanm | 15:4892fe388435 | 1255 | __O uint32_t CON_SET; |
bogdanm | 15:4892fe388435 | 1256 | __O uint32_t CON_CLR; |
bogdanm | 15:4892fe388435 | 1257 | __I uint32_t CAPCON; |
bogdanm | 15:4892fe388435 | 1258 | __O uint32_t CAPCON_SET; |
bogdanm | 15:4892fe388435 | 1259 | __O uint32_t CAPCON_CLR; |
bogdanm | 15:4892fe388435 | 1260 | __IO uint32_t TC0; |
bogdanm | 15:4892fe388435 | 1261 | __IO uint32_t TC1; |
bogdanm | 15:4892fe388435 | 1262 | __IO uint32_t TC2; |
bogdanm | 15:4892fe388435 | 1263 | __IO uint32_t LIM0; |
bogdanm | 15:4892fe388435 | 1264 | __IO uint32_t LIM1; |
bogdanm | 15:4892fe388435 | 1265 | __IO uint32_t LIM2; |
bogdanm | 15:4892fe388435 | 1266 | __IO uint32_t MAT0; |
bogdanm | 15:4892fe388435 | 1267 | __IO uint32_t MAT1; |
bogdanm | 15:4892fe388435 | 1268 | __IO uint32_t MAT2; |
bogdanm | 15:4892fe388435 | 1269 | __IO uint32_t DT; |
bogdanm | 15:4892fe388435 | 1270 | __IO uint32_t CP; |
bogdanm | 15:4892fe388435 | 1271 | __IO uint32_t CAP0; |
bogdanm | 15:4892fe388435 | 1272 | __IO uint32_t CAP1; |
bogdanm | 15:4892fe388435 | 1273 | __IO uint32_t CAP2; |
bogdanm | 15:4892fe388435 | 1274 | __I uint32_t INTEN; |
bogdanm | 15:4892fe388435 | 1275 | __O uint32_t INTEN_SET; |
bogdanm | 15:4892fe388435 | 1276 | __O uint32_t INTEN_CLR; |
bogdanm | 15:4892fe388435 | 1277 | __I uint32_t CNTCON; |
bogdanm | 15:4892fe388435 | 1278 | __O uint32_t CNTCON_SET; |
bogdanm | 15:4892fe388435 | 1279 | __O uint32_t CNTCON_CLR; |
bogdanm | 15:4892fe388435 | 1280 | __I uint32_t INTF; |
bogdanm | 15:4892fe388435 | 1281 | __O uint32_t INTF_SET; |
bogdanm | 15:4892fe388435 | 1282 | __O uint32_t INTF_CLR; |
bogdanm | 15:4892fe388435 | 1283 | __O uint32_t CAP_CLR; |
bogdanm | 15:4892fe388435 | 1284 | } LPC_MCPWM_TypeDef; |
bogdanm | 15:4892fe388435 | 1285 | |
bogdanm | 15:4892fe388435 | 1286 | /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ |
bogdanm | 15:4892fe388435 | 1287 | typedef struct |
bogdanm | 15:4892fe388435 | 1288 | { |
bogdanm | 15:4892fe388435 | 1289 | __O uint32_t CON; |
bogdanm | 15:4892fe388435 | 1290 | __I uint32_t STAT; |
bogdanm | 15:4892fe388435 | 1291 | __IO uint32_t CONF; |
bogdanm | 15:4892fe388435 | 1292 | __I uint32_t POS; |
bogdanm | 15:4892fe388435 | 1293 | __IO uint32_t MAXPOS; |
bogdanm | 15:4892fe388435 | 1294 | __IO uint32_t CMPOS0; |
bogdanm | 15:4892fe388435 | 1295 | __IO uint32_t CMPOS1; |
bogdanm | 15:4892fe388435 | 1296 | __IO uint32_t CMPOS2; |
bogdanm | 15:4892fe388435 | 1297 | __I uint32_t INXCNT; |
bogdanm | 15:4892fe388435 | 1298 | __IO uint32_t INXCMP0; |
bogdanm | 15:4892fe388435 | 1299 | __IO uint32_t LOAD; |
bogdanm | 15:4892fe388435 | 1300 | __I uint32_t TIME; |
bogdanm | 15:4892fe388435 | 1301 | __I uint32_t VEL; |
bogdanm | 15:4892fe388435 | 1302 | __I uint32_t CAP; |
bogdanm | 15:4892fe388435 | 1303 | __IO uint32_t VELCOMP; |
bogdanm | 15:4892fe388435 | 1304 | __IO uint32_t FILTERPHA; |
bogdanm | 15:4892fe388435 | 1305 | __IO uint32_t FILTERPHB; |
bogdanm | 15:4892fe388435 | 1306 | __IO uint32_t FILTERINX; |
bogdanm | 15:4892fe388435 | 1307 | __IO uint32_t WINDOW; |
bogdanm | 15:4892fe388435 | 1308 | __IO uint32_t INXCMP1; |
bogdanm | 15:4892fe388435 | 1309 | __IO uint32_t INXCMP2; |
bogdanm | 15:4892fe388435 | 1310 | uint32_t RESERVED0[993]; |
bogdanm | 15:4892fe388435 | 1311 | __O uint32_t IEC; |
bogdanm | 15:4892fe388435 | 1312 | __O uint32_t IES; |
bogdanm | 15:4892fe388435 | 1313 | __I uint32_t INTSTAT; |
bogdanm | 15:4892fe388435 | 1314 | __I uint32_t IE; |
bogdanm | 15:4892fe388435 | 1315 | __O uint32_t CLR; |
bogdanm | 15:4892fe388435 | 1316 | __O uint32_t SET; |
bogdanm | 15:4892fe388435 | 1317 | } LPC_QEI_TypeDef; |
bogdanm | 15:4892fe388435 | 1318 | |
bogdanm | 15:4892fe388435 | 1319 | /*------------- SD/MMC card Interface (MCI)-----------------------------------*/ |
bogdanm | 15:4892fe388435 | 1320 | typedef struct |
bogdanm | 15:4892fe388435 | 1321 | { |
bogdanm | 15:4892fe388435 | 1322 | __IO uint32_t POWER; |
bogdanm | 15:4892fe388435 | 1323 | __IO uint32_t CLOCK; |
bogdanm | 15:4892fe388435 | 1324 | __IO uint32_t ARGUMENT; |
bogdanm | 15:4892fe388435 | 1325 | __IO uint32_t COMMAND; |
bogdanm | 15:4892fe388435 | 1326 | __I uint32_t RESP_CMD; |
bogdanm | 15:4892fe388435 | 1327 | __I uint32_t RESP0; |
bogdanm | 15:4892fe388435 | 1328 | __I uint32_t RESP1; |
bogdanm | 15:4892fe388435 | 1329 | __I uint32_t RESP2; |
bogdanm | 15:4892fe388435 | 1330 | __I uint32_t RESP3; |
bogdanm | 15:4892fe388435 | 1331 | __IO uint32_t DATATMR; |
bogdanm | 15:4892fe388435 | 1332 | __IO uint32_t DATALEN; |
bogdanm | 15:4892fe388435 | 1333 | __IO uint32_t DATACTRL; |
bogdanm | 15:4892fe388435 | 1334 | __I uint32_t DATACNT; |
bogdanm | 15:4892fe388435 | 1335 | __I uint32_t STATUS; |
bogdanm | 15:4892fe388435 | 1336 | __O uint32_t CLEAR; |
bogdanm | 15:4892fe388435 | 1337 | __IO uint32_t MASK0; |
bogdanm | 15:4892fe388435 | 1338 | uint32_t RESERVED0[2]; |
bogdanm | 15:4892fe388435 | 1339 | __I uint32_t FIFOCNT; |
bogdanm | 15:4892fe388435 | 1340 | uint32_t RESERVED1[13]; |
bogdanm | 15:4892fe388435 | 1341 | __IO uint32_t FIFO[16]; |
bogdanm | 15:4892fe388435 | 1342 | } LPC_MCI_TypeDef; |
bogdanm | 15:4892fe388435 | 1343 | |
bogdanm | 15:4892fe388435 | 1344 | |
bogdanm | 15:4892fe388435 | 1345 | |
bogdanm | 15:4892fe388435 | 1346 | |
bogdanm | 15:4892fe388435 | 1347 | |
bogdanm | 15:4892fe388435 | 1348 | |
bogdanm | 15:4892fe388435 | 1349 | |
bogdanm | 15:4892fe388435 | 1350 | |
bogdanm | 15:4892fe388435 | 1351 | |
bogdanm | 15:4892fe388435 | 1352 | |
bogdanm | 15:4892fe388435 | 1353 | /*------------- EEPROM Controller (EEPROM) -----------------------------------*/ |
bogdanm | 15:4892fe388435 | 1354 | typedef struct |
bogdanm | 15:4892fe388435 | 1355 | { |
bogdanm | 15:4892fe388435 | 1356 | __IO uint32_t CMD; /* 0x0080 */ |
bogdanm | 15:4892fe388435 | 1357 | __IO uint32_t ADDR; |
bogdanm | 15:4892fe388435 | 1358 | __IO uint32_t WDATA; |
bogdanm | 15:4892fe388435 | 1359 | __IO uint32_t RDATA; |
bogdanm | 15:4892fe388435 | 1360 | __IO uint32_t WSTATE; /* 0x0090 */ |
bogdanm | 15:4892fe388435 | 1361 | __IO uint32_t CLKDIV; |
bogdanm | 15:4892fe388435 | 1362 | __IO uint32_t PWRDWN; /* 0x0098 */ |
bogdanm | 15:4892fe388435 | 1363 | uint32_t RESERVED0[975]; |
bogdanm | 15:4892fe388435 | 1364 | __IO uint32_t INT_CLR_ENABLE; /* 0x0FD8 */ |
bogdanm | 15:4892fe388435 | 1365 | __IO uint32_t INT_SET_ENABLE; |
bogdanm | 15:4892fe388435 | 1366 | __IO uint32_t INT_STATUS; /* 0x0FE0 */ |
bogdanm | 15:4892fe388435 | 1367 | __IO uint32_t INT_ENABLE; |
bogdanm | 15:4892fe388435 | 1368 | __IO uint32_t INT_CLR_STATUS; |
bogdanm | 15:4892fe388435 | 1369 | __IO uint32_t INT_SET_STATUS; |
bogdanm | 15:4892fe388435 | 1370 | } LPC_EEPROM_TypeDef; |
bogdanm | 15:4892fe388435 | 1371 | |
bogdanm | 15:4892fe388435 | 1372 | |
bogdanm | 15:4892fe388435 | 1373 | /*------------- COMPARATOR ----------------------------------------------------*/ |
bogdanm | 15:4892fe388435 | 1374 | |
bogdanm | 15:4892fe388435 | 1375 | typedef struct { /*!< (@ 0x40020000) COMPARATOR Structure */ |
bogdanm | 15:4892fe388435 | 1376 | __IO uint32_t CTRL; /*!< (@ 0x40020000) Comparator block control register */ |
bogdanm | 15:4892fe388435 | 1377 | __IO uint32_t CTRL0; /*!< (@ 0x40020004) Comparator 0 control register */ |
bogdanm | 15:4892fe388435 | 1378 | __IO uint32_t CTRL1; /*!< (@ 0x40020008) Comparator 1 control register */ |
bogdanm | 15:4892fe388435 | 1379 | } LPC_COMPARATOR_Type; |
bogdanm | 15:4892fe388435 | 1380 | |
bogdanm | 15:4892fe388435 | 1381 | |
bogdanm | 15:4892fe388435 | 1382 | #if defined ( __CC_ARM ) |
bogdanm | 15:4892fe388435 | 1383 | #pragma no_anon_unions |
bogdanm | 15:4892fe388435 | 1384 | #endif |
bogdanm | 15:4892fe388435 | 1385 | |
bogdanm | 15:4892fe388435 | 1386 | /******************************************************************************/ |
bogdanm | 15:4892fe388435 | 1387 | /* Peripheral memory map */ |
bogdanm | 15:4892fe388435 | 1388 | /******************************************************************************/ |
bogdanm | 15:4892fe388435 | 1389 | /* Base addresses */ |
bogdanm | 15:4892fe388435 | 1390 | #define LPC_FLASH_BASE (0x00000000UL) |
bogdanm | 15:4892fe388435 | 1391 | #define LPC_RAM_BASE (0x10000000UL) |
bogdanm | 15:4892fe388435 | 1392 | #define LPC_PERI_RAM_BASE (0x20000000UL) |
bogdanm | 15:4892fe388435 | 1393 | #define LPC_APB0_BASE (0x40000000UL) |
bogdanm | 15:4892fe388435 | 1394 | #define LPC_APB1_BASE (0x40080000UL) |
bogdanm | 15:4892fe388435 | 1395 | #define LPC_AHBRAM1_BASE (0x20004000UL) |
bogdanm | 15:4892fe388435 | 1396 | #define LPC_AHB_BASE (0x20080000UL) |
bogdanm | 15:4892fe388435 | 1397 | #define LPC_CM3_BASE (0xE0000000UL) |
bogdanm | 15:4892fe388435 | 1398 | |
bogdanm | 15:4892fe388435 | 1399 | /* APB0 peripherals */ |
bogdanm | 15:4892fe388435 | 1400 | #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) |
bogdanm | 15:4892fe388435 | 1401 | #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) |
bogdanm | 15:4892fe388435 | 1402 | #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) |
bogdanm | 15:4892fe388435 | 1403 | #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) |
bogdanm | 15:4892fe388435 | 1404 | #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) |
bogdanm | 15:4892fe388435 | 1405 | #define LPC_PWM0_BASE (LPC_APB0_BASE + 0x14000) |
bogdanm | 15:4892fe388435 | 1406 | #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) |
bogdanm | 15:4892fe388435 | 1407 | #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) |
bogdanm | 15:4892fe388435 | 1408 | #define LPC_COMPARATOR_BASE (LPC_APB0_BASE + 0x20000) |
bogdanm | 15:4892fe388435 | 1409 | #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) |
bogdanm | 15:4892fe388435 | 1410 | #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) |
bogdanm | 15:4892fe388435 | 1411 | #define LPC_IOCON_BASE (LPC_APB0_BASE + 0x2C000) |
bogdanm | 15:4892fe388435 | 1412 | #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) |
bogdanm | 15:4892fe388435 | 1413 | #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) |
bogdanm | 15:4892fe388435 | 1414 | #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) |
bogdanm | 15:4892fe388435 | 1415 | #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) |
bogdanm | 15:4892fe388435 | 1416 | #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) |
bogdanm | 15:4892fe388435 | 1417 | #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) |
bogdanm | 15:4892fe388435 | 1418 | #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) |
bogdanm | 15:4892fe388435 | 1419 | #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) |
bogdanm | 15:4892fe388435 | 1420 | |
bogdanm | 15:4892fe388435 | 1421 | /* APB1 peripherals */ |
bogdanm | 15:4892fe388435 | 1422 | #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) |
bogdanm | 15:4892fe388435 | 1423 | #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) |
bogdanm | 15:4892fe388435 | 1424 | #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) |
bogdanm | 15:4892fe388435 | 1425 | #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) |
bogdanm | 15:4892fe388435 | 1426 | #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) |
bogdanm | 15:4892fe388435 | 1427 | #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) |
bogdanm | 15:4892fe388435 | 1428 | #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) |
bogdanm | 15:4892fe388435 | 1429 | #define LPC_UART4_BASE (LPC_APB1_BASE + 0x24000) |
bogdanm | 15:4892fe388435 | 1430 | #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) |
bogdanm | 15:4892fe388435 | 1431 | #define LPC_SSP2_BASE (LPC_APB1_BASE + 0x2C000) |
bogdanm | 15:4892fe388435 | 1432 | #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) |
bogdanm | 15:4892fe388435 | 1433 | #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) |
bogdanm | 15:4892fe388435 | 1434 | #define LPC_MCI_BASE (LPC_APB1_BASE + 0x40000) |
bogdanm | 15:4892fe388435 | 1435 | #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) |
bogdanm | 15:4892fe388435 | 1436 | |
bogdanm | 15:4892fe388435 | 1437 | /* AHB peripherals */ |
bogdanm | 15:4892fe388435 | 1438 | #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x00000) |
bogdanm | 15:4892fe388435 | 1439 | #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x00100) |
bogdanm | 15:4892fe388435 | 1440 | #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x00120) |
bogdanm | 15:4892fe388435 | 1441 | #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x00140) |
bogdanm | 15:4892fe388435 | 1442 | #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x00160) |
bogdanm | 15:4892fe388435 | 1443 | #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x00180) |
bogdanm | 15:4892fe388435 | 1444 | #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x001A0) |
bogdanm | 15:4892fe388435 | 1445 | #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x001C0) |
bogdanm | 15:4892fe388435 | 1446 | #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x001E0) |
bogdanm | 15:4892fe388435 | 1447 | #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x04000) |
bogdanm | 15:4892fe388435 | 1448 | #define LPC_LCD_BASE (LPC_AHB_BASE + 0x08000) |
bogdanm | 15:4892fe388435 | 1449 | #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) |
bogdanm | 15:4892fe388435 | 1450 | #define LPC_CRC_BASE (LPC_AHB_BASE + 0x10000) |
bogdanm | 15:4892fe388435 | 1451 | #define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x18000) |
bogdanm | 15:4892fe388435 | 1452 | #define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x18020) |
bogdanm | 15:4892fe388435 | 1453 | #define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x18040) |
bogdanm | 15:4892fe388435 | 1454 | #define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x18060) |
bogdanm | 15:4892fe388435 | 1455 | #define LPC_GPIO4_BASE (LPC_AHB_BASE + 0x18080) |
bogdanm | 15:4892fe388435 | 1456 | #define LPC_GPIO5_BASE (LPC_AHB_BASE + 0x180A0) |
bogdanm | 15:4892fe388435 | 1457 | #define LPC_EMC_BASE (LPC_AHB_BASE + 0x1C000) |
bogdanm | 15:4892fe388435 | 1458 | |
bogdanm | 15:4892fe388435 | 1459 | #define LPC_EEPROM_BASE (LPC_FLASH_BASE+ 0x200080) |
bogdanm | 15:4892fe388435 | 1460 | |
bogdanm | 15:4892fe388435 | 1461 | |
bogdanm | 15:4892fe388435 | 1462 | /******************************************************************************/ |
bogdanm | 15:4892fe388435 | 1463 | /* Peripheral declaration */ |
bogdanm | 15:4892fe388435 | 1464 | /******************************************************************************/ |
bogdanm | 15:4892fe388435 | 1465 | #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) |
bogdanm | 15:4892fe388435 | 1466 | #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) |
bogdanm | 15:4892fe388435 | 1467 | #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) |
bogdanm | 15:4892fe388435 | 1468 | #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) |
bogdanm | 15:4892fe388435 | 1469 | #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) |
bogdanm | 15:4892fe388435 | 1470 | #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) |
bogdanm | 15:4892fe388435 | 1471 | #define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE ) |
bogdanm | 15:4892fe388435 | 1472 | #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) |
bogdanm | 15:4892fe388435 | 1473 | #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) |
bogdanm | 15:4892fe388435 | 1474 | #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) |
bogdanm | 15:4892fe388435 | 1475 | #define LPC_UART4 ((LPC_UART4_TypeDef *) LPC_UART4_BASE ) |
bogdanm | 15:4892fe388435 | 1476 | #define LPC_PWM0 ((LPC_PWM_TypeDef *) LPC_PWM0_BASE ) |
bogdanm | 15:4892fe388435 | 1477 | #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) |
bogdanm | 15:4892fe388435 | 1478 | #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) |
bogdanm | 15:4892fe388435 | 1479 | #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) |
bogdanm | 15:4892fe388435 | 1480 | #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) |
bogdanm | 15:4892fe388435 | 1481 | #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) |
bogdanm | 15:4892fe388435 | 1482 | #define LPC_COMPARATOR ((LPC_COMPARATOR_Type *) LPC_COMPARATOR_BASE) |
bogdanm | 15:4892fe388435 | 1483 | #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) |
bogdanm | 15:4892fe388435 | 1484 | #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) |
bogdanm | 15:4892fe388435 | 1485 | #define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) |
bogdanm | 15:4892fe388435 | 1486 | #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) |
bogdanm | 15:4892fe388435 | 1487 | #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) |
bogdanm | 15:4892fe388435 | 1488 | #define LPC_SSP2 ((LPC_SSP_TypeDef *) LPC_SSP2_BASE ) |
bogdanm | 15:4892fe388435 | 1489 | #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) |
bogdanm | 15:4892fe388435 | 1490 | #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) |
bogdanm | 15:4892fe388435 | 1491 | #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) |
bogdanm | 15:4892fe388435 | 1492 | #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) |
bogdanm | 15:4892fe388435 | 1493 | #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) |
bogdanm | 15:4892fe388435 | 1494 | #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) |
bogdanm | 15:4892fe388435 | 1495 | #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) |
bogdanm | 15:4892fe388435 | 1496 | #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) |
bogdanm | 15:4892fe388435 | 1497 | #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) |
bogdanm | 15:4892fe388435 | 1498 | #define LPC_MCI ((LPC_MCI_TypeDef *) LPC_MCI_BASE ) |
bogdanm | 15:4892fe388435 | 1499 | #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) |
bogdanm | 15:4892fe388435 | 1500 | #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) |
bogdanm | 15:4892fe388435 | 1501 | #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) |
bogdanm | 15:4892fe388435 | 1502 | #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) |
bogdanm | 15:4892fe388435 | 1503 | #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) |
bogdanm | 15:4892fe388435 | 1504 | #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) |
bogdanm | 15:4892fe388435 | 1505 | #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) |
bogdanm | 15:4892fe388435 | 1506 | #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) |
bogdanm | 15:4892fe388435 | 1507 | #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) |
bogdanm | 15:4892fe388435 | 1508 | #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) |
bogdanm | 15:4892fe388435 | 1509 | #define LPC_LCD ((LPC_LCD_TypeDef *) LPC_LCD_BASE ) |
bogdanm | 15:4892fe388435 | 1510 | #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) |
bogdanm | 15:4892fe388435 | 1511 | #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) |
bogdanm | 15:4892fe388435 | 1512 | #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) |
bogdanm | 15:4892fe388435 | 1513 | #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) |
bogdanm | 15:4892fe388435 | 1514 | #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) |
bogdanm | 15:4892fe388435 | 1515 | #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) |
bogdanm | 15:4892fe388435 | 1516 | #define LPC_GPIO5 ((LPC_GPIO_TypeDef *) LPC_GPIO5_BASE ) |
bogdanm | 15:4892fe388435 | 1517 | #define LPC_EMC ((LPC_EMC_TypeDef *) LPC_EMC_BASE ) |
bogdanm | 15:4892fe388435 | 1518 | #define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE ) |
bogdanm | 15:4892fe388435 | 1519 | #define LPC_EEPROM ((LPC_EEPROM_TypeDef *) LPC_EEPROM_BASE ) |
bogdanm | 15:4892fe388435 | 1520 | |
bogdanm | 15:4892fe388435 | 1521 | |
bogdanm | 15:4892fe388435 | 1522 | |
bogdanm | 15:4892fe388435 | 1523 | #endif // __LPC407x_8x_177x_8x_H__ |