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targets/cmsis/core_cm0plus.h@13:0645d8841f51, 2013-08-05 (annotated)

Committer:
bogdanm
Date:
Mon Aug 05 14:12:34 2013 +0300
Revision:
13:0645d8841f51
Update mbed sources to revision 64

Who changed what in which revision?

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bogdanm 13:0645d8841f51 1 /**************************************************************************//**
bogdanm 13:0645d8841f51 2 * @file core_cm0plus.h
bogdanm 13:0645d8841f51 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
bogdanm 13:0645d8841f51 4 * @version V3.20
bogdanm 13:0645d8841f51 5 * @date 25. February 2013
bogdanm 13:0645d8841f51 6 *
bogdanm 13:0645d8841f51 7 * @note
bogdanm 13:0645d8841f51 8 *
bogdanm 13:0645d8841f51 9 ******************************************************************************/
bogdanm 13:0645d8841f51 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
bogdanm 13:0645d8841f51 11
bogdanm 13:0645d8841f51 12 All rights reserved.
bogdanm 13:0645d8841f51 13 Redistribution and use in source and binary forms, with or without
bogdanm 13:0645d8841f51 14 modification, are permitted provided that the following conditions are met:
bogdanm 13:0645d8841f51 15 - Redistributions of source code must retain the above copyright
bogdanm 13:0645d8841f51 16 notice, this list of conditions and the following disclaimer.
bogdanm 13:0645d8841f51 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 13:0645d8841f51 18 notice, this list of conditions and the following disclaimer in the
bogdanm 13:0645d8841f51 19 documentation and/or other materials provided with the distribution.
bogdanm 13:0645d8841f51 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 13:0645d8841f51 21 to endorse or promote products derived from this software without
bogdanm 13:0645d8841f51 22 specific prior written permission.
bogdanm 13:0645d8841f51 23 *
bogdanm 13:0645d8841f51 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 13:0645d8841f51 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 13:0645d8841f51 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 13:0645d8841f51 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 13:0645d8841f51 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 13:0645d8841f51 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 13:0645d8841f51 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 13:0645d8841f51 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 13:0645d8841f51 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 13:0645d8841f51 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 13:0645d8841f51 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 13:0645d8841f51 35 ---------------------------------------------------------------------------*/
bogdanm 13:0645d8841f51 36
bogdanm 13:0645d8841f51 37
bogdanm 13:0645d8841f51 38 #if defined ( __ICCARM__ )
bogdanm 13:0645d8841f51 39 #pragma system_include /* treat file as system include file for MISRA check */
bogdanm 13:0645d8841f51 40 #endif
bogdanm 13:0645d8841f51 41
bogdanm 13:0645d8841f51 42 #ifdef __cplusplus
bogdanm 13:0645d8841f51 43 extern "C" {
bogdanm 13:0645d8841f51 44 #endif
bogdanm 13:0645d8841f51 45
bogdanm 13:0645d8841f51 46 #ifndef __CORE_CM0PLUS_H_GENERIC
bogdanm 13:0645d8841f51 47 #define __CORE_CM0PLUS_H_GENERIC
bogdanm 13:0645d8841f51 48
bogdanm 13:0645d8841f51 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
bogdanm 13:0645d8841f51 50 CMSIS violates the following MISRA-C:2004 rules:
bogdanm 13:0645d8841f51 51
bogdanm 13:0645d8841f51 52 \li Required Rule 8.5, object/function definition in header file.<br>
bogdanm 13:0645d8841f51 53 Function definitions in header files are used to allow 'inlining'.
bogdanm 13:0645d8841f51 54
bogdanm 13:0645d8841f51 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
bogdanm 13:0645d8841f51 56 Unions are used for effective representation of core registers.
bogdanm 13:0645d8841f51 57
bogdanm 13:0645d8841f51 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
bogdanm 13:0645d8841f51 59 Function-like macros are used to allow more efficient code.
bogdanm 13:0645d8841f51 60 */
bogdanm 13:0645d8841f51 61
bogdanm 13:0645d8841f51 62
bogdanm 13:0645d8841f51 63 /*******************************************************************************
bogdanm 13:0645d8841f51 64 * CMSIS definitions
bogdanm 13:0645d8841f51 65 ******************************************************************************/
bogdanm 13:0645d8841f51 66 /** \ingroup Cortex-M0+
bogdanm 13:0645d8841f51 67 @{
bogdanm 13:0645d8841f51 68 */
bogdanm 13:0645d8841f51 69
bogdanm 13:0645d8841f51 70 /* CMSIS CM0P definitions */
bogdanm 13:0645d8841f51 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
bogdanm 13:0645d8841f51 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
bogdanm 13:0645d8841f51 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
bogdanm 13:0645d8841f51 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
bogdanm 13:0645d8841f51 75
bogdanm 13:0645d8841f51 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
bogdanm 13:0645d8841f51 77
bogdanm 13:0645d8841f51 78
bogdanm 13:0645d8841f51 79 #if defined ( __CC_ARM )
bogdanm 13:0645d8841f51 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
bogdanm 13:0645d8841f51 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
bogdanm 13:0645d8841f51 82 #define __STATIC_INLINE static __inline
bogdanm 13:0645d8841f51 83
bogdanm 13:0645d8841f51 84 #elif defined ( __ICCARM__ )
bogdanm 13:0645d8841f51 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
bogdanm 13:0645d8841f51 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
bogdanm 13:0645d8841f51 87 #define __STATIC_INLINE static inline
bogdanm 13:0645d8841f51 88
bogdanm 13:0645d8841f51 89 #elif defined ( __GNUC__ )
bogdanm 13:0645d8841f51 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
bogdanm 13:0645d8841f51 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
bogdanm 13:0645d8841f51 92 #define __STATIC_INLINE static inline
bogdanm 13:0645d8841f51 93
bogdanm 13:0645d8841f51 94 #elif defined ( __TASKING__ )
bogdanm 13:0645d8841f51 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
bogdanm 13:0645d8841f51 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
bogdanm 13:0645d8841f51 97 #define __STATIC_INLINE static inline
bogdanm 13:0645d8841f51 98
bogdanm 13:0645d8841f51 99 #endif
bogdanm 13:0645d8841f51 100
bogdanm 13:0645d8841f51 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
bogdanm 13:0645d8841f51 102 */
bogdanm 13:0645d8841f51 103 #define __FPU_USED 0
bogdanm 13:0645d8841f51 104
bogdanm 13:0645d8841f51 105 #if defined ( __CC_ARM )
bogdanm 13:0645d8841f51 106 #if defined __TARGET_FPU_VFP
bogdanm 13:0645d8841f51 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 13:0645d8841f51 108 #endif
bogdanm 13:0645d8841f51 109
bogdanm 13:0645d8841f51 110 #elif defined ( __ICCARM__ )
bogdanm 13:0645d8841f51 111 #if defined __ARMVFP__
bogdanm 13:0645d8841f51 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 13:0645d8841f51 113 #endif
bogdanm 13:0645d8841f51 114
bogdanm 13:0645d8841f51 115 #elif defined ( __GNUC__ )
bogdanm 13:0645d8841f51 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
bogdanm 13:0645d8841f51 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 13:0645d8841f51 118 #endif
bogdanm 13:0645d8841f51 119
bogdanm 13:0645d8841f51 120 #elif defined ( __TASKING__ )
bogdanm 13:0645d8841f51 121 #if defined __FPU_VFP__
bogdanm 13:0645d8841f51 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 13:0645d8841f51 123 #endif
bogdanm 13:0645d8841f51 124 #endif
bogdanm 13:0645d8841f51 125
bogdanm 13:0645d8841f51 126 #include <stdint.h> /* standard types definitions */
bogdanm 13:0645d8841f51 127 #include <core_cmInstr.h> /* Core Instruction Access */
bogdanm 13:0645d8841f51 128 #include <core_cmFunc.h> /* Core Function Access */
bogdanm 13:0645d8841f51 129
bogdanm 13:0645d8841f51 130 #endif /* __CORE_CM0PLUS_H_GENERIC */
bogdanm 13:0645d8841f51 131
bogdanm 13:0645d8841f51 132 #ifndef __CMSIS_GENERIC
bogdanm 13:0645d8841f51 133
bogdanm 13:0645d8841f51 134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
bogdanm 13:0645d8841f51 135 #define __CORE_CM0PLUS_H_DEPENDANT
bogdanm 13:0645d8841f51 136
bogdanm 13:0645d8841f51 137 /* check device defines and use defaults */
bogdanm 13:0645d8841f51 138 #if defined __CHECK_DEVICE_DEFINES
bogdanm 13:0645d8841f51 139 #ifndef __CM0PLUS_REV
bogdanm 13:0645d8841f51 140 #define __CM0PLUS_REV 0x0000
bogdanm 13:0645d8841f51 141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
bogdanm 13:0645d8841f51 142 #endif
bogdanm 13:0645d8841f51 143
bogdanm 13:0645d8841f51 144 #ifndef __MPU_PRESENT
bogdanm 13:0645d8841f51 145 #define __MPU_PRESENT 0
bogdanm 13:0645d8841f51 146 #warning "__MPU_PRESENT not defined in device header file; using default!"
bogdanm 13:0645d8841f51 147 #endif
bogdanm 13:0645d8841f51 148
bogdanm 13:0645d8841f51 149 #ifndef __VTOR_PRESENT
bogdanm 13:0645d8841f51 150 #define __VTOR_PRESENT 0
bogdanm 13:0645d8841f51 151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
bogdanm 13:0645d8841f51 152 #endif
bogdanm 13:0645d8841f51 153
bogdanm 13:0645d8841f51 154 #ifndef __NVIC_PRIO_BITS
bogdanm 13:0645d8841f51 155 #define __NVIC_PRIO_BITS 2
bogdanm 13:0645d8841f51 156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
bogdanm 13:0645d8841f51 157 #endif
bogdanm 13:0645d8841f51 158
bogdanm 13:0645d8841f51 159 #ifndef __Vendor_SysTickConfig
bogdanm 13:0645d8841f51 160 #define __Vendor_SysTickConfig 0
bogdanm 13:0645d8841f51 161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
bogdanm 13:0645d8841f51 162 #endif
bogdanm 13:0645d8841f51 163 #endif
bogdanm 13:0645d8841f51 164
bogdanm 13:0645d8841f51 165 /* IO definitions (access restrictions to peripheral registers) */
bogdanm 13:0645d8841f51 166 /**
bogdanm 13:0645d8841f51 167 \defgroup CMSIS_glob_defs CMSIS Global Defines
bogdanm 13:0645d8841f51 168
bogdanm 13:0645d8841f51 169 <strong>IO Type Qualifiers</strong> are used
bogdanm 13:0645d8841f51 170 \li to specify the access to peripheral variables.
bogdanm 13:0645d8841f51 171 \li for automatic generation of peripheral register debug information.
bogdanm 13:0645d8841f51 172 */
bogdanm 13:0645d8841f51 173 #ifdef __cplusplus
bogdanm 13:0645d8841f51 174 #define __I volatile /*!< Defines 'read only' permissions */
bogdanm 13:0645d8841f51 175 #else
bogdanm 13:0645d8841f51 176 #define __I volatile const /*!< Defines 'read only' permissions */
bogdanm 13:0645d8841f51 177 #endif
bogdanm 13:0645d8841f51 178 #define __O volatile /*!< Defines 'write only' permissions */
bogdanm 13:0645d8841f51 179 #define __IO volatile /*!< Defines 'read / write' permissions */
bogdanm 13:0645d8841f51 180
bogdanm 13:0645d8841f51 181 /*@} end of group Cortex-M0+ */
bogdanm 13:0645d8841f51 182
bogdanm 13:0645d8841f51 183
bogdanm 13:0645d8841f51 184
bogdanm 13:0645d8841f51 185 /*******************************************************************************
bogdanm 13:0645d8841f51 186 * Register Abstraction
bogdanm 13:0645d8841f51 187 Core Register contain:
bogdanm 13:0645d8841f51 188 - Core Register
bogdanm 13:0645d8841f51 189 - Core NVIC Register
bogdanm 13:0645d8841f51 190 - Core SCB Register
bogdanm 13:0645d8841f51 191 - Core SysTick Register
bogdanm 13:0645d8841f51 192 - Core MPU Register
bogdanm 13:0645d8841f51 193 ******************************************************************************/
bogdanm 13:0645d8841f51 194 /** \defgroup CMSIS_core_register Defines and Type Definitions
bogdanm 13:0645d8841f51 195 \brief Type definitions and defines for Cortex-M processor based devices.
bogdanm 13:0645d8841f51 196 */
bogdanm 13:0645d8841f51 197
bogdanm 13:0645d8841f51 198 /** \ingroup CMSIS_core_register
bogdanm 13:0645d8841f51 199 \defgroup CMSIS_CORE Status and Control Registers
bogdanm 13:0645d8841f51 200 \brief Core Register type definitions.
bogdanm 13:0645d8841f51 201 @{
bogdanm 13:0645d8841f51 202 */
bogdanm 13:0645d8841f51 203
bogdanm 13:0645d8841f51 204 /** \brief Union type to access the Application Program Status Register (APSR).
bogdanm 13:0645d8841f51 205 */
bogdanm 13:0645d8841f51 206 typedef union
bogdanm 13:0645d8841f51 207 {
bogdanm 13:0645d8841f51 208 struct
bogdanm 13:0645d8841f51 209 {
bogdanm 13:0645d8841f51 210 #if (__CORTEX_M != 0x04)
bogdanm 13:0645d8841f51 211 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
bogdanm 13:0645d8841f51 212 #else
bogdanm 13:0645d8841f51 213 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
bogdanm 13:0645d8841f51 214 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
bogdanm 13:0645d8841f51 215 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
bogdanm 13:0645d8841f51 216 #endif
bogdanm 13:0645d8841f51 217 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
bogdanm 13:0645d8841f51 218 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 13:0645d8841f51 219 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 13:0645d8841f51 220 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 13:0645d8841f51 221 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 13:0645d8841f51 222 } b; /*!< Structure used for bit access */
bogdanm 13:0645d8841f51 223 uint32_t w; /*!< Type used for word access */
bogdanm 13:0645d8841f51 224 } APSR_Type;
bogdanm 13:0645d8841f51 225
bogdanm 13:0645d8841f51 226
bogdanm 13:0645d8841f51 227 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
bogdanm 13:0645d8841f51 228 */
bogdanm 13:0645d8841f51 229 typedef union
bogdanm 13:0645d8841f51 230 {
bogdanm 13:0645d8841f51 231 struct
bogdanm 13:0645d8841f51 232 {
bogdanm 13:0645d8841f51 233 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 13:0645d8841f51 234 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
bogdanm 13:0645d8841f51 235 } b; /*!< Structure used for bit access */
bogdanm 13:0645d8841f51 236 uint32_t w; /*!< Type used for word access */
bogdanm 13:0645d8841f51 237 } IPSR_Type;
bogdanm 13:0645d8841f51 238
bogdanm 13:0645d8841f51 239
bogdanm 13:0645d8841f51 240 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
bogdanm 13:0645d8841f51 241 */
bogdanm 13:0645d8841f51 242 typedef union
bogdanm 13:0645d8841f51 243 {
bogdanm 13:0645d8841f51 244 struct
bogdanm 13:0645d8841f51 245 {
bogdanm 13:0645d8841f51 246 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 13:0645d8841f51 247 #if (__CORTEX_M != 0x04)
bogdanm 13:0645d8841f51 248 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
bogdanm 13:0645d8841f51 249 #else
bogdanm 13:0645d8841f51 250 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
bogdanm 13:0645d8841f51 251 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
bogdanm 13:0645d8841f51 252 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
bogdanm 13:0645d8841f51 253 #endif
bogdanm 13:0645d8841f51 254 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
bogdanm 13:0645d8841f51 255 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
bogdanm 13:0645d8841f51 256 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
bogdanm 13:0645d8841f51 257 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 13:0645d8841f51 258 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 13:0645d8841f51 259 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 13:0645d8841f51 260 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 13:0645d8841f51 261 } b; /*!< Structure used for bit access */
bogdanm 13:0645d8841f51 262 uint32_t w; /*!< Type used for word access */
bogdanm 13:0645d8841f51 263 } xPSR_Type;
bogdanm 13:0645d8841f51 264
bogdanm 13:0645d8841f51 265
bogdanm 13:0645d8841f51 266 /** \brief Union type to access the Control Registers (CONTROL).
bogdanm 13:0645d8841f51 267 */
bogdanm 13:0645d8841f51 268 typedef union
bogdanm 13:0645d8841f51 269 {
bogdanm 13:0645d8841f51 270 struct
bogdanm 13:0645d8841f51 271 {
bogdanm 13:0645d8841f51 272 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
bogdanm 13:0645d8841f51 273 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
bogdanm 13:0645d8841f51 274 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
bogdanm 13:0645d8841f51 275 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
bogdanm 13:0645d8841f51 276 } b; /*!< Structure used for bit access */
bogdanm 13:0645d8841f51 277 uint32_t w; /*!< Type used for word access */
bogdanm 13:0645d8841f51 278 } CONTROL_Type;
bogdanm 13:0645d8841f51 279
bogdanm 13:0645d8841f51 280 /*@} end of group CMSIS_CORE */
bogdanm 13:0645d8841f51 281
bogdanm 13:0645d8841f51 282
bogdanm 13:0645d8841f51 283 /** \ingroup CMSIS_core_register
bogdanm 13:0645d8841f51 284 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
bogdanm 13:0645d8841f51 285 \brief Type definitions for the NVIC Registers
bogdanm 13:0645d8841f51 286 @{
bogdanm 13:0645d8841f51 287 */
bogdanm 13:0645d8841f51 288
bogdanm 13:0645d8841f51 289 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
bogdanm 13:0645d8841f51 290 */
bogdanm 13:0645d8841f51 291 typedef struct
bogdanm 13:0645d8841f51 292 {
bogdanm 13:0645d8841f51 293 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
bogdanm 13:0645d8841f51 294 uint32_t RESERVED0[31];
bogdanm 13:0645d8841f51 295 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
bogdanm 13:0645d8841f51 296 uint32_t RSERVED1[31];
bogdanm 13:0645d8841f51 297 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
bogdanm 13:0645d8841f51 298 uint32_t RESERVED2[31];
bogdanm 13:0645d8841f51 299 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
bogdanm 13:0645d8841f51 300 uint32_t RESERVED3[31];
bogdanm 13:0645d8841f51 301 uint32_t RESERVED4[64];
bogdanm 13:0645d8841f51 302 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
bogdanm 13:0645d8841f51 303 } NVIC_Type;
bogdanm 13:0645d8841f51 304
bogdanm 13:0645d8841f51 305 /*@} end of group CMSIS_NVIC */
bogdanm 13:0645d8841f51 306
bogdanm 13:0645d8841f51 307
bogdanm 13:0645d8841f51 308 /** \ingroup CMSIS_core_register
bogdanm 13:0645d8841f51 309 \defgroup CMSIS_SCB System Control Block (SCB)
bogdanm 13:0645d8841f51 310 \brief Type definitions for the System Control Block Registers
bogdanm 13:0645d8841f51 311 @{
bogdanm 13:0645d8841f51 312 */
bogdanm 13:0645d8841f51 313
bogdanm 13:0645d8841f51 314 /** \brief Structure type to access the System Control Block (SCB).
bogdanm 13:0645d8841f51 315 */
bogdanm 13:0645d8841f51 316 typedef struct
bogdanm 13:0645d8841f51 317 {
bogdanm 13:0645d8841f51 318 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
bogdanm 13:0645d8841f51 319 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
bogdanm 13:0645d8841f51 320 #if (__VTOR_PRESENT == 1)
bogdanm 13:0645d8841f51 321 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
bogdanm 13:0645d8841f51 322 #else
bogdanm 13:0645d8841f51 323 uint32_t RESERVED0;
bogdanm 13:0645d8841f51 324 #endif
bogdanm 13:0645d8841f51 325 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
bogdanm 13:0645d8841f51 326 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
bogdanm 13:0645d8841f51 327 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
bogdanm 13:0645d8841f51 328 uint32_t RESERVED1;
bogdanm 13:0645d8841f51 329 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
bogdanm 13:0645d8841f51 330 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
bogdanm 13:0645d8841f51 331 } SCB_Type;
bogdanm 13:0645d8841f51 332
bogdanm 13:0645d8841f51 333 /* SCB CPUID Register Definitions */
bogdanm 13:0645d8841f51 334 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
bogdanm 13:0645d8841f51 335 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
bogdanm 13:0645d8841f51 336
bogdanm 13:0645d8841f51 337 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
bogdanm 13:0645d8841f51 338 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
bogdanm 13:0645d8841f51 339
bogdanm 13:0645d8841f51 340 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
bogdanm 13:0645d8841f51 341 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
bogdanm 13:0645d8841f51 342
bogdanm 13:0645d8841f51 343 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
bogdanm 13:0645d8841f51 344 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
bogdanm 13:0645d8841f51 345
bogdanm 13:0645d8841f51 346 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
bogdanm 13:0645d8841f51 347 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
bogdanm 13:0645d8841f51 348
bogdanm 13:0645d8841f51 349 /* SCB Interrupt Control State Register Definitions */
bogdanm 13:0645d8841f51 350 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
bogdanm 13:0645d8841f51 351 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
bogdanm 13:0645d8841f51 352
bogdanm 13:0645d8841f51 353 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
bogdanm 13:0645d8841f51 354 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
bogdanm 13:0645d8841f51 355
bogdanm 13:0645d8841f51 356 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
bogdanm 13:0645d8841f51 357 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
bogdanm 13:0645d8841f51 358
bogdanm 13:0645d8841f51 359 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
bogdanm 13:0645d8841f51 360 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
bogdanm 13:0645d8841f51 361
bogdanm 13:0645d8841f51 362 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
bogdanm 13:0645d8841f51 363 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
bogdanm 13:0645d8841f51 364
bogdanm 13:0645d8841f51 365 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
bogdanm 13:0645d8841f51 366 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
bogdanm 13:0645d8841f51 367
bogdanm 13:0645d8841f51 368 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
bogdanm 13:0645d8841f51 369 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
bogdanm 13:0645d8841f51 370
bogdanm 13:0645d8841f51 371 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
bogdanm 13:0645d8841f51 372 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
bogdanm 13:0645d8841f51 373
bogdanm 13:0645d8841f51 374 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
bogdanm 13:0645d8841f51 375 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
bogdanm 13:0645d8841f51 376
bogdanm 13:0645d8841f51 377 #if (__VTOR_PRESENT == 1)
bogdanm 13:0645d8841f51 378 /* SCB Interrupt Control State Register Definitions */
bogdanm 13:0645d8841f51 379 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
bogdanm 13:0645d8841f51 380 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
bogdanm 13:0645d8841f51 381 #endif
bogdanm 13:0645d8841f51 382
bogdanm 13:0645d8841f51 383 /* SCB Application Interrupt and Reset Control Register Definitions */
bogdanm 13:0645d8841f51 384 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
bogdanm 13:0645d8841f51 385 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
bogdanm 13:0645d8841f51 386
bogdanm 13:0645d8841f51 387 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
bogdanm 13:0645d8841f51 388 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
bogdanm 13:0645d8841f51 389
bogdanm 13:0645d8841f51 390 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
bogdanm 13:0645d8841f51 391 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
bogdanm 13:0645d8841f51 392
bogdanm 13:0645d8841f51 393 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
bogdanm 13:0645d8841f51 394 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
bogdanm 13:0645d8841f51 395
bogdanm 13:0645d8841f51 396 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
bogdanm 13:0645d8841f51 397 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
bogdanm 13:0645d8841f51 398
bogdanm 13:0645d8841f51 399 /* SCB System Control Register Definitions */
bogdanm 13:0645d8841f51 400 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
bogdanm 13:0645d8841f51 401 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
bogdanm 13:0645d8841f51 402
bogdanm 13:0645d8841f51 403 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
bogdanm 13:0645d8841f51 404 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
bogdanm 13:0645d8841f51 405
bogdanm 13:0645d8841f51 406 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
bogdanm 13:0645d8841f51 407 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
bogdanm 13:0645d8841f51 408
bogdanm 13:0645d8841f51 409 /* SCB Configuration Control Register Definitions */
bogdanm 13:0645d8841f51 410 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
bogdanm 13:0645d8841f51 411 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
bogdanm 13:0645d8841f51 412
bogdanm 13:0645d8841f51 413 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
bogdanm 13:0645d8841f51 414 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
bogdanm 13:0645d8841f51 415
bogdanm 13:0645d8841f51 416 /* SCB System Handler Control and State Register Definitions */
bogdanm 13:0645d8841f51 417 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
bogdanm 13:0645d8841f51 418 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
bogdanm 13:0645d8841f51 419
bogdanm 13:0645d8841f51 420 /*@} end of group CMSIS_SCB */
bogdanm 13:0645d8841f51 421
bogdanm 13:0645d8841f51 422
bogdanm 13:0645d8841f51 423 /** \ingroup CMSIS_core_register
bogdanm 13:0645d8841f51 424 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
bogdanm 13:0645d8841f51 425 \brief Type definitions for the System Timer Registers.
bogdanm 13:0645d8841f51 426 @{
bogdanm 13:0645d8841f51 427 */
bogdanm 13:0645d8841f51 428
bogdanm 13:0645d8841f51 429 /** \brief Structure type to access the System Timer (SysTick).
bogdanm 13:0645d8841f51 430 */
bogdanm 13:0645d8841f51 431 typedef struct
bogdanm 13:0645d8841f51 432 {
bogdanm 13:0645d8841f51 433 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
bogdanm 13:0645d8841f51 434 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
bogdanm 13:0645d8841f51 435 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
bogdanm 13:0645d8841f51 436 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
bogdanm 13:0645d8841f51 437 } SysTick_Type;
bogdanm 13:0645d8841f51 438
bogdanm 13:0645d8841f51 439 /* SysTick Control / Status Register Definitions */
bogdanm 13:0645d8841f51 440 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
bogdanm 13:0645d8841f51 441 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
bogdanm 13:0645d8841f51 442
bogdanm 13:0645d8841f51 443 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
bogdanm 13:0645d8841f51 444 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
bogdanm 13:0645d8841f51 445
bogdanm 13:0645d8841f51 446 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
bogdanm 13:0645d8841f51 447 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
bogdanm 13:0645d8841f51 448
bogdanm 13:0645d8841f51 449 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
bogdanm 13:0645d8841f51 450 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
bogdanm 13:0645d8841f51 451
bogdanm 13:0645d8841f51 452 /* SysTick Reload Register Definitions */
bogdanm 13:0645d8841f51 453 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
bogdanm 13:0645d8841f51 454 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
bogdanm 13:0645d8841f51 455
bogdanm 13:0645d8841f51 456 /* SysTick Current Register Definitions */
bogdanm 13:0645d8841f51 457 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
bogdanm 13:0645d8841f51 458 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
bogdanm 13:0645d8841f51 459
bogdanm 13:0645d8841f51 460 /* SysTick Calibration Register Definitions */
bogdanm 13:0645d8841f51 461 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
bogdanm 13:0645d8841f51 462 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
bogdanm 13:0645d8841f51 463
bogdanm 13:0645d8841f51 464 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
bogdanm 13:0645d8841f51 465 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
bogdanm 13:0645d8841f51 466
bogdanm 13:0645d8841f51 467 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
bogdanm 13:0645d8841f51 468 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
bogdanm 13:0645d8841f51 469
bogdanm 13:0645d8841f51 470 /*@} end of group CMSIS_SysTick */
bogdanm 13:0645d8841f51 471
bogdanm 13:0645d8841f51 472 #if (__MPU_PRESENT == 1)
bogdanm 13:0645d8841f51 473 /** \ingroup CMSIS_core_register
bogdanm 13:0645d8841f51 474 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
bogdanm 13:0645d8841f51 475 \brief Type definitions for the Memory Protection Unit (MPU)
bogdanm 13:0645d8841f51 476 @{
bogdanm 13:0645d8841f51 477 */
bogdanm 13:0645d8841f51 478
bogdanm 13:0645d8841f51 479 /** \brief Structure type to access the Memory Protection Unit (MPU).
bogdanm 13:0645d8841f51 480 */
bogdanm 13:0645d8841f51 481 typedef struct
bogdanm 13:0645d8841f51 482 {
bogdanm 13:0645d8841f51 483 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
bogdanm 13:0645d8841f51 484 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
bogdanm 13:0645d8841f51 485 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
bogdanm 13:0645d8841f51 486 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
bogdanm 13:0645d8841f51 487 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
bogdanm 13:0645d8841f51 488 } MPU_Type;
bogdanm 13:0645d8841f51 489
bogdanm 13:0645d8841f51 490 /* MPU Type Register */
bogdanm 13:0645d8841f51 491 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
bogdanm 13:0645d8841f51 492 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
bogdanm 13:0645d8841f51 493
bogdanm 13:0645d8841f51 494 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
bogdanm 13:0645d8841f51 495 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
bogdanm 13:0645d8841f51 496
bogdanm 13:0645d8841f51 497 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
bogdanm 13:0645d8841f51 498 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
bogdanm 13:0645d8841f51 499
bogdanm 13:0645d8841f51 500 /* MPU Control Register */
bogdanm 13:0645d8841f51 501 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
bogdanm 13:0645d8841f51 502 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
bogdanm 13:0645d8841f51 503
bogdanm 13:0645d8841f51 504 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
bogdanm 13:0645d8841f51 505 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
bogdanm 13:0645d8841f51 506
bogdanm 13:0645d8841f51 507 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
bogdanm 13:0645d8841f51 508 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
bogdanm 13:0645d8841f51 509
bogdanm 13:0645d8841f51 510 /* MPU Region Number Register */
bogdanm 13:0645d8841f51 511 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
bogdanm 13:0645d8841f51 512 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
bogdanm 13:0645d8841f51 513
bogdanm 13:0645d8841f51 514 /* MPU Region Base Address Register */
bogdanm 13:0645d8841f51 515 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
bogdanm 13:0645d8841f51 516 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
bogdanm 13:0645d8841f51 517
bogdanm 13:0645d8841f51 518 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
bogdanm 13:0645d8841f51 519 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
bogdanm 13:0645d8841f51 520
bogdanm 13:0645d8841f51 521 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
bogdanm 13:0645d8841f51 522 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
bogdanm 13:0645d8841f51 523
bogdanm 13:0645d8841f51 524 /* MPU Region Attribute and Size Register */
bogdanm 13:0645d8841f51 525 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
bogdanm 13:0645d8841f51 526 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
bogdanm 13:0645d8841f51 527
bogdanm 13:0645d8841f51 528 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
bogdanm 13:0645d8841f51 529 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
bogdanm 13:0645d8841f51 530
bogdanm 13:0645d8841f51 531 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
bogdanm 13:0645d8841f51 532 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
bogdanm 13:0645d8841f51 533
bogdanm 13:0645d8841f51 534 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
bogdanm 13:0645d8841f51 535 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
bogdanm 13:0645d8841f51 536
bogdanm 13:0645d8841f51 537 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
bogdanm 13:0645d8841f51 538 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
bogdanm 13:0645d8841f51 539
bogdanm 13:0645d8841f51 540 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
bogdanm 13:0645d8841f51 541 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
bogdanm 13:0645d8841f51 542
bogdanm 13:0645d8841f51 543 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
bogdanm 13:0645d8841f51 544 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
bogdanm 13:0645d8841f51 545
bogdanm 13:0645d8841f51 546 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
bogdanm 13:0645d8841f51 547 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
bogdanm 13:0645d8841f51 548
bogdanm 13:0645d8841f51 549 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
bogdanm 13:0645d8841f51 550 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
bogdanm 13:0645d8841f51 551
bogdanm 13:0645d8841f51 552 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
bogdanm 13:0645d8841f51 553 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
bogdanm 13:0645d8841f51 554
bogdanm 13:0645d8841f51 555 /*@} end of group CMSIS_MPU */
bogdanm 13:0645d8841f51 556 #endif
bogdanm 13:0645d8841f51 557
bogdanm 13:0645d8841f51 558
bogdanm 13:0645d8841f51 559 /** \ingroup CMSIS_core_register
bogdanm 13:0645d8841f51 560 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
bogdanm 13:0645d8841f51 561 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
bogdanm 13:0645d8841f51 562 are only accessible over DAP and not via processor. Therefore
bogdanm 13:0645d8841f51 563 they are not covered by the Cortex-M0 header file.
bogdanm 13:0645d8841f51 564 @{
bogdanm 13:0645d8841f51 565 */
bogdanm 13:0645d8841f51 566 /*@} end of group CMSIS_CoreDebug */
bogdanm 13:0645d8841f51 567
bogdanm 13:0645d8841f51 568
bogdanm 13:0645d8841f51 569 /** \ingroup CMSIS_core_register
bogdanm 13:0645d8841f51 570 \defgroup CMSIS_core_base Core Definitions
bogdanm 13:0645d8841f51 571 \brief Definitions for base addresses, unions, and structures.
bogdanm 13:0645d8841f51 572 @{
bogdanm 13:0645d8841f51 573 */
bogdanm 13:0645d8841f51 574
bogdanm 13:0645d8841f51 575 /* Memory mapping of Cortex-M0+ Hardware */
bogdanm 13:0645d8841f51 576 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
bogdanm 13:0645d8841f51 577 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
bogdanm 13:0645d8841f51 578 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
bogdanm 13:0645d8841f51 579 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
bogdanm 13:0645d8841f51 580
bogdanm 13:0645d8841f51 581 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
bogdanm 13:0645d8841f51 582 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
bogdanm 13:0645d8841f51 583 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
bogdanm 13:0645d8841f51 584
bogdanm 13:0645d8841f51 585 #if (__MPU_PRESENT == 1)
bogdanm 13:0645d8841f51 586 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
bogdanm 13:0645d8841f51 587 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
bogdanm 13:0645d8841f51 588 #endif
bogdanm 13:0645d8841f51 589
bogdanm 13:0645d8841f51 590 /*@} */
bogdanm 13:0645d8841f51 591
bogdanm 13:0645d8841f51 592
bogdanm 13:0645d8841f51 593
bogdanm 13:0645d8841f51 594 /*******************************************************************************
bogdanm 13:0645d8841f51 595 * Hardware Abstraction Layer
bogdanm 13:0645d8841f51 596 Core Function Interface contains:
bogdanm 13:0645d8841f51 597 - Core NVIC Functions
bogdanm 13:0645d8841f51 598 - Core SysTick Functions
bogdanm 13:0645d8841f51 599 - Core Register Access Functions
bogdanm 13:0645d8841f51 600 ******************************************************************************/
bogdanm 13:0645d8841f51 601 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
bogdanm 13:0645d8841f51 602 */
bogdanm 13:0645d8841f51 603
bogdanm 13:0645d8841f51 604
bogdanm 13:0645d8841f51 605
bogdanm 13:0645d8841f51 606 /* ########################## NVIC functions #################################### */
bogdanm 13:0645d8841f51 607 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 13:0645d8841f51 608 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
bogdanm 13:0645d8841f51 609 \brief Functions that manage interrupts and exceptions via the NVIC.
bogdanm 13:0645d8841f51 610 @{
bogdanm 13:0645d8841f51 611 */
bogdanm 13:0645d8841f51 612
bogdanm 13:0645d8841f51 613 /* Interrupt Priorities are WORD accessible only under ARMv6M */
bogdanm 13:0645d8841f51 614 /* The following MACROS handle generation of the register offset and byte masks */
bogdanm 13:0645d8841f51 615 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
bogdanm 13:0645d8841f51 616 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
bogdanm 13:0645d8841f51 617 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
bogdanm 13:0645d8841f51 618
bogdanm 13:0645d8841f51 619
bogdanm 13:0645d8841f51 620 /** \brief Enable External Interrupt
bogdanm 13:0645d8841f51 621
bogdanm 13:0645d8841f51 622 The function enables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 13:0645d8841f51 623
bogdanm 13:0645d8841f51 624 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 13:0645d8841f51 625 */
bogdanm 13:0645d8841f51 626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 13:0645d8841f51 627 {
bogdanm 13:0645d8841f51 628 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
bogdanm 13:0645d8841f51 629 }
bogdanm 13:0645d8841f51 630
bogdanm 13:0645d8841f51 631
bogdanm 13:0645d8841f51 632 /** \brief Disable External Interrupt
bogdanm 13:0645d8841f51 633
bogdanm 13:0645d8841f51 634 The function disables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 13:0645d8841f51 635
bogdanm 13:0645d8841f51 636 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 13:0645d8841f51 637 */
bogdanm 13:0645d8841f51 638 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 13:0645d8841f51 639 {
bogdanm 13:0645d8841f51 640 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
bogdanm 13:0645d8841f51 641 }
bogdanm 13:0645d8841f51 642
bogdanm 13:0645d8841f51 643
bogdanm 13:0645d8841f51 644 /** \brief Get Pending Interrupt
bogdanm 13:0645d8841f51 645
bogdanm 13:0645d8841f51 646 The function reads the pending register in the NVIC and returns the pending bit
bogdanm 13:0645d8841f51 647 for the specified interrupt.
bogdanm 13:0645d8841f51 648
bogdanm 13:0645d8841f51 649 \param [in] IRQn Interrupt number.
bogdanm 13:0645d8841f51 650
bogdanm 13:0645d8841f51 651 \return 0 Interrupt status is not pending.
bogdanm 13:0645d8841f51 652 \return 1 Interrupt status is pending.
bogdanm 13:0645d8841f51 653 */
bogdanm 13:0645d8841f51 654 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
bogdanm 13:0645d8841f51 655 {
bogdanm 13:0645d8841f51 656 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
bogdanm 13:0645d8841f51 657 }
bogdanm 13:0645d8841f51 658
bogdanm 13:0645d8841f51 659
bogdanm 13:0645d8841f51 660 /** \brief Set Pending Interrupt
bogdanm 13:0645d8841f51 661
bogdanm 13:0645d8841f51 662 The function sets the pending bit of an external interrupt.
bogdanm 13:0645d8841f51 663
bogdanm 13:0645d8841f51 664 \param [in] IRQn Interrupt number. Value cannot be negative.
bogdanm 13:0645d8841f51 665 */
bogdanm 13:0645d8841f51 666 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
bogdanm 13:0645d8841f51 667 {
bogdanm 13:0645d8841f51 668 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
bogdanm 13:0645d8841f51 669 }
bogdanm 13:0645d8841f51 670
bogdanm 13:0645d8841f51 671
bogdanm 13:0645d8841f51 672 /** \brief Clear Pending Interrupt
bogdanm 13:0645d8841f51 673
bogdanm 13:0645d8841f51 674 The function clears the pending bit of an external interrupt.
bogdanm 13:0645d8841f51 675
bogdanm 13:0645d8841f51 676 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 13:0645d8841f51 677 */
bogdanm 13:0645d8841f51 678 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
bogdanm 13:0645d8841f51 679 {
bogdanm 13:0645d8841f51 680 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
bogdanm 13:0645d8841f51 681 }
bogdanm 13:0645d8841f51 682
bogdanm 13:0645d8841f51 683
bogdanm 13:0645d8841f51 684 /** \brief Set Interrupt Priority
bogdanm 13:0645d8841f51 685
bogdanm 13:0645d8841f51 686 The function sets the priority of an interrupt.
bogdanm 13:0645d8841f51 687
bogdanm 13:0645d8841f51 688 \note The priority cannot be set for every core interrupt.
bogdanm 13:0645d8841f51 689
bogdanm 13:0645d8841f51 690 \param [in] IRQn Interrupt number.
bogdanm 13:0645d8841f51 691 \param [in] priority Priority to set.
bogdanm 13:0645d8841f51 692 */
bogdanm 13:0645d8841f51 693 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
bogdanm 13:0645d8841f51 694 {
bogdanm 13:0645d8841f51 695 if(IRQn < 0) {
bogdanm 13:0645d8841f51 696 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
bogdanm 13:0645d8841f51 697 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
bogdanm 13:0645d8841f51 698 else {
bogdanm 13:0645d8841f51 699 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
bogdanm 13:0645d8841f51 700 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
bogdanm 13:0645d8841f51 701 }
bogdanm 13:0645d8841f51 702
bogdanm 13:0645d8841f51 703
bogdanm 13:0645d8841f51 704 /** \brief Get Interrupt Priority
bogdanm 13:0645d8841f51 705
bogdanm 13:0645d8841f51 706 The function reads the priority of an interrupt. The interrupt
bogdanm 13:0645d8841f51 707 number can be positive to specify an external (device specific)
bogdanm 13:0645d8841f51 708 interrupt, or negative to specify an internal (core) interrupt.
bogdanm 13:0645d8841f51 709
bogdanm 13:0645d8841f51 710
bogdanm 13:0645d8841f51 711 \param [in] IRQn Interrupt number.
bogdanm 13:0645d8841f51 712 \return Interrupt Priority. Value is aligned automatically to the implemented
bogdanm 13:0645d8841f51 713 priority bits of the microcontroller.
bogdanm 13:0645d8841f51 714 */
bogdanm 13:0645d8841f51 715 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
bogdanm 13:0645d8841f51 716 {
bogdanm 13:0645d8841f51 717
bogdanm 13:0645d8841f51 718 if(IRQn < 0) {
bogdanm 13:0645d8841f51 719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
bogdanm 13:0645d8841f51 720 else {
bogdanm 13:0645d8841f51 721 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
bogdanm 13:0645d8841f51 722 }
bogdanm 13:0645d8841f51 723
bogdanm 13:0645d8841f51 724
bogdanm 13:0645d8841f51 725 /** \brief System Reset
bogdanm 13:0645d8841f51 726
bogdanm 13:0645d8841f51 727 The function initiates a system reset request to reset the MCU.
bogdanm 13:0645d8841f51 728 */
bogdanm 13:0645d8841f51 729 __STATIC_INLINE void NVIC_SystemReset(void)
bogdanm 13:0645d8841f51 730 {
bogdanm 13:0645d8841f51 731 __DSB(); /* Ensure all outstanding memory accesses included
bogdanm 13:0645d8841f51 732 buffered write are completed before reset */
bogdanm 13:0645d8841f51 733 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
bogdanm 13:0645d8841f51 734 SCB_AIRCR_SYSRESETREQ_Msk);
bogdanm 13:0645d8841f51 735 __DSB(); /* Ensure completion of memory access */
bogdanm 13:0645d8841f51 736 while(1); /* wait until reset */
bogdanm 13:0645d8841f51 737 }
bogdanm 13:0645d8841f51 738
bogdanm 13:0645d8841f51 739 /*@} end of CMSIS_Core_NVICFunctions */
bogdanm 13:0645d8841f51 740
bogdanm 13:0645d8841f51 741
bogdanm 13:0645d8841f51 742
bogdanm 13:0645d8841f51 743 /* ################################## SysTick function ############################################ */
bogdanm 13:0645d8841f51 744 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 13:0645d8841f51 745 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
bogdanm 13:0645d8841f51 746 \brief Functions that configure the System.
bogdanm 13:0645d8841f51 747 @{
bogdanm 13:0645d8841f51 748 */
bogdanm 13:0645d8841f51 749
bogdanm 13:0645d8841f51 750 #if (__Vendor_SysTickConfig == 0)
bogdanm 13:0645d8841f51 751
bogdanm 13:0645d8841f51 752 /** \brief System Tick Configuration
bogdanm 13:0645d8841f51 753
bogdanm 13:0645d8841f51 754 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
bogdanm 13:0645d8841f51 755 Counter is in free running mode to generate periodic interrupts.
bogdanm 13:0645d8841f51 756
bogdanm 13:0645d8841f51 757 \param [in] ticks Number of ticks between two interrupts.
bogdanm 13:0645d8841f51 758
bogdanm 13:0645d8841f51 759 \return 0 Function succeeded.
bogdanm 13:0645d8841f51 760 \return 1 Function failed.
bogdanm 13:0645d8841f51 761
bogdanm 13:0645d8841f51 762 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
bogdanm 13:0645d8841f51 763 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
bogdanm 13:0645d8841f51 764 must contain a vendor-specific implementation of this function.
bogdanm 13:0645d8841f51 765
bogdanm 13:0645d8841f51 766 */
bogdanm 13:0645d8841f51 767 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
bogdanm 13:0645d8841f51 768 {
bogdanm 13:0645d8841f51 769 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
bogdanm 13:0645d8841f51 770
bogdanm 13:0645d8841f51 771 SysTick->LOAD = ticks - 1; /* set reload register */
bogdanm 13:0645d8841f51 772 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
bogdanm 13:0645d8841f51 773 SysTick->VAL = 0; /* Load the SysTick Counter Value */
bogdanm 13:0645d8841f51 774 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
bogdanm 13:0645d8841f51 775 SysTick_CTRL_TICKINT_Msk |
bogdanm 13:0645d8841f51 776 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
bogdanm 13:0645d8841f51 777 return (0); /* Function successful */
bogdanm 13:0645d8841f51 778 }
bogdanm 13:0645d8841f51 779
bogdanm 13:0645d8841f51 780 #endif
bogdanm 13:0645d8841f51 781
bogdanm 13:0645d8841f51 782 /*@} end of CMSIS_Core_SysTickFunctions */
bogdanm 13:0645d8841f51 783
bogdanm 13:0645d8841f51 784
bogdanm 13:0645d8841f51 785
bogdanm 13:0645d8841f51 786
bogdanm 13:0645d8841f51 787 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
bogdanm 13:0645d8841f51 788
bogdanm 13:0645d8841f51 789 #endif /* __CMSIS_GENERIC */
bogdanm 13:0645d8841f51 790
bogdanm 13:0645d8841f51 791 #ifdef __cplusplus
bogdanm 13:0645d8841f51 792 }
bogdanm 13:0645d8841f51 793 #endif