lpc17xx_gpdma.c

00001 /***********************************************************************//**
00002  * @file        lpc17xx_gpdma.c
00003  * @brief        Contains all functions support for GPDMA firmware library on LPC17xx
00004  * @version        2.0
00005  * @date        21. May. 2010
00006  * @author        NXP MCU SW Application Team
00007  **************************************************************************
00008  * Software that is described herein is for illustrative purposes only
00009  * which provides customers with programming information regarding the
00010  * products. This software is supplied "AS IS" without any warranties.
00011  * NXP Semiconductors assumes no responsibility or liability for the
00012  * use of the software, conveys no license or title under any patent,
00013  * copyright, or mask work right to the product. NXP Semiconductors
00014  * reserves the right to make changes in the software without
00015  * notification. NXP Semiconductors also make no representation or
00016  * warranty that such application will be suitable for the specified
00017  * use without further testing or modification.
00018  **********************************************************************/
00019 
00020 /* Peripheral group ----------------------------------------------------------- */
00021 /** @addtogroup GPDMA
00022  * @{
00023  */
00024 
00025 /* Includes ------------------------------------------------------------------- */
00026 #include "lpc17xx_gpdma.h"
00027 #include "lpc17xx_clkpwr.h"
00028 
00029 /* If this source file built with example, the LPC17xx FW library configuration
00030  * file in each example directory ("lpc17xx_libcfg.h") must be included,
00031  * otherwise the default FW library configuration file must be included instead
00032  */
00033 #include "lpc17xx_libcfg.h"
00034 
00035 #ifdef _GPDMA
00036 
00037 
00038 /* Private Variables ---------------------------------------------------------- */
00039 /** @defgroup GPDMA_Private_Variables GPDMA Private Variables
00040  * @{
00041  */
00042 
00043 /**
00044  * @brief Lookup Table of Connection Type matched with
00045  * Peripheral Data (FIFO) register base address
00046  */
00047 #ifdef __IAR_SYSTEMS_ICC__
00048 volatile const void *GPDMA_LUTPerAddr[] = {
00049         (&LPC_SSP0->DR),                // SSP0 Tx
00050         (&LPC_SSP0->DR),                // SSP0 Rx
00051         (&LPC_SSP1->DR),                // SSP1 Tx
00052         (&LPC_SSP1->DR),                // SSP1 Rx
00053         (&LPC_ADC->ADGDR),            // ADC
00054         (&LPC_I2S->I2STXFIFO),         // I2S Tx
00055         (&LPC_I2S->I2SRXFIFO),         // I2S Rx
00056         (&LPC_DAC->DACR),                // DAC
00057         (&LPC_UART0->/*RBTHDLR.*/THR),    // UART0 Tx
00058         (&LPC_UART0->/*RBTHDLR.*/RBR),    // UART0 Rx
00059         (&LPC_UART1->/*RBTHDLR.*/THR),    // UART1 Tx
00060         (&LPC_UART1->/*RBTHDLR.*/RBR),    // UART1 Rx
00061         (&LPC_UART2->/*RBTHDLR.*/THR),    // UART2 Tx
00062         (&LPC_UART2->/*RBTHDLR.*/RBR),    // UART2 Rx
00063         (&LPC_UART3->/*RBTHDLR.*/THR),    // UART3 Tx
00064         (&LPC_UART3->/*RBTHDLR.*/RBR),    // UART3 Rx
00065         (&LPC_TIM0->MR0),                // MAT0.0
00066         (&LPC_TIM0->MR1),                // MAT0.1
00067         (&LPC_TIM1->MR0),                // MAT1.0
00068         (&LPC_TIM1->MR1),                // MAT1.1
00069         (&LPC_TIM2->MR0),                // MAT2.0
00070         (&LPC_TIM2->MR1),                // MAT2.1
00071         (&LPC_TIM3->MR0),                // MAT3.0
00072         (&LPC_TIM3->MR1),                // MAT3.1
00073 };
00074 #else
00075 const uint32_t GPDMA_LUTPerAddr[] = {
00076         ((uint32_t)&LPC_SSP0->DR),                // SSP0 Tx
00077         ((uint32_t)&LPC_SSP0->DR),                // SSP0 Rx
00078         ((uint32_t)&LPC_SSP1->DR),                // SSP1 Tx
00079         ((uint32_t)&LPC_SSP1->DR),                // SSP1 Rx
00080         ((uint32_t)&LPC_ADC->ADGDR),            // ADC
00081         ((uint32_t)&LPC_I2S->I2STXFIFO),         // I2S Tx
00082         ((uint32_t)&LPC_I2S->I2SRXFIFO),         // I2S Rx
00083         ((uint32_t)&LPC_DAC->DACR),                // DAC
00084         ((uint32_t)&LPC_UART0->/*RBTHDLR.*/THR),    // UART0 Tx
00085         ((uint32_t)&LPC_UART0->/*RBTHDLR.*/RBR),    // UART0 Rx
00086         ((uint32_t)&LPC_UART1->/*RBTHDLR.*/THR),    // UART1 Tx
00087         ((uint32_t)&LPC_UART1->/*RBTHDLR.*/RBR),    // UART1 Rx
00088         ((uint32_t)&LPC_UART2->/*RBTHDLR.*/THR),    // UART2 Tx
00089         ((uint32_t)&LPC_UART2->/*RBTHDLR.*/RBR),    // UART2 Rx
00090         ((uint32_t)&LPC_UART3->/*RBTHDLR.*/THR),    // UART3 Tx
00091         ((uint32_t)&LPC_UART3->/*RBTHDLR.*/RBR),    // UART3 Rx
00092         ((uint32_t)&LPC_TIM0->MR0),                // MAT0.0
00093         ((uint32_t)&LPC_TIM0->MR1),                // MAT0.1
00094         ((uint32_t)&LPC_TIM1->MR0),                // MAT1.0
00095         ((uint32_t)&LPC_TIM1->MR1),                // MAT1.1
00096         ((uint32_t)&LPC_TIM2->MR0),                // MAT2.0
00097         ((uint32_t)&LPC_TIM2->MR1),                // MAT2.1
00098         ((uint32_t)&LPC_TIM3->MR0),                // MAT3.0
00099         ((uint32_t)&LPC_TIM3->MR1),                // MAT3.1
00100 };
00101 #endif
00102 /**
00103  * @brief Lookup Table of GPDMA Channel Number matched with
00104  * GPDMA channel pointer
00105  */
00106 const LPC_GPDMACH_TypeDef *pGPDMACh[8] = {
00107         LPC_GPDMACH0,    // GPDMA Channel 0
00108         LPC_GPDMACH1,    // GPDMA Channel 1
00109         LPC_GPDMACH2,    // GPDMA Channel 2
00110         LPC_GPDMACH3,    // GPDMA Channel 3
00111         LPC_GPDMACH4,    // GPDMA Channel 4
00112         LPC_GPDMACH5,    // GPDMA Channel 5
00113         LPC_GPDMACH6,    // GPDMA Channel 6
00114         LPC_GPDMACH7,    // GPDMA Channel 7
00115 };
00116 /**
00117  * @brief Optimized Peripheral Source and Destination burst size
00118  */
00119 const uint8_t GPDMA_LUTPerBurst[] = {
00120         GPDMA_BSIZE_4,                // SSP0 Tx
00121         GPDMA_BSIZE_4,                // SSP0 Rx
00122         GPDMA_BSIZE_4,                // SSP1 Tx
00123         GPDMA_BSIZE_4,                // SSP1 Rx
00124         GPDMA_BSIZE_4,                // ADC
00125         GPDMA_BSIZE_32,             // I2S channel 0
00126         GPDMA_BSIZE_32,             // I2S channel 1
00127         GPDMA_BSIZE_1,                // DAC
00128         GPDMA_BSIZE_1,                // UART0 Tx
00129         GPDMA_BSIZE_1,                // UART0 Rx
00130         GPDMA_BSIZE_1,                // UART1 Tx
00131         GPDMA_BSIZE_1,                // UART1 Rx
00132         GPDMA_BSIZE_1,                // UART2 Tx
00133         GPDMA_BSIZE_1,                // UART2 Rx
00134         GPDMA_BSIZE_1,                // UART3 Tx
00135         GPDMA_BSIZE_1,                // UART3 Rx
00136         GPDMA_BSIZE_1,                // MAT0.0
00137         GPDMA_BSIZE_1,                // MAT0.1
00138         GPDMA_BSIZE_1,                // MAT1.0
00139         GPDMA_BSIZE_1,                // MAT1.1
00140         GPDMA_BSIZE_1,                // MAT2.0
00141         GPDMA_BSIZE_1,                // MAT2.1
00142         GPDMA_BSIZE_1,                // MAT3.0
00143         GPDMA_BSIZE_1,                // MAT3.1
00144 };
00145 /**
00146  * @brief Optimized Peripheral Source and Destination transfer width
00147  */
00148 const uint8_t GPDMA_LUTPerWid[] = {
00149         GPDMA_WIDTH_BYTE,                // SSP0 Tx
00150         GPDMA_WIDTH_BYTE,                // SSP0 Rx
00151         GPDMA_WIDTH_BYTE,                // SSP1 Tx
00152         GPDMA_WIDTH_BYTE,                // SSP1 Rx
00153         GPDMA_WIDTH_WORD,                // ADC
00154         GPDMA_WIDTH_WORD,                 // I2S channel 0
00155         GPDMA_WIDTH_WORD,                 // I2S channel 1
00156         GPDMA_WIDTH_BYTE,                // DAC
00157         GPDMA_WIDTH_BYTE,                // UART0 Tx
00158         GPDMA_WIDTH_BYTE,                // UART0 Rx
00159         GPDMA_WIDTH_BYTE,                // UART1 Tx
00160         GPDMA_WIDTH_BYTE,                // UART1 Rx
00161         GPDMA_WIDTH_BYTE,                // UART2 Tx
00162         GPDMA_WIDTH_BYTE,                // UART2 Rx
00163         GPDMA_WIDTH_BYTE,                // UART3 Tx
00164         GPDMA_WIDTH_BYTE,                // UART3 Rx
00165         GPDMA_WIDTH_WORD,                // MAT0.0
00166         GPDMA_WIDTH_WORD,                // MAT0.1
00167         GPDMA_WIDTH_WORD,                // MAT1.0
00168         GPDMA_WIDTH_WORD,                // MAT1.1
00169         GPDMA_WIDTH_WORD,                // MAT2.0
00170         GPDMA_WIDTH_WORD,                // MAT2.1
00171         GPDMA_WIDTH_WORD,                // MAT3.0
00172         GPDMA_WIDTH_WORD,                // MAT3.1
00173 };
00174 
00175 /**
00176  * @}
00177  */
00178 
00179 /* Public Functions ----------------------------------------------------------- */
00180 /** @addtogroup GPDMA_Public_Functions
00181  * @{
00182  */
00183 
00184 /********************************************************************//**
00185  * @brief         Initialize GPDMA controller
00186  * @param         None
00187  * @return         None
00188  *********************************************************************/
00189 void GPDMA_Init(void)
00190 {
00191     /* Enable GPDMA clock */
00192     CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCGPDMA, ENABLE);
00193 
00194     // Reset all channel configuration register
00195     LPC_GPDMACH0->DMACCConfig = 0;
00196     LPC_GPDMACH1->DMACCConfig = 0;
00197     LPC_GPDMACH2->DMACCConfig = 0;
00198     LPC_GPDMACH3->DMACCConfig = 0;
00199     LPC_GPDMACH4->DMACCConfig = 0;
00200     LPC_GPDMACH5->DMACCConfig = 0;
00201     LPC_GPDMACH6->DMACCConfig = 0;
00202     LPC_GPDMACH7->DMACCConfig = 0;
00203 
00204     /* Clear all DMA interrupt and error flag */
00205     LPC_GPDMA->DMACIntTCClear = 0xFF;
00206     LPC_GPDMA->DMACIntErrClr = 0xFF;
00207 }
00208 
00209 /********************************************************************//**
00210  * @brief         Setup GPDMA channel peripheral according to the specified
00211  *               parameters in the GPDMAChannelConfig.
00212  * @param[in]    GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type
00213  *                                     structure that contains the configuration
00214  *                                     information for the specified GPDMA channel peripheral.
00215  * @return        ERROR if selected channel is enabled before
00216  *                 or SUCCESS if channel is configured successfully
00217  *********************************************************************/
00218 Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig)
00219 {
00220     LPC_GPDMACH_TypeDef *pDMAch;
00221     uint32_t tmp1, tmp2;
00222 
00223     if (LPC_GPDMA->DMACEnbldChns & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) {
00224         // This channel is enabled, return ERROR, need to release this channel first
00225         return ERROR;
00226     }
00227 
00228     // Get Channel pointer
00229     pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum];
00230 
00231     // Reset the Interrupt status
00232     LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum);
00233     LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum);
00234 
00235     // Clear DMA configure
00236     pDMAch->DMACCControl = 0x00;
00237     pDMAch->DMACCConfig = 0x00;
00238 
00239     /* Assign Linker List Item value */
00240     pDMAch->DMACCLLI = GPDMAChannelConfig->DMALLI;
00241 
00242     /* Set value to Channel Control Registers */
00243     switch (GPDMAChannelConfig->TransferType)
00244     {
00245     // Memory to memory
00246     case GPDMA_TRANSFERTYPE_M2M:
00247         // Assign physical source and destination address
00248         pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr;
00249         pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr;
00250         pDMAch->DMACCControl
00251                 = GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \
00252                         | GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \
00253                         | GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \
00254                         | GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \
00255                         | GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \
00256                         | GPDMA_DMACCxControl_SI \
00257                         | GPDMA_DMACCxControl_DI \
00258                         | GPDMA_DMACCxControl_I;
00259         break;
00260     // Memory to peripheral
00261     case GPDMA_TRANSFERTYPE_M2P:
00262         // Assign physical source
00263         pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr;
00264         // Assign peripheral destination address
00265         pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
00266         pDMAch->DMACCControl
00267                 = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
00268                         | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
00269                         | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
00270                         | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
00271                         | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
00272                         | GPDMA_DMACCxControl_SI \
00273                         | GPDMA_DMACCxControl_I;
00274         break;
00275     // Peripheral to memory
00276     case GPDMA_TRANSFERTYPE_P2M:
00277         // Assign peripheral source address
00278         pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
00279         // Assign memory destination address
00280         pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr;
00281         pDMAch->DMACCControl
00282                 = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
00283                         | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
00284                         | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
00285                         | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
00286                         | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
00287                         | GPDMA_DMACCxControl_DI \
00288                         | GPDMA_DMACCxControl_I;
00289         break;
00290     // Peripheral to peripheral
00291     case GPDMA_TRANSFERTYPE_P2P:
00292         // Assign peripheral source address
00293         pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
00294         // Assign peripheral destination address
00295         pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
00296         pDMAch->DMACCControl
00297                 = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
00298                         | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
00299                         | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
00300                         | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
00301                         | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
00302                         | GPDMA_DMACCxControl_I;
00303         break;
00304     // Do not support any more transfer type, return ERROR
00305     default:
00306         return ERROR;
00307     }
00308 
00309     /* Re-Configure DMA Request Select for source peripheral */
00310     if (GPDMAChannelConfig->SrcConn > 15)
00311     {
00312         DMAREQSEL |= (1<<(GPDMAChannelConfig->SrcConn - 16));
00313     } else {
00314         DMAREQSEL &= ~(1<<(GPDMAChannelConfig->SrcConn - 8));
00315     }
00316 
00317     /* Re-Configure DMA Request Select for Destination peripheral */
00318     if (GPDMAChannelConfig->DstConn > 15)
00319     {
00320         DMAREQSEL |= (1<<(GPDMAChannelConfig->DstConn - 16));
00321     } else {
00322         DMAREQSEL &= ~(1<<(GPDMAChannelConfig->DstConn - 8));
00323     }
00324 
00325     /* Enable DMA channels, little endian */
00326     LPC_GPDMA->DMACConfig = GPDMA_DMACConfig_E;
00327     while (!(LPC_GPDMA->DMACConfig & GPDMA_DMACConfig_E));
00328 
00329     // Calculate absolute value for Connection number
00330     tmp1 = GPDMAChannelConfig->SrcConn;
00331     tmp1 = ((tmp1 > 15) ? (tmp1 - 8) : tmp1);
00332     tmp2 = GPDMAChannelConfig->DstConn;
00333     tmp2 = ((tmp2 > 15) ? (tmp2 - 8) : tmp2);
00334 
00335     // Configure DMA Channel, enable Error Counter and Terminate counter
00336     pDMAch->DMACCConfig = GPDMA_DMACCxConfig_IE | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ \
00337         | GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \
00338         | GPDMA_DMACCxConfig_SrcPeripheral(tmp1) \
00339         | GPDMA_DMACCxConfig_DestPeripheral(tmp2);
00340 
00341     return SUCCESS;
00342 }
00343 
00344 
00345 /*********************************************************************//**
00346  * @brief        Enable/Disable DMA channel
00347  * @param[in]    channelNum    GPDMA channel, should be in range from 0 to 7
00348  * @param[in]    NewState    New State of this command, should be:
00349  *                     - ENABLE.
00350  *                     - DISABLE.
00351  * @return        None
00352  **********************************************************************/
00353 void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState)
00354 {
00355     LPC_GPDMACH_TypeDef *pDMAch;
00356 
00357     // Get Channel pointer
00358     pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[channelNum];
00359 
00360     if (NewState == ENABLE) {
00361         pDMAch->DMACCConfig |= GPDMA_DMACCxConfig_E;
00362     } else {
00363         pDMAch->DMACCConfig &= ~GPDMA_DMACCxConfig_E;
00364     }
00365 }
00366 /*********************************************************************//**
00367  * @brief        Check if corresponding channel does have an active interrupt
00368  *                 request or not
00369  * @param[in]    type        type of status, should be:
00370  *                     - GPDMA_STAT_INT:         GPDMA Interrupt Status
00371  *                     - GPDMA_STAT_INTTC:     GPDMA Interrupt Terminal Count Request Status
00372  *                     - GPDMA_STAT_INTERR:    GPDMA Interrupt Error Status
00373  *                     - GPDMA_STAT_RAWINTTC:    GPDMA Raw Interrupt Terminal Count Status
00374  *                     - GPDMA_STAT_RAWINTERR:    GPDMA Raw Error Interrupt Status
00375  *                     - GPDMA_STAT_ENABLED_CH:GPDMA Enabled Channel Status
00376  * @param[in]    channel        GPDMA channel, should be in range from 0 to 7
00377  * @return        IntStatus    status of DMA channel interrupt after masking
00378  *                 Should be:
00379  *                     - SET: the corresponding channel has no active interrupt request
00380  *                     - RESET: the corresponding channel does have an active interrupt request
00381  **********************************************************************/
00382 IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel)
00383 {
00384     CHECK_PARAM(PARAM_GPDMA_STAT(type));
00385     CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel));
00386 
00387     switch (type)
00388     {
00389     case GPDMA_STAT_INT: //check status of DMA channel interrupts
00390         if (LPC_GPDMA->DMACIntStat & (GPDMA_DMACIntStat_Ch(channel)))
00391             return SET;
00392         return RESET;
00393     case GPDMA_STAT_INTTC: // check terminal count interrupt request status for DMA
00394         if (LPC_GPDMA->DMACIntTCStat & GPDMA_DMACIntTCStat_Ch(channel))
00395             return SET;
00396         return RESET;
00397     case GPDMA_STAT_INTERR: //check interrupt status for DMA channels
00398         if (LPC_GPDMA->DMACIntErrStat & GPDMA_DMACIntTCClear_Ch(channel))
00399             return SET;
00400         return RESET;
00401     case GPDMA_STAT_RAWINTTC: //check status of the terminal count interrupt for DMA channels
00402         if (LPC_GPDMA->DMACRawIntErrStat & GPDMA_DMACRawIntTCStat_Ch(channel))
00403             return SET;
00404         return RESET;
00405     case GPDMA_STAT_RAWINTERR: //check status of the error interrupt for DMA channels
00406         if (LPC_GPDMA->DMACRawIntTCStat & GPDMA_DMACRawIntErrStat_Ch(channel))
00407             return SET;
00408         return RESET;
00409     default: //check enable status for DMA channels
00410         if (LPC_GPDMA->DMACEnbldChns & GPDMA_DMACEnbldChns_Ch(channel))
00411             return SET;
00412         return RESET;
00413     }
00414 }
00415 
00416 /*********************************************************************//**
00417  * @brief        Clear one or more interrupt requests on DMA channels
00418  * @param[in]    type        type of interrupt request, should be:
00419  *                     - GPDMA_STATCLR_INTTC:     GPDMA Interrupt Terminal Count Request Clear
00420  *                     - GPDMA_STATCLR_INTERR: GPDMA Interrupt Error Clear
00421  * @param[in]    channel        GPDMA channel, should be in range from 0 to 7
00422  * @return        None
00423  **********************************************************************/
00424 void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel)
00425 {
00426     CHECK_PARAM(PARAM_GPDMA_STATCLR(type));
00427     CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel));
00428 
00429     if (type == GPDMA_STATCLR_INTTC) // clears the terminal count interrupt request on DMA channel
00430         LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(channel);
00431     else // clear the error interrupt request
00432         LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(channel);
00433 }
00434 
00435 /**
00436  * @}
00437  */
00438 
00439 #endif /* _GPDMA */
00440 
00441 /**
00442  * @}
00443  */
00444 
00445 /* --------------------------------- End Of File ------------------------------ */
00446