Timothy Mulrooney / SX1272Liby

first draft

Dependents:   LoRaWAN-demo-72_tjm frdm_LoRa_Connect_Woodstream_Demo_tjm frdm_LoRa_Connect_Woodstream_Demo_jlc

Fork of SX1272Lib by Semtech

sx1272/sx1272.cpp@6:af0463c03b8b, 2016-08-09 (annotated)

Committer:
tmulrooney
Date:
Tue Aug 09 18:19:47 2016 +0000
Revision:
6:af0463c03b8b
Parent:
5:e6a3f05e4743 
update

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mluis 0:45c4f0364ca4 1 /*
mluis 0:45c4f0364ca4 2 / _____) _ | |
mluis 0:45c4f0364ca4 3 ( (____ _____ ____ _| |_ _____ ____| |__
mluis 0:45c4f0364ca4 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
mluis 0:45c4f0364ca4 5 _____) ) ____| | | || |_| ____( (___| | | |
mluis 0:45c4f0364ca4 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 0:45c4f0364ca4 7 (C) 2015 Semtech
mluis 0:45c4f0364ca4 8
mluis 0:45c4f0364ca4 9 Description: Actual implementation of a SX1272 radio, inherits Radio
mluis 0:45c4f0364ca4 10
mluis 0:45c4f0364ca4 11 License: Revised BSD License, see LICENSE.TXT file include in the project
mluis 0:45c4f0364ca4 12
mluis 0:45c4f0364ca4 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
mluis 0:45c4f0364ca4 14 */
mluis 0:45c4f0364ca4 15 #include "sx1272.h"
mluis 0:45c4f0364ca4 16
mluis 0:45c4f0364ca4 17 const FskBandwidth_t SX1272::FskBandwidths[] =
mluis 0:45c4f0364ca4 18 {
mluis 0:45c4f0364ca4 19 { 2600 , 0x17 },
mluis 0:45c4f0364ca4 20 { 3100 , 0x0F },
mluis 0:45c4f0364ca4 21 { 3900 , 0x07 },
mluis 0:45c4f0364ca4 22 { 5200 , 0x16 },
mluis 0:45c4f0364ca4 23 { 6300 , 0x0E },
mluis 0:45c4f0364ca4 24 { 7800 , 0x06 },
mluis 0:45c4f0364ca4 25 { 10400 , 0x15 },
mluis 0:45c4f0364ca4 26 { 12500 , 0x0D },
mluis 0:45c4f0364ca4 27 { 15600 , 0x05 },
mluis 0:45c4f0364ca4 28 { 20800 , 0x14 },
mluis 0:45c4f0364ca4 29 { 25000 , 0x0C },
mluis 0:45c4f0364ca4 30 { 31300 , 0x04 },
mluis 0:45c4f0364ca4 31 { 41700 , 0x13 },
mluis 0:45c4f0364ca4 32 { 50000 , 0x0B },
mluis 0:45c4f0364ca4 33 { 62500 , 0x03 },
mluis 0:45c4f0364ca4 34 { 83333 , 0x12 },
mluis 0:45c4f0364ca4 35 { 100000, 0x0A },
mluis 0:45c4f0364ca4 36 { 125000, 0x02 },
mluis 0:45c4f0364ca4 37 { 166700, 0x11 },
mluis 0:45c4f0364ca4 38 { 200000, 0x09 },
mluis 0:45c4f0364ca4 39 { 250000, 0x01 },
mluis 0:45c4f0364ca4 40 { 300000, 0x00 }, // Invalid Badwidth
mluis 0:45c4f0364ca4 41 };
mluis 0:45c4f0364ca4 42
mluis 0:45c4f0364ca4 43
mluis 0:45c4f0364ca4 44 SX1272::SX1272( RadioEvents_t *events,
mluis 0:45c4f0364ca4 45 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
mluis 0:45c4f0364ca4 46 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
mluis 0:45c4f0364ca4 47 : Radio( events ),
tmulrooney 3:73a1f904eaa5 48 // spi( mosi, miso, sclk ),
tmulrooney 3:73a1f904eaa5 49 // nss( nss ),
tmulrooney 5:e6a3f05e4743 50 // spi( PTD6, PTD7, PTD5 ),
tmulrooney 5:e6a3f05e4743 51 // nss( PTD4 ),
tmulrooney 5:e6a3f05e4743 52 spi( PTC6, PTC7, PTC5 ),
tmulrooney 5:e6a3f05e4743 53 nss( PTC4 ),
mluis 0:45c4f0364ca4 54 reset( reset ),
tmulrooney 3:73a1f904eaa5 55 // dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ),
tmulrooney 5:e6a3f05e4743 56 // dio0( PTC2 ), dio1( PTB1 ), dio2( PTC3 ), dio3( PTB0 ), dio4( PTC4 ), dio5( PTC1 ),
tmulrooney 5:e6a3f05e4743 57 dio0( PTC8 ), dio1( PTC9 ), dio2( PTC10), dio3( PTC11 ), dio4( PTD0 ), dio5( PTD1 ),
mluis 0:45c4f0364ca4 58 isRadioActive( false )
mluis 0:45c4f0364ca4 59 {
mluis 0:45c4f0364ca4 60 wait_ms( 10 );
mluis 0:45c4f0364ca4 61 this->rxTx = 0;
mluis 0:45c4f0364ca4 62 this->rxBuffer = new uint8_t[RX_BUFFER_SIZE];
mluis 0:45c4f0364ca4 63 currentOpMode = RF_OPMODE_STANDBY;
mluis 0:45c4f0364ca4 64
mluis 0:45c4f0364ca4 65 this->RadioEvents = events;
mluis 0:45c4f0364ca4 66
mluis 0:45c4f0364ca4 67 this->dioIrq = new DioIrqHandler[6];
mluis 0:45c4f0364ca4 68
mluis 0:45c4f0364ca4 69 this->dioIrq[0] = &SX1272::OnDio0Irq;
mluis 0:45c4f0364ca4 70 this->dioIrq[1] = &SX1272::OnDio1Irq;
mluis 0:45c4f0364ca4 71 this->dioIrq[2] = &SX1272::OnDio2Irq;
mluis 0:45c4f0364ca4 72 this->dioIrq[3] = &SX1272::OnDio3Irq;
mluis 0:45c4f0364ca4 73 this->dioIrq[4] = &SX1272::OnDio4Irq;
mluis 0:45c4f0364ca4 74 this->dioIrq[5] = NULL;
mluis 0:45c4f0364ca4 75
mluis 0:45c4f0364ca4 76 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 77 }
mluis 0:45c4f0364ca4 78
mluis 0:45c4f0364ca4 79 SX1272::~SX1272( )
mluis 0:45c4f0364ca4 80 {
mluis 0:45c4f0364ca4 81 delete this->rxBuffer;
mluis 0:45c4f0364ca4 82 delete this->dioIrq;
mluis 0:45c4f0364ca4 83 }
mluis 0:45c4f0364ca4 84
mluis 0:45c4f0364ca4 85 void SX1272::Init( RadioEvents_t *events )
mluis 0:45c4f0364ca4 86 {
mluis 0:45c4f0364ca4 87 this->RadioEvents = events;
mluis 0:45c4f0364ca4 88 }
mluis 0:45c4f0364ca4 89
mluis 0:45c4f0364ca4 90 RadioState SX1272::GetStatus( void )
mluis 0:45c4f0364ca4 91 {
mluis 0:45c4f0364ca4 92 return this->settings.State;
mluis 0:45c4f0364ca4 93 }
mluis 0:45c4f0364ca4 94
mluis 0:45c4f0364ca4 95 void SX1272::SetChannel( uint32_t freq )
mluis 0:45c4f0364ca4 96 {
mluis 0:45c4f0364ca4 97 this->settings.Channel = freq;
mluis 0:45c4f0364ca4 98 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
mluis 0:45c4f0364ca4 99 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
mluis 0:45c4f0364ca4 100 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
mluis 0:45c4f0364ca4 101 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
mluis 0:45c4f0364ca4 102 }
mluis 0:45c4f0364ca4 103
mluis 0:45c4f0364ca4 104 bool SX1272::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh )
mluis 0:45c4f0364ca4 105 {
mluis 0:45c4f0364ca4 106 int16_t rssi = 0;
mluis 0:45c4f0364ca4 107
mluis 0:45c4f0364ca4 108 SetModem( modem );
mluis 0:45c4f0364ca4 109
mluis 0:45c4f0364ca4 110 SetChannel( freq );
mluis 0:45c4f0364ca4 111
mluis 0:45c4f0364ca4 112 SetOpMode( RF_OPMODE_RECEIVER );
mluis 0:45c4f0364ca4 113
mluis 0:45c4f0364ca4 114 wait_ms( 1 );
mluis 0:45c4f0364ca4 115
mluis 0:45c4f0364ca4 116 rssi = GetRssi( modem );
mluis 0:45c4f0364ca4 117
mluis 0:45c4f0364ca4 118 Sleep( );
mluis 0:45c4f0364ca4 119
mluis 0:45c4f0364ca4 120 if( rssi > rssiThresh )
mluis 0:45c4f0364ca4 121 {
mluis 0:45c4f0364ca4 122 return false;
mluis 0:45c4f0364ca4 123 }
mluis 0:45c4f0364ca4 124 return true;
mluis 0:45c4f0364ca4 125 }
mluis 0:45c4f0364ca4 126
mluis 0:45c4f0364ca4 127 uint32_t SX1272::Random( void )
mluis 0:45c4f0364ca4 128 {
mluis 0:45c4f0364ca4 129 uint8_t i;
mluis 0:45c4f0364ca4 130 uint32_t rnd = 0;
mluis 0:45c4f0364ca4 131
mluis 0:45c4f0364ca4 132 /*
mluis 0:45c4f0364ca4 133 * Radio setup for random number generation
mluis 0:45c4f0364ca4 134 */
mluis 0:45c4f0364ca4 135 // Set LoRa modem ON
mluis 0:45c4f0364ca4 136 SetModem( MODEM_LORA );
mluis 0:45c4f0364ca4 137
mluis 0:45c4f0364ca4 138 // Disable LoRa modem interrupts
mluis 0:45c4f0364ca4 139 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 140 RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 141 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 142 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 143 RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 144 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 145 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 146 RFLR_IRQFLAGS_CADDETECTED );
mluis 0:45c4f0364ca4 147
mluis 0:45c4f0364ca4 148 // Set radio in continuous reception
mluis 0:45c4f0364ca4 149 SetOpMode( RF_OPMODE_RECEIVER );
mluis 0:45c4f0364ca4 150
mluis 0:45c4f0364ca4 151 for( i = 0; i < 32; i++ )
mluis 0:45c4f0364ca4 152 {
mluis 0:45c4f0364ca4 153 wait_ms( 1 );
mluis 0:45c4f0364ca4 154 // Unfiltered RSSI value reading. Only takes the LSB value
mluis 0:45c4f0364ca4 155 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
mluis 0:45c4f0364ca4 156 }
mluis 0:45c4f0364ca4 157
mluis 0:45c4f0364ca4 158 Sleep( );
mluis 0:45c4f0364ca4 159
mluis 0:45c4f0364ca4 160 return rnd;
mluis 0:45c4f0364ca4 161 }
mluis 0:45c4f0364ca4 162
mluis 0:45c4f0364ca4 163 /*!
mluis 0:45c4f0364ca4 164 * Returns the known FSK bandwidth registers value
mluis 0:45c4f0364ca4 165 *
mluis 0:45c4f0364ca4 166 * \param [IN] bandwidth Bandwidth value in Hz
mluis 0:45c4f0364ca4 167 * \retval regValue Bandwidth register value.
mluis 0:45c4f0364ca4 168 */
mluis 0:45c4f0364ca4 169 uint8_t SX1272::GetFskBandwidthRegValue( uint32_t bandwidth )
mluis 0:45c4f0364ca4 170 {
mluis 0:45c4f0364ca4 171 uint8_t i;
mluis 0:45c4f0364ca4 172
mluis 0:45c4f0364ca4 173 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
mluis 0:45c4f0364ca4 174 {
mluis 0:45c4f0364ca4 175 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
mluis 0:45c4f0364ca4 176 {
mluis 0:45c4f0364ca4 177 return FskBandwidths[i].RegValue;
mluis 0:45c4f0364ca4 178 }
mluis 0:45c4f0364ca4 179 }
mluis 0:45c4f0364ca4 180 // ERROR: Value not found
mluis 0:45c4f0364ca4 181 while( 1 );
mluis 0:45c4f0364ca4 182 }
mluis 0:45c4f0364ca4 183
mluis 0:45c4f0364ca4 184 void SX1272::SetRxConfig( RadioModems_t modem, uint32_t bandwidth,
mluis 0:45c4f0364ca4 185 uint32_t datarate, uint8_t coderate,
mluis 0:45c4f0364ca4 186 uint32_t bandwidthAfc, uint16_t preambleLen,
mluis 0:45c4f0364ca4 187 uint16_t symbTimeout, bool fixLen,
mluis 0:45c4f0364ca4 188 uint8_t payloadLen,
mluis 0:45c4f0364ca4 189 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
mluis 0:45c4f0364ca4 190 bool iqInverted, bool rxContinuous )
mluis 0:45c4f0364ca4 191 {
mluis 0:45c4f0364ca4 192 SetModem( modem );
mluis 0:45c4f0364ca4 193
mluis 0:45c4f0364ca4 194 switch( modem )
mluis 0:45c4f0364ca4 195 {
mluis 0:45c4f0364ca4 196 case MODEM_FSK:
mluis 0:45c4f0364ca4 197 {
mluis 0:45c4f0364ca4 198 this->settings.Fsk.Bandwidth = bandwidth;
mluis 0:45c4f0364ca4 199 this->settings.Fsk.Datarate = datarate;
mluis 0:45c4f0364ca4 200 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
mluis 0:45c4f0364ca4 201 this->settings.Fsk.FixLen = fixLen;
mluis 0:45c4f0364ca4 202 this->settings.Fsk.PayloadLen = payloadLen;
mluis 0:45c4f0364ca4 203 this->settings.Fsk.CrcOn = crcOn;
mluis 0:45c4f0364ca4 204 this->settings.Fsk.IqInverted = iqInverted;
mluis 0:45c4f0364ca4 205 this->settings.Fsk.RxContinuous = rxContinuous;
mluis 0:45c4f0364ca4 206 this->settings.Fsk.PreambleLen = preambleLen;
mluis 0:45c4f0364ca4 207
mluis 0:45c4f0364ca4 208 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
mluis 0:45c4f0364ca4 209 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
mluis 0:45c4f0364ca4 210 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
mluis 0:45c4f0364ca4 211
mluis 0:45c4f0364ca4 212 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
mluis 0:45c4f0364ca4 213 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
mluis 0:45c4f0364ca4 214
mluis 0:45c4f0364ca4 215 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
mluis 0:45c4f0364ca4 216 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
mluis 0:45c4f0364ca4 217
mluis 0:45c4f0364ca4 218 if( fixLen == 1 )
mluis 0:45c4f0364ca4 219 {
mluis 0:45c4f0364ca4 220 Write( REG_PAYLOADLENGTH, payloadLen );
mluis 0:45c4f0364ca4 221 }
mluis 0:45c4f0364ca4 222
mluis 0:45c4f0364ca4 223 Write( REG_PACKETCONFIG1,
mluis 0:45c4f0364ca4 224 ( Read( REG_PACKETCONFIG1 ) &
mluis 0:45c4f0364ca4 225 RF_PACKETCONFIG1_CRC_MASK &
mluis 0:45c4f0364ca4 226 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
mluis 0:45c4f0364ca4 227 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
mluis 0:45c4f0364ca4 228 ( crcOn << 4 ) );
mluis 0:45c4f0364ca4 229 }
mluis 0:45c4f0364ca4 230 break;
mluis 0:45c4f0364ca4 231 case MODEM_LORA:
mluis 0:45c4f0364ca4 232 {
mluis 0:45c4f0364ca4 233 this->settings.LoRa.Bandwidth = bandwidth;
mluis 0:45c4f0364ca4 234 this->settings.LoRa.Datarate = datarate;
mluis 0:45c4f0364ca4 235 this->settings.LoRa.Coderate = coderate;
mluis 0:45c4f0364ca4 236 this->settings.LoRa.PreambleLen = preambleLen;
mluis 0:45c4f0364ca4 237 this->settings.LoRa.FixLen = fixLen;
mluis 0:45c4f0364ca4 238 this->settings.LoRa.PayloadLen = payloadLen;
mluis 0:45c4f0364ca4 239 this->settings.LoRa.CrcOn = crcOn;
mluis 0:45c4f0364ca4 240 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 0:45c4f0364ca4 241 this->settings.LoRa.HopPeriod = hopPeriod;
mluis 0:45c4f0364ca4 242 this->settings.LoRa.IqInverted = iqInverted;
mluis 0:45c4f0364ca4 243 this->settings.LoRa.RxContinuous = rxContinuous;
mluis 0:45c4f0364ca4 244
mluis 0:45c4f0364ca4 245 if( datarate > 12 )
mluis 0:45c4f0364ca4 246 {
mluis 0:45c4f0364ca4 247 datarate = 12;
mluis 0:45c4f0364ca4 248 }
mluis 0:45c4f0364ca4 249 else if( datarate < 6 )
mluis 0:45c4f0364ca4 250 {
mluis 0:45c4f0364ca4 251 datarate = 6;
mluis 0:45c4f0364ca4 252 }
mluis 0:45c4f0364ca4 253
mluis 0:45c4f0364ca4 254 if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
mluis 0:45c4f0364ca4 255 ( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
mluis 0:45c4f0364ca4 256 {
mluis 0:45c4f0364ca4 257 this->settings.LoRa.LowDatarateOptimize = 0x01;
mluis 0:45c4f0364ca4 258 }
mluis 0:45c4f0364ca4 259 else
mluis 0:45c4f0364ca4 260 {
mluis 0:45c4f0364ca4 261 this->settings.LoRa.LowDatarateOptimize = 0x00;
mluis 0:45c4f0364ca4 262 }
mluis 0:45c4f0364ca4 263
mluis 0:45c4f0364ca4 264 Write( REG_LR_MODEMCONFIG1,
mluis 0:45c4f0364ca4 265 ( Read( REG_LR_MODEMCONFIG1 ) &
mluis 0:45c4f0364ca4 266 RFLR_MODEMCONFIG1_BW_MASK &
mluis 0:45c4f0364ca4 267 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
mluis 0:45c4f0364ca4 268 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK &
mluis 0:45c4f0364ca4 269 RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK &
mluis 0:45c4f0364ca4 270 RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 271 ( bandwidth << 6 ) | ( coderate << 3 ) |
mluis 0:45c4f0364ca4 272 ( fixLen << 2 ) | ( crcOn << 1 ) |
mluis 0:45c4f0364ca4 273 this->settings.LoRa.LowDatarateOptimize );
mluis 0:45c4f0364ca4 274
mluis 0:45c4f0364ca4 275 Write( REG_LR_MODEMCONFIG2,
mluis 0:45c4f0364ca4 276 ( Read( REG_LR_MODEMCONFIG2 ) &
mluis 0:45c4f0364ca4 277 RFLR_MODEMCONFIG2_SF_MASK &
mluis 0:45c4f0364ca4 278 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
mluis 0:45c4f0364ca4 279 ( datarate << 4 ) |
mluis 0:45c4f0364ca4 280 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
mluis 0:45c4f0364ca4 281
mluis 0:45c4f0364ca4 282 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
mluis 0:45c4f0364ca4 283
mluis 0:45c4f0364ca4 284 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
mluis 0:45c4f0364ca4 285 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
mluis 0:45c4f0364ca4 286
mluis 0:45c4f0364ca4 287 if( fixLen == 1 )
mluis 0:45c4f0364ca4 288 {
mluis 0:45c4f0364ca4 289 Write( REG_LR_PAYLOADLENGTH, payloadLen );
mluis 0:45c4f0364ca4 290 }
mluis 0:45c4f0364ca4 291
mluis 0:45c4f0364ca4 292 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 293 {
mluis 0:45c4f0364ca4 294 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
mluis 0:45c4f0364ca4 295 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
mluis 0:45c4f0364ca4 296 }
mluis 0:45c4f0364ca4 297
mluis 0:45c4f0364ca4 298 if( datarate == 6 )
mluis 0:45c4f0364ca4 299 {
mluis 0:45c4f0364ca4 300 Write( REG_LR_DETECTOPTIMIZE,
mluis 0:45c4f0364ca4 301 ( Read( REG_LR_DETECTOPTIMIZE ) &
mluis 0:45c4f0364ca4 302 RFLR_DETECTIONOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 303 RFLR_DETECTIONOPTIMIZE_SF6 );
mluis 0:45c4f0364ca4 304 Write( REG_LR_DETECTIONTHRESHOLD,
mluis 0:45c4f0364ca4 305 RFLR_DETECTIONTHRESH_SF6 );
mluis 0:45c4f0364ca4 306 }
mluis 0:45c4f0364ca4 307 else
mluis 0:45c4f0364ca4 308 {
mluis 0:45c4f0364ca4 309 Write( REG_LR_DETECTOPTIMIZE,
mluis 0:45c4f0364ca4 310 ( Read( REG_LR_DETECTOPTIMIZE ) &
mluis 0:45c4f0364ca4 311 RFLR_DETECTIONOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 312 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
mluis 0:45c4f0364ca4 313 Write( REG_LR_DETECTIONTHRESHOLD,
mluis 0:45c4f0364ca4 314 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
mluis 0:45c4f0364ca4 315 }
mluis 0:45c4f0364ca4 316 }
mluis 0:45c4f0364ca4 317 break;
mluis 0:45c4f0364ca4 318 }
mluis 0:45c4f0364ca4 319 }
mluis 0:45c4f0364ca4 320 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 321 /* PD_2=0 PD_2=1
mluis 0:45c4f0364ca4 322 op PaB rfo rfo
mluis 0:45c4f0364ca4 323 0 4.6 18.5 27.0
mluis 0:45c4f0364ca4 324 1 5.6 21.1 28.1
mluis 0:45c4f0364ca4 325 2 6.7 23.3 29.1
mluis 0:45c4f0364ca4 326 3 7.7 25.3 30.1
mluis 0:45c4f0364ca4 327 4 8.8 26.2 30.7
mluis 0:45c4f0364ca4 328 5 9.8 27.3 31.2
mluis 0:45c4f0364ca4 329 6 10.7 28.1 31.6
mluis 0:45c4f0364ca4 330 7 11.7 28.6 32.2
mluis 0:45c4f0364ca4 331 8 12.8 29.2 32.4
mluis 0:45c4f0364ca4 332 9 13.7 29.9 32.9
mluis 0:45c4f0364ca4 333 10 14.7 30.5 33.1
mluis 0:45c4f0364ca4 334 11 15.6 30.8 33.4
mluis 0:45c4f0364ca4 335 12 16.4 30.9 33.6
mluis 0:45c4f0364ca4 336 13 17.1 31.0 33.7
mluis 0:45c4f0364ca4 337 14 17.8 31.1 33.7
mluis 0:45c4f0364ca4 338 15 18.4 31.1 33.7
mluis 0:45c4f0364ca4 339 */
mluis 0:45c4f0364ca4 340 // txpow: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
mluis 0:45c4f0364ca4 341 static const uint8_t PaBTable[20] = { 0, 0, 0, 0, 0, 1, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15 };
mluis 0:45c4f0364ca4 342
mluis 0:45c4f0364ca4 343 // txpow: 20 21 22 23 24 25 26 27 28 29 30
mluis 0:45c4f0364ca4 344 static const uint8_t RfoTable[11] = { 1, 1, 1, 2, 2, 3, 4, 5, 6, 8, 9 };
mluis 0:45c4f0364ca4 345 #endif
mluis 0:45c4f0364ca4 346
mluis 0:45c4f0364ca4 347 void SX1272::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
mluis 0:45c4f0364ca4 348 uint32_t bandwidth, uint32_t datarate,
mluis 0:45c4f0364ca4 349 uint8_t coderate, uint16_t preambleLen,
mluis 0:45c4f0364ca4 350 bool fixLen, bool crcOn, bool freqHopOn,
mluis 0:45c4f0364ca4 351 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
mluis 0:45c4f0364ca4 352 {
mluis 0:45c4f0364ca4 353 uint8_t paConfig = 0;
mluis 0:45c4f0364ca4 354 uint8_t paDac = 0;
mluis 0:45c4f0364ca4 355
mluis 0:45c4f0364ca4 356 SetModem( modem );
mluis 0:45c4f0364ca4 357
mluis 0:45c4f0364ca4 358 paConfig = Read( REG_PACONFIG );
mluis 0:45c4f0364ca4 359 paDac = Read( REG_PADAC );
mluis 0:45c4f0364ca4 360
mluis 0:45c4f0364ca4 361 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 362 if( power > 19 )
mluis 0:45c4f0364ca4 363 {
mluis 0:45c4f0364ca4 364 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | RF_PACONFIG_PASELECT_RFO;
mluis 0:45c4f0364ca4 365 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | RfoTable[power - 20];
mluis 0:45c4f0364ca4 366 }
mluis 0:45c4f0364ca4 367 else
mluis 0:45c4f0364ca4 368 {
mluis 0:45c4f0364ca4 369 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | RF_PACONFIG_PASELECT_PABOOST;
mluis 0:45c4f0364ca4 370 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | PaBTable[power];
mluis 0:45c4f0364ca4 371 }
mluis 0:45c4f0364ca4 372 #else
mluis 0:45c4f0364ca4 373 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
mluis 0:45c4f0364ca4 374
mluis 0:45c4f0364ca4 375 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
mluis 0:45c4f0364ca4 376 {
mluis 0:45c4f0364ca4 377 if( power > 17 )
mluis 0:45c4f0364ca4 378 {
mluis 0:45c4f0364ca4 379 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
mluis 0:45c4f0364ca4 380 }
mluis 0:45c4f0364ca4 381 else
mluis 0:45c4f0364ca4 382 {
mluis 0:45c4f0364ca4 383 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
mluis 0:45c4f0364ca4 384 }
mluis 0:45c4f0364ca4 385 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
mluis 0:45c4f0364ca4 386 {
mluis 0:45c4f0364ca4 387 if( power < 5 )
mluis 0:45c4f0364ca4 388 {
mluis 0:45c4f0364ca4 389 power = 5;
mluis 0:45c4f0364ca4 390 }
mluis 0:45c4f0364ca4 391 if( power > 20 )
mluis 0:45c4f0364ca4 392 {
mluis 0:45c4f0364ca4 393 power = 20;
mluis 0:45c4f0364ca4 394 }
mluis 0:45c4f0364ca4 395 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
mluis 0:45c4f0364ca4 396 }
mluis 0:45c4f0364ca4 397 else
mluis 0:45c4f0364ca4 398 {
mluis 0:45c4f0364ca4 399 if( power < 2 )
mluis 0:45c4f0364ca4 400 {
mluis 0:45c4f0364ca4 401 power = 2;
mluis 0:45c4f0364ca4 402 }
mluis 0:45c4f0364ca4 403 if( power > 17 )
mluis 0:45c4f0364ca4 404 {
mluis 0:45c4f0364ca4 405 power = 17;
mluis 0:45c4f0364ca4 406 }
mluis 0:45c4f0364ca4 407 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
mluis 0:45c4f0364ca4 408 }
mluis 0:45c4f0364ca4 409 }
mluis 0:45c4f0364ca4 410 else
mluis 0:45c4f0364ca4 411 {
mluis 0:45c4f0364ca4 412 if( power < -1 )
mluis 0:45c4f0364ca4 413 {
mluis 0:45c4f0364ca4 414 power = -1;
mluis 0:45c4f0364ca4 415 }
mluis 0:45c4f0364ca4 416 if( power > 14 )
mluis 0:45c4f0364ca4 417 {
mluis 0:45c4f0364ca4 418 power = 14;
mluis 0:45c4f0364ca4 419 }
mluis 0:45c4f0364ca4 420 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
mluis 0:45c4f0364ca4 421 }
mluis 0:45c4f0364ca4 422 #endif
mluis 0:45c4f0364ca4 423
mluis 0:45c4f0364ca4 424 Write( REG_PACONFIG, paConfig );
mluis 0:45c4f0364ca4 425 Write( REG_PADAC, paDac );
mluis 0:45c4f0364ca4 426
mluis 0:45c4f0364ca4 427 switch( modem )
mluis 0:45c4f0364ca4 428 {
mluis 0:45c4f0364ca4 429 case MODEM_FSK:
mluis 0:45c4f0364ca4 430 {
mluis 0:45c4f0364ca4 431 this->settings.Fsk.Power = power;
mluis 0:45c4f0364ca4 432 this->settings.Fsk.Fdev = fdev;
mluis 0:45c4f0364ca4 433 this->settings.Fsk.Bandwidth = bandwidth;
mluis 0:45c4f0364ca4 434 this->settings.Fsk.Datarate = datarate;
mluis 0:45c4f0364ca4 435 this->settings.Fsk.PreambleLen = preambleLen;
mluis 0:45c4f0364ca4 436 this->settings.Fsk.FixLen = fixLen;
mluis 0:45c4f0364ca4 437 this->settings.Fsk.CrcOn = crcOn;
mluis 0:45c4f0364ca4 438 this->settings.Fsk.IqInverted = iqInverted;
mluis 0:45c4f0364ca4 439 this->settings.Fsk.TxTimeout = timeout;
mluis 0:45c4f0364ca4 440
mluis 0:45c4f0364ca4 441 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
mluis 0:45c4f0364ca4 442 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
mluis 0:45c4f0364ca4 443 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
mluis 0:45c4f0364ca4 444
mluis 0:45c4f0364ca4 445 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
mluis 0:45c4f0364ca4 446 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
mluis 0:45c4f0364ca4 447 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
mluis 0:45c4f0364ca4 448
mluis 0:45c4f0364ca4 449 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
mluis 0:45c4f0364ca4 450 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
mluis 0:45c4f0364ca4 451
mluis 0:45c4f0364ca4 452 Write( REG_PACKETCONFIG1,
mluis 0:45c4f0364ca4 453 ( Read( REG_PACKETCONFIG1 ) &
mluis 0:45c4f0364ca4 454 RF_PACKETCONFIG1_CRC_MASK &
mluis 0:45c4f0364ca4 455 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
mluis 0:45c4f0364ca4 456 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
mluis 0:45c4f0364ca4 457 ( crcOn << 4 ) );
mluis 0:45c4f0364ca4 458
mluis 0:45c4f0364ca4 459 }
mluis 0:45c4f0364ca4 460 break;
mluis 0:45c4f0364ca4 461 case MODEM_LORA:
mluis 0:45c4f0364ca4 462 {
mluis 0:45c4f0364ca4 463 this->settings.LoRa.Power = power;
mluis 0:45c4f0364ca4 464 this->settings.LoRa.Bandwidth = bandwidth;
mluis 0:45c4f0364ca4 465 this->settings.LoRa.Datarate = datarate;
mluis 0:45c4f0364ca4 466 this->settings.LoRa.Coderate = coderate;
mluis 0:45c4f0364ca4 467 this->settings.LoRa.PreambleLen = preambleLen;
mluis 0:45c4f0364ca4 468 this->settings.LoRa.FixLen = fixLen;
mluis 0:45c4f0364ca4 469 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 0:45c4f0364ca4 470 this->settings.LoRa.HopPeriod = hopPeriod;
mluis 0:45c4f0364ca4 471 this->settings.LoRa.CrcOn = crcOn;
mluis 0:45c4f0364ca4 472 this->settings.LoRa.IqInverted = iqInverted;
mluis 0:45c4f0364ca4 473 this->settings.LoRa.TxTimeout = timeout;
mluis 0:45c4f0364ca4 474
mluis 0:45c4f0364ca4 475 if( datarate > 12 )
mluis 0:45c4f0364ca4 476 {
mluis 0:45c4f0364ca4 477 datarate = 12;
mluis 0:45c4f0364ca4 478 }
mluis 0:45c4f0364ca4 479 else if( datarate < 6 )
mluis 0:45c4f0364ca4 480 {
mluis 0:45c4f0364ca4 481 datarate = 6;
mluis 0:45c4f0364ca4 482 }
mluis 0:45c4f0364ca4 483 if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
mluis 0:45c4f0364ca4 484 ( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
mluis 0:45c4f0364ca4 485 {
mluis 0:45c4f0364ca4 486 this->settings.LoRa.LowDatarateOptimize = 0x01;
mluis 0:45c4f0364ca4 487 }
mluis 0:45c4f0364ca4 488 else
mluis 0:45c4f0364ca4 489 {
mluis 0:45c4f0364ca4 490 this->settings.LoRa.LowDatarateOptimize = 0x00;
mluis 0:45c4f0364ca4 491 }
mluis 0:45c4f0364ca4 492
mluis 0:45c4f0364ca4 493 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 494 {
mluis 0:45c4f0364ca4 495 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
mluis 0:45c4f0364ca4 496 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
mluis 0:45c4f0364ca4 497 }
mluis 0:45c4f0364ca4 498
mluis 0:45c4f0364ca4 499 Write( REG_LR_MODEMCONFIG1,
mluis 0:45c4f0364ca4 500 ( Read( REG_LR_MODEMCONFIG1 ) &
mluis 0:45c4f0364ca4 501 RFLR_MODEMCONFIG1_BW_MASK &
mluis 0:45c4f0364ca4 502 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
mluis 0:45c4f0364ca4 503 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK &
mluis 0:45c4f0364ca4 504 RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK &
mluis 0:45c4f0364ca4 505 RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 506 ( bandwidth << 6 ) | ( coderate << 3 ) |
mluis 0:45c4f0364ca4 507 ( fixLen << 2 ) | ( crcOn << 1 ) |
mluis 0:45c4f0364ca4 508 this->settings.LoRa.LowDatarateOptimize );
mluis 0:45c4f0364ca4 509
mluis 0:45c4f0364ca4 510 Write( REG_LR_MODEMCONFIG2,
mluis 0:45c4f0364ca4 511 ( Read( REG_LR_MODEMCONFIG2 ) &
mluis 0:45c4f0364ca4 512 RFLR_MODEMCONFIG2_SF_MASK ) |
mluis 0:45c4f0364ca4 513 ( datarate << 4 ) );
mluis 0:45c4f0364ca4 514
mluis 0:45c4f0364ca4 515
mluis 0:45c4f0364ca4 516 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
mluis 0:45c4f0364ca4 517 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
mluis 0:45c4f0364ca4 518
mluis 0:45c4f0364ca4 519 if( datarate == 6 )
mluis 0:45c4f0364ca4 520 {
mluis 0:45c4f0364ca4 521 Write( REG_LR_DETECTOPTIMIZE,
mluis 0:45c4f0364ca4 522 ( Read( REG_LR_DETECTOPTIMIZE ) &
mluis 0:45c4f0364ca4 523 RFLR_DETECTIONOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 524 RFLR_DETECTIONOPTIMIZE_SF6 );
mluis 0:45c4f0364ca4 525 Write( REG_LR_DETECTIONTHRESHOLD,
mluis 0:45c4f0364ca4 526 RFLR_DETECTIONTHRESH_SF6 );
mluis 0:45c4f0364ca4 527 }
mluis 0:45c4f0364ca4 528 else
mluis 0:45c4f0364ca4 529 {
mluis 0:45c4f0364ca4 530 Write( REG_LR_DETECTOPTIMIZE,
mluis 0:45c4f0364ca4 531 ( Read( REG_LR_DETECTOPTIMIZE ) &
mluis 0:45c4f0364ca4 532 RFLR_DETECTIONOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 533 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
mluis 0:45c4f0364ca4 534 Write( REG_LR_DETECTIONTHRESHOLD,
mluis 0:45c4f0364ca4 535 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
mluis 0:45c4f0364ca4 536 }
mluis 0:45c4f0364ca4 537 }
mluis 0:45c4f0364ca4 538 break;
mluis 0:45c4f0364ca4 539 }
mluis 0:45c4f0364ca4 540 }
mluis 0:45c4f0364ca4 541
mluis 0:45c4f0364ca4 542 double SX1272::TimeOnAir( RadioModems_t modem, uint8_t pktLen )
mluis 0:45c4f0364ca4 543 {
mluis 0:45c4f0364ca4 544 uint32_t airTime = 0;
mluis 0:45c4f0364ca4 545
mluis 0:45c4f0364ca4 546 switch( modem )
mluis 0:45c4f0364ca4 547 {
mluis 0:45c4f0364ca4 548 case MODEM_FSK:
mluis 0:45c4f0364ca4 549 {
mluis 0:45c4f0364ca4 550 airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen +
mluis 0:45c4f0364ca4 551 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
mluis 0:45c4f0364ca4 552 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
mluis 0:45c4f0364ca4 553 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
mluis 0:45c4f0364ca4 554 pktLen +
mluis 0:45c4f0364ca4 555 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
mluis 0:45c4f0364ca4 556 this->settings.Fsk.Datarate ) * 1e6 );
mluis 0:45c4f0364ca4 557 }
mluis 0:45c4f0364ca4 558 break;
mluis 0:45c4f0364ca4 559 case MODEM_LORA:
mluis 0:45c4f0364ca4 560 {
mluis 0:45c4f0364ca4 561 double bw = 0.0;
mluis 0:45c4f0364ca4 562 switch( this->settings.LoRa.Bandwidth )
mluis 0:45c4f0364ca4 563 {
mluis 0:45c4f0364ca4 564 case 0: // 125 kHz
mluis 0:45c4f0364ca4 565 bw = 125e3;
mluis 0:45c4f0364ca4 566 break;
mluis 0:45c4f0364ca4 567 case 1: // 250 kHz
mluis 0:45c4f0364ca4 568 bw = 250e3;
mluis 0:45c4f0364ca4 569 break;
mluis 0:45c4f0364ca4 570 case 2: // 500 kHz
mluis 0:45c4f0364ca4 571 bw = 500e3;
mluis 0:45c4f0364ca4 572 break;
mluis 0:45c4f0364ca4 573 }
mluis 0:45c4f0364ca4 574
mluis 0:45c4f0364ca4 575 // Symbol rate : time for one symbol (secs)
mluis 0:45c4f0364ca4 576 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
mluis 0:45c4f0364ca4 577 double ts = 1 / rs;
mluis 0:45c4f0364ca4 578 // time of preamble
mluis 0:45c4f0364ca4 579 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
mluis 0:45c4f0364ca4 580 // Symbol length of payload and time
mluis 0:45c4f0364ca4 581 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
mluis 0:45c4f0364ca4 582 28 + 16 * this->settings.LoRa.CrcOn -
mluis 0:45c4f0364ca4 583 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
mluis 0:45c4f0364ca4 584 ( double )( 4 * this->settings.LoRa.Datarate -
mluis 0:45c4f0364ca4 585 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) *
mluis 0:45c4f0364ca4 586 ( this->settings.LoRa.Coderate + 4 );
mluis 0:45c4f0364ca4 587 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
mluis 0:45c4f0364ca4 588 double tPayload = nPayload * ts;
mluis 0:45c4f0364ca4 589 // Time on air
mluis 0:45c4f0364ca4 590 double tOnAir = tPreamble + tPayload;
mluis 0:45c4f0364ca4 591 // return us secs
mluis 0:45c4f0364ca4 592 airTime = floor( tOnAir * 1e6 + 0.999 );
mluis 0:45c4f0364ca4 593 }
mluis 0:45c4f0364ca4 594 break;
mluis 0:45c4f0364ca4 595 }
mluis 0:45c4f0364ca4 596 return airTime;
mluis 0:45c4f0364ca4 597 }
mluis 0:45c4f0364ca4 598
mluis 0:45c4f0364ca4 599 void SX1272::Send( uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 600 {
mluis 0:45c4f0364ca4 601 uint32_t txTimeout = 0;
mluis 0:45c4f0364ca4 602
mluis 0:45c4f0364ca4 603 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 604 {
mluis 0:45c4f0364ca4 605 case MODEM_FSK:
mluis 0:45c4f0364ca4 606 {
mluis 0:45c4f0364ca4 607 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 608 this->settings.FskPacketHandler.Size = size;
mluis 0:45c4f0364ca4 609
mluis 0:45c4f0364ca4 610 if( this->settings.Fsk.FixLen == false )
mluis 0:45c4f0364ca4 611 {
mluis 0:45c4f0364ca4 612 WriteFifo( ( uint8_t* )&size, 1 );
mluis 0:45c4f0364ca4 613 }
mluis 0:45c4f0364ca4 614 else
mluis 0:45c4f0364ca4 615 {
mluis 0:45c4f0364ca4 616 Write( REG_PAYLOADLENGTH, size );
mluis 0:45c4f0364ca4 617 }
mluis 0:45c4f0364ca4 618
mluis 0:45c4f0364ca4 619 if( ( size > 0 ) && ( size <= 64 ) )
mluis 0:45c4f0364ca4 620 {
mluis 0:45c4f0364ca4 621 this->settings.FskPacketHandler.ChunkSize = size;
mluis 0:45c4f0364ca4 622 }
mluis 0:45c4f0364ca4 623 else
mluis 0:45c4f0364ca4 624 {
mluis 0:45c4f0364ca4 625 this->settings.FskPacketHandler.ChunkSize = 32;
mluis 0:45c4f0364ca4 626 }
mluis 0:45c4f0364ca4 627
mluis 0:45c4f0364ca4 628 // Write payload buffer
mluis 0:45c4f0364ca4 629 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
mluis 0:45c4f0364ca4 630 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
mluis 0:45c4f0364ca4 631 txTimeout = this->settings.Fsk.TxTimeout;
mluis 0:45c4f0364ca4 632 }
mluis 0:45c4f0364ca4 633 break;
mluis 0:45c4f0364ca4 634 case MODEM_LORA:
mluis 0:45c4f0364ca4 635 {
mluis 0:45c4f0364ca4 636 if( this->settings.LoRa.IqInverted == true )
mluis 0:45c4f0364ca4 637 {
mluis 0:45c4f0364ca4 638 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
mluis 0:45c4f0364ca4 639 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
mluis 0:45c4f0364ca4 640 }
mluis 0:45c4f0364ca4 641 else
mluis 0:45c4f0364ca4 642 {
mluis 0:45c4f0364ca4 643 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
mluis 0:45c4f0364ca4 644 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
mluis 0:45c4f0364ca4 645 }
mluis 0:45c4f0364ca4 646
mluis 0:45c4f0364ca4 647 this->settings.LoRaPacketHandler.Size = size;
mluis 0:45c4f0364ca4 648
mluis 0:45c4f0364ca4 649 // Initializes the payload size
mluis 0:45c4f0364ca4 650 Write( REG_LR_PAYLOADLENGTH, size );
mluis 0:45c4f0364ca4 651
mluis 0:45c4f0364ca4 652 // Full buffer used for Tx
mluis 0:45c4f0364ca4 653 Write( REG_LR_FIFOTXBASEADDR, 0 );
mluis 0:45c4f0364ca4 654 Write( REG_LR_FIFOADDRPTR, 0 );
mluis 0:45c4f0364ca4 655
mluis 0:45c4f0364ca4 656 // FIFO operations can not take place in Sleep mode
mluis 0:45c4f0364ca4 657 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
mluis 0:45c4f0364ca4 658 {
mluis 0:45c4f0364ca4 659 Standby( );
mluis 0:45c4f0364ca4 660 wait_ms( 1 );
mluis 0:45c4f0364ca4 661 }
mluis 0:45c4f0364ca4 662 // Write payload buffer
mluis 0:45c4f0364ca4 663 WriteFifo( buffer, size );
mluis 0:45c4f0364ca4 664 txTimeout = this->settings.LoRa.TxTimeout;
mluis 0:45c4f0364ca4 665 }
mluis 0:45c4f0364ca4 666 break;
mluis 0:45c4f0364ca4 667 }
mluis 0:45c4f0364ca4 668
mluis 0:45c4f0364ca4 669 Tx( txTimeout );
mluis 0:45c4f0364ca4 670 }
mluis 0:45c4f0364ca4 671
mluis 0:45c4f0364ca4 672 void SX1272::Sleep( void )
mluis 0:45c4f0364ca4 673 {
mluis 0:45c4f0364ca4 674 txTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 675 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 676
mluis 0:45c4f0364ca4 677 SetOpMode( RF_OPMODE_SLEEP );
mluis 0:45c4f0364ca4 678 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 679 }
mluis 0:45c4f0364ca4 680
mluis 0:45c4f0364ca4 681 void SX1272::Standby( void )
mluis 0:45c4f0364ca4 682 {
mluis 0:45c4f0364ca4 683 txTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 684 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 685
mluis 0:45c4f0364ca4 686 SetOpMode( RF_OPMODE_STANDBY );
mluis 0:45c4f0364ca4 687 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 688 }
mluis 0:45c4f0364ca4 689
mluis 0:45c4f0364ca4 690 void SX1272::Rx( uint32_t timeout )
mluis 0:45c4f0364ca4 691 {
mluis 0:45c4f0364ca4 692 bool rxContinuous = false;
mluis 0:45c4f0364ca4 693
mluis 0:45c4f0364ca4 694 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 695 {
mluis 0:45c4f0364ca4 696 case MODEM_FSK:
mluis 0:45c4f0364ca4 697 {
mluis 0:45c4f0364ca4 698 rxContinuous = this->settings.Fsk.RxContinuous;
mluis 0:45c4f0364ca4 699
mluis 0:45c4f0364ca4 700 // DIO0=PayloadReady
mluis 0:45c4f0364ca4 701 // DIO1=FifoLevel
mluis 0:45c4f0364ca4 702 // DIO2=SyncAddr
mluis 0:45c4f0364ca4 703 // DIO3=FifoEmpty
mluis 0:45c4f0364ca4 704 // DIO4=Preamble
mluis 0:45c4f0364ca4 705 // DIO5=ModeReady
mluis 0:45c4f0364ca4 706 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
mluis 0:45c4f0364ca4 707 RF_DIOMAPPING1_DIO2_MASK ) |
mluis 0:45c4f0364ca4 708 RF_DIOMAPPING1_DIO0_00 |
mluis 0:45c4f0364ca4 709 RF_DIOMAPPING1_DIO2_11 );
mluis 0:45c4f0364ca4 710
mluis 0:45c4f0364ca4 711 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
mluis 0:45c4f0364ca4 712 RF_DIOMAPPING2_MAP_MASK ) |
mluis 0:45c4f0364ca4 713 RF_DIOMAPPING2_DIO4_11 |
mluis 0:45c4f0364ca4 714 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
mluis 0:45c4f0364ca4 715
mluis 0:45c4f0364ca4 716 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
mluis 0:45c4f0364ca4 717
mluis 0:45c4f0364ca4 718 this->settings.FskPacketHandler.PreambleDetected = false;
mluis 0:45c4f0364ca4 719 this->settings.FskPacketHandler.SyncWordDetected = false;
mluis 0:45c4f0364ca4 720 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 721 this->settings.FskPacketHandler.Size = 0;
mluis 0:45c4f0364ca4 722 }
mluis 0:45c4f0364ca4 723 break;
mluis 0:45c4f0364ca4 724 case MODEM_LORA:
mluis 0:45c4f0364ca4 725 {
mluis 0:45c4f0364ca4 726 if( this->settings.LoRa.IqInverted == true )
mluis 0:45c4f0364ca4 727 {
mluis 0:45c4f0364ca4 728 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
mluis 0:45c4f0364ca4 729 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
mluis 0:45c4f0364ca4 730 }
mluis 0:45c4f0364ca4 731 else
mluis 0:45c4f0364ca4 732 {
mluis 0:45c4f0364ca4 733 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
mluis 0:45c4f0364ca4 734 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
mluis 0:45c4f0364ca4 735 }
mluis 0:45c4f0364ca4 736
mluis 0:45c4f0364ca4 737 rxContinuous = this->settings.LoRa.RxContinuous;
mluis 0:45c4f0364ca4 738
mluis 0:45c4f0364ca4 739 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 740 {
mluis 0:45c4f0364ca4 741 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 742 //RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 743 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 744 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 745 RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 746 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 747 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 748 RFLR_IRQFLAGS_CADDETECTED );
mluis 0:45c4f0364ca4 749
mluis 0:45c4f0364ca4 750 // DIO0=RxDone, DIO2=FhssChangeChannel
mluis 0:45c4f0364ca4 751 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
mluis 0:45c4f0364ca4 752 }
mluis 0:45c4f0364ca4 753 else
mluis 0:45c4f0364ca4 754 {
mluis 0:45c4f0364ca4 755 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 756 //RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 757 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 758 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 759 RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 760 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 761 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 762 RFLR_IRQFLAGS_CADDETECTED );
mluis 0:45c4f0364ca4 763
mluis 0:45c4f0364ca4 764 // DIO0=RxDone
mluis 0:45c4f0364ca4 765 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
mluis 0:45c4f0364ca4 766 }
mluis 0:45c4f0364ca4 767 Write( REG_LR_FIFORXBASEADDR, 0 );
mluis 0:45c4f0364ca4 768 Write( REG_LR_FIFOADDRPTR, 0 );
mluis 0:45c4f0364ca4 769 }
mluis 0:45c4f0364ca4 770 break;
mluis 0:45c4f0364ca4 771 }
mluis 0:45c4f0364ca4 772
mluis 0:45c4f0364ca4 773 memset( rxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
mluis 0:45c4f0364ca4 774
mluis 0:45c4f0364ca4 775 this->settings.State = RF_RX_RUNNING;
mluis 0:45c4f0364ca4 776 if( timeout != 0 )
mluis 0:45c4f0364ca4 777 {
mluis 0:45c4f0364ca4 778 rxTimeoutTimer.attach_us( this, &SX1272::OnTimeoutIrq, timeout );
mluis 0:45c4f0364ca4 779 }
mluis 0:45c4f0364ca4 780
mluis 0:45c4f0364ca4 781 if( this->settings.Modem == MODEM_FSK )
mluis 0:45c4f0364ca4 782 {
mluis 0:45c4f0364ca4 783 SetOpMode( RF_OPMODE_RECEIVER );
mluis 0:45c4f0364ca4 784
mluis 0:45c4f0364ca4 785 if( rxContinuous == false )
mluis 0:45c4f0364ca4 786 {
mluis 0:45c4f0364ca4 787 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
mluis 0:45c4f0364ca4 788 ( ( Read( REG_SYNCCONFIG ) &
mluis 0:45c4f0364ca4 789 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 0:45c4f0364ca4 790 1.0 ) + 10.0 ) /
mluis 0:45c4f0364ca4 791 ( double )this->settings.Fsk.Datarate ) * 1e6 );
mluis 0:45c4f0364ca4 792 }
mluis 0:45c4f0364ca4 793 }
mluis 0:45c4f0364ca4 794 else
mluis 0:45c4f0364ca4 795 {
mluis 0:45c4f0364ca4 796 if( rxContinuous == true )
mluis 0:45c4f0364ca4 797 {
mluis 0:45c4f0364ca4 798 SetOpMode( RFLR_OPMODE_RECEIVER );
mluis 0:45c4f0364ca4 799 }
mluis 0:45c4f0364ca4 800 else
mluis 0:45c4f0364ca4 801 {
mluis 0:45c4f0364ca4 802 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
mluis 0:45c4f0364ca4 803 }
mluis 0:45c4f0364ca4 804 }
mluis 0:45c4f0364ca4 805 }
mluis 0:45c4f0364ca4 806
mluis 0:45c4f0364ca4 807 void SX1272::Tx( uint32_t timeout )
mluis 0:45c4f0364ca4 808 {
mluis 0:45c4f0364ca4 809
mluis 0:45c4f0364ca4 810 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 811 {
mluis 0:45c4f0364ca4 812 case MODEM_FSK:
mluis 0:45c4f0364ca4 813 {
mluis 0:45c4f0364ca4 814 // DIO0=PacketSent
mluis 0:45c4f0364ca4 815 // DIO1=FifoLevel
mluis 0:45c4f0364ca4 816 // DIO2=FifoFull
mluis 0:45c4f0364ca4 817 // DIO3=FifoEmpty
mluis 0:45c4f0364ca4 818 // DIO4=LowBat
mluis 0:45c4f0364ca4 819 // DIO5=ModeReady
mluis 0:45c4f0364ca4 820 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
mluis 0:45c4f0364ca4 821 RF_DIOMAPPING1_DIO2_MASK ) );
mluis 0:45c4f0364ca4 822
mluis 0:45c4f0364ca4 823 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
mluis 0:45c4f0364ca4 824 RF_DIOMAPPING2_MAP_MASK ) );
mluis 0:45c4f0364ca4 825 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
mluis 0:45c4f0364ca4 826 }
mluis 0:45c4f0364ca4 827 break;
mluis 0:45c4f0364ca4 828 case MODEM_LORA:
mluis 0:45c4f0364ca4 829 {
mluis 0:45c4f0364ca4 830 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 831 {
mluis 0:45c4f0364ca4 832 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 833 RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 834 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 835 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 836 //RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 837 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 838 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 839 RFLR_IRQFLAGS_CADDETECTED );
mluis 0:45c4f0364ca4 840
mluis 0:45c4f0364ca4 841 // DIO0=TxDone, DIO2=FhssChangeChannel
mluis 0:45c4f0364ca4 842 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
mluis 0:45c4f0364ca4 843 }
mluis 0:45c4f0364ca4 844 else
mluis 0:45c4f0364ca4 845 {
mluis 0:45c4f0364ca4 846 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 847 RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 848 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 849 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 850 //RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 851 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 852 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 853 RFLR_IRQFLAGS_CADDETECTED );
mluis 0:45c4f0364ca4 854
mluis 0:45c4f0364ca4 855 // DIO0=TxDone
mluis 0:45c4f0364ca4 856 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
mluis 0:45c4f0364ca4 857 }
mluis 0:45c4f0364ca4 858 }
mluis 0:45c4f0364ca4 859 break;
mluis 0:45c4f0364ca4 860 }
mluis 0:45c4f0364ca4 861
mluis 0:45c4f0364ca4 862 this->settings.State = RF_TX_RUNNING;
mluis 0:45c4f0364ca4 863 txTimeoutTimer.attach_us( this, &SX1272::OnTimeoutIrq, timeout );
mluis 0:45c4f0364ca4 864 SetOpMode( RF_OPMODE_TRANSMITTER );
mluis 0:45c4f0364ca4 865 }
mluis 0:45c4f0364ca4 866
mluis 0:45c4f0364ca4 867 void SX1272::StartCad( void )
mluis 0:45c4f0364ca4 868 {
mluis 0:45c4f0364ca4 869 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 870 {
mluis 0:45c4f0364ca4 871 case MODEM_FSK:
mluis 0:45c4f0364ca4 872 {
mluis 0:45c4f0364ca4 873
mluis 0:45c4f0364ca4 874 }
mluis 0:45c4f0364ca4 875 break;
mluis 0:45c4f0364ca4 876 case MODEM_LORA:
mluis 0:45c4f0364ca4 877 {
mluis 0:45c4f0364ca4 878 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 879 RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 880 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 881 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 882 RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 883 //RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 884 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
mluis 0:45c4f0364ca4 885 //RFLR_IRQFLAGS_CADDETECTED
mluis 0:45c4f0364ca4 886 );
mluis 0:45c4f0364ca4 887
mluis 0:45c4f0364ca4 888 // DIO3=CADDone
mluis 0:45c4f0364ca4 889 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
mluis 0:45c4f0364ca4 890
mluis 0:45c4f0364ca4 891 this->settings.State = RF_CAD;
mluis 0:45c4f0364ca4 892 SetOpMode( RFLR_OPMODE_CAD );
mluis 0:45c4f0364ca4 893 }
mluis 0:45c4f0364ca4 894 break;
mluis 0:45c4f0364ca4 895 default:
mluis 0:45c4f0364ca4 896 break;
mluis 0:45c4f0364ca4 897 }
mluis 0:45c4f0364ca4 898 }
mluis 0:45c4f0364ca4 899
mluis 0:45c4f0364ca4 900 int16_t SX1272::GetRssi( RadioModems_t modem )
mluis 0:45c4f0364ca4 901 {
mluis 0:45c4f0364ca4 902 int16_t rssi = 0;
mluis 0:45c4f0364ca4 903
mluis 0:45c4f0364ca4 904 switch( modem )
mluis 0:45c4f0364ca4 905 {
mluis 0:45c4f0364ca4 906 case MODEM_FSK:
mluis 0:45c4f0364ca4 907 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
mluis 0:45c4f0364ca4 908 break;
mluis 0:45c4f0364ca4 909 case MODEM_LORA:
mluis 0:45c4f0364ca4 910 rssi = RSSI_OFFSET + Read( REG_LR_RSSIVALUE );
mluis 0:45c4f0364ca4 911 break;
mluis 0:45c4f0364ca4 912 default:
mluis 0:45c4f0364ca4 913 rssi = -1;
mluis 0:45c4f0364ca4 914 break;
mluis 0:45c4f0364ca4 915 }
mluis 0:45c4f0364ca4 916 return rssi;
mluis 0:45c4f0364ca4 917 }
mluis 0:45c4f0364ca4 918
mluis 0:45c4f0364ca4 919 void SX1272::SetOpMode( uint8_t opMode )
mluis 0:45c4f0364ca4 920 {
mluis 0:45c4f0364ca4 921 if( opMode != currentOpMode )
mluis 0:45c4f0364ca4 922 {
mluis 0:45c4f0364ca4 923 currentOpMode = opMode;
mluis 0:45c4f0364ca4 924 if( opMode == RF_OPMODE_SLEEP )
mluis 0:45c4f0364ca4 925 {
mluis 0:45c4f0364ca4 926 SetAntSwLowPower( true );
mluis 0:45c4f0364ca4 927 }
mluis 0:45c4f0364ca4 928 else
mluis 0:45c4f0364ca4 929 {
mluis 0:45c4f0364ca4 930 SetAntSwLowPower( false );
mluis 0:45c4f0364ca4 931 if( opMode == RF_OPMODE_TRANSMITTER )
mluis 0:45c4f0364ca4 932 {
mluis 0:45c4f0364ca4 933 SetAntSw( 1 );
mluis 0:45c4f0364ca4 934 }
mluis 0:45c4f0364ca4 935 else
mluis 0:45c4f0364ca4 936 {
mluis 0:45c4f0364ca4 937 SetAntSw( 0 );
mluis 0:45c4f0364ca4 938 }
mluis 0:45c4f0364ca4 939 }
mluis 0:45c4f0364ca4 940 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
mluis 0:45c4f0364ca4 941 }
mluis 0:45c4f0364ca4 942 }
mluis 0:45c4f0364ca4 943
mluis 0:45c4f0364ca4 944 void SX1272::SetModem( RadioModems_t modem )
mluis 0:45c4f0364ca4 945 {
mluis 0:45c4f0364ca4 946 if( this->settings.Modem == modem )
mluis 0:45c4f0364ca4 947 {
mluis 0:45c4f0364ca4 948 return;
mluis 0:45c4f0364ca4 949 }
mluis 0:45c4f0364ca4 950
mluis 0:45c4f0364ca4 951 this->settings.Modem = modem;
mluis 0:45c4f0364ca4 952 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 953 {
mluis 0:45c4f0364ca4 954 default:
mluis 0:45c4f0364ca4 955 case MODEM_FSK:
mluis 0:45c4f0364ca4 956 SetOpMode( RF_OPMODE_SLEEP );
mluis 0:45c4f0364ca4 957 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
mluis 0:45c4f0364ca4 958
mluis 0:45c4f0364ca4 959 Write( REG_DIOMAPPING1, 0x00 );
mluis 0:45c4f0364ca4 960 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
mluis 0:45c4f0364ca4 961 break;
mluis 0:45c4f0364ca4 962 case MODEM_LORA:
mluis 0:45c4f0364ca4 963 SetOpMode( RF_OPMODE_SLEEP );
mluis 0:45c4f0364ca4 964 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
mluis 0:45c4f0364ca4 965
mluis 0:45c4f0364ca4 966 Write( REG_DIOMAPPING1, 0x00 );
mluis 0:45c4f0364ca4 967 Write( REG_DIOMAPPING2, 0x00 );
mluis 0:45c4f0364ca4 968 break;
mluis 0:45c4f0364ca4 969 }
mluis 0:45c4f0364ca4 970 }
mluis 0:45c4f0364ca4 971
mluis 0:45c4f0364ca4 972 void SX1272::SetMaxPayloadLength( RadioModems_t modem, uint8_t max )
mluis 0:45c4f0364ca4 973 {
mluis 0:45c4f0364ca4 974 this->SetModem( modem );
mluis 0:45c4f0364ca4 975
mluis 0:45c4f0364ca4 976 switch( modem )
mluis 0:45c4f0364ca4 977 {
mluis 0:45c4f0364ca4 978 case MODEM_FSK:
mluis 0:45c4f0364ca4 979 if( this->settings.Fsk.FixLen == false )
mluis 0:45c4f0364ca4 980 {
mluis 0:45c4f0364ca4 981 this->Write( REG_PAYLOADLENGTH, max );
mluis 0:45c4f0364ca4 982 }
mluis 0:45c4f0364ca4 983 break;
mluis 0:45c4f0364ca4 984 case MODEM_LORA:
mluis 0:45c4f0364ca4 985 this->Write( REG_LR_PAYLOADMAXLENGTH, max );
mluis 0:45c4f0364ca4 986 break;
mluis 0:45c4f0364ca4 987 }
mluis 0:45c4f0364ca4 988 }
mluis 0:45c4f0364ca4 989
mluis 0:45c4f0364ca4 990 void SX1272::OnTimeoutIrq( void )
mluis 0:45c4f0364ca4 991 {
mluis 0:45c4f0364ca4 992 switch( this->settings.State )
mluis 0:45c4f0364ca4 993 {
mluis 0:45c4f0364ca4 994 case RF_RX_RUNNING:
mluis 0:45c4f0364ca4 995 if( this->settings.Modem == MODEM_FSK )
mluis 0:45c4f0364ca4 996 {
mluis 0:45c4f0364ca4 997 this->settings.FskPacketHandler.PreambleDetected = false;
mluis 0:45c4f0364ca4 998 this->settings.FskPacketHandler.SyncWordDetected = false;
mluis 0:45c4f0364ca4 999 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 1000 this->settings.FskPacketHandler.Size = 0;
mluis 0:45c4f0364ca4 1001
mluis 0:45c4f0364ca4 1002 // Clear Irqs
mluis 0:45c4f0364ca4 1003 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
mluis 0:45c4f0364ca4 1004 RF_IRQFLAGS1_PREAMBLEDETECT |
mluis 0:45c4f0364ca4 1005 RF_IRQFLAGS1_SYNCADDRESSMATCH );
mluis 0:45c4f0364ca4 1006 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
mluis 0:45c4f0364ca4 1007
mluis 0:45c4f0364ca4 1008 if( this->settings.Fsk.RxContinuous == true )
mluis 0:45c4f0364ca4 1009 {
mluis 0:45c4f0364ca4 1010 // Continuous mode restart Rx chain
mluis 0:45c4f0364ca4 1011 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
mluis 0:45c4f0364ca4 1012 }
mluis 0:45c4f0364ca4 1013 else
mluis 0:45c4f0364ca4 1014 {
mluis 0:45c4f0364ca4 1015 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1016 rxTimeoutSyncWord.detach( );
mluis 0:45c4f0364ca4 1017 }
mluis 0:45c4f0364ca4 1018 }
mluis 0:45c4f0364ca4 1019 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
mluis 0:45c4f0364ca4 1020 {
mluis 0:45c4f0364ca4 1021 this->RadioEvents->RxTimeout( );
mluis 0:45c4f0364ca4 1022 }
mluis 0:45c4f0364ca4 1023 break;
mluis 0:45c4f0364ca4 1024 case RF_TX_RUNNING:
mluis 0:45c4f0364ca4 1025 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1026 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxTimeout != NULL ) )
mluis 0:45c4f0364ca4 1027 {
mluis 0:45c4f0364ca4 1028 this->RadioEvents->TxTimeout( );
mluis 0:45c4f0364ca4 1029 }
mluis 0:45c4f0364ca4 1030 break;
mluis 0:45c4f0364ca4 1031 default:
mluis 0:45c4f0364ca4 1032 break;
mluis 0:45c4f0364ca4 1033 }
mluis 0:45c4f0364ca4 1034 }
mluis 0:45c4f0364ca4 1035
mluis 0:45c4f0364ca4 1036 void SX1272::OnDio0Irq( void )
mluis 0:45c4f0364ca4 1037 {
mluis 0:45c4f0364ca4 1038 volatile uint8_t irqFlags = 0;
mluis 0:45c4f0364ca4 1039
mluis 0:45c4f0364ca4 1040 switch( this->settings.State )
mluis 0:45c4f0364ca4 1041 {
mluis 0:45c4f0364ca4 1042 case RF_RX_RUNNING:
mluis 0:45c4f0364ca4 1043 //TimerStop( &RxTimeoutTimer );
mluis 0:45c4f0364ca4 1044 // RxDone interrupt
mluis 0:45c4f0364ca4 1045 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1046 {
mluis 0:45c4f0364ca4 1047 case MODEM_FSK:
mluis 0:45c4f0364ca4 1048 if( this->settings.Fsk.CrcOn == true )
mluis 0:45c4f0364ca4 1049 {
mluis 0:45c4f0364ca4 1050 irqFlags = Read( REG_IRQFLAGS2 );
mluis 0:45c4f0364ca4 1051 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
mluis 0:45c4f0364ca4 1052 {
mluis 0:45c4f0364ca4 1053 // Clear Irqs
mluis 0:45c4f0364ca4 1054 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
mluis 0:45c4f0364ca4 1055 RF_IRQFLAGS1_PREAMBLEDETECT |
mluis 0:45c4f0364ca4 1056 RF_IRQFLAGS1_SYNCADDRESSMATCH );
mluis 0:45c4f0364ca4 1057 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
mluis 0:45c4f0364ca4 1058
mluis 0:45c4f0364ca4 1059 if( this->settings.Fsk.RxContinuous == false )
mluis 0:45c4f0364ca4 1060 {
mluis 0:45c4f0364ca4 1061 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1062 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
mluis 0:45c4f0364ca4 1063 ( ( Read( REG_SYNCCONFIG ) &
mluis 0:45c4f0364ca4 1064 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 0:45c4f0364ca4 1065 1.0 ) + 10.0 ) /
mluis 0:45c4f0364ca4 1066 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
mluis 0:45c4f0364ca4 1067 }
mluis 0:45c4f0364ca4 1068 else
mluis 0:45c4f0364ca4 1069 {
mluis 0:45c4f0364ca4 1070 // Continuous mode restart Rx chain
mluis 0:45c4f0364ca4 1071 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
mluis 0:45c4f0364ca4 1072 }
mluis 0:45c4f0364ca4 1073 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 1074
mluis 0:45c4f0364ca4 1075 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
mluis 0:45c4f0364ca4 1076 {
mluis 0:45c4f0364ca4 1077 this->RadioEvents->RxError( );
mluis 0:45c4f0364ca4 1078 }
mluis 0:45c4f0364ca4 1079 this->settings.FskPacketHandler.PreambleDetected = false;
mluis 0:45c4f0364ca4 1080 this->settings.FskPacketHandler.SyncWordDetected = false;
mluis 0:45c4f0364ca4 1081 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 1082 this->settings.FskPacketHandler.Size = 0;
mluis 0:45c4f0364ca4 1083 break;
mluis 0:45c4f0364ca4 1084 }
mluis 0:45c4f0364ca4 1085 }
mluis 0:45c4f0364ca4 1086
mluis 0:45c4f0364ca4 1087 // Read received packet size
mluis 0:45c4f0364ca4 1088 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
mluis 0:45c4f0364ca4 1089 {
mluis 0:45c4f0364ca4 1090 if( this->settings.Fsk.FixLen == false )
mluis 0:45c4f0364ca4 1091 {
mluis 0:45c4f0364ca4 1092 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
mluis 0:45c4f0364ca4 1093 }
mluis 0:45c4f0364ca4 1094 else
mluis 0:45c4f0364ca4 1095 {
mluis 0:45c4f0364ca4 1096 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
mluis 0:45c4f0364ca4 1097 }
mluis 0:45c4f0364ca4 1098 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1099 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1100 }
mluis 0:45c4f0364ca4 1101 else
mluis 0:45c4f0364ca4 1102 {
mluis 0:45c4f0364ca4 1103 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1104 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1105 }
mluis 0:45c4f0364ca4 1106
mluis 0:45c4f0364ca4 1107 if( this->settings.Fsk.RxContinuous == false )
mluis 0:45c4f0364ca4 1108 {
mluis 0:45c4f0364ca4 1109 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1110 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
mluis 0:45c4f0364ca4 1111 ( ( Read( REG_SYNCCONFIG ) &
mluis 0:45c4f0364ca4 1112 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 0:45c4f0364ca4 1113 1.0 ) + 10.0 ) /
mluis 0:45c4f0364ca4 1114 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
mluis 0:45c4f0364ca4 1115 }
mluis 0:45c4f0364ca4 1116 else
mluis 0:45c4f0364ca4 1117 {
mluis 0:45c4f0364ca4 1118 // Continuous mode restart Rx chain
mluis 0:45c4f0364ca4 1119 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
mluis 0:45c4f0364ca4 1120 }
mluis 0:45c4f0364ca4 1121 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 1122
mluis 0:45c4f0364ca4 1123 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
mluis 0:45c4f0364ca4 1124 {
mluis 0:45c4f0364ca4 1125 this->RadioEvents->RxDone( rxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
mluis 0:45c4f0364ca4 1126 }
mluis 0:45c4f0364ca4 1127 this->settings.FskPacketHandler.PreambleDetected = false;
mluis 0:45c4f0364ca4 1128 this->settings.FskPacketHandler.SyncWordDetected = false;
mluis 0:45c4f0364ca4 1129 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 1130 this->settings.FskPacketHandler.Size = 0;
mluis 0:45c4f0364ca4 1131 break;
mluis 0:45c4f0364ca4 1132 case MODEM_LORA:
mluis 0:45c4f0364ca4 1133 {
mluis 0:45c4f0364ca4 1134 int8_t snr = 0;
mluis 0:45c4f0364ca4 1135
mluis 0:45c4f0364ca4 1136 // Clear Irq
mluis 0:45c4f0364ca4 1137 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
mluis 0:45c4f0364ca4 1138
mluis 0:45c4f0364ca4 1139 irqFlags = Read( REG_LR_IRQFLAGS );
mluis 0:45c4f0364ca4 1140 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
mluis 0:45c4f0364ca4 1141 {
mluis 0:45c4f0364ca4 1142 // Clear Irq
mluis 0:45c4f0364ca4 1143 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
mluis 0:45c4f0364ca4 1144
mluis 0:45c4f0364ca4 1145 if( this->settings.LoRa.RxContinuous == false )
mluis 0:45c4f0364ca4 1146 {
mluis 0:45c4f0364ca4 1147 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1148 }
mluis 0:45c4f0364ca4 1149 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 1150
mluis 0:45c4f0364ca4 1151 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
mluis 0:45c4f0364ca4 1152 {
mluis 0:45c4f0364ca4 1153 this->RadioEvents->RxError( );
mluis 0:45c4f0364ca4 1154 }
mluis 0:45c4f0364ca4 1155 break;
mluis 0:45c4f0364ca4 1156 }
mluis 0:45c4f0364ca4 1157
mluis 0:45c4f0364ca4 1158 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
mluis 0:45c4f0364ca4 1159 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
mluis 0:45c4f0364ca4 1160 {
mluis 0:45c4f0364ca4 1161 // Invert and divide by 4
mluis 0:45c4f0364ca4 1162 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
mluis 0:45c4f0364ca4 1163 snr = -snr;
mluis 0:45c4f0364ca4 1164 }
mluis 0:45c4f0364ca4 1165 else
mluis 0:45c4f0364ca4 1166 {
mluis 0:45c4f0364ca4 1167 // Divide by 4
mluis 0:45c4f0364ca4 1168 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
mluis 0:45c4f0364ca4 1169 }
mluis 0:45c4f0364ca4 1170
mluis 0:45c4f0364ca4 1171 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
mluis 0:45c4f0364ca4 1172 if( snr < 0 )
mluis 0:45c4f0364ca4 1173 {
mluis 0:45c4f0364ca4 1174 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET + rssi + ( rssi >> 4 ) +
mluis 0:45c4f0364ca4 1175 snr;
mluis 0:45c4f0364ca4 1176 }
mluis 0:45c4f0364ca4 1177 else
mluis 0:45c4f0364ca4 1178 {
mluis 0:45c4f0364ca4 1179 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET + rssi + ( rssi >> 4 );
mluis 0:45c4f0364ca4 1180 }
mluis 0:45c4f0364ca4 1181
mluis 0:45c4f0364ca4 1182 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
mluis 0:45c4f0364ca4 1183 ReadFifo( rxBuffer, this->settings.LoRaPacketHandler.Size );
mluis 0:45c4f0364ca4 1184
mluis 0:45c4f0364ca4 1185 if( this->settings.LoRa.RxContinuous == false )
mluis 0:45c4f0364ca4 1186 {
mluis 0:45c4f0364ca4 1187 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1188 }
mluis 0:45c4f0364ca4 1189 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 1190
mluis 0:45c4f0364ca4 1191 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
mluis 0:45c4f0364ca4 1192 {
mluis 0:45c4f0364ca4 1193 this->RadioEvents->RxDone( rxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
mluis 0:45c4f0364ca4 1194 }
mluis 0:45c4f0364ca4 1195 }
mluis 0:45c4f0364ca4 1196 break;
mluis 0:45c4f0364ca4 1197 default:
mluis 0:45c4f0364ca4 1198 break;
mluis 0:45c4f0364ca4 1199 }
mluis 0:45c4f0364ca4 1200 break;
mluis 0:45c4f0364ca4 1201 case RF_TX_RUNNING:
mluis 0:45c4f0364ca4 1202 txTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 1203 // TxDone interrupt
mluis 0:45c4f0364ca4 1204 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1205 {
mluis 0:45c4f0364ca4 1206 case MODEM_LORA:
mluis 0:45c4f0364ca4 1207 // Clear Irq
mluis 0:45c4f0364ca4 1208 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
mluis 0:45c4f0364ca4 1209 // Intentional fall through
mluis 0:45c4f0364ca4 1210 case MODEM_FSK:
mluis 0:45c4f0364ca4 1211 default:
mluis 0:45c4f0364ca4 1212 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1213 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) )
mluis 0:45c4f0364ca4 1214 {
mluis 0:45c4f0364ca4 1215 this->RadioEvents->TxDone( );
mluis 0:45c4f0364ca4 1216 }
mluis 0:45c4f0364ca4 1217 break;
mluis 0:45c4f0364ca4 1218 }
mluis 0:45c4f0364ca4 1219 break;
mluis 0:45c4f0364ca4 1220 default:
mluis 0:45c4f0364ca4 1221 break;
mluis 0:45c4f0364ca4 1222 }
mluis 0:45c4f0364ca4 1223 }
mluis 0:45c4f0364ca4 1224
mluis 0:45c4f0364ca4 1225 void SX1272::OnDio1Irq( void )
mluis 0:45c4f0364ca4 1226 {
mluis 0:45c4f0364ca4 1227 switch( this->settings.State )
mluis 0:45c4f0364ca4 1228 {
mluis 0:45c4f0364ca4 1229 case RF_RX_RUNNING:
mluis 0:45c4f0364ca4 1230 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1231 {
mluis 0:45c4f0364ca4 1232 case MODEM_FSK:
mluis 0:45c4f0364ca4 1233 // FifoLevel interrupt
mluis 0:45c4f0364ca4 1234 // Read received packet size
mluis 0:45c4f0364ca4 1235 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
mluis 0:45c4f0364ca4 1236 {
mluis 0:45c4f0364ca4 1237 if( this->settings.Fsk.FixLen == false )
mluis 0:45c4f0364ca4 1238 {
mluis 0:45c4f0364ca4 1239 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
mluis 0:45c4f0364ca4 1240 }
mluis 0:45c4f0364ca4 1241 else
mluis 0:45c4f0364ca4 1242 {
mluis 0:45c4f0364ca4 1243 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
mluis 0:45c4f0364ca4 1244 }
mluis 0:45c4f0364ca4 1245 }
mluis 0:45c4f0364ca4 1246
mluis 0:45c4f0364ca4 1247 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
mluis 0:45c4f0364ca4 1248 {
mluis 0:45c4f0364ca4 1249 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
mluis 0:45c4f0364ca4 1250 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
mluis 0:45c4f0364ca4 1251 }
mluis 0:45c4f0364ca4 1252 else
mluis 0:45c4f0364ca4 1253 {
mluis 0:45c4f0364ca4 1254 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1255 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1256 }
mluis 0:45c4f0364ca4 1257 break;
mluis 0:45c4f0364ca4 1258 case MODEM_LORA:
mluis 0:45c4f0364ca4 1259 // Sync time out
mluis 0:45c4f0364ca4 1260 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 1261 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1262 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
mluis 0:45c4f0364ca4 1263 {
mluis 0:45c4f0364ca4 1264 this->RadioEvents->RxTimeout( );
mluis 0:45c4f0364ca4 1265 }
mluis 0:45c4f0364ca4 1266 break;
mluis 0:45c4f0364ca4 1267 default:
mluis 0:45c4f0364ca4 1268 break;
mluis 0:45c4f0364ca4 1269 }
mluis 0:45c4f0364ca4 1270 break;
mluis 0:45c4f0364ca4 1271 case RF_TX_RUNNING:
mluis 0:45c4f0364ca4 1272 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1273 {
mluis 0:45c4f0364ca4 1274 case MODEM_FSK:
mluis 0:45c4f0364ca4 1275 // FifoLevel interrupt
mluis 0:45c4f0364ca4 1276 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
mluis 0:45c4f0364ca4 1277 {
mluis 0:45c4f0364ca4 1278 WriteFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
mluis 0:45c4f0364ca4 1279 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
mluis 0:45c4f0364ca4 1280 }
mluis 0:45c4f0364ca4 1281 else
mluis 0:45c4f0364ca4 1282 {
mluis 0:45c4f0364ca4 1283 // Write the last chunk of data
mluis 0:45c4f0364ca4 1284 WriteFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1285 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
mluis 0:45c4f0364ca4 1286 }
mluis 0:45c4f0364ca4 1287 break;
mluis 0:45c4f0364ca4 1288 case MODEM_LORA:
mluis 0:45c4f0364ca4 1289 break;
mluis 0:45c4f0364ca4 1290 default:
mluis 0:45c4f0364ca4 1291 break;
mluis 0:45c4f0364ca4 1292 }
mluis 0:45c4f0364ca4 1293 break;
mluis 0:45c4f0364ca4 1294 default:
mluis 0:45c4f0364ca4 1295 break;
mluis 0:45c4f0364ca4 1296 }
mluis 0:45c4f0364ca4 1297 }
mluis 0:45c4f0364ca4 1298
mluis 0:45c4f0364ca4 1299 void SX1272::OnDio2Irq( void )
mluis 0:45c4f0364ca4 1300 {
mluis 0:45c4f0364ca4 1301 switch( this->settings.State )
mluis 0:45c4f0364ca4 1302 {
mluis 0:45c4f0364ca4 1303 case RF_RX_RUNNING:
mluis 0:45c4f0364ca4 1304 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1305 {
mluis 0:45c4f0364ca4 1306 case MODEM_FSK:
mluis 0:45c4f0364ca4 1307 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
mluis 0:45c4f0364ca4 1308 {
mluis 0:45c4f0364ca4 1309 rxTimeoutSyncWord.detach( );
mluis 0:45c4f0364ca4 1310
mluis 0:45c4f0364ca4 1311 this->settings.FskPacketHandler.SyncWordDetected = true;
mluis 0:45c4f0364ca4 1312
mluis 0:45c4f0364ca4 1313 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
mluis 0:45c4f0364ca4 1314
mluis 0:45c4f0364ca4 1315 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
mluis 0:45c4f0364ca4 1316 ( uint16_t )Read( REG_AFCLSB ) ) *
mluis 0:45c4f0364ca4 1317 ( double )FREQ_STEP;
mluis 0:45c4f0364ca4 1318 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
mluis 0:45c4f0364ca4 1319 }
mluis 0:45c4f0364ca4 1320 break;
mluis 0:45c4f0364ca4 1321 case MODEM_LORA:
mluis 0:45c4f0364ca4 1322 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 1323 {
mluis 0:45c4f0364ca4 1324 // Clear Irq
mluis 0:45c4f0364ca4 1325 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
mluis 0:45c4f0364ca4 1326
mluis 0:45c4f0364ca4 1327 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
mluis 0:45c4f0364ca4 1328 {
mluis 0:45c4f0364ca4 1329 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 0:45c4f0364ca4 1330 }
mluis 0:45c4f0364ca4 1331 }
mluis 0:45c4f0364ca4 1332 break;
mluis 0:45c4f0364ca4 1333 default:
mluis 0:45c4f0364ca4 1334 break;
mluis 0:45c4f0364ca4 1335 }
mluis 0:45c4f0364ca4 1336 break;
mluis 0:45c4f0364ca4 1337 case RF_TX_RUNNING:
mluis 0:45c4f0364ca4 1338 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1339 {
mluis 0:45c4f0364ca4 1340 case MODEM_FSK:
mluis 0:45c4f0364ca4 1341 break;
mluis 0:45c4f0364ca4 1342 case MODEM_LORA:
mluis 0:45c4f0364ca4 1343 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 1344 {
mluis 0:45c4f0364ca4 1345 // Clear Irq
mluis 0:45c4f0364ca4 1346 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
mluis 0:45c4f0364ca4 1347
mluis 0:45c4f0364ca4 1348 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
mluis 0:45c4f0364ca4 1349 {
mluis 0:45c4f0364ca4 1350 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 0:45c4f0364ca4 1351 }
mluis 0:45c4f0364ca4 1352 }
mluis 0:45c4f0364ca4 1353 break;
mluis 0:45c4f0364ca4 1354 default:
mluis 0:45c4f0364ca4 1355 break;
mluis 0:45c4f0364ca4 1356 }
mluis 0:45c4f0364ca4 1357 break;
mluis 0:45c4f0364ca4 1358 default:
mluis 0:45c4f0364ca4 1359 break;
mluis 0:45c4f0364ca4 1360 }
mluis 0:45c4f0364ca4 1361 }
mluis 0:45c4f0364ca4 1362
mluis 0:45c4f0364ca4 1363 void SX1272::OnDio3Irq( void )
mluis 0:45c4f0364ca4 1364 {
mluis 0:45c4f0364ca4 1365 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1366 {
mluis 0:45c4f0364ca4 1367 case MODEM_FSK:
mluis 0:45c4f0364ca4 1368 break;
mluis 0:45c4f0364ca4 1369 case MODEM_LORA:
mluis 0:45c4f0364ca4 1370 if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
mluis 0:45c4f0364ca4 1371 {
mluis 0:45c4f0364ca4 1372 // Clear Irq
mluis 0:45c4f0364ca4 1373 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
mluis 0:45c4f0364ca4 1374 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
mluis 0:45c4f0364ca4 1375 {
mluis 0:45c4f0364ca4 1376 this->RadioEvents->CadDone( true );
mluis 0:45c4f0364ca4 1377 }
mluis 0:45c4f0364ca4 1378 }
mluis 0:45c4f0364ca4 1379 else
mluis 0:45c4f0364ca4 1380 {
mluis 0:45c4f0364ca4 1381 // Clear Irq
mluis 0:45c4f0364ca4 1382 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
mluis 0:45c4f0364ca4 1383 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
mluis 0:45c4f0364ca4 1384 {
mluis 0:45c4f0364ca4 1385 this->RadioEvents->CadDone( false );
mluis 0:45c4f0364ca4 1386 }
mluis 0:45c4f0364ca4 1387 }
mluis 0:45c4f0364ca4 1388 break;
mluis 0:45c4f0364ca4 1389 default:
mluis 0:45c4f0364ca4 1390 break;
mluis 0:45c4f0364ca4 1391 }
mluis 0:45c4f0364ca4 1392 }
mluis 0:45c4f0364ca4 1393
mluis 0:45c4f0364ca4 1394 void SX1272::OnDio4Irq( void )
mluis 0:45c4f0364ca4 1395 {
mluis 0:45c4f0364ca4 1396 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1397 {
mluis 0:45c4f0364ca4 1398 case MODEM_FSK:
mluis 0:45c4f0364ca4 1399 {
mluis 0:45c4f0364ca4 1400 if( this->settings.FskPacketHandler.PreambleDetected == false )
mluis 0:45c4f0364ca4 1401 {
mluis 0:45c4f0364ca4 1402 this->settings.FskPacketHandler.PreambleDetected = true;
mluis 0:45c4f0364ca4 1403 }
mluis 0:45c4f0364ca4 1404 }
mluis 0:45c4f0364ca4 1405 break;
mluis 0:45c4f0364ca4 1406 case MODEM_LORA:
mluis 0:45c4f0364ca4 1407 break;
mluis 0:45c4f0364ca4 1408 default:
mluis 0:45c4f0364ca4 1409 break;
mluis 0:45c4f0364ca4 1410 }
mluis 0:45c4f0364ca4 1411 }
mluis 0:45c4f0364ca4 1412
mluis 0:45c4f0364ca4 1413 void SX1272::OnDio5Irq( void )
mluis 0:45c4f0364ca4 1414 {
mluis 0:45c4f0364ca4 1415 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1416 {
mluis 0:45c4f0364ca4 1417 case MODEM_FSK:
mluis 0:45c4f0364ca4 1418 break;
mluis 0:45c4f0364ca4 1419 case MODEM_LORA:
mluis 0:45c4f0364ca4 1420 break;
mluis 0:45c4f0364ca4 1421 default:
mluis 0:45c4f0364ca4 1422 break;
mluis 0:45c4f0364ca4 1423 }
mluis 0:45c4f0364ca4 1424 }