Timothy Mulrooney / SX1272Liby

first draft

Dependents:   LoRaWAN-demo-72_tjm frdm_LoRa_Connect_Woodstream_Demo_tjm frdm_LoRa_Connect_Woodstream_Demo_jlc

Fork of SX1272Lib by Semtech

sx1272/sx1272.cpp@3:73a1f904eaa5, 2016-03-09 (annotated)

Committer:
tmulrooney
Date:
Wed Mar 09 15:13:46 2016 +0000
Revision:
3:73a1f904eaa5
Parent:
0:45c4f0364ca4
Child:
5:e6a3f05e4743
first draft

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mluis 0:45c4f0364ca4 1 /*
mluis 0:45c4f0364ca4 2 / _____) _ | |
mluis 0:45c4f0364ca4 3 ( (____ _____ ____ _| |_ _____ ____| |__
mluis 0:45c4f0364ca4 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
mluis 0:45c4f0364ca4 5 _____) ) ____| | | || |_| ____( (___| | | |
mluis 0:45c4f0364ca4 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 0:45c4f0364ca4 7 (C) 2015 Semtech
mluis 0:45c4f0364ca4 8
mluis 0:45c4f0364ca4 9 Description: Actual implementation of a SX1272 radio, inherits Radio
mluis 0:45c4f0364ca4 10
mluis 0:45c4f0364ca4 11 License: Revised BSD License, see LICENSE.TXT file include in the project
mluis 0:45c4f0364ca4 12
mluis 0:45c4f0364ca4 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
mluis 0:45c4f0364ca4 14 */
mluis 0:45c4f0364ca4 15 #include "sx1272.h"
mluis 0:45c4f0364ca4 16
mluis 0:45c4f0364ca4 17 const FskBandwidth_t SX1272::FskBandwidths[] =
mluis 0:45c4f0364ca4 18 {
mluis 0:45c4f0364ca4 19 { 2600 , 0x17 },
mluis 0:45c4f0364ca4 20 { 3100 , 0x0F },
mluis 0:45c4f0364ca4 21 { 3900 , 0x07 },
mluis 0:45c4f0364ca4 22 { 5200 , 0x16 },
mluis 0:45c4f0364ca4 23 { 6300 , 0x0E },
mluis 0:45c4f0364ca4 24 { 7800 , 0x06 },
mluis 0:45c4f0364ca4 25 { 10400 , 0x15 },
mluis 0:45c4f0364ca4 26 { 12500 , 0x0D },
mluis 0:45c4f0364ca4 27 { 15600 , 0x05 },
mluis 0:45c4f0364ca4 28 { 20800 , 0x14 },
mluis 0:45c4f0364ca4 29 { 25000 , 0x0C },
mluis 0:45c4f0364ca4 30 { 31300 , 0x04 },
mluis 0:45c4f0364ca4 31 { 41700 , 0x13 },
mluis 0:45c4f0364ca4 32 { 50000 , 0x0B },
mluis 0:45c4f0364ca4 33 { 62500 , 0x03 },
mluis 0:45c4f0364ca4 34 { 83333 , 0x12 },
mluis 0:45c4f0364ca4 35 { 100000, 0x0A },
mluis 0:45c4f0364ca4 36 { 125000, 0x02 },
mluis 0:45c4f0364ca4 37 { 166700, 0x11 },
mluis 0:45c4f0364ca4 38 { 200000, 0x09 },
mluis 0:45c4f0364ca4 39 { 250000, 0x01 },
mluis 0:45c4f0364ca4 40 { 300000, 0x00 }, // Invalid Badwidth
mluis 0:45c4f0364ca4 41 };
mluis 0:45c4f0364ca4 42
mluis 0:45c4f0364ca4 43
mluis 0:45c4f0364ca4 44 SX1272::SX1272( RadioEvents_t *events,
mluis 0:45c4f0364ca4 45 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
mluis 0:45c4f0364ca4 46 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
mluis 0:45c4f0364ca4 47 : Radio( events ),
tmulrooney 3:73a1f904eaa5 48 // spi( mosi, miso, sclk ),
tmulrooney 3:73a1f904eaa5 49 // nss( nss ),
tmulrooney 3:73a1f904eaa5 50 spi( PTD6, PTD7, PTD5 ),
tmulrooney 3:73a1f904eaa5 51 nss( PTD4 ),
mluis 0:45c4f0364ca4 52 reset( reset ),
tmulrooney 3:73a1f904eaa5 53 // dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ),
tmulrooney 3:73a1f904eaa5 54 dio0( PTC2 ), dio1( PTB1 ), dio2( PTC3 ), dio3( PTB0 ), dio4( PTC4 ), dio5( PTC1 ),
mluis 0:45c4f0364ca4 55 isRadioActive( false )
mluis 0:45c4f0364ca4 56 {
mluis 0:45c4f0364ca4 57 wait_ms( 10 );
mluis 0:45c4f0364ca4 58 this->rxTx = 0;
mluis 0:45c4f0364ca4 59 this->rxBuffer = new uint8_t[RX_BUFFER_SIZE];
mluis 0:45c4f0364ca4 60 currentOpMode = RF_OPMODE_STANDBY;
mluis 0:45c4f0364ca4 61
mluis 0:45c4f0364ca4 62 this->RadioEvents = events;
mluis 0:45c4f0364ca4 63
mluis 0:45c4f0364ca4 64 this->dioIrq = new DioIrqHandler[6];
mluis 0:45c4f0364ca4 65
mluis 0:45c4f0364ca4 66 this->dioIrq[0] = &SX1272::OnDio0Irq;
mluis 0:45c4f0364ca4 67 this->dioIrq[1] = &SX1272::OnDio1Irq;
mluis 0:45c4f0364ca4 68 this->dioIrq[2] = &SX1272::OnDio2Irq;
mluis 0:45c4f0364ca4 69 this->dioIrq[3] = &SX1272::OnDio3Irq;
mluis 0:45c4f0364ca4 70 this->dioIrq[4] = &SX1272::OnDio4Irq;
mluis 0:45c4f0364ca4 71 this->dioIrq[5] = NULL;
mluis 0:45c4f0364ca4 72
mluis 0:45c4f0364ca4 73 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 74 }
mluis 0:45c4f0364ca4 75
mluis 0:45c4f0364ca4 76 SX1272::~SX1272( )
mluis 0:45c4f0364ca4 77 {
mluis 0:45c4f0364ca4 78 delete this->rxBuffer;
mluis 0:45c4f0364ca4 79 delete this->dioIrq;
mluis 0:45c4f0364ca4 80 }
mluis 0:45c4f0364ca4 81
mluis 0:45c4f0364ca4 82 void SX1272::Init( RadioEvents_t *events )
mluis 0:45c4f0364ca4 83 {
mluis 0:45c4f0364ca4 84 this->RadioEvents = events;
mluis 0:45c4f0364ca4 85 }
mluis 0:45c4f0364ca4 86
mluis 0:45c4f0364ca4 87 RadioState SX1272::GetStatus( void )
mluis 0:45c4f0364ca4 88 {
mluis 0:45c4f0364ca4 89 return this->settings.State;
mluis 0:45c4f0364ca4 90 }
mluis 0:45c4f0364ca4 91
mluis 0:45c4f0364ca4 92 void SX1272::SetChannel( uint32_t freq )
mluis 0:45c4f0364ca4 93 {
mluis 0:45c4f0364ca4 94 this->settings.Channel = freq;
mluis 0:45c4f0364ca4 95 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
mluis 0:45c4f0364ca4 96 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
mluis 0:45c4f0364ca4 97 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
mluis 0:45c4f0364ca4 98 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
mluis 0:45c4f0364ca4 99 }
mluis 0:45c4f0364ca4 100
mluis 0:45c4f0364ca4 101 bool SX1272::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh )
mluis 0:45c4f0364ca4 102 {
mluis 0:45c4f0364ca4 103 int16_t rssi = 0;
mluis 0:45c4f0364ca4 104
mluis 0:45c4f0364ca4 105 SetModem( modem );
mluis 0:45c4f0364ca4 106
mluis 0:45c4f0364ca4 107 SetChannel( freq );
mluis 0:45c4f0364ca4 108
mluis 0:45c4f0364ca4 109 SetOpMode( RF_OPMODE_RECEIVER );
mluis 0:45c4f0364ca4 110
mluis 0:45c4f0364ca4 111 wait_ms( 1 );
mluis 0:45c4f0364ca4 112
mluis 0:45c4f0364ca4 113 rssi = GetRssi( modem );
mluis 0:45c4f0364ca4 114
mluis 0:45c4f0364ca4 115 Sleep( );
mluis 0:45c4f0364ca4 116
mluis 0:45c4f0364ca4 117 if( rssi > rssiThresh )
mluis 0:45c4f0364ca4 118 {
mluis 0:45c4f0364ca4 119 return false;
mluis 0:45c4f0364ca4 120 }
mluis 0:45c4f0364ca4 121 return true;
mluis 0:45c4f0364ca4 122 }
mluis 0:45c4f0364ca4 123
mluis 0:45c4f0364ca4 124 uint32_t SX1272::Random( void )
mluis 0:45c4f0364ca4 125 {
mluis 0:45c4f0364ca4 126 uint8_t i;
mluis 0:45c4f0364ca4 127 uint32_t rnd = 0;
mluis 0:45c4f0364ca4 128
mluis 0:45c4f0364ca4 129 /*
mluis 0:45c4f0364ca4 130 * Radio setup for random number generation
mluis 0:45c4f0364ca4 131 */
mluis 0:45c4f0364ca4 132 // Set LoRa modem ON
mluis 0:45c4f0364ca4 133 SetModem( MODEM_LORA );
mluis 0:45c4f0364ca4 134
mluis 0:45c4f0364ca4 135 // Disable LoRa modem interrupts
mluis 0:45c4f0364ca4 136 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 137 RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 138 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 139 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 140 RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 141 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 142 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 143 RFLR_IRQFLAGS_CADDETECTED );
mluis 0:45c4f0364ca4 144
mluis 0:45c4f0364ca4 145 // Set radio in continuous reception
mluis 0:45c4f0364ca4 146 SetOpMode( RF_OPMODE_RECEIVER );
mluis 0:45c4f0364ca4 147
mluis 0:45c4f0364ca4 148 for( i = 0; i < 32; i++ )
mluis 0:45c4f0364ca4 149 {
mluis 0:45c4f0364ca4 150 wait_ms( 1 );
mluis 0:45c4f0364ca4 151 // Unfiltered RSSI value reading. Only takes the LSB value
mluis 0:45c4f0364ca4 152 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
mluis 0:45c4f0364ca4 153 }
mluis 0:45c4f0364ca4 154
mluis 0:45c4f0364ca4 155 Sleep( );
mluis 0:45c4f0364ca4 156
mluis 0:45c4f0364ca4 157 return rnd;
mluis 0:45c4f0364ca4 158 }
mluis 0:45c4f0364ca4 159
mluis 0:45c4f0364ca4 160 /*!
mluis 0:45c4f0364ca4 161 * Returns the known FSK bandwidth registers value
mluis 0:45c4f0364ca4 162 *
mluis 0:45c4f0364ca4 163 * \param [IN] bandwidth Bandwidth value in Hz
mluis 0:45c4f0364ca4 164 * \retval regValue Bandwidth register value.
mluis 0:45c4f0364ca4 165 */
mluis 0:45c4f0364ca4 166 uint8_t SX1272::GetFskBandwidthRegValue( uint32_t bandwidth )
mluis 0:45c4f0364ca4 167 {
mluis 0:45c4f0364ca4 168 uint8_t i;
mluis 0:45c4f0364ca4 169
mluis 0:45c4f0364ca4 170 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
mluis 0:45c4f0364ca4 171 {
mluis 0:45c4f0364ca4 172 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
mluis 0:45c4f0364ca4 173 {
mluis 0:45c4f0364ca4 174 return FskBandwidths[i].RegValue;
mluis 0:45c4f0364ca4 175 }
mluis 0:45c4f0364ca4 176 }
mluis 0:45c4f0364ca4 177 // ERROR: Value not found
mluis 0:45c4f0364ca4 178 while( 1 );
mluis 0:45c4f0364ca4 179 }
mluis 0:45c4f0364ca4 180
mluis 0:45c4f0364ca4 181 void SX1272::SetRxConfig( RadioModems_t modem, uint32_t bandwidth,
mluis 0:45c4f0364ca4 182 uint32_t datarate, uint8_t coderate,
mluis 0:45c4f0364ca4 183 uint32_t bandwidthAfc, uint16_t preambleLen,
mluis 0:45c4f0364ca4 184 uint16_t symbTimeout, bool fixLen,
mluis 0:45c4f0364ca4 185 uint8_t payloadLen,
mluis 0:45c4f0364ca4 186 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
mluis 0:45c4f0364ca4 187 bool iqInverted, bool rxContinuous )
mluis 0:45c4f0364ca4 188 {
mluis 0:45c4f0364ca4 189 SetModem( modem );
mluis 0:45c4f0364ca4 190
mluis 0:45c4f0364ca4 191 switch( modem )
mluis 0:45c4f0364ca4 192 {
mluis 0:45c4f0364ca4 193 case MODEM_FSK:
mluis 0:45c4f0364ca4 194 {
mluis 0:45c4f0364ca4 195 this->settings.Fsk.Bandwidth = bandwidth;
mluis 0:45c4f0364ca4 196 this->settings.Fsk.Datarate = datarate;
mluis 0:45c4f0364ca4 197 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
mluis 0:45c4f0364ca4 198 this->settings.Fsk.FixLen = fixLen;
mluis 0:45c4f0364ca4 199 this->settings.Fsk.PayloadLen = payloadLen;
mluis 0:45c4f0364ca4 200 this->settings.Fsk.CrcOn = crcOn;
mluis 0:45c4f0364ca4 201 this->settings.Fsk.IqInverted = iqInverted;
mluis 0:45c4f0364ca4 202 this->settings.Fsk.RxContinuous = rxContinuous;
mluis 0:45c4f0364ca4 203 this->settings.Fsk.PreambleLen = preambleLen;
mluis 0:45c4f0364ca4 204
mluis 0:45c4f0364ca4 205 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
mluis 0:45c4f0364ca4 206 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
mluis 0:45c4f0364ca4 207 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
mluis 0:45c4f0364ca4 208
mluis 0:45c4f0364ca4 209 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
mluis 0:45c4f0364ca4 210 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
mluis 0:45c4f0364ca4 211
mluis 0:45c4f0364ca4 212 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
mluis 0:45c4f0364ca4 213 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
mluis 0:45c4f0364ca4 214
mluis 0:45c4f0364ca4 215 if( fixLen == 1 )
mluis 0:45c4f0364ca4 216 {
mluis 0:45c4f0364ca4 217 Write( REG_PAYLOADLENGTH, payloadLen );
mluis 0:45c4f0364ca4 218 }
mluis 0:45c4f0364ca4 219
mluis 0:45c4f0364ca4 220 Write( REG_PACKETCONFIG1,
mluis 0:45c4f0364ca4 221 ( Read( REG_PACKETCONFIG1 ) &
mluis 0:45c4f0364ca4 222 RF_PACKETCONFIG1_CRC_MASK &
mluis 0:45c4f0364ca4 223 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
mluis 0:45c4f0364ca4 224 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
mluis 0:45c4f0364ca4 225 ( crcOn << 4 ) );
mluis 0:45c4f0364ca4 226 }
mluis 0:45c4f0364ca4 227 break;
mluis 0:45c4f0364ca4 228 case MODEM_LORA:
mluis 0:45c4f0364ca4 229 {
mluis 0:45c4f0364ca4 230 this->settings.LoRa.Bandwidth = bandwidth;
mluis 0:45c4f0364ca4 231 this->settings.LoRa.Datarate = datarate;
mluis 0:45c4f0364ca4 232 this->settings.LoRa.Coderate = coderate;
mluis 0:45c4f0364ca4 233 this->settings.LoRa.PreambleLen = preambleLen;
mluis 0:45c4f0364ca4 234 this->settings.LoRa.FixLen = fixLen;
mluis 0:45c4f0364ca4 235 this->settings.LoRa.PayloadLen = payloadLen;
mluis 0:45c4f0364ca4 236 this->settings.LoRa.CrcOn = crcOn;
mluis 0:45c4f0364ca4 237 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 0:45c4f0364ca4 238 this->settings.LoRa.HopPeriod = hopPeriod;
mluis 0:45c4f0364ca4 239 this->settings.LoRa.IqInverted = iqInverted;
mluis 0:45c4f0364ca4 240 this->settings.LoRa.RxContinuous = rxContinuous;
mluis 0:45c4f0364ca4 241
mluis 0:45c4f0364ca4 242 if( datarate > 12 )
mluis 0:45c4f0364ca4 243 {
mluis 0:45c4f0364ca4 244 datarate = 12;
mluis 0:45c4f0364ca4 245 }
mluis 0:45c4f0364ca4 246 else if( datarate < 6 )
mluis 0:45c4f0364ca4 247 {
mluis 0:45c4f0364ca4 248 datarate = 6;
mluis 0:45c4f0364ca4 249 }
mluis 0:45c4f0364ca4 250
mluis 0:45c4f0364ca4 251 if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
mluis 0:45c4f0364ca4 252 ( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
mluis 0:45c4f0364ca4 253 {
mluis 0:45c4f0364ca4 254 this->settings.LoRa.LowDatarateOptimize = 0x01;
mluis 0:45c4f0364ca4 255 }
mluis 0:45c4f0364ca4 256 else
mluis 0:45c4f0364ca4 257 {
mluis 0:45c4f0364ca4 258 this->settings.LoRa.LowDatarateOptimize = 0x00;
mluis 0:45c4f0364ca4 259 }
mluis 0:45c4f0364ca4 260
mluis 0:45c4f0364ca4 261 Write( REG_LR_MODEMCONFIG1,
mluis 0:45c4f0364ca4 262 ( Read( REG_LR_MODEMCONFIG1 ) &
mluis 0:45c4f0364ca4 263 RFLR_MODEMCONFIG1_BW_MASK &
mluis 0:45c4f0364ca4 264 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
mluis 0:45c4f0364ca4 265 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK &
mluis 0:45c4f0364ca4 266 RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK &
mluis 0:45c4f0364ca4 267 RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 268 ( bandwidth << 6 ) | ( coderate << 3 ) |
mluis 0:45c4f0364ca4 269 ( fixLen << 2 ) | ( crcOn << 1 ) |
mluis 0:45c4f0364ca4 270 this->settings.LoRa.LowDatarateOptimize );
mluis 0:45c4f0364ca4 271
mluis 0:45c4f0364ca4 272 Write( REG_LR_MODEMCONFIG2,
mluis 0:45c4f0364ca4 273 ( Read( REG_LR_MODEMCONFIG2 ) &
mluis 0:45c4f0364ca4 274 RFLR_MODEMCONFIG2_SF_MASK &
mluis 0:45c4f0364ca4 275 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
mluis 0:45c4f0364ca4 276 ( datarate << 4 ) |
mluis 0:45c4f0364ca4 277 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
mluis 0:45c4f0364ca4 278
mluis 0:45c4f0364ca4 279 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
mluis 0:45c4f0364ca4 280
mluis 0:45c4f0364ca4 281 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
mluis 0:45c4f0364ca4 282 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
mluis 0:45c4f0364ca4 283
mluis 0:45c4f0364ca4 284 if( fixLen == 1 )
mluis 0:45c4f0364ca4 285 {
mluis 0:45c4f0364ca4 286 Write( REG_LR_PAYLOADLENGTH, payloadLen );
mluis 0:45c4f0364ca4 287 }
mluis 0:45c4f0364ca4 288
mluis 0:45c4f0364ca4 289 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 290 {
mluis 0:45c4f0364ca4 291 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
mluis 0:45c4f0364ca4 292 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
mluis 0:45c4f0364ca4 293 }
mluis 0:45c4f0364ca4 294
mluis 0:45c4f0364ca4 295 if( datarate == 6 )
mluis 0:45c4f0364ca4 296 {
mluis 0:45c4f0364ca4 297 Write( REG_LR_DETECTOPTIMIZE,
mluis 0:45c4f0364ca4 298 ( Read( REG_LR_DETECTOPTIMIZE ) &
mluis 0:45c4f0364ca4 299 RFLR_DETECTIONOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 300 RFLR_DETECTIONOPTIMIZE_SF6 );
mluis 0:45c4f0364ca4 301 Write( REG_LR_DETECTIONTHRESHOLD,
mluis 0:45c4f0364ca4 302 RFLR_DETECTIONTHRESH_SF6 );
mluis 0:45c4f0364ca4 303 }
mluis 0:45c4f0364ca4 304 else
mluis 0:45c4f0364ca4 305 {
mluis 0:45c4f0364ca4 306 Write( REG_LR_DETECTOPTIMIZE,
mluis 0:45c4f0364ca4 307 ( Read( REG_LR_DETECTOPTIMIZE ) &
mluis 0:45c4f0364ca4 308 RFLR_DETECTIONOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 309 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
mluis 0:45c4f0364ca4 310 Write( REG_LR_DETECTIONTHRESHOLD,
mluis 0:45c4f0364ca4 311 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
mluis 0:45c4f0364ca4 312 }
mluis 0:45c4f0364ca4 313 }
mluis 0:45c4f0364ca4 314 break;
mluis 0:45c4f0364ca4 315 }
mluis 0:45c4f0364ca4 316 }
mluis 0:45c4f0364ca4 317 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 318 /* PD_2=0 PD_2=1
mluis 0:45c4f0364ca4 319 op PaB rfo rfo
mluis 0:45c4f0364ca4 320 0 4.6 18.5 27.0
mluis 0:45c4f0364ca4 321 1 5.6 21.1 28.1
mluis 0:45c4f0364ca4 322 2 6.7 23.3 29.1
mluis 0:45c4f0364ca4 323 3 7.7 25.3 30.1
mluis 0:45c4f0364ca4 324 4 8.8 26.2 30.7
mluis 0:45c4f0364ca4 325 5 9.8 27.3 31.2
mluis 0:45c4f0364ca4 326 6 10.7 28.1 31.6
mluis 0:45c4f0364ca4 327 7 11.7 28.6 32.2
mluis 0:45c4f0364ca4 328 8 12.8 29.2 32.4
mluis 0:45c4f0364ca4 329 9 13.7 29.9 32.9
mluis 0:45c4f0364ca4 330 10 14.7 30.5 33.1
mluis 0:45c4f0364ca4 331 11 15.6 30.8 33.4
mluis 0:45c4f0364ca4 332 12 16.4 30.9 33.6
mluis 0:45c4f0364ca4 333 13 17.1 31.0 33.7
mluis 0:45c4f0364ca4 334 14 17.8 31.1 33.7
mluis 0:45c4f0364ca4 335 15 18.4 31.1 33.7
mluis 0:45c4f0364ca4 336 */
mluis 0:45c4f0364ca4 337 // txpow: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
mluis 0:45c4f0364ca4 338 static const uint8_t PaBTable[20] = { 0, 0, 0, 0, 0, 1, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15 };
mluis 0:45c4f0364ca4 339
mluis 0:45c4f0364ca4 340 // txpow: 20 21 22 23 24 25 26 27 28 29 30
mluis 0:45c4f0364ca4 341 static const uint8_t RfoTable[11] = { 1, 1, 1, 2, 2, 3, 4, 5, 6, 8, 9 };
mluis 0:45c4f0364ca4 342 #endif
mluis 0:45c4f0364ca4 343
mluis 0:45c4f0364ca4 344 void SX1272::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
mluis 0:45c4f0364ca4 345 uint32_t bandwidth, uint32_t datarate,
mluis 0:45c4f0364ca4 346 uint8_t coderate, uint16_t preambleLen,
mluis 0:45c4f0364ca4 347 bool fixLen, bool crcOn, bool freqHopOn,
mluis 0:45c4f0364ca4 348 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
mluis 0:45c4f0364ca4 349 {
mluis 0:45c4f0364ca4 350 uint8_t paConfig = 0;
mluis 0:45c4f0364ca4 351 uint8_t paDac = 0;
mluis 0:45c4f0364ca4 352
mluis 0:45c4f0364ca4 353 SetModem( modem );
mluis 0:45c4f0364ca4 354
mluis 0:45c4f0364ca4 355 paConfig = Read( REG_PACONFIG );
mluis 0:45c4f0364ca4 356 paDac = Read( REG_PADAC );
mluis 0:45c4f0364ca4 357
mluis 0:45c4f0364ca4 358 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 359 if( power > 19 )
mluis 0:45c4f0364ca4 360 {
mluis 0:45c4f0364ca4 361 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | RF_PACONFIG_PASELECT_RFO;
mluis 0:45c4f0364ca4 362 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | RfoTable[power - 20];
mluis 0:45c4f0364ca4 363 }
mluis 0:45c4f0364ca4 364 else
mluis 0:45c4f0364ca4 365 {
mluis 0:45c4f0364ca4 366 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | RF_PACONFIG_PASELECT_PABOOST;
mluis 0:45c4f0364ca4 367 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | PaBTable[power];
mluis 0:45c4f0364ca4 368 }
mluis 0:45c4f0364ca4 369 #else
mluis 0:45c4f0364ca4 370 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
mluis 0:45c4f0364ca4 371
mluis 0:45c4f0364ca4 372 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
mluis 0:45c4f0364ca4 373 {
mluis 0:45c4f0364ca4 374 if( power > 17 )
mluis 0:45c4f0364ca4 375 {
mluis 0:45c4f0364ca4 376 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
mluis 0:45c4f0364ca4 377 }
mluis 0:45c4f0364ca4 378 else
mluis 0:45c4f0364ca4 379 {
mluis 0:45c4f0364ca4 380 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
mluis 0:45c4f0364ca4 381 }
mluis 0:45c4f0364ca4 382 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
mluis 0:45c4f0364ca4 383 {
mluis 0:45c4f0364ca4 384 if( power < 5 )
mluis 0:45c4f0364ca4 385 {
mluis 0:45c4f0364ca4 386 power = 5;
mluis 0:45c4f0364ca4 387 }
mluis 0:45c4f0364ca4 388 if( power > 20 )
mluis 0:45c4f0364ca4 389 {
mluis 0:45c4f0364ca4 390 power = 20;
mluis 0:45c4f0364ca4 391 }
mluis 0:45c4f0364ca4 392 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
mluis 0:45c4f0364ca4 393 }
mluis 0:45c4f0364ca4 394 else
mluis 0:45c4f0364ca4 395 {
mluis 0:45c4f0364ca4 396 if( power < 2 )
mluis 0:45c4f0364ca4 397 {
mluis 0:45c4f0364ca4 398 power = 2;
mluis 0:45c4f0364ca4 399 }
mluis 0:45c4f0364ca4 400 if( power > 17 )
mluis 0:45c4f0364ca4 401 {
mluis 0:45c4f0364ca4 402 power = 17;
mluis 0:45c4f0364ca4 403 }
mluis 0:45c4f0364ca4 404 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
mluis 0:45c4f0364ca4 405 }
mluis 0:45c4f0364ca4 406 }
mluis 0:45c4f0364ca4 407 else
mluis 0:45c4f0364ca4 408 {
mluis 0:45c4f0364ca4 409 if( power < -1 )
mluis 0:45c4f0364ca4 410 {
mluis 0:45c4f0364ca4 411 power = -1;
mluis 0:45c4f0364ca4 412 }
mluis 0:45c4f0364ca4 413 if( power > 14 )
mluis 0:45c4f0364ca4 414 {
mluis 0:45c4f0364ca4 415 power = 14;
mluis 0:45c4f0364ca4 416 }
mluis 0:45c4f0364ca4 417 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
mluis 0:45c4f0364ca4 418 }
mluis 0:45c4f0364ca4 419 #endif
mluis 0:45c4f0364ca4 420
mluis 0:45c4f0364ca4 421 Write( REG_PACONFIG, paConfig );
mluis 0:45c4f0364ca4 422 Write( REG_PADAC, paDac );
mluis 0:45c4f0364ca4 423
mluis 0:45c4f0364ca4 424 switch( modem )
mluis 0:45c4f0364ca4 425 {
mluis 0:45c4f0364ca4 426 case MODEM_FSK:
mluis 0:45c4f0364ca4 427 {
mluis 0:45c4f0364ca4 428 this->settings.Fsk.Power = power;
mluis 0:45c4f0364ca4 429 this->settings.Fsk.Fdev = fdev;
mluis 0:45c4f0364ca4 430 this->settings.Fsk.Bandwidth = bandwidth;
mluis 0:45c4f0364ca4 431 this->settings.Fsk.Datarate = datarate;
mluis 0:45c4f0364ca4 432 this->settings.Fsk.PreambleLen = preambleLen;
mluis 0:45c4f0364ca4 433 this->settings.Fsk.FixLen = fixLen;
mluis 0:45c4f0364ca4 434 this->settings.Fsk.CrcOn = crcOn;
mluis 0:45c4f0364ca4 435 this->settings.Fsk.IqInverted = iqInverted;
mluis 0:45c4f0364ca4 436 this->settings.Fsk.TxTimeout = timeout;
mluis 0:45c4f0364ca4 437
mluis 0:45c4f0364ca4 438 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
mluis 0:45c4f0364ca4 439 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
mluis 0:45c4f0364ca4 440 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
mluis 0:45c4f0364ca4 441
mluis 0:45c4f0364ca4 442 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
mluis 0:45c4f0364ca4 443 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
mluis 0:45c4f0364ca4 444 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
mluis 0:45c4f0364ca4 445
mluis 0:45c4f0364ca4 446 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
mluis 0:45c4f0364ca4 447 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
mluis 0:45c4f0364ca4 448
mluis 0:45c4f0364ca4 449 Write( REG_PACKETCONFIG1,
mluis 0:45c4f0364ca4 450 ( Read( REG_PACKETCONFIG1 ) &
mluis 0:45c4f0364ca4 451 RF_PACKETCONFIG1_CRC_MASK &
mluis 0:45c4f0364ca4 452 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
mluis 0:45c4f0364ca4 453 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
mluis 0:45c4f0364ca4 454 ( crcOn << 4 ) );
mluis 0:45c4f0364ca4 455
mluis 0:45c4f0364ca4 456 }
mluis 0:45c4f0364ca4 457 break;
mluis 0:45c4f0364ca4 458 case MODEM_LORA:
mluis 0:45c4f0364ca4 459 {
mluis 0:45c4f0364ca4 460 this->settings.LoRa.Power = power;
mluis 0:45c4f0364ca4 461 this->settings.LoRa.Bandwidth = bandwidth;
mluis 0:45c4f0364ca4 462 this->settings.LoRa.Datarate = datarate;
mluis 0:45c4f0364ca4 463 this->settings.LoRa.Coderate = coderate;
mluis 0:45c4f0364ca4 464 this->settings.LoRa.PreambleLen = preambleLen;
mluis 0:45c4f0364ca4 465 this->settings.LoRa.FixLen = fixLen;
mluis 0:45c4f0364ca4 466 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 0:45c4f0364ca4 467 this->settings.LoRa.HopPeriod = hopPeriod;
mluis 0:45c4f0364ca4 468 this->settings.LoRa.CrcOn = crcOn;
mluis 0:45c4f0364ca4 469 this->settings.LoRa.IqInverted = iqInverted;
mluis 0:45c4f0364ca4 470 this->settings.LoRa.TxTimeout = timeout;
mluis 0:45c4f0364ca4 471
mluis 0:45c4f0364ca4 472 if( datarate > 12 )
mluis 0:45c4f0364ca4 473 {
mluis 0:45c4f0364ca4 474 datarate = 12;
mluis 0:45c4f0364ca4 475 }
mluis 0:45c4f0364ca4 476 else if( datarate < 6 )
mluis 0:45c4f0364ca4 477 {
mluis 0:45c4f0364ca4 478 datarate = 6;
mluis 0:45c4f0364ca4 479 }
mluis 0:45c4f0364ca4 480 if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
mluis 0:45c4f0364ca4 481 ( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
mluis 0:45c4f0364ca4 482 {
mluis 0:45c4f0364ca4 483 this->settings.LoRa.LowDatarateOptimize = 0x01;
mluis 0:45c4f0364ca4 484 }
mluis 0:45c4f0364ca4 485 else
mluis 0:45c4f0364ca4 486 {
mluis 0:45c4f0364ca4 487 this->settings.LoRa.LowDatarateOptimize = 0x00;
mluis 0:45c4f0364ca4 488 }
mluis 0:45c4f0364ca4 489
mluis 0:45c4f0364ca4 490 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 491 {
mluis 0:45c4f0364ca4 492 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
mluis 0:45c4f0364ca4 493 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
mluis 0:45c4f0364ca4 494 }
mluis 0:45c4f0364ca4 495
mluis 0:45c4f0364ca4 496 Write( REG_LR_MODEMCONFIG1,
mluis 0:45c4f0364ca4 497 ( Read( REG_LR_MODEMCONFIG1 ) &
mluis 0:45c4f0364ca4 498 RFLR_MODEMCONFIG1_BW_MASK &
mluis 0:45c4f0364ca4 499 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
mluis 0:45c4f0364ca4 500 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK &
mluis 0:45c4f0364ca4 501 RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK &
mluis 0:45c4f0364ca4 502 RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 503 ( bandwidth << 6 ) | ( coderate << 3 ) |
mluis 0:45c4f0364ca4 504 ( fixLen << 2 ) | ( crcOn << 1 ) |
mluis 0:45c4f0364ca4 505 this->settings.LoRa.LowDatarateOptimize );
mluis 0:45c4f0364ca4 506
mluis 0:45c4f0364ca4 507 Write( REG_LR_MODEMCONFIG2,
mluis 0:45c4f0364ca4 508 ( Read( REG_LR_MODEMCONFIG2 ) &
mluis 0:45c4f0364ca4 509 RFLR_MODEMCONFIG2_SF_MASK ) |
mluis 0:45c4f0364ca4 510 ( datarate << 4 ) );
mluis 0:45c4f0364ca4 511
mluis 0:45c4f0364ca4 512
mluis 0:45c4f0364ca4 513 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
mluis 0:45c4f0364ca4 514 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
mluis 0:45c4f0364ca4 515
mluis 0:45c4f0364ca4 516 if( datarate == 6 )
mluis 0:45c4f0364ca4 517 {
mluis 0:45c4f0364ca4 518 Write( REG_LR_DETECTOPTIMIZE,
mluis 0:45c4f0364ca4 519 ( Read( REG_LR_DETECTOPTIMIZE ) &
mluis 0:45c4f0364ca4 520 RFLR_DETECTIONOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 521 RFLR_DETECTIONOPTIMIZE_SF6 );
mluis 0:45c4f0364ca4 522 Write( REG_LR_DETECTIONTHRESHOLD,
mluis 0:45c4f0364ca4 523 RFLR_DETECTIONTHRESH_SF6 );
mluis 0:45c4f0364ca4 524 }
mluis 0:45c4f0364ca4 525 else
mluis 0:45c4f0364ca4 526 {
mluis 0:45c4f0364ca4 527 Write( REG_LR_DETECTOPTIMIZE,
mluis 0:45c4f0364ca4 528 ( Read( REG_LR_DETECTOPTIMIZE ) &
mluis 0:45c4f0364ca4 529 RFLR_DETECTIONOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 530 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
mluis 0:45c4f0364ca4 531 Write( REG_LR_DETECTIONTHRESHOLD,
mluis 0:45c4f0364ca4 532 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
mluis 0:45c4f0364ca4 533 }
mluis 0:45c4f0364ca4 534 }
mluis 0:45c4f0364ca4 535 break;
mluis 0:45c4f0364ca4 536 }
mluis 0:45c4f0364ca4 537 }
mluis 0:45c4f0364ca4 538
mluis 0:45c4f0364ca4 539 double SX1272::TimeOnAir( RadioModems_t modem, uint8_t pktLen )
mluis 0:45c4f0364ca4 540 {
mluis 0:45c4f0364ca4 541 uint32_t airTime = 0;
mluis 0:45c4f0364ca4 542
mluis 0:45c4f0364ca4 543 switch( modem )
mluis 0:45c4f0364ca4 544 {
mluis 0:45c4f0364ca4 545 case MODEM_FSK:
mluis 0:45c4f0364ca4 546 {
mluis 0:45c4f0364ca4 547 airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen +
mluis 0:45c4f0364ca4 548 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
mluis 0:45c4f0364ca4 549 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
mluis 0:45c4f0364ca4 550 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
mluis 0:45c4f0364ca4 551 pktLen +
mluis 0:45c4f0364ca4 552 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
mluis 0:45c4f0364ca4 553 this->settings.Fsk.Datarate ) * 1e6 );
mluis 0:45c4f0364ca4 554 }
mluis 0:45c4f0364ca4 555 break;
mluis 0:45c4f0364ca4 556 case MODEM_LORA:
mluis 0:45c4f0364ca4 557 {
mluis 0:45c4f0364ca4 558 double bw = 0.0;
mluis 0:45c4f0364ca4 559 switch( this->settings.LoRa.Bandwidth )
mluis 0:45c4f0364ca4 560 {
mluis 0:45c4f0364ca4 561 case 0: // 125 kHz
mluis 0:45c4f0364ca4 562 bw = 125e3;
mluis 0:45c4f0364ca4 563 break;
mluis 0:45c4f0364ca4 564 case 1: // 250 kHz
mluis 0:45c4f0364ca4 565 bw = 250e3;
mluis 0:45c4f0364ca4 566 break;
mluis 0:45c4f0364ca4 567 case 2: // 500 kHz
mluis 0:45c4f0364ca4 568 bw = 500e3;
mluis 0:45c4f0364ca4 569 break;
mluis 0:45c4f0364ca4 570 }
mluis 0:45c4f0364ca4 571
mluis 0:45c4f0364ca4 572 // Symbol rate : time for one symbol (secs)
mluis 0:45c4f0364ca4 573 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
mluis 0:45c4f0364ca4 574 double ts = 1 / rs;
mluis 0:45c4f0364ca4 575 // time of preamble
mluis 0:45c4f0364ca4 576 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
mluis 0:45c4f0364ca4 577 // Symbol length of payload and time
mluis 0:45c4f0364ca4 578 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
mluis 0:45c4f0364ca4 579 28 + 16 * this->settings.LoRa.CrcOn -
mluis 0:45c4f0364ca4 580 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
mluis 0:45c4f0364ca4 581 ( double )( 4 * this->settings.LoRa.Datarate -
mluis 0:45c4f0364ca4 582 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) *
mluis 0:45c4f0364ca4 583 ( this->settings.LoRa.Coderate + 4 );
mluis 0:45c4f0364ca4 584 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
mluis 0:45c4f0364ca4 585 double tPayload = nPayload * ts;
mluis 0:45c4f0364ca4 586 // Time on air
mluis 0:45c4f0364ca4 587 double tOnAir = tPreamble + tPayload;
mluis 0:45c4f0364ca4 588 // return us secs
mluis 0:45c4f0364ca4 589 airTime = floor( tOnAir * 1e6 + 0.999 );
mluis 0:45c4f0364ca4 590 }
mluis 0:45c4f0364ca4 591 break;
mluis 0:45c4f0364ca4 592 }
mluis 0:45c4f0364ca4 593 return airTime;
mluis 0:45c4f0364ca4 594 }
mluis 0:45c4f0364ca4 595
mluis 0:45c4f0364ca4 596 void SX1272::Send( uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 597 {
mluis 0:45c4f0364ca4 598 uint32_t txTimeout = 0;
mluis 0:45c4f0364ca4 599
mluis 0:45c4f0364ca4 600 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 601 {
mluis 0:45c4f0364ca4 602 case MODEM_FSK:
mluis 0:45c4f0364ca4 603 {
mluis 0:45c4f0364ca4 604 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 605 this->settings.FskPacketHandler.Size = size;
mluis 0:45c4f0364ca4 606
mluis 0:45c4f0364ca4 607 if( this->settings.Fsk.FixLen == false )
mluis 0:45c4f0364ca4 608 {
mluis 0:45c4f0364ca4 609 WriteFifo( ( uint8_t* )&size, 1 );
mluis 0:45c4f0364ca4 610 }
mluis 0:45c4f0364ca4 611 else
mluis 0:45c4f0364ca4 612 {
mluis 0:45c4f0364ca4 613 Write( REG_PAYLOADLENGTH, size );
mluis 0:45c4f0364ca4 614 }
mluis 0:45c4f0364ca4 615
mluis 0:45c4f0364ca4 616 if( ( size > 0 ) && ( size <= 64 ) )
mluis 0:45c4f0364ca4 617 {
mluis 0:45c4f0364ca4 618 this->settings.FskPacketHandler.ChunkSize = size;
mluis 0:45c4f0364ca4 619 }
mluis 0:45c4f0364ca4 620 else
mluis 0:45c4f0364ca4 621 {
mluis 0:45c4f0364ca4 622 this->settings.FskPacketHandler.ChunkSize = 32;
mluis 0:45c4f0364ca4 623 }
mluis 0:45c4f0364ca4 624
mluis 0:45c4f0364ca4 625 // Write payload buffer
mluis 0:45c4f0364ca4 626 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
mluis 0:45c4f0364ca4 627 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
mluis 0:45c4f0364ca4 628 txTimeout = this->settings.Fsk.TxTimeout;
mluis 0:45c4f0364ca4 629 }
mluis 0:45c4f0364ca4 630 break;
mluis 0:45c4f0364ca4 631 case MODEM_LORA:
mluis 0:45c4f0364ca4 632 {
mluis 0:45c4f0364ca4 633 if( this->settings.LoRa.IqInverted == true )
mluis 0:45c4f0364ca4 634 {
mluis 0:45c4f0364ca4 635 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
mluis 0:45c4f0364ca4 636 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
mluis 0:45c4f0364ca4 637 }
mluis 0:45c4f0364ca4 638 else
mluis 0:45c4f0364ca4 639 {
mluis 0:45c4f0364ca4 640 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
mluis 0:45c4f0364ca4 641 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
mluis 0:45c4f0364ca4 642 }
mluis 0:45c4f0364ca4 643
mluis 0:45c4f0364ca4 644 this->settings.LoRaPacketHandler.Size = size;
mluis 0:45c4f0364ca4 645
mluis 0:45c4f0364ca4 646 // Initializes the payload size
mluis 0:45c4f0364ca4 647 Write( REG_LR_PAYLOADLENGTH, size );
mluis 0:45c4f0364ca4 648
mluis 0:45c4f0364ca4 649 // Full buffer used for Tx
mluis 0:45c4f0364ca4 650 Write( REG_LR_FIFOTXBASEADDR, 0 );
mluis 0:45c4f0364ca4 651 Write( REG_LR_FIFOADDRPTR, 0 );
mluis 0:45c4f0364ca4 652
mluis 0:45c4f0364ca4 653 // FIFO operations can not take place in Sleep mode
mluis 0:45c4f0364ca4 654 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
mluis 0:45c4f0364ca4 655 {
mluis 0:45c4f0364ca4 656 Standby( );
mluis 0:45c4f0364ca4 657 wait_ms( 1 );
mluis 0:45c4f0364ca4 658 }
mluis 0:45c4f0364ca4 659 // Write payload buffer
mluis 0:45c4f0364ca4 660 WriteFifo( buffer, size );
mluis 0:45c4f0364ca4 661 txTimeout = this->settings.LoRa.TxTimeout;
mluis 0:45c4f0364ca4 662 }
mluis 0:45c4f0364ca4 663 break;
mluis 0:45c4f0364ca4 664 }
mluis 0:45c4f0364ca4 665
mluis 0:45c4f0364ca4 666 Tx( txTimeout );
mluis 0:45c4f0364ca4 667 }
mluis 0:45c4f0364ca4 668
mluis 0:45c4f0364ca4 669 void SX1272::Sleep( void )
mluis 0:45c4f0364ca4 670 {
mluis 0:45c4f0364ca4 671 txTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 672 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 673
mluis 0:45c4f0364ca4 674 SetOpMode( RF_OPMODE_SLEEP );
mluis 0:45c4f0364ca4 675 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 676 }
mluis 0:45c4f0364ca4 677
mluis 0:45c4f0364ca4 678 void SX1272::Standby( void )
mluis 0:45c4f0364ca4 679 {
mluis 0:45c4f0364ca4 680 txTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 681 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 682
mluis 0:45c4f0364ca4 683 SetOpMode( RF_OPMODE_STANDBY );
mluis 0:45c4f0364ca4 684 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 685 }
mluis 0:45c4f0364ca4 686
mluis 0:45c4f0364ca4 687 void SX1272::Rx( uint32_t timeout )
mluis 0:45c4f0364ca4 688 {
mluis 0:45c4f0364ca4 689 bool rxContinuous = false;
mluis 0:45c4f0364ca4 690
mluis 0:45c4f0364ca4 691 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 692 {
mluis 0:45c4f0364ca4 693 case MODEM_FSK:
mluis 0:45c4f0364ca4 694 {
mluis 0:45c4f0364ca4 695 rxContinuous = this->settings.Fsk.RxContinuous;
mluis 0:45c4f0364ca4 696
mluis 0:45c4f0364ca4 697 // DIO0=PayloadReady
mluis 0:45c4f0364ca4 698 // DIO1=FifoLevel
mluis 0:45c4f0364ca4 699 // DIO2=SyncAddr
mluis 0:45c4f0364ca4 700 // DIO3=FifoEmpty
mluis 0:45c4f0364ca4 701 // DIO4=Preamble
mluis 0:45c4f0364ca4 702 // DIO5=ModeReady
mluis 0:45c4f0364ca4 703 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
mluis 0:45c4f0364ca4 704 RF_DIOMAPPING1_DIO2_MASK ) |
mluis 0:45c4f0364ca4 705 RF_DIOMAPPING1_DIO0_00 |
mluis 0:45c4f0364ca4 706 RF_DIOMAPPING1_DIO2_11 );
mluis 0:45c4f0364ca4 707
mluis 0:45c4f0364ca4 708 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
mluis 0:45c4f0364ca4 709 RF_DIOMAPPING2_MAP_MASK ) |
mluis 0:45c4f0364ca4 710 RF_DIOMAPPING2_DIO4_11 |
mluis 0:45c4f0364ca4 711 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
mluis 0:45c4f0364ca4 712
mluis 0:45c4f0364ca4 713 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
mluis 0:45c4f0364ca4 714
mluis 0:45c4f0364ca4 715 this->settings.FskPacketHandler.PreambleDetected = false;
mluis 0:45c4f0364ca4 716 this->settings.FskPacketHandler.SyncWordDetected = false;
mluis 0:45c4f0364ca4 717 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 718 this->settings.FskPacketHandler.Size = 0;
mluis 0:45c4f0364ca4 719 }
mluis 0:45c4f0364ca4 720 break;
mluis 0:45c4f0364ca4 721 case MODEM_LORA:
mluis 0:45c4f0364ca4 722 {
mluis 0:45c4f0364ca4 723 if( this->settings.LoRa.IqInverted == true )
mluis 0:45c4f0364ca4 724 {
mluis 0:45c4f0364ca4 725 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
mluis 0:45c4f0364ca4 726 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
mluis 0:45c4f0364ca4 727 }
mluis 0:45c4f0364ca4 728 else
mluis 0:45c4f0364ca4 729 {
mluis 0:45c4f0364ca4 730 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
mluis 0:45c4f0364ca4 731 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
mluis 0:45c4f0364ca4 732 }
mluis 0:45c4f0364ca4 733
mluis 0:45c4f0364ca4 734 rxContinuous = this->settings.LoRa.RxContinuous;
mluis 0:45c4f0364ca4 735
mluis 0:45c4f0364ca4 736 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 737 {
mluis 0:45c4f0364ca4 738 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 739 //RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 740 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 741 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 742 RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 743 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 744 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 745 RFLR_IRQFLAGS_CADDETECTED );
mluis 0:45c4f0364ca4 746
mluis 0:45c4f0364ca4 747 // DIO0=RxDone, DIO2=FhssChangeChannel
mluis 0:45c4f0364ca4 748 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
mluis 0:45c4f0364ca4 749 }
mluis 0:45c4f0364ca4 750 else
mluis 0:45c4f0364ca4 751 {
mluis 0:45c4f0364ca4 752 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 753 //RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 754 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 755 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 756 RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 757 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 758 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 759 RFLR_IRQFLAGS_CADDETECTED );
mluis 0:45c4f0364ca4 760
mluis 0:45c4f0364ca4 761 // DIO0=RxDone
mluis 0:45c4f0364ca4 762 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
mluis 0:45c4f0364ca4 763 }
mluis 0:45c4f0364ca4 764 Write( REG_LR_FIFORXBASEADDR, 0 );
mluis 0:45c4f0364ca4 765 Write( REG_LR_FIFOADDRPTR, 0 );
mluis 0:45c4f0364ca4 766 }
mluis 0:45c4f0364ca4 767 break;
mluis 0:45c4f0364ca4 768 }
mluis 0:45c4f0364ca4 769
mluis 0:45c4f0364ca4 770 memset( rxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
mluis 0:45c4f0364ca4 771
mluis 0:45c4f0364ca4 772 this->settings.State = RF_RX_RUNNING;
mluis 0:45c4f0364ca4 773 if( timeout != 0 )
mluis 0:45c4f0364ca4 774 {
mluis 0:45c4f0364ca4 775 rxTimeoutTimer.attach_us( this, &SX1272::OnTimeoutIrq, timeout );
mluis 0:45c4f0364ca4 776 }
mluis 0:45c4f0364ca4 777
mluis 0:45c4f0364ca4 778 if( this->settings.Modem == MODEM_FSK )
mluis 0:45c4f0364ca4 779 {
mluis 0:45c4f0364ca4 780 SetOpMode( RF_OPMODE_RECEIVER );
mluis 0:45c4f0364ca4 781
mluis 0:45c4f0364ca4 782 if( rxContinuous == false )
mluis 0:45c4f0364ca4 783 {
mluis 0:45c4f0364ca4 784 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
mluis 0:45c4f0364ca4 785 ( ( Read( REG_SYNCCONFIG ) &
mluis 0:45c4f0364ca4 786 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 0:45c4f0364ca4 787 1.0 ) + 10.0 ) /
mluis 0:45c4f0364ca4 788 ( double )this->settings.Fsk.Datarate ) * 1e6 );
mluis 0:45c4f0364ca4 789 }
mluis 0:45c4f0364ca4 790 }
mluis 0:45c4f0364ca4 791 else
mluis 0:45c4f0364ca4 792 {
mluis 0:45c4f0364ca4 793 if( rxContinuous == true )
mluis 0:45c4f0364ca4 794 {
mluis 0:45c4f0364ca4 795 SetOpMode( RFLR_OPMODE_RECEIVER );
mluis 0:45c4f0364ca4 796 }
mluis 0:45c4f0364ca4 797 else
mluis 0:45c4f0364ca4 798 {
mluis 0:45c4f0364ca4 799 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
mluis 0:45c4f0364ca4 800 }
mluis 0:45c4f0364ca4 801 }
mluis 0:45c4f0364ca4 802 }
mluis 0:45c4f0364ca4 803
mluis 0:45c4f0364ca4 804 void SX1272::Tx( uint32_t timeout )
mluis 0:45c4f0364ca4 805 {
mluis 0:45c4f0364ca4 806
mluis 0:45c4f0364ca4 807 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 808 {
mluis 0:45c4f0364ca4 809 case MODEM_FSK:
mluis 0:45c4f0364ca4 810 {
mluis 0:45c4f0364ca4 811 // DIO0=PacketSent
mluis 0:45c4f0364ca4 812 // DIO1=FifoLevel
mluis 0:45c4f0364ca4 813 // DIO2=FifoFull
mluis 0:45c4f0364ca4 814 // DIO3=FifoEmpty
mluis 0:45c4f0364ca4 815 // DIO4=LowBat
mluis 0:45c4f0364ca4 816 // DIO5=ModeReady
mluis 0:45c4f0364ca4 817 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
mluis 0:45c4f0364ca4 818 RF_DIOMAPPING1_DIO2_MASK ) );
mluis 0:45c4f0364ca4 819
mluis 0:45c4f0364ca4 820 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
mluis 0:45c4f0364ca4 821 RF_DIOMAPPING2_MAP_MASK ) );
mluis 0:45c4f0364ca4 822 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
mluis 0:45c4f0364ca4 823 }
mluis 0:45c4f0364ca4 824 break;
mluis 0:45c4f0364ca4 825 case MODEM_LORA:
mluis 0:45c4f0364ca4 826 {
mluis 0:45c4f0364ca4 827 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 828 {
mluis 0:45c4f0364ca4 829 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 830 RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 831 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 832 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 833 //RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 834 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 835 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 836 RFLR_IRQFLAGS_CADDETECTED );
mluis 0:45c4f0364ca4 837
mluis 0:45c4f0364ca4 838 // DIO0=TxDone, DIO2=FhssChangeChannel
mluis 0:45c4f0364ca4 839 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
mluis 0:45c4f0364ca4 840 }
mluis 0:45c4f0364ca4 841 else
mluis 0:45c4f0364ca4 842 {
mluis 0:45c4f0364ca4 843 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 844 RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 845 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 846 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 847 //RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 848 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 849 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 850 RFLR_IRQFLAGS_CADDETECTED );
mluis 0:45c4f0364ca4 851
mluis 0:45c4f0364ca4 852 // DIO0=TxDone
mluis 0:45c4f0364ca4 853 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
mluis 0:45c4f0364ca4 854 }
mluis 0:45c4f0364ca4 855 }
mluis 0:45c4f0364ca4 856 break;
mluis 0:45c4f0364ca4 857 }
mluis 0:45c4f0364ca4 858
mluis 0:45c4f0364ca4 859 this->settings.State = RF_TX_RUNNING;
mluis 0:45c4f0364ca4 860 txTimeoutTimer.attach_us( this, &SX1272::OnTimeoutIrq, timeout );
mluis 0:45c4f0364ca4 861 SetOpMode( RF_OPMODE_TRANSMITTER );
mluis 0:45c4f0364ca4 862 }
mluis 0:45c4f0364ca4 863
mluis 0:45c4f0364ca4 864 void SX1272::StartCad( void )
mluis 0:45c4f0364ca4 865 {
mluis 0:45c4f0364ca4 866 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 867 {
mluis 0:45c4f0364ca4 868 case MODEM_FSK:
mluis 0:45c4f0364ca4 869 {
mluis 0:45c4f0364ca4 870
mluis 0:45c4f0364ca4 871 }
mluis 0:45c4f0364ca4 872 break;
mluis 0:45c4f0364ca4 873 case MODEM_LORA:
mluis 0:45c4f0364ca4 874 {
mluis 0:45c4f0364ca4 875 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 876 RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 877 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 878 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 879 RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 880 //RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 881 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
mluis 0:45c4f0364ca4 882 //RFLR_IRQFLAGS_CADDETECTED
mluis 0:45c4f0364ca4 883 );
mluis 0:45c4f0364ca4 884
mluis 0:45c4f0364ca4 885 // DIO3=CADDone
mluis 0:45c4f0364ca4 886 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
mluis 0:45c4f0364ca4 887
mluis 0:45c4f0364ca4 888 this->settings.State = RF_CAD;
mluis 0:45c4f0364ca4 889 SetOpMode( RFLR_OPMODE_CAD );
mluis 0:45c4f0364ca4 890 }
mluis 0:45c4f0364ca4 891 break;
mluis 0:45c4f0364ca4 892 default:
mluis 0:45c4f0364ca4 893 break;
mluis 0:45c4f0364ca4 894 }
mluis 0:45c4f0364ca4 895 }
mluis 0:45c4f0364ca4 896
mluis 0:45c4f0364ca4 897 int16_t SX1272::GetRssi( RadioModems_t modem )
mluis 0:45c4f0364ca4 898 {
mluis 0:45c4f0364ca4 899 int16_t rssi = 0;
mluis 0:45c4f0364ca4 900
mluis 0:45c4f0364ca4 901 switch( modem )
mluis 0:45c4f0364ca4 902 {
mluis 0:45c4f0364ca4 903 case MODEM_FSK:
mluis 0:45c4f0364ca4 904 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
mluis 0:45c4f0364ca4 905 break;
mluis 0:45c4f0364ca4 906 case MODEM_LORA:
mluis 0:45c4f0364ca4 907 rssi = RSSI_OFFSET + Read( REG_LR_RSSIVALUE );
mluis 0:45c4f0364ca4 908 break;
mluis 0:45c4f0364ca4 909 default:
mluis 0:45c4f0364ca4 910 rssi = -1;
mluis 0:45c4f0364ca4 911 break;
mluis 0:45c4f0364ca4 912 }
mluis 0:45c4f0364ca4 913 return rssi;
mluis 0:45c4f0364ca4 914 }
mluis 0:45c4f0364ca4 915
mluis 0:45c4f0364ca4 916 void SX1272::SetOpMode( uint8_t opMode )
mluis 0:45c4f0364ca4 917 {
mluis 0:45c4f0364ca4 918 if( opMode != currentOpMode )
mluis 0:45c4f0364ca4 919 {
mluis 0:45c4f0364ca4 920 currentOpMode = opMode;
mluis 0:45c4f0364ca4 921 if( opMode == RF_OPMODE_SLEEP )
mluis 0:45c4f0364ca4 922 {
mluis 0:45c4f0364ca4 923 SetAntSwLowPower( true );
mluis 0:45c4f0364ca4 924 }
mluis 0:45c4f0364ca4 925 else
mluis 0:45c4f0364ca4 926 {
mluis 0:45c4f0364ca4 927 SetAntSwLowPower( false );
mluis 0:45c4f0364ca4 928 if( opMode == RF_OPMODE_TRANSMITTER )
mluis 0:45c4f0364ca4 929 {
mluis 0:45c4f0364ca4 930 SetAntSw( 1 );
mluis 0:45c4f0364ca4 931 }
mluis 0:45c4f0364ca4 932 else
mluis 0:45c4f0364ca4 933 {
mluis 0:45c4f0364ca4 934 SetAntSw( 0 );
mluis 0:45c4f0364ca4 935 }
mluis 0:45c4f0364ca4 936 }
mluis 0:45c4f0364ca4 937 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
mluis 0:45c4f0364ca4 938 }
mluis 0:45c4f0364ca4 939 }
mluis 0:45c4f0364ca4 940
mluis 0:45c4f0364ca4 941 void SX1272::SetModem( RadioModems_t modem )
mluis 0:45c4f0364ca4 942 {
mluis 0:45c4f0364ca4 943 if( this->settings.Modem == modem )
mluis 0:45c4f0364ca4 944 {
mluis 0:45c4f0364ca4 945 return;
mluis 0:45c4f0364ca4 946 }
mluis 0:45c4f0364ca4 947
mluis 0:45c4f0364ca4 948 this->settings.Modem = modem;
mluis 0:45c4f0364ca4 949 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 950 {
mluis 0:45c4f0364ca4 951 default:
mluis 0:45c4f0364ca4 952 case MODEM_FSK:
mluis 0:45c4f0364ca4 953 SetOpMode( RF_OPMODE_SLEEP );
mluis 0:45c4f0364ca4 954 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
mluis 0:45c4f0364ca4 955
mluis 0:45c4f0364ca4 956 Write( REG_DIOMAPPING1, 0x00 );
mluis 0:45c4f0364ca4 957 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
mluis 0:45c4f0364ca4 958 break;
mluis 0:45c4f0364ca4 959 case MODEM_LORA:
mluis 0:45c4f0364ca4 960 SetOpMode( RF_OPMODE_SLEEP );
mluis 0:45c4f0364ca4 961 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
mluis 0:45c4f0364ca4 962
mluis 0:45c4f0364ca4 963 Write( REG_DIOMAPPING1, 0x00 );
mluis 0:45c4f0364ca4 964 Write( REG_DIOMAPPING2, 0x00 );
mluis 0:45c4f0364ca4 965 break;
mluis 0:45c4f0364ca4 966 }
mluis 0:45c4f0364ca4 967 }
mluis 0:45c4f0364ca4 968
mluis 0:45c4f0364ca4 969 void SX1272::SetMaxPayloadLength( RadioModems_t modem, uint8_t max )
mluis 0:45c4f0364ca4 970 {
mluis 0:45c4f0364ca4 971 this->SetModem( modem );
mluis 0:45c4f0364ca4 972
mluis 0:45c4f0364ca4 973 switch( modem )
mluis 0:45c4f0364ca4 974 {
mluis 0:45c4f0364ca4 975 case MODEM_FSK:
mluis 0:45c4f0364ca4 976 if( this->settings.Fsk.FixLen == false )
mluis 0:45c4f0364ca4 977 {
mluis 0:45c4f0364ca4 978 this->Write( REG_PAYLOADLENGTH, max );
mluis 0:45c4f0364ca4 979 }
mluis 0:45c4f0364ca4 980 break;
mluis 0:45c4f0364ca4 981 case MODEM_LORA:
mluis 0:45c4f0364ca4 982 this->Write( REG_LR_PAYLOADMAXLENGTH, max );
mluis 0:45c4f0364ca4 983 break;
mluis 0:45c4f0364ca4 984 }
mluis 0:45c4f0364ca4 985 }
mluis 0:45c4f0364ca4 986
mluis 0:45c4f0364ca4 987 void SX1272::OnTimeoutIrq( void )
mluis 0:45c4f0364ca4 988 {
mluis 0:45c4f0364ca4 989 switch( this->settings.State )
mluis 0:45c4f0364ca4 990 {
mluis 0:45c4f0364ca4 991 case RF_RX_RUNNING:
mluis 0:45c4f0364ca4 992 if( this->settings.Modem == MODEM_FSK )
mluis 0:45c4f0364ca4 993 {
mluis 0:45c4f0364ca4 994 this->settings.FskPacketHandler.PreambleDetected = false;
mluis 0:45c4f0364ca4 995 this->settings.FskPacketHandler.SyncWordDetected = false;
mluis 0:45c4f0364ca4 996 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 997 this->settings.FskPacketHandler.Size = 0;
mluis 0:45c4f0364ca4 998
mluis 0:45c4f0364ca4 999 // Clear Irqs
mluis 0:45c4f0364ca4 1000 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
mluis 0:45c4f0364ca4 1001 RF_IRQFLAGS1_PREAMBLEDETECT |
mluis 0:45c4f0364ca4 1002 RF_IRQFLAGS1_SYNCADDRESSMATCH );
mluis 0:45c4f0364ca4 1003 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
mluis 0:45c4f0364ca4 1004
mluis 0:45c4f0364ca4 1005 if( this->settings.Fsk.RxContinuous == true )
mluis 0:45c4f0364ca4 1006 {
mluis 0:45c4f0364ca4 1007 // Continuous mode restart Rx chain
mluis 0:45c4f0364ca4 1008 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
mluis 0:45c4f0364ca4 1009 }
mluis 0:45c4f0364ca4 1010 else
mluis 0:45c4f0364ca4 1011 {
mluis 0:45c4f0364ca4 1012 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1013 rxTimeoutSyncWord.detach( );
mluis 0:45c4f0364ca4 1014 }
mluis 0:45c4f0364ca4 1015 }
mluis 0:45c4f0364ca4 1016 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
mluis 0:45c4f0364ca4 1017 {
mluis 0:45c4f0364ca4 1018 this->RadioEvents->RxTimeout( );
mluis 0:45c4f0364ca4 1019 }
mluis 0:45c4f0364ca4 1020 break;
mluis 0:45c4f0364ca4 1021 case RF_TX_RUNNING:
mluis 0:45c4f0364ca4 1022 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1023 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxTimeout != NULL ) )
mluis 0:45c4f0364ca4 1024 {
mluis 0:45c4f0364ca4 1025 this->RadioEvents->TxTimeout( );
mluis 0:45c4f0364ca4 1026 }
mluis 0:45c4f0364ca4 1027 break;
mluis 0:45c4f0364ca4 1028 default:
mluis 0:45c4f0364ca4 1029 break;
mluis 0:45c4f0364ca4 1030 }
mluis 0:45c4f0364ca4 1031 }
mluis 0:45c4f0364ca4 1032
mluis 0:45c4f0364ca4 1033 void SX1272::OnDio0Irq( void )
mluis 0:45c4f0364ca4 1034 {
mluis 0:45c4f0364ca4 1035 volatile uint8_t irqFlags = 0;
mluis 0:45c4f0364ca4 1036
mluis 0:45c4f0364ca4 1037 switch( this->settings.State )
mluis 0:45c4f0364ca4 1038 {
mluis 0:45c4f0364ca4 1039 case RF_RX_RUNNING:
mluis 0:45c4f0364ca4 1040 //TimerStop( &RxTimeoutTimer );
mluis 0:45c4f0364ca4 1041 // RxDone interrupt
mluis 0:45c4f0364ca4 1042 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1043 {
mluis 0:45c4f0364ca4 1044 case MODEM_FSK:
mluis 0:45c4f0364ca4 1045 if( this->settings.Fsk.CrcOn == true )
mluis 0:45c4f0364ca4 1046 {
mluis 0:45c4f0364ca4 1047 irqFlags = Read( REG_IRQFLAGS2 );
mluis 0:45c4f0364ca4 1048 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
mluis 0:45c4f0364ca4 1049 {
mluis 0:45c4f0364ca4 1050 // Clear Irqs
mluis 0:45c4f0364ca4 1051 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
mluis 0:45c4f0364ca4 1052 RF_IRQFLAGS1_PREAMBLEDETECT |
mluis 0:45c4f0364ca4 1053 RF_IRQFLAGS1_SYNCADDRESSMATCH );
mluis 0:45c4f0364ca4 1054 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
mluis 0:45c4f0364ca4 1055
mluis 0:45c4f0364ca4 1056 if( this->settings.Fsk.RxContinuous == false )
mluis 0:45c4f0364ca4 1057 {
mluis 0:45c4f0364ca4 1058 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1059 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
mluis 0:45c4f0364ca4 1060 ( ( Read( REG_SYNCCONFIG ) &
mluis 0:45c4f0364ca4 1061 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 0:45c4f0364ca4 1062 1.0 ) + 10.0 ) /
mluis 0:45c4f0364ca4 1063 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
mluis 0:45c4f0364ca4 1064 }
mluis 0:45c4f0364ca4 1065 else
mluis 0:45c4f0364ca4 1066 {
mluis 0:45c4f0364ca4 1067 // Continuous mode restart Rx chain
mluis 0:45c4f0364ca4 1068 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
mluis 0:45c4f0364ca4 1069 }
mluis 0:45c4f0364ca4 1070 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 1071
mluis 0:45c4f0364ca4 1072 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
mluis 0:45c4f0364ca4 1073 {
mluis 0:45c4f0364ca4 1074 this->RadioEvents->RxError( );
mluis 0:45c4f0364ca4 1075 }
mluis 0:45c4f0364ca4 1076 this->settings.FskPacketHandler.PreambleDetected = false;
mluis 0:45c4f0364ca4 1077 this->settings.FskPacketHandler.SyncWordDetected = false;
mluis 0:45c4f0364ca4 1078 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 1079 this->settings.FskPacketHandler.Size = 0;
mluis 0:45c4f0364ca4 1080 break;
mluis 0:45c4f0364ca4 1081 }
mluis 0:45c4f0364ca4 1082 }
mluis 0:45c4f0364ca4 1083
mluis 0:45c4f0364ca4 1084 // Read received packet size
mluis 0:45c4f0364ca4 1085 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
mluis 0:45c4f0364ca4 1086 {
mluis 0:45c4f0364ca4 1087 if( this->settings.Fsk.FixLen == false )
mluis 0:45c4f0364ca4 1088 {
mluis 0:45c4f0364ca4 1089 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
mluis 0:45c4f0364ca4 1090 }
mluis 0:45c4f0364ca4 1091 else
mluis 0:45c4f0364ca4 1092 {
mluis 0:45c4f0364ca4 1093 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
mluis 0:45c4f0364ca4 1094 }
mluis 0:45c4f0364ca4 1095 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1096 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1097 }
mluis 0:45c4f0364ca4 1098 else
mluis 0:45c4f0364ca4 1099 {
mluis 0:45c4f0364ca4 1100 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1101 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1102 }
mluis 0:45c4f0364ca4 1103
mluis 0:45c4f0364ca4 1104 if( this->settings.Fsk.RxContinuous == false )
mluis 0:45c4f0364ca4 1105 {
mluis 0:45c4f0364ca4 1106 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1107 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
mluis 0:45c4f0364ca4 1108 ( ( Read( REG_SYNCCONFIG ) &
mluis 0:45c4f0364ca4 1109 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 0:45c4f0364ca4 1110 1.0 ) + 10.0 ) /
mluis 0:45c4f0364ca4 1111 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
mluis 0:45c4f0364ca4 1112 }
mluis 0:45c4f0364ca4 1113 else
mluis 0:45c4f0364ca4 1114 {
mluis 0:45c4f0364ca4 1115 // Continuous mode restart Rx chain
mluis 0:45c4f0364ca4 1116 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
mluis 0:45c4f0364ca4 1117 }
mluis 0:45c4f0364ca4 1118 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 1119
mluis 0:45c4f0364ca4 1120 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
mluis 0:45c4f0364ca4 1121 {
mluis 0:45c4f0364ca4 1122 this->RadioEvents->RxDone( rxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
mluis 0:45c4f0364ca4 1123 }
mluis 0:45c4f0364ca4 1124 this->settings.FskPacketHandler.PreambleDetected = false;
mluis 0:45c4f0364ca4 1125 this->settings.FskPacketHandler.SyncWordDetected = false;
mluis 0:45c4f0364ca4 1126 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 1127 this->settings.FskPacketHandler.Size = 0;
mluis 0:45c4f0364ca4 1128 break;
mluis 0:45c4f0364ca4 1129 case MODEM_LORA:
mluis 0:45c4f0364ca4 1130 {
mluis 0:45c4f0364ca4 1131 int8_t snr = 0;
mluis 0:45c4f0364ca4 1132
mluis 0:45c4f0364ca4 1133 // Clear Irq
mluis 0:45c4f0364ca4 1134 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
mluis 0:45c4f0364ca4 1135
mluis 0:45c4f0364ca4 1136 irqFlags = Read( REG_LR_IRQFLAGS );
mluis 0:45c4f0364ca4 1137 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
mluis 0:45c4f0364ca4 1138 {
mluis 0:45c4f0364ca4 1139 // Clear Irq
mluis 0:45c4f0364ca4 1140 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
mluis 0:45c4f0364ca4 1141
mluis 0:45c4f0364ca4 1142 if( this->settings.LoRa.RxContinuous == false )
mluis 0:45c4f0364ca4 1143 {
mluis 0:45c4f0364ca4 1144 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1145 }
mluis 0:45c4f0364ca4 1146 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 1147
mluis 0:45c4f0364ca4 1148 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
mluis 0:45c4f0364ca4 1149 {
mluis 0:45c4f0364ca4 1150 this->RadioEvents->RxError( );
mluis 0:45c4f0364ca4 1151 }
mluis 0:45c4f0364ca4 1152 break;
mluis 0:45c4f0364ca4 1153 }
mluis 0:45c4f0364ca4 1154
mluis 0:45c4f0364ca4 1155 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
mluis 0:45c4f0364ca4 1156 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
mluis 0:45c4f0364ca4 1157 {
mluis 0:45c4f0364ca4 1158 // Invert and divide by 4
mluis 0:45c4f0364ca4 1159 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
mluis 0:45c4f0364ca4 1160 snr = -snr;
mluis 0:45c4f0364ca4 1161 }
mluis 0:45c4f0364ca4 1162 else
mluis 0:45c4f0364ca4 1163 {
mluis 0:45c4f0364ca4 1164 // Divide by 4
mluis 0:45c4f0364ca4 1165 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
mluis 0:45c4f0364ca4 1166 }
mluis 0:45c4f0364ca4 1167
mluis 0:45c4f0364ca4 1168 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
mluis 0:45c4f0364ca4 1169 if( snr < 0 )
mluis 0:45c4f0364ca4 1170 {
mluis 0:45c4f0364ca4 1171 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET + rssi + ( rssi >> 4 ) +
mluis 0:45c4f0364ca4 1172 snr;
mluis 0:45c4f0364ca4 1173 }
mluis 0:45c4f0364ca4 1174 else
mluis 0:45c4f0364ca4 1175 {
mluis 0:45c4f0364ca4 1176 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET + rssi + ( rssi >> 4 );
mluis 0:45c4f0364ca4 1177 }
mluis 0:45c4f0364ca4 1178
mluis 0:45c4f0364ca4 1179 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
mluis 0:45c4f0364ca4 1180 ReadFifo( rxBuffer, this->settings.LoRaPacketHandler.Size );
mluis 0:45c4f0364ca4 1181
mluis 0:45c4f0364ca4 1182 if( this->settings.LoRa.RxContinuous == false )
mluis 0:45c4f0364ca4 1183 {
mluis 0:45c4f0364ca4 1184 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1185 }
mluis 0:45c4f0364ca4 1186 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 1187
mluis 0:45c4f0364ca4 1188 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
mluis 0:45c4f0364ca4 1189 {
mluis 0:45c4f0364ca4 1190 this->RadioEvents->RxDone( rxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
mluis 0:45c4f0364ca4 1191 }
mluis 0:45c4f0364ca4 1192 }
mluis 0:45c4f0364ca4 1193 break;
mluis 0:45c4f0364ca4 1194 default:
mluis 0:45c4f0364ca4 1195 break;
mluis 0:45c4f0364ca4 1196 }
mluis 0:45c4f0364ca4 1197 break;
mluis 0:45c4f0364ca4 1198 case RF_TX_RUNNING:
mluis 0:45c4f0364ca4 1199 txTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 1200 // TxDone interrupt
mluis 0:45c4f0364ca4 1201 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1202 {
mluis 0:45c4f0364ca4 1203 case MODEM_LORA:
mluis 0:45c4f0364ca4 1204 // Clear Irq
mluis 0:45c4f0364ca4 1205 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
mluis 0:45c4f0364ca4 1206 // Intentional fall through
mluis 0:45c4f0364ca4 1207 case MODEM_FSK:
mluis 0:45c4f0364ca4 1208 default:
mluis 0:45c4f0364ca4 1209 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1210 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) )
mluis 0:45c4f0364ca4 1211 {
mluis 0:45c4f0364ca4 1212 this->RadioEvents->TxDone( );
mluis 0:45c4f0364ca4 1213 }
mluis 0:45c4f0364ca4 1214 break;
mluis 0:45c4f0364ca4 1215 }
mluis 0:45c4f0364ca4 1216 break;
mluis 0:45c4f0364ca4 1217 default:
mluis 0:45c4f0364ca4 1218 break;
mluis 0:45c4f0364ca4 1219 }
mluis 0:45c4f0364ca4 1220 }
mluis 0:45c4f0364ca4 1221
mluis 0:45c4f0364ca4 1222 void SX1272::OnDio1Irq( void )
mluis 0:45c4f0364ca4 1223 {
mluis 0:45c4f0364ca4 1224 switch( this->settings.State )
mluis 0:45c4f0364ca4 1225 {
mluis 0:45c4f0364ca4 1226 case RF_RX_RUNNING:
mluis 0:45c4f0364ca4 1227 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1228 {
mluis 0:45c4f0364ca4 1229 case MODEM_FSK:
mluis 0:45c4f0364ca4 1230 // FifoLevel interrupt
mluis 0:45c4f0364ca4 1231 // Read received packet size
mluis 0:45c4f0364ca4 1232 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
mluis 0:45c4f0364ca4 1233 {
mluis 0:45c4f0364ca4 1234 if( this->settings.Fsk.FixLen == false )
mluis 0:45c4f0364ca4 1235 {
mluis 0:45c4f0364ca4 1236 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
mluis 0:45c4f0364ca4 1237 }
mluis 0:45c4f0364ca4 1238 else
mluis 0:45c4f0364ca4 1239 {
mluis 0:45c4f0364ca4 1240 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
mluis 0:45c4f0364ca4 1241 }
mluis 0:45c4f0364ca4 1242 }
mluis 0:45c4f0364ca4 1243
mluis 0:45c4f0364ca4 1244 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
mluis 0:45c4f0364ca4 1245 {
mluis 0:45c4f0364ca4 1246 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
mluis 0:45c4f0364ca4 1247 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
mluis 0:45c4f0364ca4 1248 }
mluis 0:45c4f0364ca4 1249 else
mluis 0:45c4f0364ca4 1250 {
mluis 0:45c4f0364ca4 1251 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1252 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1253 }
mluis 0:45c4f0364ca4 1254 break;
mluis 0:45c4f0364ca4 1255 case MODEM_LORA:
mluis 0:45c4f0364ca4 1256 // Sync time out
mluis 0:45c4f0364ca4 1257 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 1258 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1259 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
mluis 0:45c4f0364ca4 1260 {
mluis 0:45c4f0364ca4 1261 this->RadioEvents->RxTimeout( );
mluis 0:45c4f0364ca4 1262 }
mluis 0:45c4f0364ca4 1263 break;
mluis 0:45c4f0364ca4 1264 default:
mluis 0:45c4f0364ca4 1265 break;
mluis 0:45c4f0364ca4 1266 }
mluis 0:45c4f0364ca4 1267 break;
mluis 0:45c4f0364ca4 1268 case RF_TX_RUNNING:
mluis 0:45c4f0364ca4 1269 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1270 {
mluis 0:45c4f0364ca4 1271 case MODEM_FSK:
mluis 0:45c4f0364ca4 1272 // FifoLevel interrupt
mluis 0:45c4f0364ca4 1273 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
mluis 0:45c4f0364ca4 1274 {
mluis 0:45c4f0364ca4 1275 WriteFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
mluis 0:45c4f0364ca4 1276 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
mluis 0:45c4f0364ca4 1277 }
mluis 0:45c4f0364ca4 1278 else
mluis 0:45c4f0364ca4 1279 {
mluis 0:45c4f0364ca4 1280 // Write the last chunk of data
mluis 0:45c4f0364ca4 1281 WriteFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1282 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
mluis 0:45c4f0364ca4 1283 }
mluis 0:45c4f0364ca4 1284 break;
mluis 0:45c4f0364ca4 1285 case MODEM_LORA:
mluis 0:45c4f0364ca4 1286 break;
mluis 0:45c4f0364ca4 1287 default:
mluis 0:45c4f0364ca4 1288 break;
mluis 0:45c4f0364ca4 1289 }
mluis 0:45c4f0364ca4 1290 break;
mluis 0:45c4f0364ca4 1291 default:
mluis 0:45c4f0364ca4 1292 break;
mluis 0:45c4f0364ca4 1293 }
mluis 0:45c4f0364ca4 1294 }
mluis 0:45c4f0364ca4 1295
mluis 0:45c4f0364ca4 1296 void SX1272::OnDio2Irq( void )
mluis 0:45c4f0364ca4 1297 {
mluis 0:45c4f0364ca4 1298 switch( this->settings.State )
mluis 0:45c4f0364ca4 1299 {
mluis 0:45c4f0364ca4 1300 case RF_RX_RUNNING:
mluis 0:45c4f0364ca4 1301 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1302 {
mluis 0:45c4f0364ca4 1303 case MODEM_FSK:
mluis 0:45c4f0364ca4 1304 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
mluis 0:45c4f0364ca4 1305 {
mluis 0:45c4f0364ca4 1306 rxTimeoutSyncWord.detach( );
mluis 0:45c4f0364ca4 1307
mluis 0:45c4f0364ca4 1308 this->settings.FskPacketHandler.SyncWordDetected = true;
mluis 0:45c4f0364ca4 1309
mluis 0:45c4f0364ca4 1310 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
mluis 0:45c4f0364ca4 1311
mluis 0:45c4f0364ca4 1312 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
mluis 0:45c4f0364ca4 1313 ( uint16_t )Read( REG_AFCLSB ) ) *
mluis 0:45c4f0364ca4 1314 ( double )FREQ_STEP;
mluis 0:45c4f0364ca4 1315 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
mluis 0:45c4f0364ca4 1316 }
mluis 0:45c4f0364ca4 1317 break;
mluis 0:45c4f0364ca4 1318 case MODEM_LORA:
mluis 0:45c4f0364ca4 1319 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 1320 {
mluis 0:45c4f0364ca4 1321 // Clear Irq
mluis 0:45c4f0364ca4 1322 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
mluis 0:45c4f0364ca4 1323
mluis 0:45c4f0364ca4 1324 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
mluis 0:45c4f0364ca4 1325 {
mluis 0:45c4f0364ca4 1326 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 0:45c4f0364ca4 1327 }
mluis 0:45c4f0364ca4 1328 }
mluis 0:45c4f0364ca4 1329 break;
mluis 0:45c4f0364ca4 1330 default:
mluis 0:45c4f0364ca4 1331 break;
mluis 0:45c4f0364ca4 1332 }
mluis 0:45c4f0364ca4 1333 break;
mluis 0:45c4f0364ca4 1334 case RF_TX_RUNNING:
mluis 0:45c4f0364ca4 1335 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1336 {
mluis 0:45c4f0364ca4 1337 case MODEM_FSK:
mluis 0:45c4f0364ca4 1338 break;
mluis 0:45c4f0364ca4 1339 case MODEM_LORA:
mluis 0:45c4f0364ca4 1340 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 1341 {
mluis 0:45c4f0364ca4 1342 // Clear Irq
mluis 0:45c4f0364ca4 1343 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
mluis 0:45c4f0364ca4 1344
mluis 0:45c4f0364ca4 1345 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
mluis 0:45c4f0364ca4 1346 {
mluis 0:45c4f0364ca4 1347 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 0:45c4f0364ca4 1348 }
mluis 0:45c4f0364ca4 1349 }
mluis 0:45c4f0364ca4 1350 break;
mluis 0:45c4f0364ca4 1351 default:
mluis 0:45c4f0364ca4 1352 break;
mluis 0:45c4f0364ca4 1353 }
mluis 0:45c4f0364ca4 1354 break;
mluis 0:45c4f0364ca4 1355 default:
mluis 0:45c4f0364ca4 1356 break;
mluis 0:45c4f0364ca4 1357 }
mluis 0:45c4f0364ca4 1358 }
mluis 0:45c4f0364ca4 1359
mluis 0:45c4f0364ca4 1360 void SX1272::OnDio3Irq( void )
mluis 0:45c4f0364ca4 1361 {
mluis 0:45c4f0364ca4 1362 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1363 {
mluis 0:45c4f0364ca4 1364 case MODEM_FSK:
mluis 0:45c4f0364ca4 1365 break;
mluis 0:45c4f0364ca4 1366 case MODEM_LORA:
mluis 0:45c4f0364ca4 1367 if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
mluis 0:45c4f0364ca4 1368 {
mluis 0:45c4f0364ca4 1369 // Clear Irq
mluis 0:45c4f0364ca4 1370 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
mluis 0:45c4f0364ca4 1371 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
mluis 0:45c4f0364ca4 1372 {
mluis 0:45c4f0364ca4 1373 this->RadioEvents->CadDone( true );
mluis 0:45c4f0364ca4 1374 }
mluis 0:45c4f0364ca4 1375 }
mluis 0:45c4f0364ca4 1376 else
mluis 0:45c4f0364ca4 1377 {
mluis 0:45c4f0364ca4 1378 // Clear Irq
mluis 0:45c4f0364ca4 1379 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
mluis 0:45c4f0364ca4 1380 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
mluis 0:45c4f0364ca4 1381 {
mluis 0:45c4f0364ca4 1382 this->RadioEvents->CadDone( false );
mluis 0:45c4f0364ca4 1383 }
mluis 0:45c4f0364ca4 1384 }
mluis 0:45c4f0364ca4 1385 break;
mluis 0:45c4f0364ca4 1386 default:
mluis 0:45c4f0364ca4 1387 break;
mluis 0:45c4f0364ca4 1388 }
mluis 0:45c4f0364ca4 1389 }
mluis 0:45c4f0364ca4 1390
mluis 0:45c4f0364ca4 1391 void SX1272::OnDio4Irq( void )
mluis 0:45c4f0364ca4 1392 {
mluis 0:45c4f0364ca4 1393 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1394 {
mluis 0:45c4f0364ca4 1395 case MODEM_FSK:
mluis 0:45c4f0364ca4 1396 {
mluis 0:45c4f0364ca4 1397 if( this->settings.FskPacketHandler.PreambleDetected == false )
mluis 0:45c4f0364ca4 1398 {
mluis 0:45c4f0364ca4 1399 this->settings.FskPacketHandler.PreambleDetected = true;
mluis 0:45c4f0364ca4 1400 }
mluis 0:45c4f0364ca4 1401 }
mluis 0:45c4f0364ca4 1402 break;
mluis 0:45c4f0364ca4 1403 case MODEM_LORA:
mluis 0:45c4f0364ca4 1404 break;
mluis 0:45c4f0364ca4 1405 default:
mluis 0:45c4f0364ca4 1406 break;
mluis 0:45c4f0364ca4 1407 }
mluis 0:45c4f0364ca4 1408 }
mluis 0:45c4f0364ca4 1409
mluis 0:45c4f0364ca4 1410 void SX1272::OnDio5Irq( void )
mluis 0:45c4f0364ca4 1411 {
mluis 0:45c4f0364ca4 1412 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1413 {
mluis 0:45c4f0364ca4 1414 case MODEM_FSK:
mluis 0:45c4f0364ca4 1415 break;
mluis 0:45c4f0364ca4 1416 case MODEM_LORA:
mluis 0:45c4f0364ca4 1417 break;
mluis 0:45c4f0364ca4 1418 default:
mluis 0:45c4f0364ca4 1419 break;
mluis 0:45c4f0364ca4 1420 }
mluis 0:45c4f0364ca4 1421 }