Timothy Mulrooney / SX1272Libx

test

Dependents:   LoRaWAN-lmic-app_tjm

Fork of SX1276Lib by Semtech

sx1272/sx1272.cpp@23:952530fa968d, 2016-02-23 (annotated)

Committer:
tmulrooney
Date:
Tue Feb 23 15:34:46 2016 +0000
Revision:
23:952530fa968d
Child:
24:54935d8f4b9e
first changes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tmulrooney 23:952530fa968d 1 /*
tmulrooney 23:952530fa968d 2 / _____) _ | |
tmulrooney 23:952530fa968d 3 ( (____ _____ ____ _| |_ _____ ____| |__
tmulrooney 23:952530fa968d 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
tmulrooney 23:952530fa968d 5 _____) ) ____| | | || |_| ____( (___| | | |
tmulrooney 23:952530fa968d 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
tmulrooney 23:952530fa968d 7 (C) 2014 Semtech
tmulrooney 23:952530fa968d 8
tmulrooney 23:952530fa968d 9 Description: Actual implementation of a SX1272 radio, inherits Radio
tmulrooney 23:952530fa968d 10
tmulrooney 23:952530fa968d 11 License: Revised BSD License, see LICENSE.TXT file include in the project
tmulrooney 23:952530fa968d 12
tmulrooney 23:952530fa968d 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
tmulrooney 23:952530fa968d 14 */
tmulrooney 23:952530fa968d 15 #include "sx1272.h"
tmulrooney 23:952530fa968d 16 #include "debug.h"
tmulrooney 23:952530fa968d 17
tmulrooney 23:952530fa968d 18 const FskBandwidth_t SX1272::FskBandwidths[] =
tmulrooney 23:952530fa968d 19 {
tmulrooney 23:952530fa968d 20 { 2600 , 0x17 },
tmulrooney 23:952530fa968d 21 { 3100 , 0x0F },
tmulrooney 23:952530fa968d 22 { 3900 , 0x07 },
tmulrooney 23:952530fa968d 23 { 5200 , 0x16 },
tmulrooney 23:952530fa968d 24 { 6300 , 0x0E },
tmulrooney 23:952530fa968d 25 { 7800 , 0x06 },
tmulrooney 23:952530fa968d 26 { 10400 , 0x15 },
tmulrooney 23:952530fa968d 27 { 12500 , 0x0D },
tmulrooney 23:952530fa968d 28 { 15600 , 0x05 },
tmulrooney 23:952530fa968d 29 { 20800 , 0x14 },
tmulrooney 23:952530fa968d 30 { 25000 , 0x0C },
tmulrooney 23:952530fa968d 31 { 31300 , 0x04 },
tmulrooney 23:952530fa968d 32 { 41700 , 0x13 },
tmulrooney 23:952530fa968d 33 { 50000 , 0x0B },
tmulrooney 23:952530fa968d 34 { 62500 , 0x03 },
tmulrooney 23:952530fa968d 35 { 83333 , 0x12 },
tmulrooney 23:952530fa968d 36 { 100000, 0x0A },
tmulrooney 23:952530fa968d 37 { 125000, 0x02 },
tmulrooney 23:952530fa968d 38 { 166700, 0x11 },
tmulrooney 23:952530fa968d 39 { 200000, 0x09 },
tmulrooney 23:952530fa968d 40 { 250000, 0x01 },
tmulrooney 23:952530fa968d 41 { 300000, 0x00 }, // Invalid Badwidth
tmulrooney 23:952530fa968d 42 };
tmulrooney 23:952530fa968d 43
tmulrooney 23:952530fa968d 44
tmulrooney 23:952530fa968d 45 SX1272::SX1272( RadioEvents_t *events,
tmulrooney 23:952530fa968d 46 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
tmulrooney 23:952530fa968d 47 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
tmulrooney 23:952530fa968d 48 : Radio( events ),
tmulrooney 23:952530fa968d 49 // spi( mosi, miso, sclk ),
tmulrooney 23:952530fa968d 50 // nss( nss ),
tmulrooney 23:952530fa968d 51 spi( PTD6, PTD7, PTD5 ),
tmulrooney 23:952530fa968d 52 nss( PTD4 ),
tmulrooney 23:952530fa968d 53 reset( reset ),
tmulrooney 23:952530fa968d 54 dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ),
tmulrooney 23:952530fa968d 55 isRadioActive( false )
tmulrooney 23:952530fa968d 56 {
tmulrooney 23:952530fa968d 57 debug("SX1272 constructor\r\n");
tmulrooney 23:952530fa968d 58 wait_ms( 10 );
tmulrooney 23:952530fa968d 59 this->rxTx = 0;
tmulrooney 23:952530fa968d 60 this->rxBuffer = new uint8_t[RX_BUFFER_SIZE];
tmulrooney 23:952530fa968d 61 previousOpMode = RF_OPMODE_STANDBY;
tmulrooney 23:952530fa968d 62
tmulrooney 23:952530fa968d 63 this->RadioEvents = events;
tmulrooney 23:952530fa968d 64
tmulrooney 23:952530fa968d 65 this->dioIrq = new DioIrqHandler[6];
tmulrooney 23:952530fa968d 66
tmulrooney 23:952530fa968d 67 this->dioIrq[0] = &SX1272::OnDio0Irq;
tmulrooney 23:952530fa968d 68 this->dioIrq[1] = &SX1272::OnDio1Irq;
tmulrooney 23:952530fa968d 69 this->dioIrq[2] = &SX1272::OnDio2Irq;
tmulrooney 23:952530fa968d 70 this->dioIrq[3] = &SX1272::OnDio3Irq;
tmulrooney 23:952530fa968d 71 this->dioIrq[4] = &SX1272::OnDio4Irq;
tmulrooney 23:952530fa968d 72 this->dioIrq[5] = NULL;
tmulrooney 23:952530fa968d 73
tmulrooney 23:952530fa968d 74 this->settings.State = RF_IDLE;
tmulrooney 23:952530fa968d 75 }
tmulrooney 23:952530fa968d 76
tmulrooney 23:952530fa968d 77 SX1272::~SX1272( )
tmulrooney 23:952530fa968d 78 {
tmulrooney 23:952530fa968d 79 debug("SX1272x destructor\r\n");
tmulrooney 23:952530fa968d 80 delete this->rxBuffer;
tmulrooney 23:952530fa968d 81 delete this->dioIrq;
tmulrooney 23:952530fa968d 82 }
tmulrooney 23:952530fa968d 83
tmulrooney 23:952530fa968d 84 void SX1272::Init( RadioEvents_t *events )
tmulrooney 23:952530fa968d 85 {
tmulrooney 23:952530fa968d 86 debug("SX1272 Init\r\n");
tmulrooney 23:952530fa968d 87 this->RadioEvents = events;
tmulrooney 23:952530fa968d 88 }
tmulrooney 23:952530fa968d 89
tmulrooney 23:952530fa968d 90 RadioState SX1272::GetStatus( void )
tmulrooney 23:952530fa968d 91 {
tmulrooney 23:952530fa968d 92 debug("GetStatus\r\n");
tmulrooney 23:952530fa968d 93 return this->settings.State;
tmulrooney 23:952530fa968d 94 }
tmulrooney 23:952530fa968d 95
tmulrooney 23:952530fa968d 96 void SX1272::SetChannel( uint32_t freq )
tmulrooney 23:952530fa968d 97 {
tmulrooney 23:952530fa968d 98 debug("SetChannel %d\r\n",freq);
tmulrooney 23:952530fa968d 99 this->settings.Channel = freq;
tmulrooney 23:952530fa968d 100 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
tmulrooney 23:952530fa968d 101 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
tmulrooney 23:952530fa968d 102 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
tmulrooney 23:952530fa968d 103 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
tmulrooney 23:952530fa968d 104 }
tmulrooney 23:952530fa968d 105
tmulrooney 23:952530fa968d 106 bool SX1272::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh )
tmulrooney 23:952530fa968d 107 {
tmulrooney 23:952530fa968d 108 debug("IsChannelFree\r\n");
tmulrooney 23:952530fa968d 109 int16_t rssi = 0;
tmulrooney 23:952530fa968d 110
tmulrooney 23:952530fa968d 111 SetModem( modem );
tmulrooney 23:952530fa968d 112
tmulrooney 23:952530fa968d 113 SetChannel( freq );
tmulrooney 23:952530fa968d 114
tmulrooney 23:952530fa968d 115 SetOpMode( RF_OPMODE_RECEIVER );
tmulrooney 23:952530fa968d 116
tmulrooney 23:952530fa968d 117 wait_ms( 1 );
tmulrooney 23:952530fa968d 118
tmulrooney 23:952530fa968d 119 rssi = GetRssi( modem );
tmulrooney 23:952530fa968d 120
tmulrooney 23:952530fa968d 121 Sleep( );
tmulrooney 23:952530fa968d 122
tmulrooney 23:952530fa968d 123 if( rssi > rssiThresh )
tmulrooney 23:952530fa968d 124 {
tmulrooney 23:952530fa968d 125 return false;
tmulrooney 23:952530fa968d 126 }
tmulrooney 23:952530fa968d 127 return true;
tmulrooney 23:952530fa968d 128 }
tmulrooney 23:952530fa968d 129
tmulrooney 23:952530fa968d 130 uint32_t SX1272::Random( void )
tmulrooney 23:952530fa968d 131 {
tmulrooney 23:952530fa968d 132 debug("Random\r\n");
tmulrooney 23:952530fa968d 133 uint8_t i;
tmulrooney 23:952530fa968d 134 uint32_t rnd = 0;
tmulrooney 23:952530fa968d 135
tmulrooney 23:952530fa968d 136 /*
tmulrooney 23:952530fa968d 137 * Radio setup for random number generation
tmulrooney 23:952530fa968d 138 */
tmulrooney 23:952530fa968d 139 // Set LoRa modem ON
tmulrooney 23:952530fa968d 140 SetModem( MODEM_LORA );
tmulrooney 23:952530fa968d 141
tmulrooney 23:952530fa968d 142 // Disable LoRa modem interrupts
tmulrooney 23:952530fa968d 143 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
tmulrooney 23:952530fa968d 144 RFLR_IRQFLAGS_RXDONE |
tmulrooney 23:952530fa968d 145 RFLR_IRQFLAGS_PAYLOADCRCERROR |
tmulrooney 23:952530fa968d 146 RFLR_IRQFLAGS_VALIDHEADER |
tmulrooney 23:952530fa968d 147 RFLR_IRQFLAGS_TXDONE |
tmulrooney 23:952530fa968d 148 RFLR_IRQFLAGS_CADDONE |
tmulrooney 23:952530fa968d 149 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
tmulrooney 23:952530fa968d 150 RFLR_IRQFLAGS_CADDETECTED );
tmulrooney 23:952530fa968d 151
tmulrooney 23:952530fa968d 152 // Set radio in continuous reception
tmulrooney 23:952530fa968d 153 SetOpMode( RF_OPMODE_RECEIVER );
tmulrooney 23:952530fa968d 154
tmulrooney 23:952530fa968d 155 for( i = 0; i < 32; i++ )
tmulrooney 23:952530fa968d 156 {
tmulrooney 23:952530fa968d 157 wait_ms( 1 );
tmulrooney 23:952530fa968d 158 // Unfiltered RSSI value reading. Only takes the LSB value
tmulrooney 23:952530fa968d 159 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
tmulrooney 23:952530fa968d 160 }
tmulrooney 23:952530fa968d 161
tmulrooney 23:952530fa968d 162 Sleep( );
tmulrooney 23:952530fa968d 163
tmulrooney 23:952530fa968d 164 return rnd;
tmulrooney 23:952530fa968d 165 }
tmulrooney 23:952530fa968d 166
tmulrooney 23:952530fa968d 167 /*!
tmulrooney 23:952530fa968d 168 * Performs the Rx chain calibration for LF and HF bands
tmulrooney 23:952530fa968d 169 * \remark Must be called just after the reset so all registers are at their
tmulrooney 23:952530fa968d 170 * default values
tmulrooney 23:952530fa968d 171 */
tmulrooney 23:952530fa968d 172 void SX1272::RxChainCalibration( void )
tmulrooney 23:952530fa968d 173 {
tmulrooney 23:952530fa968d 174 debug("RxChainCalibration enter\r\n");
tmulrooney 23:952530fa968d 175 uint8_t regPaConfigInitVal;
tmulrooney 23:952530fa968d 176 uint32_t initialFreq;
tmulrooney 23:952530fa968d 177
tmulrooney 23:952530fa968d 178 // Save context
tmulrooney 23:952530fa968d 179 regPaConfigInitVal = this->Read( REG_PACONFIG );
tmulrooney 23:952530fa968d 180 initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) |
tmulrooney 23:952530fa968d 181 ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) |
tmulrooney 23:952530fa968d 182 ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
tmulrooney 23:952530fa968d 183 debug("Initial Freq: %d\r\n", initialFreq);
tmulrooney 23:952530fa968d 184
tmulrooney 23:952530fa968d 185 // Cut the PA just in case, RFO output, power = -1 dBm
tmulrooney 23:952530fa968d 186 this->Write( REG_PACONFIG, 0x00 );
tmulrooney 23:952530fa968d 187
tmulrooney 23:952530fa968d 188 // Launch Rx chain calibration for LF band
tmulrooney 23:952530fa968d 189 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
tmulrooney 23:952530fa968d 190 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
tmulrooney 23:952530fa968d 191 {
tmulrooney 23:952530fa968d 192 }
tmulrooney 23:952530fa968d 193
tmulrooney 23:952530fa968d 194 // Sets a Frequency in HF band
tmulrooney 23:952530fa968d 195 SetChannel( 868000000 );
tmulrooney 23:952530fa968d 196
tmulrooney 23:952530fa968d 197 // Launch Rx chain calibration for HF band
tmulrooney 23:952530fa968d 198 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
tmulrooney 23:952530fa968d 199 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
tmulrooney 23:952530fa968d 200 {
tmulrooney 23:952530fa968d 201 }
tmulrooney 23:952530fa968d 202
tmulrooney 23:952530fa968d 203 // Restore context
tmulrooney 23:952530fa968d 204 this->Write( REG_PACONFIG, regPaConfigInitVal );
tmulrooney 23:952530fa968d 205 SetChannel( initialFreq );
tmulrooney 23:952530fa968d 206 }
tmulrooney 23:952530fa968d 207
tmulrooney 23:952530fa968d 208 /*!
tmulrooney 23:952530fa968d 209 * Returns the known FSK bandwidth registers value
tmulrooney 23:952530fa968d 210 *
tmulrooney 23:952530fa968d 211 * \param [IN] bandwidth Bandwidth value in Hz
tmulrooney 23:952530fa968d 212 * \retval regValue Bandwidth register value.
tmulrooney 23:952530fa968d 213 */
tmulrooney 23:952530fa968d 214 uint8_t SX1272::GetFskBandwidthRegValue( uint32_t bandwidth )
tmulrooney 23:952530fa968d 215 {
tmulrooney 23:952530fa968d 216 debug("GetFskBandwidthRegValue\r\n");
tmulrooney 23:952530fa968d 217 uint8_t i;
tmulrooney 23:952530fa968d 218
tmulrooney 23:952530fa968d 219 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
tmulrooney 23:952530fa968d 220 {
tmulrooney 23:952530fa968d 221 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
tmulrooney 23:952530fa968d 222 {
tmulrooney 23:952530fa968d 223 return FskBandwidths[i].RegValue;
tmulrooney 23:952530fa968d 224 }
tmulrooney 23:952530fa968d 225 }
tmulrooney 23:952530fa968d 226 // ERROR: Value not found
tmulrooney 23:952530fa968d 227 while( 1 );
tmulrooney 23:952530fa968d 228 }
tmulrooney 23:952530fa968d 229
tmulrooney 23:952530fa968d 230 void SX1272::SetRxConfig( RadioModems_t modem, uint32_t bandwidth,
tmulrooney 23:952530fa968d 231 uint32_t datarate, uint8_t coderate,
tmulrooney 23:952530fa968d 232 uint32_t bandwidthAfc, uint16_t preambleLen,
tmulrooney 23:952530fa968d 233 uint16_t symbTimeout, bool fixLen,
tmulrooney 23:952530fa968d 234 uint8_t payloadLen,
tmulrooney 23:952530fa968d 235 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
tmulrooney 23:952530fa968d 236 bool iqInverted, bool rxContinuous )
tmulrooney 23:952530fa968d 237 {
tmulrooney 23:952530fa968d 238 debug("SetRxConfig enter\r\n");
tmulrooney 23:952530fa968d 239 SetModem( modem );
tmulrooney 23:952530fa968d 240
tmulrooney 23:952530fa968d 241 switch( modem )
tmulrooney 23:952530fa968d 242 {
tmulrooney 23:952530fa968d 243 case MODEM_FSK:
tmulrooney 23:952530fa968d 244 {
tmulrooney 23:952530fa968d 245 this->settings.Fsk.Bandwidth = bandwidth;
tmulrooney 23:952530fa968d 246 this->settings.Fsk.Datarate = datarate;
tmulrooney 23:952530fa968d 247 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
tmulrooney 23:952530fa968d 248 this->settings.Fsk.FixLen = fixLen;
tmulrooney 23:952530fa968d 249 this->settings.Fsk.PayloadLen = payloadLen;
tmulrooney 23:952530fa968d 250 this->settings.Fsk.CrcOn = crcOn;
tmulrooney 23:952530fa968d 251 this->settings.Fsk.IqInverted = iqInverted;
tmulrooney 23:952530fa968d 252 this->settings.Fsk.RxContinuous = rxContinuous;
tmulrooney 23:952530fa968d 253 this->settings.Fsk.PreambleLen = preambleLen;
tmulrooney 23:952530fa968d 254
tmulrooney 23:952530fa968d 255 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
tmulrooney 23:952530fa968d 256 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
tmulrooney 23:952530fa968d 257 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
tmulrooney 23:952530fa968d 258
tmulrooney 23:952530fa968d 259 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
tmulrooney 23:952530fa968d 260 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
tmulrooney 23:952530fa968d 261
tmulrooney 23:952530fa968d 262 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
tmulrooney 23:952530fa968d 263 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
tmulrooney 23:952530fa968d 264
tmulrooney 23:952530fa968d 265 if( fixLen == 1 )
tmulrooney 23:952530fa968d 266 {
tmulrooney 23:952530fa968d 267 Write( REG_PAYLOADLENGTH, payloadLen );
tmulrooney 23:952530fa968d 268 }
tmulrooney 23:952530fa968d 269
tmulrooney 23:952530fa968d 270 Write( REG_PACKETCONFIG1,
tmulrooney 23:952530fa968d 271 ( Read( REG_PACKETCONFIG1 ) &
tmulrooney 23:952530fa968d 272 RF_PACKETCONFIG1_CRC_MASK &
tmulrooney 23:952530fa968d 273 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
tmulrooney 23:952530fa968d 274 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
tmulrooney 23:952530fa968d 275 ( crcOn << 4 ) );
tmulrooney 23:952530fa968d 276 }
tmulrooney 23:952530fa968d 277 break;
tmulrooney 23:952530fa968d 278 case MODEM_LORA:
tmulrooney 23:952530fa968d 279 {
tmulrooney 23:952530fa968d 280 if( bandwidth > 2 )
tmulrooney 23:952530fa968d 281 {
tmulrooney 23:952530fa968d 282 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
tmulrooney 23:952530fa968d 283 while( 1 );
tmulrooney 23:952530fa968d 284 }
tmulrooney 23:952530fa968d 285 bandwidth += 7;
tmulrooney 23:952530fa968d 286 this->settings.LoRa.Bandwidth = bandwidth;
tmulrooney 23:952530fa968d 287 this->settings.LoRa.Datarate = datarate;
tmulrooney 23:952530fa968d 288 this->settings.LoRa.Coderate = coderate;
tmulrooney 23:952530fa968d 289 this->settings.LoRa.PreambleLen = preambleLen;
tmulrooney 23:952530fa968d 290 this->settings.LoRa.FixLen = fixLen;
tmulrooney 23:952530fa968d 291 this->settings.LoRa.PayloadLen = payloadLen;
tmulrooney 23:952530fa968d 292 this->settings.LoRa.CrcOn = crcOn;
tmulrooney 23:952530fa968d 293 this->settings.LoRa.FreqHopOn = freqHopOn;
tmulrooney 23:952530fa968d 294 this->settings.LoRa.HopPeriod = hopPeriod;
tmulrooney 23:952530fa968d 295 this->settings.LoRa.IqInverted = iqInverted;
tmulrooney 23:952530fa968d 296 this->settings.LoRa.RxContinuous = rxContinuous;
tmulrooney 23:952530fa968d 297
tmulrooney 23:952530fa968d 298 if( datarate > 12 )
tmulrooney 23:952530fa968d 299 {
tmulrooney 23:952530fa968d 300 datarate = 12;
tmulrooney 23:952530fa968d 301 }
tmulrooney 23:952530fa968d 302 else if( datarate < 6 )
tmulrooney 23:952530fa968d 303 {
tmulrooney 23:952530fa968d 304 datarate = 6;
tmulrooney 23:952530fa968d 305 }
tmulrooney 23:952530fa968d 306
tmulrooney 23:952530fa968d 307 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
tmulrooney 23:952530fa968d 308 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
tmulrooney 23:952530fa968d 309 {
tmulrooney 23:952530fa968d 310 this->settings.LoRa.LowDatarateOptimize = 0x01;
tmulrooney 23:952530fa968d 311 }
tmulrooney 23:952530fa968d 312 else
tmulrooney 23:952530fa968d 313 {
tmulrooney 23:952530fa968d 314 this->settings.LoRa.LowDatarateOptimize = 0x00;
tmulrooney 23:952530fa968d 315 }
tmulrooney 23:952530fa968d 316
tmulrooney 23:952530fa968d 317 Write( REG_LR_MODEMCONFIG1,
tmulrooney 23:952530fa968d 318 ( Read( REG_LR_MODEMCONFIG1 ) &
tmulrooney 23:952530fa968d 319 RFLR_MODEMCONFIG1_BW_MASK &
tmulrooney 23:952530fa968d 320 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
tmulrooney 23:952530fa968d 321 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
tmulrooney 23:952530fa968d 322 ( bandwidth << 4 ) | ( coderate << 1 ) |
tmulrooney 23:952530fa968d 323 fixLen );
tmulrooney 23:952530fa968d 324
tmulrooney 23:952530fa968d 325 Write( REG_LR_MODEMCONFIG2,
tmulrooney 23:952530fa968d 326 ( Read( REG_LR_MODEMCONFIG2 ) &
tmulrooney 23:952530fa968d 327 RFLR_MODEMCONFIG2_SF_MASK &
tmulrooney 23:952530fa968d 328 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
tmulrooney 23:952530fa968d 329 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
tmulrooney 23:952530fa968d 330 ( datarate << 4 ) | ( crcOn << 2 ) |
tmulrooney 23:952530fa968d 331 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
tmulrooney 23:952530fa968d 332
tmulrooney 23:952530fa968d 333 Write( REG_LR_MODEMCONFIG3,
tmulrooney 23:952530fa968d 334 ( Read( REG_LR_MODEMCONFIG3 ) &
tmulrooney 23:952530fa968d 335 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
tmulrooney 23:952530fa968d 336 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
tmulrooney 23:952530fa968d 337
tmulrooney 23:952530fa968d 338 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
tmulrooney 23:952530fa968d 339
tmulrooney 23:952530fa968d 340 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
tmulrooney 23:952530fa968d 341 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
tmulrooney 23:952530fa968d 342
tmulrooney 23:952530fa968d 343 if( fixLen == 1 )
tmulrooney 23:952530fa968d 344 {
tmulrooney 23:952530fa968d 345 Write( REG_LR_PAYLOADLENGTH, payloadLen );
tmulrooney 23:952530fa968d 346 }
tmulrooney 23:952530fa968d 347
tmulrooney 23:952530fa968d 348 if( this->settings.LoRa.FreqHopOn == true )
tmulrooney 23:952530fa968d 349 {
tmulrooney 23:952530fa968d 350 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
tmulrooney 23:952530fa968d 351 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
tmulrooney 23:952530fa968d 352 }
tmulrooney 23:952530fa968d 353
tmulrooney 23:952530fa968d 354 if( ( bandwidth == 9 ) && ( RF_MID_BAND_THRESH ) )
tmulrooney 23:952530fa968d 355 {
tmulrooney 23:952530fa968d 356 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
tmulrooney 23:952530fa968d 357 Write( REG_LR_TEST36, 0x02 );
tmulrooney 23:952530fa968d 358 Write( REG_LR_TEST3A, 0x64 );
tmulrooney 23:952530fa968d 359 }
tmulrooney 23:952530fa968d 360 else if( bandwidth == 9 )
tmulrooney 23:952530fa968d 361 {
tmulrooney 23:952530fa968d 362 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
tmulrooney 23:952530fa968d 363 Write( REG_LR_TEST36, 0x02 );
tmulrooney 23:952530fa968d 364 Write( REG_LR_TEST3A, 0x7F );
tmulrooney 23:952530fa968d 365 }
tmulrooney 23:952530fa968d 366 else
tmulrooney 23:952530fa968d 367 {
tmulrooney 23:952530fa968d 368 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
tmulrooney 23:952530fa968d 369 Write( REG_LR_TEST36, 0x03 );
tmulrooney 23:952530fa968d 370 }
tmulrooney 23:952530fa968d 371
tmulrooney 23:952530fa968d 372 if( datarate == 6 )
tmulrooney 23:952530fa968d 373 {
tmulrooney 23:952530fa968d 374 Write( REG_LR_DETECTOPTIMIZE,
tmulrooney 23:952530fa968d 375 ( Read( REG_LR_DETECTOPTIMIZE ) &
tmulrooney 23:952530fa968d 376 RFLR_DETECTIONOPTIMIZE_MASK ) |
tmulrooney 23:952530fa968d 377 RFLR_DETECTIONOPTIMIZE_SF6 );
tmulrooney 23:952530fa968d 378 Write( REG_LR_DETECTIONTHRESHOLD,
tmulrooney 23:952530fa968d 379 RFLR_DETECTIONTHRESH_SF6 );
tmulrooney 23:952530fa968d 380 }
tmulrooney 23:952530fa968d 381 else
tmulrooney 23:952530fa968d 382 {
tmulrooney 23:952530fa968d 383 Write( REG_LR_DETECTOPTIMIZE,
tmulrooney 23:952530fa968d 384 ( Read( REG_LR_DETECTOPTIMIZE ) &
tmulrooney 23:952530fa968d 385 RFLR_DETECTIONOPTIMIZE_MASK ) |
tmulrooney 23:952530fa968d 386 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
tmulrooney 23:952530fa968d 387 Write( REG_LR_DETECTIONTHRESHOLD,
tmulrooney 23:952530fa968d 388 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
tmulrooney 23:952530fa968d 389 }
tmulrooney 23:952530fa968d 390 }
tmulrooney 23:952530fa968d 391 break;
tmulrooney 23:952530fa968d 392 }
tmulrooney 23:952530fa968d 393 }
tmulrooney 23:952530fa968d 394
tmulrooney 23:952530fa968d 395 void SX1272::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
tmulrooney 23:952530fa968d 396 uint32_t bandwidth, uint32_t datarate,
tmulrooney 23:952530fa968d 397 uint8_t coderate, uint16_t preambleLen,
tmulrooney 23:952530fa968d 398 bool fixLen, bool crcOn, bool freqHopOn,
tmulrooney 23:952530fa968d 399 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
tmulrooney 23:952530fa968d 400 {
tmulrooney 23:952530fa968d 401 debug("SetTxConfig enter\r\n");
tmulrooney 23:952530fa968d 402 debug("modem: %d power: %d fdev: %d\r\n",modem,power,fdev);
tmulrooney 23:952530fa968d 403 debug("bandwidth: %d datarate:%d\r\n",bandwidth,datarate);
tmulrooney 23:952530fa968d 404 debug("timeout: %d\r\n",timeout);
tmulrooney 23:952530fa968d 405 uint8_t paConfig = 0;
tmulrooney 23:952530fa968d 406 uint8_t paDac = 0;
tmulrooney 23:952530fa968d 407
tmulrooney 23:952530fa968d 408 SetModem( modem );
tmulrooney 23:952530fa968d 409
tmulrooney 23:952530fa968d 410 paConfig = Read( REG_PACONFIG );
tmulrooney 23:952530fa968d 411 paDac = Read( REG_PADAC );
tmulrooney 23:952530fa968d 412
tmulrooney 23:952530fa968d 413 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
tmulrooney 23:952530fa968d 414 paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
tmulrooney 23:952530fa968d 415
tmulrooney 23:952530fa968d 416 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
tmulrooney 23:952530fa968d 417 {
tmulrooney 23:952530fa968d 418 if( power > 17 )
tmulrooney 23:952530fa968d 419 {
tmulrooney 23:952530fa968d 420 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
tmulrooney 23:952530fa968d 421 }
tmulrooney 23:952530fa968d 422 else
tmulrooney 23:952530fa968d 423 {
tmulrooney 23:952530fa968d 424 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
tmulrooney 23:952530fa968d 425 }
tmulrooney 23:952530fa968d 426 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
tmulrooney 23:952530fa968d 427 {
tmulrooney 23:952530fa968d 428 if( power < 5 )
tmulrooney 23:952530fa968d 429 {
tmulrooney 23:952530fa968d 430 power = 5;
tmulrooney 23:952530fa968d 431 }
tmulrooney 23:952530fa968d 432 if( power > 20 )
tmulrooney 23:952530fa968d 433 {
tmulrooney 23:952530fa968d 434 power = 20;
tmulrooney 23:952530fa968d 435 }
tmulrooney 23:952530fa968d 436 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
tmulrooney 23:952530fa968d 437 }
tmulrooney 23:952530fa968d 438 else
tmulrooney 23:952530fa968d 439 {
tmulrooney 23:952530fa968d 440 if( power < 2 )
tmulrooney 23:952530fa968d 441 {
tmulrooney 23:952530fa968d 442 power = 2;
tmulrooney 23:952530fa968d 443 }
tmulrooney 23:952530fa968d 444 if( power > 17 )
tmulrooney 23:952530fa968d 445 {
tmulrooney 23:952530fa968d 446 power = 17;
tmulrooney 23:952530fa968d 447 }
tmulrooney 23:952530fa968d 448 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
tmulrooney 23:952530fa968d 449 }
tmulrooney 23:952530fa968d 450 }
tmulrooney 23:952530fa968d 451 else
tmulrooney 23:952530fa968d 452 {
tmulrooney 23:952530fa968d 453 if( power < -1 )
tmulrooney 23:952530fa968d 454 {
tmulrooney 23:952530fa968d 455 power = -1;
tmulrooney 23:952530fa968d 456 }
tmulrooney 23:952530fa968d 457 if( power > 14 )
tmulrooney 23:952530fa968d 458 {
tmulrooney 23:952530fa968d 459 power = 14;
tmulrooney 23:952530fa968d 460 }
tmulrooney 23:952530fa968d 461 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
tmulrooney 23:952530fa968d 462 }
tmulrooney 23:952530fa968d 463 Write( REG_PACONFIG, paConfig );
tmulrooney 23:952530fa968d 464 Write( REG_PADAC, paDac );
tmulrooney 23:952530fa968d 465
tmulrooney 23:952530fa968d 466 switch( modem )
tmulrooney 23:952530fa968d 467 {
tmulrooney 23:952530fa968d 468 case MODEM_FSK:
tmulrooney 23:952530fa968d 469 {
tmulrooney 23:952530fa968d 470 this->settings.Fsk.Power = power;
tmulrooney 23:952530fa968d 471 this->settings.Fsk.Fdev = fdev;
tmulrooney 23:952530fa968d 472 this->settings.Fsk.Bandwidth = bandwidth;
tmulrooney 23:952530fa968d 473 this->settings.Fsk.Datarate = datarate;
tmulrooney 23:952530fa968d 474 this->settings.Fsk.PreambleLen = preambleLen;
tmulrooney 23:952530fa968d 475 this->settings.Fsk.FixLen = fixLen;
tmulrooney 23:952530fa968d 476 this->settings.Fsk.CrcOn = crcOn;
tmulrooney 23:952530fa968d 477 this->settings.Fsk.IqInverted = iqInverted;
tmulrooney 23:952530fa968d 478 this->settings.Fsk.TxTimeout = timeout;
tmulrooney 23:952530fa968d 479
tmulrooney 23:952530fa968d 480 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
tmulrooney 23:952530fa968d 481 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
tmulrooney 23:952530fa968d 482 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
tmulrooney 23:952530fa968d 483
tmulrooney 23:952530fa968d 484 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
tmulrooney 23:952530fa968d 485 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
tmulrooney 23:952530fa968d 486 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
tmulrooney 23:952530fa968d 487
tmulrooney 23:952530fa968d 488 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
tmulrooney 23:952530fa968d 489 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
tmulrooney 23:952530fa968d 490
tmulrooney 23:952530fa968d 491 Write( REG_PACKETCONFIG1,
tmulrooney 23:952530fa968d 492 ( Read( REG_PACKETCONFIG1 ) &
tmulrooney 23:952530fa968d 493 RF_PACKETCONFIG1_CRC_MASK &
tmulrooney 23:952530fa968d 494 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
tmulrooney 23:952530fa968d 495 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
tmulrooney 23:952530fa968d 496 ( crcOn << 4 ) );
tmulrooney 23:952530fa968d 497
tmulrooney 23:952530fa968d 498 }
tmulrooney 23:952530fa968d 499 break;
tmulrooney 23:952530fa968d 500 case MODEM_LORA:
tmulrooney 23:952530fa968d 501 {
tmulrooney 23:952530fa968d 502 this->settings.LoRa.Power = power;
tmulrooney 23:952530fa968d 503 if( bandwidth > 2 )
tmulrooney 23:952530fa968d 504 {
tmulrooney 23:952530fa968d 505 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
tmulrooney 23:952530fa968d 506 while( 1 );
tmulrooney 23:952530fa968d 507 }
tmulrooney 23:952530fa968d 508 bandwidth += 7;
tmulrooney 23:952530fa968d 509 this->settings.LoRa.Bandwidth = bandwidth;
tmulrooney 23:952530fa968d 510 this->settings.LoRa.Datarate = datarate;
tmulrooney 23:952530fa968d 511 this->settings.LoRa.Coderate = coderate;
tmulrooney 23:952530fa968d 512 this->settings.LoRa.PreambleLen = preambleLen;
tmulrooney 23:952530fa968d 513 this->settings.LoRa.FixLen = fixLen;
tmulrooney 23:952530fa968d 514 this->settings.LoRa.FreqHopOn = freqHopOn;
tmulrooney 23:952530fa968d 515 this->settings.LoRa.HopPeriod = hopPeriod;
tmulrooney 23:952530fa968d 516 this->settings.LoRa.CrcOn = crcOn;
tmulrooney 23:952530fa968d 517 this->settings.LoRa.IqInverted = iqInverted;
tmulrooney 23:952530fa968d 518 this->settings.LoRa.TxTimeout = timeout;
tmulrooney 23:952530fa968d 519
tmulrooney 23:952530fa968d 520 if( datarate > 12 )
tmulrooney 23:952530fa968d 521 {
tmulrooney 23:952530fa968d 522 datarate = 12;
tmulrooney 23:952530fa968d 523 }
tmulrooney 23:952530fa968d 524 else if( datarate < 6 )
tmulrooney 23:952530fa968d 525 {
tmulrooney 23:952530fa968d 526 datarate = 6;
tmulrooney 23:952530fa968d 527 }
tmulrooney 23:952530fa968d 528 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
tmulrooney 23:952530fa968d 529 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
tmulrooney 23:952530fa968d 530 {
tmulrooney 23:952530fa968d 531 this->settings.LoRa.LowDatarateOptimize = 0x01;
tmulrooney 23:952530fa968d 532 }
tmulrooney 23:952530fa968d 533 else
tmulrooney 23:952530fa968d 534 {
tmulrooney 23:952530fa968d 535 this->settings.LoRa.LowDatarateOptimize = 0x00;
tmulrooney 23:952530fa968d 536 }
tmulrooney 23:952530fa968d 537
tmulrooney 23:952530fa968d 538 if( this->settings.LoRa.FreqHopOn == true )
tmulrooney 23:952530fa968d 539 {
tmulrooney 23:952530fa968d 540 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
tmulrooney 23:952530fa968d 541 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
tmulrooney 23:952530fa968d 542 }
tmulrooney 23:952530fa968d 543
tmulrooney 23:952530fa968d 544 Write( REG_LR_MODEMCONFIG1,
tmulrooney 23:952530fa968d 545 ( Read( REG_LR_MODEMCONFIG1 ) &
tmulrooney 23:952530fa968d 546 RFLR_MODEMCONFIG1_BW_MASK &
tmulrooney 23:952530fa968d 547 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
tmulrooney 23:952530fa968d 548 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
tmulrooney 23:952530fa968d 549 ( bandwidth << 4 ) | ( coderate << 1 ) |
tmulrooney 23:952530fa968d 550 fixLen );
tmulrooney 23:952530fa968d 551
tmulrooney 23:952530fa968d 552 Write( REG_LR_MODEMCONFIG2,
tmulrooney 23:952530fa968d 553 ( Read( REG_LR_MODEMCONFIG2 ) &
tmulrooney 23:952530fa968d 554 RFLR_MODEMCONFIG2_SF_MASK &
tmulrooney 23:952530fa968d 555 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) |
tmulrooney 23:952530fa968d 556 ( datarate << 4 ) | ( crcOn << 2 ) );
tmulrooney 23:952530fa968d 557
tmulrooney 23:952530fa968d 558 Write( REG_LR_MODEMCONFIG3,
tmulrooney 23:952530fa968d 559 ( Read( REG_LR_MODEMCONFIG3 ) &
tmulrooney 23:952530fa968d 560 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
tmulrooney 23:952530fa968d 561 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
tmulrooney 23:952530fa968d 562
tmulrooney 23:952530fa968d 563 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
tmulrooney 23:952530fa968d 564 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
tmulrooney 23:952530fa968d 565
tmulrooney 23:952530fa968d 566 if( datarate == 6 )
tmulrooney 23:952530fa968d 567 {
tmulrooney 23:952530fa968d 568 Write( REG_LR_DETECTOPTIMIZE,
tmulrooney 23:952530fa968d 569 ( Read( REG_LR_DETECTOPTIMIZE ) &
tmulrooney 23:952530fa968d 570 RFLR_DETECTIONOPTIMIZE_MASK ) |
tmulrooney 23:952530fa968d 571 RFLR_DETECTIONOPTIMIZE_SF6 );
tmulrooney 23:952530fa968d 572 Write( REG_LR_DETECTIONTHRESHOLD,
tmulrooney 23:952530fa968d 573 RFLR_DETECTIONTHRESH_SF6 );
tmulrooney 23:952530fa968d 574 }
tmulrooney 23:952530fa968d 575 else
tmulrooney 23:952530fa968d 576 {
tmulrooney 23:952530fa968d 577 Write( REG_LR_DETECTOPTIMIZE,
tmulrooney 23:952530fa968d 578 ( Read( REG_LR_DETECTOPTIMIZE ) &
tmulrooney 23:952530fa968d 579 RFLR_DETECTIONOPTIMIZE_MASK ) |
tmulrooney 23:952530fa968d 580 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
tmulrooney 23:952530fa968d 581 Write( REG_LR_DETECTIONTHRESHOLD,
tmulrooney 23:952530fa968d 582 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
tmulrooney 23:952530fa968d 583 }
tmulrooney 23:952530fa968d 584 }
tmulrooney 23:952530fa968d 585 break;
tmulrooney 23:952530fa968d 586 }
tmulrooney 23:952530fa968d 587 }
tmulrooney 23:952530fa968d 588
tmulrooney 23:952530fa968d 589 double SX1272::TimeOnAir( RadioModems_t modem, uint8_t pktLen )
tmulrooney 23:952530fa968d 590 {
tmulrooney 23:952530fa968d 591 debug("TimeOnAir\r\n");
tmulrooney 23:952530fa968d 592 uint32_t airTime = 0;
tmulrooney 23:952530fa968d 593
tmulrooney 23:952530fa968d 594 switch( modem )
tmulrooney 23:952530fa968d 595 {
tmulrooney 23:952530fa968d 596 case MODEM_FSK:
tmulrooney 23:952530fa968d 597 {
tmulrooney 23:952530fa968d 598 airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen +
tmulrooney 23:952530fa968d 599 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
tmulrooney 23:952530fa968d 600 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
tmulrooney 23:952530fa968d 601 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
tmulrooney 23:952530fa968d 602 pktLen +
tmulrooney 23:952530fa968d 603 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
tmulrooney 23:952530fa968d 604 this->settings.Fsk.Datarate ) * 1e6 );
tmulrooney 23:952530fa968d 605 }
tmulrooney 23:952530fa968d 606 break;
tmulrooney 23:952530fa968d 607 case MODEM_LORA:
tmulrooney 23:952530fa968d 608 {
tmulrooney 23:952530fa968d 609 double bw = 0.0;
tmulrooney 23:952530fa968d 610 // REMARK: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
tmulrooney 23:952530fa968d 611 switch( this->settings.LoRa.Bandwidth )
tmulrooney 23:952530fa968d 612 {
tmulrooney 23:952530fa968d 613 //case 0: // 7.8 kHz
tmulrooney 23:952530fa968d 614 // bw = 78e2;
tmulrooney 23:952530fa968d 615 // break;
tmulrooney 23:952530fa968d 616 //case 1: // 10.4 kHz
tmulrooney 23:952530fa968d 617 // bw = 104e2;
tmulrooney 23:952530fa968d 618 // break;
tmulrooney 23:952530fa968d 619 //case 2: // 15.6 kHz
tmulrooney 23:952530fa968d 620 // bw = 156e2;
tmulrooney 23:952530fa968d 621 // break;
tmulrooney 23:952530fa968d 622 //case 3: // 20.8 kHz
tmulrooney 23:952530fa968d 623 // bw = 208e2;
tmulrooney 23:952530fa968d 624 // break;
tmulrooney 23:952530fa968d 625 //case 4: // 31.2 kHz
tmulrooney 23:952530fa968d 626 // bw = 312e2;
tmulrooney 23:952530fa968d 627 // break;
tmulrooney 23:952530fa968d 628 //case 5: // 41.4 kHz
tmulrooney 23:952530fa968d 629 // bw = 414e2;
tmulrooney 23:952530fa968d 630 // break;
tmulrooney 23:952530fa968d 631 //case 6: // 62.5 kHz
tmulrooney 23:952530fa968d 632 // bw = 625e2;
tmulrooney 23:952530fa968d 633 // break;
tmulrooney 23:952530fa968d 634 case 7: // 125 kHz
tmulrooney 23:952530fa968d 635 bw = 125e3;
tmulrooney 23:952530fa968d 636 break;
tmulrooney 23:952530fa968d 637 case 8: // 250 kHz
tmulrooney 23:952530fa968d 638 bw = 250e3;
tmulrooney 23:952530fa968d 639 break;
tmulrooney 23:952530fa968d 640 case 9: // 500 kHz
tmulrooney 23:952530fa968d 641 bw = 500e3;
tmulrooney 23:952530fa968d 642 break;
tmulrooney 23:952530fa968d 643 }
tmulrooney 23:952530fa968d 644
tmulrooney 23:952530fa968d 645 // Symbol rate : time for one symbol (secs)
tmulrooney 23:952530fa968d 646 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
tmulrooney 23:952530fa968d 647 double ts = 1 / rs;
tmulrooney 23:952530fa968d 648 // time of preamble
tmulrooney 23:952530fa968d 649 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
tmulrooney 23:952530fa968d 650 // Symbol length of payload and time
tmulrooney 23:952530fa968d 651 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
tmulrooney 23:952530fa968d 652 28 + 16 * this->settings.LoRa.CrcOn -
tmulrooney 23:952530fa968d 653 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
tmulrooney 23:952530fa968d 654 ( double )( 4 * this->settings.LoRa.Datarate -
tmulrooney 23:952530fa968d 655 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) *
tmulrooney 23:952530fa968d 656 ( this->settings.LoRa.Coderate + 4 );
tmulrooney 23:952530fa968d 657 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
tmulrooney 23:952530fa968d 658 double tPayload = nPayload * ts;
tmulrooney 23:952530fa968d 659 // Time on air
tmulrooney 23:952530fa968d 660 double tOnAir = tPreamble + tPayload;
tmulrooney 23:952530fa968d 661 // return us secs
tmulrooney 23:952530fa968d 662 airTime = floor( tOnAir * 1e6 + 0.999 );
tmulrooney 23:952530fa968d 663 }
tmulrooney 23:952530fa968d 664 break;
tmulrooney 23:952530fa968d 665 }
tmulrooney 23:952530fa968d 666 return airTime;
tmulrooney 23:952530fa968d 667 }
tmulrooney 23:952530fa968d 668
tmulrooney 23:952530fa968d 669 void SX1272::Send( uint8_t *buffer, uint8_t size )
tmulrooney 23:952530fa968d 670 {
tmulrooney 23:952530fa968d 671 debug("Send\r\n");
tmulrooney 23:952530fa968d 672 uint32_t txTimeout = 0;
tmulrooney 23:952530fa968d 673
tmulrooney 23:952530fa968d 674 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 675 {
tmulrooney 23:952530fa968d 676 case MODEM_FSK:
tmulrooney 23:952530fa968d 677 {
tmulrooney 23:952530fa968d 678 this->settings.FskPacketHandler.NbBytes = 0;
tmulrooney 23:952530fa968d 679 this->settings.FskPacketHandler.Size = size;
tmulrooney 23:952530fa968d 680
tmulrooney 23:952530fa968d 681 if( this->settings.Fsk.FixLen == false )
tmulrooney 23:952530fa968d 682 {
tmulrooney 23:952530fa968d 683 WriteFifo( ( uint8_t* )&size, 1 );
tmulrooney 23:952530fa968d 684 }
tmulrooney 23:952530fa968d 685 else
tmulrooney 23:952530fa968d 686 {
tmulrooney 23:952530fa968d 687 Write( REG_PAYLOADLENGTH, size );
tmulrooney 23:952530fa968d 688 }
tmulrooney 23:952530fa968d 689
tmulrooney 23:952530fa968d 690 if( ( size > 0 ) && ( size <= 64 ) )
tmulrooney 23:952530fa968d 691 {
tmulrooney 23:952530fa968d 692 this->settings.FskPacketHandler.ChunkSize = size;
tmulrooney 23:952530fa968d 693 }
tmulrooney 23:952530fa968d 694 else
tmulrooney 23:952530fa968d 695 {
tmulrooney 23:952530fa968d 696 this->settings.FskPacketHandler.ChunkSize = 32;
tmulrooney 23:952530fa968d 697 }
tmulrooney 23:952530fa968d 698
tmulrooney 23:952530fa968d 699 // Write payload buffer
tmulrooney 23:952530fa968d 700 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
tmulrooney 23:952530fa968d 701 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
tmulrooney 23:952530fa968d 702 txTimeout = this->settings.Fsk.TxTimeout;
tmulrooney 23:952530fa968d 703 }
tmulrooney 23:952530fa968d 704 break;
tmulrooney 23:952530fa968d 705 case MODEM_LORA:
tmulrooney 23:952530fa968d 706 {
tmulrooney 23:952530fa968d 707 if( this->settings.LoRa.IqInverted == true )
tmulrooney 23:952530fa968d 708 {
tmulrooney 23:952530fa968d 709 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
tmulrooney 23:952530fa968d 710 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
tmulrooney 23:952530fa968d 711 }
tmulrooney 23:952530fa968d 712 else
tmulrooney 23:952530fa968d 713 {
tmulrooney 23:952530fa968d 714 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
tmulrooney 23:952530fa968d 715 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
tmulrooney 23:952530fa968d 716 }
tmulrooney 23:952530fa968d 717
tmulrooney 23:952530fa968d 718 this->settings.LoRaPacketHandler.Size = size;
tmulrooney 23:952530fa968d 719
tmulrooney 23:952530fa968d 720 // Initializes the payload size
tmulrooney 23:952530fa968d 721 Write( REG_LR_PAYLOADLENGTH, size );
tmulrooney 23:952530fa968d 722
tmulrooney 23:952530fa968d 723 // Full buffer used for Tx
tmulrooney 23:952530fa968d 724 Write( REG_LR_FIFOTXBASEADDR, 0 );
tmulrooney 23:952530fa968d 725 Write( REG_LR_FIFOADDRPTR, 0 );
tmulrooney 23:952530fa968d 726
tmulrooney 23:952530fa968d 727 // FIFO operations can not take place in Sleep mode
tmulrooney 23:952530fa968d 728 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
tmulrooney 23:952530fa968d 729 {
tmulrooney 23:952530fa968d 730 Standby( );
tmulrooney 23:952530fa968d 731 wait_ms( 1 );
tmulrooney 23:952530fa968d 732 }
tmulrooney 23:952530fa968d 733 // Write payload buffer
tmulrooney 23:952530fa968d 734 WriteFifo( buffer, size );
tmulrooney 23:952530fa968d 735 txTimeout = this->settings.LoRa.TxTimeout;
tmulrooney 23:952530fa968d 736 }
tmulrooney 23:952530fa968d 737 break;
tmulrooney 23:952530fa968d 738 }
tmulrooney 23:952530fa968d 739
tmulrooney 23:952530fa968d 740 Tx( txTimeout );
tmulrooney 23:952530fa968d 741 }
tmulrooney 23:952530fa968d 742
tmulrooney 23:952530fa968d 743 void SX1272::Sleep( void )
tmulrooney 23:952530fa968d 744 {
tmulrooney 23:952530fa968d 745 debug("Sleep\r\n");
tmulrooney 23:952530fa968d 746 txTimeoutTimer.detach( );
tmulrooney 23:952530fa968d 747 rxTimeoutTimer.detach( );
tmulrooney 23:952530fa968d 748
tmulrooney 23:952530fa968d 749 SetOpMode( RF_OPMODE_SLEEP );
tmulrooney 23:952530fa968d 750 this->settings.State = RF_IDLE;
tmulrooney 23:952530fa968d 751 }
tmulrooney 23:952530fa968d 752
tmulrooney 23:952530fa968d 753 void SX1272::Standby( void )
tmulrooney 23:952530fa968d 754 {
tmulrooney 23:952530fa968d 755 debug("Standby\r\n");
tmulrooney 23:952530fa968d 756 txTimeoutTimer.detach( );
tmulrooney 23:952530fa968d 757 rxTimeoutTimer.detach( );
tmulrooney 23:952530fa968d 758
tmulrooney 23:952530fa968d 759 SetOpMode( RF_OPMODE_STANDBY );
tmulrooney 23:952530fa968d 760 this->settings.State = RF_IDLE;
tmulrooney 23:952530fa968d 761 }
tmulrooney 23:952530fa968d 762
tmulrooney 23:952530fa968d 763 void SX1272::Rx( uint32_t timeout )
tmulrooney 23:952530fa968d 764 {
tmulrooney 23:952530fa968d 765 debug("Rx enter %d\r\n",timeout);
tmulrooney 23:952530fa968d 766 bool rxContinuous = false;
tmulrooney 23:952530fa968d 767
tmulrooney 23:952530fa968d 768 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 769 {
tmulrooney 23:952530fa968d 770 case MODEM_FSK:
tmulrooney 23:952530fa968d 771 {
tmulrooney 23:952530fa968d 772 rxContinuous = this->settings.Fsk.RxContinuous;
tmulrooney 23:952530fa968d 773
tmulrooney 23:952530fa968d 774 // DIO0=PayloadReady
tmulrooney 23:952530fa968d 775 // DIO1=FifoLevel
tmulrooney 23:952530fa968d 776 // DIO2=SyncAddr
tmulrooney 23:952530fa968d 777 // DIO3=FifoEmpty
tmulrooney 23:952530fa968d 778 // DIO4=Preamble
tmulrooney 23:952530fa968d 779 // DIO5=ModeReady
tmulrooney 23:952530fa968d 780 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
tmulrooney 23:952530fa968d 781 RF_DIOMAPPING1_DIO2_MASK ) |
tmulrooney 23:952530fa968d 782 RF_DIOMAPPING1_DIO0_00 |
tmulrooney 23:952530fa968d 783 RF_DIOMAPPING1_DIO2_11 );
tmulrooney 23:952530fa968d 784
tmulrooney 23:952530fa968d 785 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
tmulrooney 23:952530fa968d 786 RF_DIOMAPPING2_MAP_MASK ) |
tmulrooney 23:952530fa968d 787 RF_DIOMAPPING2_DIO4_11 |
tmulrooney 23:952530fa968d 788 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
tmulrooney 23:952530fa968d 789
tmulrooney 23:952530fa968d 790 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
tmulrooney 23:952530fa968d 791
tmulrooney 23:952530fa968d 792 this->settings.FskPacketHandler.PreambleDetected = false;
tmulrooney 23:952530fa968d 793 this->settings.FskPacketHandler.SyncWordDetected = false;
tmulrooney 23:952530fa968d 794 this->settings.FskPacketHandler.NbBytes = 0;
tmulrooney 23:952530fa968d 795 this->settings.FskPacketHandler.Size = 0;
tmulrooney 23:952530fa968d 796 }
tmulrooney 23:952530fa968d 797 break;
tmulrooney 23:952530fa968d 798 case MODEM_LORA:
tmulrooney 23:952530fa968d 799 {
tmulrooney 23:952530fa968d 800 if( this->settings.LoRa.IqInverted == true )
tmulrooney 23:952530fa968d 801 {
tmulrooney 23:952530fa968d 802 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
tmulrooney 23:952530fa968d 803 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
tmulrooney 23:952530fa968d 804 }
tmulrooney 23:952530fa968d 805 else
tmulrooney 23:952530fa968d 806 {
tmulrooney 23:952530fa968d 807 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
tmulrooney 23:952530fa968d 808 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
tmulrooney 23:952530fa968d 809 }
tmulrooney 23:952530fa968d 810
tmulrooney 23:952530fa968d 811
tmulrooney 23:952530fa968d 812 // ERRATA 2.3 - Receiver Spurious Reception of a LoRa Signal
tmulrooney 23:952530fa968d 813 if( this->settings.LoRa.Bandwidth < 9 )
tmulrooney 23:952530fa968d 814 {
tmulrooney 23:952530fa968d 815 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) & 0x7F );
tmulrooney 23:952530fa968d 816 Write( REG_LR_TEST30, 0x00 );
tmulrooney 23:952530fa968d 817 switch( this->settings.LoRa.Bandwidth )
tmulrooney 23:952530fa968d 818 {
tmulrooney 23:952530fa968d 819 case 0: // 7.8 kHz
tmulrooney 23:952530fa968d 820 Write( REG_LR_TEST2F, 0x48 );
tmulrooney 23:952530fa968d 821 SetChannel(this->settings.Channel + 7.81e3 );
tmulrooney 23:952530fa968d 822 break;
tmulrooney 23:952530fa968d 823 case 1: // 10.4 kHz
tmulrooney 23:952530fa968d 824 Write( REG_LR_TEST2F, 0x44 );
tmulrooney 23:952530fa968d 825 SetChannel(this->settings.Channel + 10.42e3 );
tmulrooney 23:952530fa968d 826 break;
tmulrooney 23:952530fa968d 827 case 2: // 15.6 kHz
tmulrooney 23:952530fa968d 828 Write( REG_LR_TEST2F, 0x44 );
tmulrooney 23:952530fa968d 829 SetChannel(this->settings.Channel + 15.62e3 );
tmulrooney 23:952530fa968d 830 break;
tmulrooney 23:952530fa968d 831 case 3: // 20.8 kHz
tmulrooney 23:952530fa968d 832 Write( REG_LR_TEST2F, 0x44 );
tmulrooney 23:952530fa968d 833 SetChannel(this->settings.Channel + 20.83e3 );
tmulrooney 23:952530fa968d 834 break;
tmulrooney 23:952530fa968d 835 case 4: // 31.2 kHz
tmulrooney 23:952530fa968d 836 Write( REG_LR_TEST2F, 0x44 );
tmulrooney 23:952530fa968d 837 SetChannel(this->settings.Channel + 31.25e3 );
tmulrooney 23:952530fa968d 838 break;
tmulrooney 23:952530fa968d 839 case 5: // 41.4 kHz
tmulrooney 23:952530fa968d 840 Write( REG_LR_TEST2F, 0x44 );
tmulrooney 23:952530fa968d 841 SetChannel(this->settings.Channel + 41.67e3 );
tmulrooney 23:952530fa968d 842 break;
tmulrooney 23:952530fa968d 843 case 6: // 62.5 kHz
tmulrooney 23:952530fa968d 844 Write( REG_LR_TEST2F, 0x40 );
tmulrooney 23:952530fa968d 845 break;
tmulrooney 23:952530fa968d 846 case 7: // 125 kHz
tmulrooney 23:952530fa968d 847 Write( REG_LR_TEST2F, 0x40 );
tmulrooney 23:952530fa968d 848 break;
tmulrooney 23:952530fa968d 849 case 8: // 250 kHz
tmulrooney 23:952530fa968d 850 Write( REG_LR_TEST2F, 0x40 );
tmulrooney 23:952530fa968d 851 break;
tmulrooney 23:952530fa968d 852 }
tmulrooney 23:952530fa968d 853 }
tmulrooney 23:952530fa968d 854 else
tmulrooney 23:952530fa968d 855 {
tmulrooney 23:952530fa968d 856 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) | 0x80 );
tmulrooney 23:952530fa968d 857 }
tmulrooney 23:952530fa968d 858 this->settings.LoRa.RxContinuous = true; /* *********** added for test TJM **********/
tmulrooney 23:952530fa968d 859 rxContinuous = this->settings.LoRa.RxContinuous;
tmulrooney 23:952530fa968d 860
tmulrooney 23:952530fa968d 861 if( this->settings.LoRa.FreqHopOn == true )
tmulrooney 23:952530fa968d 862 {
tmulrooney 23:952530fa968d 863 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
tmulrooney 23:952530fa968d 864 //RFLR_IRQFLAGS_RXDONE |
tmulrooney 23:952530fa968d 865 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
tmulrooney 23:952530fa968d 866 RFLR_IRQFLAGS_VALIDHEADER |
tmulrooney 23:952530fa968d 867 RFLR_IRQFLAGS_TXDONE |
tmulrooney 23:952530fa968d 868 RFLR_IRQFLAGS_CADDONE |
tmulrooney 23:952530fa968d 869 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
tmulrooney 23:952530fa968d 870 RFLR_IRQFLAGS_CADDETECTED );
tmulrooney 23:952530fa968d 871
tmulrooney 23:952530fa968d 872 // DIO0=RxDone, DIO2=FhssChangeChannel
tmulrooney 23:952530fa968d 873 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
tmulrooney 23:952530fa968d 874 }
tmulrooney 23:952530fa968d 875 else
tmulrooney 23:952530fa968d 876 {
tmulrooney 23:952530fa968d 877 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
tmulrooney 23:952530fa968d 878 //RFLR_IRQFLAGS_RXDONE |
tmulrooney 23:952530fa968d 879 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
tmulrooney 23:952530fa968d 880 RFLR_IRQFLAGS_VALIDHEADER |
tmulrooney 23:952530fa968d 881 RFLR_IRQFLAGS_TXDONE |
tmulrooney 23:952530fa968d 882 RFLR_IRQFLAGS_CADDONE |
tmulrooney 23:952530fa968d 883 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
tmulrooney 23:952530fa968d 884 RFLR_IRQFLAGS_CADDETECTED );
tmulrooney 23:952530fa968d 885
tmulrooney 23:952530fa968d 886 // DIO0=RxDone
tmulrooney 23:952530fa968d 887 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
tmulrooney 23:952530fa968d 888 }
tmulrooney 23:952530fa968d 889 Write( REG_LR_FIFORXBASEADDR, 0 );
tmulrooney 23:952530fa968d 890 Write( REG_LR_FIFOADDRPTR, 0 );
tmulrooney 23:952530fa968d 891 }
tmulrooney 23:952530fa968d 892 break;
tmulrooney 23:952530fa968d 893 }
tmulrooney 23:952530fa968d 894
tmulrooney 23:952530fa968d 895 memset( rxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
tmulrooney 23:952530fa968d 896
tmulrooney 23:952530fa968d 897 this->settings.State = RF_RX_RUNNING;
tmulrooney 23:952530fa968d 898 if( timeout != 0 )
tmulrooney 23:952530fa968d 899 {
tmulrooney 23:952530fa968d 900 rxTimeoutTimer.attach_us( this, &SX1272::OnTimeoutIrq, timeout );
tmulrooney 23:952530fa968d 901 }
tmulrooney 23:952530fa968d 902
tmulrooney 23:952530fa968d 903 if( this->settings.Modem == MODEM_FSK )
tmulrooney 23:952530fa968d 904 {
tmulrooney 23:952530fa968d 905 SetOpMode( RF_OPMODE_RECEIVER );
tmulrooney 23:952530fa968d 906
tmulrooney 23:952530fa968d 907 if( rxContinuous == false )
tmulrooney 23:952530fa968d 908 {
tmulrooney 23:952530fa968d 909 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
tmulrooney 23:952530fa968d 910 ( ( Read( REG_SYNCCONFIG ) &
tmulrooney 23:952530fa968d 911 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
tmulrooney 23:952530fa968d 912 1.0 ) + 10.0 ) /
tmulrooney 23:952530fa968d 913 ( double )this->settings.Fsk.Datarate ) * 1e6 );
tmulrooney 23:952530fa968d 914 }
tmulrooney 23:952530fa968d 915 }
tmulrooney 23:952530fa968d 916 else
tmulrooney 23:952530fa968d 917 {
tmulrooney 23:952530fa968d 918 debug("rxContinuous %d\r\n",rxContinuous);
tmulrooney 23:952530fa968d 919 if( rxContinuous == true )
tmulrooney 23:952530fa968d 920 {
tmulrooney 23:952530fa968d 921 SetOpMode( RFLR_OPMODE_RECEIVER );
tmulrooney 23:952530fa968d 922 }
tmulrooney 23:952530fa968d 923 else
tmulrooney 23:952530fa968d 924 {
tmulrooney 23:952530fa968d 925 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
tmulrooney 23:952530fa968d 926 }
tmulrooney 23:952530fa968d 927 }
tmulrooney 23:952530fa968d 928 }
tmulrooney 23:952530fa968d 929
tmulrooney 23:952530fa968d 930 void SX1272::Tx( uint32_t timeout )
tmulrooney 23:952530fa968d 931 {
tmulrooney 23:952530fa968d 932 debug("Tx enter\r\n");
tmulrooney 23:952530fa968d 933
tmulrooney 23:952530fa968d 934 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 935 {
tmulrooney 23:952530fa968d 936 case MODEM_FSK:
tmulrooney 23:952530fa968d 937 {
tmulrooney 23:952530fa968d 938 // DIO0=PacketSent
tmulrooney 23:952530fa968d 939 // DIO1=FifoLevel
tmulrooney 23:952530fa968d 940 // DIO2=FifoFull
tmulrooney 23:952530fa968d 941 // DIO3=FifoEmpty
tmulrooney 23:952530fa968d 942 // DIO4=LowBat
tmulrooney 23:952530fa968d 943 // DIO5=ModeReady
tmulrooney 23:952530fa968d 944 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
tmulrooney 23:952530fa968d 945 RF_DIOMAPPING1_DIO2_MASK ) );
tmulrooney 23:952530fa968d 946
tmulrooney 23:952530fa968d 947 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
tmulrooney 23:952530fa968d 948 RF_DIOMAPPING2_MAP_MASK ) );
tmulrooney 23:952530fa968d 949 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
tmulrooney 23:952530fa968d 950 }
tmulrooney 23:952530fa968d 951 break;
tmulrooney 23:952530fa968d 952 case MODEM_LORA:
tmulrooney 23:952530fa968d 953 {
tmulrooney 23:952530fa968d 954 if( this->settings.LoRa.FreqHopOn == true )
tmulrooney 23:952530fa968d 955 {
tmulrooney 23:952530fa968d 956 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
tmulrooney 23:952530fa968d 957 RFLR_IRQFLAGS_RXDONE |
tmulrooney 23:952530fa968d 958 RFLR_IRQFLAGS_PAYLOADCRCERROR |
tmulrooney 23:952530fa968d 959 RFLR_IRQFLAGS_VALIDHEADER |
tmulrooney 23:952530fa968d 960 //RFLR_IRQFLAGS_TXDONE |
tmulrooney 23:952530fa968d 961 RFLR_IRQFLAGS_CADDONE |
tmulrooney 23:952530fa968d 962 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
tmulrooney 23:952530fa968d 963 RFLR_IRQFLAGS_CADDETECTED );
tmulrooney 23:952530fa968d 964
tmulrooney 23:952530fa968d 965 // DIO0=TxDone, DIO2=FhssChangeChannel
tmulrooney 23:952530fa968d 966 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
tmulrooney 23:952530fa968d 967 }
tmulrooney 23:952530fa968d 968 else
tmulrooney 23:952530fa968d 969 {
tmulrooney 23:952530fa968d 970 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
tmulrooney 23:952530fa968d 971 RFLR_IRQFLAGS_RXDONE |
tmulrooney 23:952530fa968d 972 RFLR_IRQFLAGS_PAYLOADCRCERROR |
tmulrooney 23:952530fa968d 973 RFLR_IRQFLAGS_VALIDHEADER |
tmulrooney 23:952530fa968d 974 //RFLR_IRQFLAGS_TXDONE |
tmulrooney 23:952530fa968d 975 RFLR_IRQFLAGS_CADDONE |
tmulrooney 23:952530fa968d 976 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
tmulrooney 23:952530fa968d 977 RFLR_IRQFLAGS_CADDETECTED );
tmulrooney 23:952530fa968d 978
tmulrooney 23:952530fa968d 979 // DIO0=TxDone
tmulrooney 23:952530fa968d 980 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
tmulrooney 23:952530fa968d 981 }
tmulrooney 23:952530fa968d 982 }
tmulrooney 23:952530fa968d 983 break;
tmulrooney 23:952530fa968d 984 }
tmulrooney 23:952530fa968d 985
tmulrooney 23:952530fa968d 986 this->settings.State = RF_TX_RUNNING;
tmulrooney 23:952530fa968d 987 txTimeoutTimer.attach_us( this, &SX1272::OnTimeoutIrq, timeout );
tmulrooney 23:952530fa968d 988 SetOpMode( RF_OPMODE_TRANSMITTER );
tmulrooney 23:952530fa968d 989 }
tmulrooney 23:952530fa968d 990
tmulrooney 23:952530fa968d 991 void SX1272::StartCad( void )
tmulrooney 23:952530fa968d 992 {
tmulrooney 23:952530fa968d 993 debug("StartCad\r\n");
tmulrooney 23:952530fa968d 994 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 995 {
tmulrooney 23:952530fa968d 996 case MODEM_FSK:
tmulrooney 23:952530fa968d 997 {
tmulrooney 23:952530fa968d 998
tmulrooney 23:952530fa968d 999 }
tmulrooney 23:952530fa968d 1000 break;
tmulrooney 23:952530fa968d 1001 case MODEM_LORA:
tmulrooney 23:952530fa968d 1002 {
tmulrooney 23:952530fa968d 1003 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
tmulrooney 23:952530fa968d 1004 RFLR_IRQFLAGS_RXDONE |
tmulrooney 23:952530fa968d 1005 RFLR_IRQFLAGS_PAYLOADCRCERROR |
tmulrooney 23:952530fa968d 1006 RFLR_IRQFLAGS_VALIDHEADER |
tmulrooney 23:952530fa968d 1007 RFLR_IRQFLAGS_TXDONE |
tmulrooney 23:952530fa968d 1008 //RFLR_IRQFLAGS_CADDONE |
tmulrooney 23:952530fa968d 1009 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
tmulrooney 23:952530fa968d 1010 //RFLR_IRQFLAGS_CADDETECTED
tmulrooney 23:952530fa968d 1011 );
tmulrooney 23:952530fa968d 1012
tmulrooney 23:952530fa968d 1013 // DIO3=CADDone
tmulrooney 23:952530fa968d 1014 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
tmulrooney 23:952530fa968d 1015
tmulrooney 23:952530fa968d 1016 this->settings.State = RF_CAD;
tmulrooney 23:952530fa968d 1017 SetOpMode( RFLR_OPMODE_CAD );
tmulrooney 23:952530fa968d 1018 }
tmulrooney 23:952530fa968d 1019 break;
tmulrooney 23:952530fa968d 1020 default:
tmulrooney 23:952530fa968d 1021 break;
tmulrooney 23:952530fa968d 1022 }
tmulrooney 23:952530fa968d 1023 }
tmulrooney 23:952530fa968d 1024
tmulrooney 23:952530fa968d 1025 int16_t SX1272::GetRssi( RadioModems_t modem )
tmulrooney 23:952530fa968d 1026 {
tmulrooney 23:952530fa968d 1027 debug("GetRssi\r\n");
tmulrooney 23:952530fa968d 1028 int16_t rssi = 0;
tmulrooney 23:952530fa968d 1029
tmulrooney 23:952530fa968d 1030 switch( modem )
tmulrooney 23:952530fa968d 1031 {
tmulrooney 23:952530fa968d 1032 case MODEM_FSK:
tmulrooney 23:952530fa968d 1033 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
tmulrooney 23:952530fa968d 1034 break;
tmulrooney 23:952530fa968d 1035 case MODEM_LORA:
tmulrooney 23:952530fa968d 1036 if( this->settings.Channel > RF_MID_BAND_THRESH )
tmulrooney 23:952530fa968d 1037 {
tmulrooney 23:952530fa968d 1038 rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE );
tmulrooney 23:952530fa968d 1039 }
tmulrooney 23:952530fa968d 1040 else
tmulrooney 23:952530fa968d 1041 {
tmulrooney 23:952530fa968d 1042 rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE );
tmulrooney 23:952530fa968d 1043 }
tmulrooney 23:952530fa968d 1044 break;
tmulrooney 23:952530fa968d 1045 default:
tmulrooney 23:952530fa968d 1046 rssi = -1;
tmulrooney 23:952530fa968d 1047 break;
tmulrooney 23:952530fa968d 1048 }
tmulrooney 23:952530fa968d 1049 return rssi;
tmulrooney 23:952530fa968d 1050 }
tmulrooney 23:952530fa968d 1051
tmulrooney 23:952530fa968d 1052 void SX1272::SetOpMode( uint8_t opMode )
tmulrooney 23:952530fa968d 1053 {
tmulrooney 23:952530fa968d 1054 debug("SetOpMode enter %02X\r\n",opMode);
tmulrooney 23:952530fa968d 1055 if( opMode != previousOpMode )
tmulrooney 23:952530fa968d 1056 {
tmulrooney 23:952530fa968d 1057 previousOpMode = opMode;
tmulrooney 23:952530fa968d 1058 if( opMode == RF_OPMODE_SLEEP )
tmulrooney 23:952530fa968d 1059 {
tmulrooney 23:952530fa968d 1060 SetAntSwLowPower( true );
tmulrooney 23:952530fa968d 1061 }
tmulrooney 23:952530fa968d 1062 else
tmulrooney 23:952530fa968d 1063 {
tmulrooney 23:952530fa968d 1064 SetAntSwLowPower( false );
tmulrooney 23:952530fa968d 1065 if( opMode == RF_OPMODE_TRANSMITTER )
tmulrooney 23:952530fa968d 1066 {
tmulrooney 23:952530fa968d 1067 SetAntSw( 1 );
tmulrooney 23:952530fa968d 1068 }
tmulrooney 23:952530fa968d 1069 else
tmulrooney 23:952530fa968d 1070 {
tmulrooney 23:952530fa968d 1071 SetAntSw( 0 );
tmulrooney 23:952530fa968d 1072 }
tmulrooney 23:952530fa968d 1073 }
tmulrooney 23:952530fa968d 1074 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
tmulrooney 23:952530fa968d 1075 }
tmulrooney 23:952530fa968d 1076 }
tmulrooney 23:952530fa968d 1077
tmulrooney 23:952530fa968d 1078 void SX1272::SetModem( RadioModems_t modem )
tmulrooney 23:952530fa968d 1079 {
tmulrooney 23:952530fa968d 1080 debug("SetModem enter %d\r\n",modem);
tmulrooney 23:952530fa968d 1081 if( this->settings.Modem == modem )
tmulrooney 23:952530fa968d 1082 {
tmulrooney 23:952530fa968d 1083 return;
tmulrooney 23:952530fa968d 1084 }
tmulrooney 23:952530fa968d 1085
tmulrooney 23:952530fa968d 1086 this->settings.Modem = modem;
tmulrooney 23:952530fa968d 1087 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 1088 {
tmulrooney 23:952530fa968d 1089 default:
tmulrooney 23:952530fa968d 1090 case MODEM_FSK:
tmulrooney 23:952530fa968d 1091 SetOpMode( RF_OPMODE_SLEEP );
tmulrooney 23:952530fa968d 1092 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
tmulrooney 23:952530fa968d 1093
tmulrooney 23:952530fa968d 1094 Write( REG_DIOMAPPING1, 0x00 );
tmulrooney 23:952530fa968d 1095 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
tmulrooney 23:952530fa968d 1096 break;
tmulrooney 23:952530fa968d 1097 case MODEM_LORA:
tmulrooney 23:952530fa968d 1098 SetOpMode( RF_OPMODE_SLEEP );
tmulrooney 23:952530fa968d 1099 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
tmulrooney 23:952530fa968d 1100
tmulrooney 23:952530fa968d 1101 Write( REG_DIOMAPPING1, 0x00 );
tmulrooney 23:952530fa968d 1102 Write( REG_DIOMAPPING2, 0x00 );
tmulrooney 23:952530fa968d 1103 break;
tmulrooney 23:952530fa968d 1104 }
tmulrooney 23:952530fa968d 1105 }
tmulrooney 23:952530fa968d 1106
tmulrooney 23:952530fa968d 1107 void SX1272::SetMaxPayloadLength( RadioModems_t modem, uint8_t max )
tmulrooney 23:952530fa968d 1108 {
tmulrooney 23:952530fa968d 1109 debug("SetMaxPayloadLength\r\n");
tmulrooney 23:952530fa968d 1110 this->SetModem( modem );
tmulrooney 23:952530fa968d 1111
tmulrooney 23:952530fa968d 1112 switch( modem )
tmulrooney 23:952530fa968d 1113 {
tmulrooney 23:952530fa968d 1114 case MODEM_FSK:
tmulrooney 23:952530fa968d 1115 if( this->settings.Fsk.FixLen == false )
tmulrooney 23:952530fa968d 1116 {
tmulrooney 23:952530fa968d 1117 this->Write( REG_PAYLOADLENGTH, max );
tmulrooney 23:952530fa968d 1118 }
tmulrooney 23:952530fa968d 1119 break;
tmulrooney 23:952530fa968d 1120 case MODEM_LORA:
tmulrooney 23:952530fa968d 1121 this->Write( REG_LR_PAYLOADMAXLENGTH, max );
tmulrooney 23:952530fa968d 1122 break;
tmulrooney 23:952530fa968d 1123 }
tmulrooney 23:952530fa968d 1124 }
tmulrooney 23:952530fa968d 1125
tmulrooney 23:952530fa968d 1126 void SX1272::OnTimeoutIrq( void )
tmulrooney 23:952530fa968d 1127 {
tmulrooney 23:952530fa968d 1128 debug("OnTimeoutIrq\r\n");
tmulrooney 23:952530fa968d 1129 switch( this->settings.State )
tmulrooney 23:952530fa968d 1130 {
tmulrooney 23:952530fa968d 1131 case RF_RX_RUNNING:
tmulrooney 23:952530fa968d 1132 if( this->settings.Modem == MODEM_FSK )
tmulrooney 23:952530fa968d 1133 {
tmulrooney 23:952530fa968d 1134 this->settings.FskPacketHandler.PreambleDetected = false;
tmulrooney 23:952530fa968d 1135 this->settings.FskPacketHandler.SyncWordDetected = false;
tmulrooney 23:952530fa968d 1136 this->settings.FskPacketHandler.NbBytes = 0;
tmulrooney 23:952530fa968d 1137 this->settings.FskPacketHandler.Size = 0;
tmulrooney 23:952530fa968d 1138
tmulrooney 23:952530fa968d 1139 // Clear Irqs
tmulrooney 23:952530fa968d 1140 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
tmulrooney 23:952530fa968d 1141 RF_IRQFLAGS1_PREAMBLEDETECT |
tmulrooney 23:952530fa968d 1142 RF_IRQFLAGS1_SYNCADDRESSMATCH );
tmulrooney 23:952530fa968d 1143 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
tmulrooney 23:952530fa968d 1144
tmulrooney 23:952530fa968d 1145 if( this->settings.Fsk.RxContinuous == true )
tmulrooney 23:952530fa968d 1146 {
tmulrooney 23:952530fa968d 1147 // Continuous mode restart Rx chain
tmulrooney 23:952530fa968d 1148 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
tmulrooney 23:952530fa968d 1149 }
tmulrooney 23:952530fa968d 1150 else
tmulrooney 23:952530fa968d 1151 {
tmulrooney 23:952530fa968d 1152 this->settings.State = RF_IDLE;
tmulrooney 23:952530fa968d 1153 rxTimeoutSyncWord.detach( );
tmulrooney 23:952530fa968d 1154 }
tmulrooney 23:952530fa968d 1155 }
tmulrooney 23:952530fa968d 1156 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
tmulrooney 23:952530fa968d 1157 {
tmulrooney 23:952530fa968d 1158 this->RadioEvents->RxTimeout( );
tmulrooney 23:952530fa968d 1159 }
tmulrooney 23:952530fa968d 1160 break;
tmulrooney 23:952530fa968d 1161 case RF_TX_RUNNING:
tmulrooney 23:952530fa968d 1162 this->settings.State = RF_IDLE;
tmulrooney 23:952530fa968d 1163 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxTimeout != NULL ) )
tmulrooney 23:952530fa968d 1164 {
tmulrooney 23:952530fa968d 1165 this->RadioEvents->TxTimeout( );
tmulrooney 23:952530fa968d 1166 }
tmulrooney 23:952530fa968d 1167 break;
tmulrooney 23:952530fa968d 1168 default:
tmulrooney 23:952530fa968d 1169 break;
tmulrooney 23:952530fa968d 1170 }
tmulrooney 23:952530fa968d 1171 }
tmulrooney 23:952530fa968d 1172
tmulrooney 23:952530fa968d 1173 void SX1272::OnDio0Irq( void )
tmulrooney 23:952530fa968d 1174 {
tmulrooney 23:952530fa968d 1175 debug("OnDio0Irq enter\r\n");
tmulrooney 23:952530fa968d 1176 volatile uint8_t irqFlags = 0;
tmulrooney 23:952530fa968d 1177
tmulrooney 23:952530fa968d 1178 switch( this->settings.State )
tmulrooney 23:952530fa968d 1179 {
tmulrooney 23:952530fa968d 1180 case RF_RX_RUNNING:
tmulrooney 23:952530fa968d 1181 //TimerStop( &RxTimeoutTimer );
tmulrooney 23:952530fa968d 1182 // RxDone interrupt
tmulrooney 23:952530fa968d 1183 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 1184 {
tmulrooney 23:952530fa968d 1185 case MODEM_FSK:
tmulrooney 23:952530fa968d 1186 if( this->settings.Fsk.CrcOn == true )
tmulrooney 23:952530fa968d 1187 {
tmulrooney 23:952530fa968d 1188 irqFlags = Read( REG_IRQFLAGS2 );
tmulrooney 23:952530fa968d 1189 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
tmulrooney 23:952530fa968d 1190 {
tmulrooney 23:952530fa968d 1191 // Clear Irqs
tmulrooney 23:952530fa968d 1192 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
tmulrooney 23:952530fa968d 1193 RF_IRQFLAGS1_PREAMBLEDETECT |
tmulrooney 23:952530fa968d 1194 RF_IRQFLAGS1_SYNCADDRESSMATCH );
tmulrooney 23:952530fa968d 1195 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
tmulrooney 23:952530fa968d 1196
tmulrooney 23:952530fa968d 1197 if( this->settings.Fsk.RxContinuous == false )
tmulrooney 23:952530fa968d 1198 {
tmulrooney 23:952530fa968d 1199 this->settings.State = RF_IDLE;
tmulrooney 23:952530fa968d 1200 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
tmulrooney 23:952530fa968d 1201 ( ( Read( REG_SYNCCONFIG ) &
tmulrooney 23:952530fa968d 1202 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
tmulrooney 23:952530fa968d 1203 1.0 ) + 10.0 ) /
tmulrooney 23:952530fa968d 1204 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
tmulrooney 23:952530fa968d 1205 }
tmulrooney 23:952530fa968d 1206 else
tmulrooney 23:952530fa968d 1207 {
tmulrooney 23:952530fa968d 1208 // Continuous mode restart Rx chain
tmulrooney 23:952530fa968d 1209 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
tmulrooney 23:952530fa968d 1210 }
tmulrooney 23:952530fa968d 1211 rxTimeoutTimer.detach( );
tmulrooney 23:952530fa968d 1212
tmulrooney 23:952530fa968d 1213 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
tmulrooney 23:952530fa968d 1214 {
tmulrooney 23:952530fa968d 1215 this->RadioEvents->RxError( );
tmulrooney 23:952530fa968d 1216 }
tmulrooney 23:952530fa968d 1217 this->settings.FskPacketHandler.PreambleDetected = false;
tmulrooney 23:952530fa968d 1218 this->settings.FskPacketHandler.SyncWordDetected = false;
tmulrooney 23:952530fa968d 1219 this->settings.FskPacketHandler.NbBytes = 0;
tmulrooney 23:952530fa968d 1220 this->settings.FskPacketHandler.Size = 0;
tmulrooney 23:952530fa968d 1221 break;
tmulrooney 23:952530fa968d 1222 }
tmulrooney 23:952530fa968d 1223 }
tmulrooney 23:952530fa968d 1224
tmulrooney 23:952530fa968d 1225 // Read received packet size
tmulrooney 23:952530fa968d 1226 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
tmulrooney 23:952530fa968d 1227 {
tmulrooney 23:952530fa968d 1228 if( this->settings.Fsk.FixLen == false )
tmulrooney 23:952530fa968d 1229 {
tmulrooney 23:952530fa968d 1230 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
tmulrooney 23:952530fa968d 1231 }
tmulrooney 23:952530fa968d 1232 else
tmulrooney 23:952530fa968d 1233 {
tmulrooney 23:952530fa968d 1234 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
tmulrooney 23:952530fa968d 1235 }
tmulrooney 23:952530fa968d 1236 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:952530fa968d 1237 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:952530fa968d 1238 }
tmulrooney 23:952530fa968d 1239 else
tmulrooney 23:952530fa968d 1240 {
tmulrooney 23:952530fa968d 1241 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:952530fa968d 1242 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:952530fa968d 1243 }
tmulrooney 23:952530fa968d 1244
tmulrooney 23:952530fa968d 1245 if( this->settings.Fsk.RxContinuous == false )
tmulrooney 23:952530fa968d 1246 {
tmulrooney 23:952530fa968d 1247 this->settings.State = RF_IDLE;
tmulrooney 23:952530fa968d 1248 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
tmulrooney 23:952530fa968d 1249 ( ( Read( REG_SYNCCONFIG ) &
tmulrooney 23:952530fa968d 1250 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
tmulrooney 23:952530fa968d 1251 1.0 ) + 10.0 ) /
tmulrooney 23:952530fa968d 1252 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
tmulrooney 23:952530fa968d 1253 }
tmulrooney 23:952530fa968d 1254 else
tmulrooney 23:952530fa968d 1255 {
tmulrooney 23:952530fa968d 1256 // Continuous mode restart Rx chain
tmulrooney 23:952530fa968d 1257 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
tmulrooney 23:952530fa968d 1258 }
tmulrooney 23:952530fa968d 1259 rxTimeoutTimer.detach( );
tmulrooney 23:952530fa968d 1260
tmulrooney 23:952530fa968d 1261 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
tmulrooney 23:952530fa968d 1262 {
tmulrooney 23:952530fa968d 1263 this->RadioEvents->RxDone( rxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
tmulrooney 23:952530fa968d 1264 }
tmulrooney 23:952530fa968d 1265 this->settings.FskPacketHandler.PreambleDetected = false;
tmulrooney 23:952530fa968d 1266 this->settings.FskPacketHandler.SyncWordDetected = false;
tmulrooney 23:952530fa968d 1267 this->settings.FskPacketHandler.NbBytes = 0;
tmulrooney 23:952530fa968d 1268 this->settings.FskPacketHandler.Size = 0;
tmulrooney 23:952530fa968d 1269 break;
tmulrooney 23:952530fa968d 1270 case MODEM_LORA:
tmulrooney 23:952530fa968d 1271 {
tmulrooney 23:952530fa968d 1272 int8_t snr = 0;
tmulrooney 23:952530fa968d 1273
tmulrooney 23:952530fa968d 1274 // Clear Irq
tmulrooney 23:952530fa968d 1275 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
tmulrooney 23:952530fa968d 1276
tmulrooney 23:952530fa968d 1277 irqFlags = Read( REG_LR_IRQFLAGS );
tmulrooney 23:952530fa968d 1278 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
tmulrooney 23:952530fa968d 1279 {
tmulrooney 23:952530fa968d 1280 // Clear Irq
tmulrooney 23:952530fa968d 1281 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
tmulrooney 23:952530fa968d 1282
tmulrooney 23:952530fa968d 1283 if( this->settings.LoRa.RxContinuous == false )
tmulrooney 23:952530fa968d 1284 {
tmulrooney 23:952530fa968d 1285 this->settings.State = RF_IDLE;
tmulrooney 23:952530fa968d 1286 }
tmulrooney 23:952530fa968d 1287 rxTimeoutTimer.detach( );
tmulrooney 23:952530fa968d 1288
tmulrooney 23:952530fa968d 1289 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
tmulrooney 23:952530fa968d 1290 {
tmulrooney 23:952530fa968d 1291 this->RadioEvents->RxError( );
tmulrooney 23:952530fa968d 1292 }
tmulrooney 23:952530fa968d 1293 break;
tmulrooney 23:952530fa968d 1294 }
tmulrooney 23:952530fa968d 1295
tmulrooney 23:952530fa968d 1296 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
tmulrooney 23:952530fa968d 1297 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
tmulrooney 23:952530fa968d 1298 {
tmulrooney 23:952530fa968d 1299 // Invert and divide by 4
tmulrooney 23:952530fa968d 1300 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
tmulrooney 23:952530fa968d 1301 snr = -snr;
tmulrooney 23:952530fa968d 1302 }
tmulrooney 23:952530fa968d 1303 else
tmulrooney 23:952530fa968d 1304 {
tmulrooney 23:952530fa968d 1305 // Divide by 4
tmulrooney 23:952530fa968d 1306 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
tmulrooney 23:952530fa968d 1307 }
tmulrooney 23:952530fa968d 1308
tmulrooney 23:952530fa968d 1309 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
tmulrooney 23:952530fa968d 1310 if( snr < 0 )
tmulrooney 23:952530fa968d 1311 {
tmulrooney 23:952530fa968d 1312 if( this->settings.Channel > RF_MID_BAND_THRESH )
tmulrooney 23:952530fa968d 1313 {
tmulrooney 23:952530fa968d 1314 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) +
tmulrooney 23:952530fa968d 1315 snr;
tmulrooney 23:952530fa968d 1316 }
tmulrooney 23:952530fa968d 1317 else
tmulrooney 23:952530fa968d 1318 {
tmulrooney 23:952530fa968d 1319 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) +
tmulrooney 23:952530fa968d 1320 snr;
tmulrooney 23:952530fa968d 1321 }
tmulrooney 23:952530fa968d 1322 }
tmulrooney 23:952530fa968d 1323 else
tmulrooney 23:952530fa968d 1324 {
tmulrooney 23:952530fa968d 1325 if( this->settings.Channel > RF_MID_BAND_THRESH )
tmulrooney 23:952530fa968d 1326 {
tmulrooney 23:952530fa968d 1327 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 );
tmulrooney 23:952530fa968d 1328 }
tmulrooney 23:952530fa968d 1329 else
tmulrooney 23:952530fa968d 1330 {
tmulrooney 23:952530fa968d 1331 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 );
tmulrooney 23:952530fa968d 1332 }
tmulrooney 23:952530fa968d 1333 }
tmulrooney 23:952530fa968d 1334
tmulrooney 23:952530fa968d 1335 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
tmulrooney 23:952530fa968d 1336 ReadFifo( rxBuffer, this->settings.LoRaPacketHandler.Size );
tmulrooney 23:952530fa968d 1337
tmulrooney 23:952530fa968d 1338 if( this->settings.LoRa.RxContinuous == false )
tmulrooney 23:952530fa968d 1339 {
tmulrooney 23:952530fa968d 1340 this->settings.State = RF_IDLE;
tmulrooney 23:952530fa968d 1341 }
tmulrooney 23:952530fa968d 1342 rxTimeoutTimer.detach( );
tmulrooney 23:952530fa968d 1343
tmulrooney 23:952530fa968d 1344 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
tmulrooney 23:952530fa968d 1345 {
tmulrooney 23:952530fa968d 1346 this->RadioEvents->RxDone( rxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
tmulrooney 23:952530fa968d 1347 }
tmulrooney 23:952530fa968d 1348 }
tmulrooney 23:952530fa968d 1349 break;
tmulrooney 23:952530fa968d 1350 default:
tmulrooney 23:952530fa968d 1351 break;
tmulrooney 23:952530fa968d 1352 }
tmulrooney 23:952530fa968d 1353 break;
tmulrooney 23:952530fa968d 1354 case RF_TX_RUNNING:
tmulrooney 23:952530fa968d 1355 txTimeoutTimer.detach( );
tmulrooney 23:952530fa968d 1356 // TxDone interrupt
tmulrooney 23:952530fa968d 1357 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 1358 {
tmulrooney 23:952530fa968d 1359 case MODEM_LORA:
tmulrooney 23:952530fa968d 1360 // Clear Irq
tmulrooney 23:952530fa968d 1361 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
tmulrooney 23:952530fa968d 1362 // Intentional fall through
tmulrooney 23:952530fa968d 1363 case MODEM_FSK:
tmulrooney 23:952530fa968d 1364 default:
tmulrooney 23:952530fa968d 1365 this->settings.State = RF_IDLE;
tmulrooney 23:952530fa968d 1366 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) )
tmulrooney 23:952530fa968d 1367 {
tmulrooney 23:952530fa968d 1368 this->RadioEvents->TxDone( );
tmulrooney 23:952530fa968d 1369 }
tmulrooney 23:952530fa968d 1370 break;
tmulrooney 23:952530fa968d 1371 }
tmulrooney 23:952530fa968d 1372 break;
tmulrooney 23:952530fa968d 1373 default:
tmulrooney 23:952530fa968d 1374 break;
tmulrooney 23:952530fa968d 1375 }
tmulrooney 23:952530fa968d 1376 }
tmulrooney 23:952530fa968d 1377
tmulrooney 23:952530fa968d 1378 void SX1272::OnDio1Irq( void )
tmulrooney 23:952530fa968d 1379 {
tmulrooney 23:952530fa968d 1380 debug("OnDio1Irq\r\n");
tmulrooney 23:952530fa968d 1381 switch( this->settings.State )
tmulrooney 23:952530fa968d 1382 {
tmulrooney 23:952530fa968d 1383 case RF_RX_RUNNING:
tmulrooney 23:952530fa968d 1384 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 1385 {
tmulrooney 23:952530fa968d 1386 case MODEM_FSK:
tmulrooney 23:952530fa968d 1387 // FifoLevel interrupt
tmulrooney 23:952530fa968d 1388 // Read received packet size
tmulrooney 23:952530fa968d 1389 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
tmulrooney 23:952530fa968d 1390 {
tmulrooney 23:952530fa968d 1391 if( this->settings.Fsk.FixLen == false )
tmulrooney 23:952530fa968d 1392 {
tmulrooney 23:952530fa968d 1393 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
tmulrooney 23:952530fa968d 1394 }
tmulrooney 23:952530fa968d 1395 else
tmulrooney 23:952530fa968d 1396 {
tmulrooney 23:952530fa968d 1397 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
tmulrooney 23:952530fa968d 1398 }
tmulrooney 23:952530fa968d 1399 }
tmulrooney 23:952530fa968d 1400
tmulrooney 23:952530fa968d 1401 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
tmulrooney 23:952530fa968d 1402 {
tmulrooney 23:952530fa968d 1403 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
tmulrooney 23:952530fa968d 1404 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
tmulrooney 23:952530fa968d 1405 }
tmulrooney 23:952530fa968d 1406 else
tmulrooney 23:952530fa968d 1407 {
tmulrooney 23:952530fa968d 1408 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:952530fa968d 1409 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:952530fa968d 1410 }
tmulrooney 23:952530fa968d 1411 break;
tmulrooney 23:952530fa968d 1412 case MODEM_LORA:
tmulrooney 23:952530fa968d 1413 // Sync time out
tmulrooney 23:952530fa968d 1414 rxTimeoutTimer.detach( );
tmulrooney 23:952530fa968d 1415 this->settings.State = RF_IDLE;
tmulrooney 23:952530fa968d 1416 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
tmulrooney 23:952530fa968d 1417 {
tmulrooney 23:952530fa968d 1418 this->RadioEvents->RxTimeout( );
tmulrooney 23:952530fa968d 1419 }
tmulrooney 23:952530fa968d 1420 break;
tmulrooney 23:952530fa968d 1421 default:
tmulrooney 23:952530fa968d 1422 break;
tmulrooney 23:952530fa968d 1423 }
tmulrooney 23:952530fa968d 1424 break;
tmulrooney 23:952530fa968d 1425 case RF_TX_RUNNING:
tmulrooney 23:952530fa968d 1426 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 1427 {
tmulrooney 23:952530fa968d 1428 case MODEM_FSK:
tmulrooney 23:952530fa968d 1429 // FifoLevel interrupt
tmulrooney 23:952530fa968d 1430 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
tmulrooney 23:952530fa968d 1431 {
tmulrooney 23:952530fa968d 1432 WriteFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
tmulrooney 23:952530fa968d 1433 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
tmulrooney 23:952530fa968d 1434 }
tmulrooney 23:952530fa968d 1435 else
tmulrooney 23:952530fa968d 1436 {
tmulrooney 23:952530fa968d 1437 // Write the last chunk of data
tmulrooney 23:952530fa968d 1438 WriteFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:952530fa968d 1439 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
tmulrooney 23:952530fa968d 1440 }
tmulrooney 23:952530fa968d 1441 break;
tmulrooney 23:952530fa968d 1442 case MODEM_LORA:
tmulrooney 23:952530fa968d 1443 break;
tmulrooney 23:952530fa968d 1444 default:
tmulrooney 23:952530fa968d 1445 break;
tmulrooney 23:952530fa968d 1446 }
tmulrooney 23:952530fa968d 1447 break;
tmulrooney 23:952530fa968d 1448 default:
tmulrooney 23:952530fa968d 1449 break;
tmulrooney 23:952530fa968d 1450 }
tmulrooney 23:952530fa968d 1451 }
tmulrooney 23:952530fa968d 1452
tmulrooney 23:952530fa968d 1453 void SX1272::OnDio2Irq( void )
tmulrooney 23:952530fa968d 1454 {
tmulrooney 23:952530fa968d 1455 debug("OnDio2Irq\r\n");
tmulrooney 23:952530fa968d 1456 switch( this->settings.State )
tmulrooney 23:952530fa968d 1457 {
tmulrooney 23:952530fa968d 1458 case RF_RX_RUNNING:
tmulrooney 23:952530fa968d 1459 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 1460 {
tmulrooney 23:952530fa968d 1461 case MODEM_FSK:
tmulrooney 23:952530fa968d 1462 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
tmulrooney 23:952530fa968d 1463 {
tmulrooney 23:952530fa968d 1464 rxTimeoutSyncWord.detach( );
tmulrooney 23:952530fa968d 1465
tmulrooney 23:952530fa968d 1466 this->settings.FskPacketHandler.SyncWordDetected = true;
tmulrooney 23:952530fa968d 1467
tmulrooney 23:952530fa968d 1468 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
tmulrooney 23:952530fa968d 1469
tmulrooney 23:952530fa968d 1470 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
tmulrooney 23:952530fa968d 1471 ( uint16_t )Read( REG_AFCLSB ) ) *
tmulrooney 23:952530fa968d 1472 ( double )FREQ_STEP;
tmulrooney 23:952530fa968d 1473 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
tmulrooney 23:952530fa968d 1474 }
tmulrooney 23:952530fa968d 1475 break;
tmulrooney 23:952530fa968d 1476 case MODEM_LORA:
tmulrooney 23:952530fa968d 1477 if( this->settings.LoRa.FreqHopOn == true )
tmulrooney 23:952530fa968d 1478 {
tmulrooney 23:952530fa968d 1479 // Clear Irq
tmulrooney 23:952530fa968d 1480 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
tmulrooney 23:952530fa968d 1481
tmulrooney 23:952530fa968d 1482 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
tmulrooney 23:952530fa968d 1483 {
tmulrooney 23:952530fa968d 1484 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
tmulrooney 23:952530fa968d 1485 }
tmulrooney 23:952530fa968d 1486 }
tmulrooney 23:952530fa968d 1487 break;
tmulrooney 23:952530fa968d 1488 default:
tmulrooney 23:952530fa968d 1489 break;
tmulrooney 23:952530fa968d 1490 }
tmulrooney 23:952530fa968d 1491 break;
tmulrooney 23:952530fa968d 1492 case RF_TX_RUNNING:
tmulrooney 23:952530fa968d 1493 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 1494 {
tmulrooney 23:952530fa968d 1495 case MODEM_FSK:
tmulrooney 23:952530fa968d 1496 break;
tmulrooney 23:952530fa968d 1497 case MODEM_LORA:
tmulrooney 23:952530fa968d 1498 if( this->settings.LoRa.FreqHopOn == true )
tmulrooney 23:952530fa968d 1499 {
tmulrooney 23:952530fa968d 1500 // Clear Irq
tmulrooney 23:952530fa968d 1501 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
tmulrooney 23:952530fa968d 1502
tmulrooney 23:952530fa968d 1503 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
tmulrooney 23:952530fa968d 1504 {
tmulrooney 23:952530fa968d 1505 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
tmulrooney 23:952530fa968d 1506 }
tmulrooney 23:952530fa968d 1507 }
tmulrooney 23:952530fa968d 1508 break;
tmulrooney 23:952530fa968d 1509 default:
tmulrooney 23:952530fa968d 1510 break;
tmulrooney 23:952530fa968d 1511 }
tmulrooney 23:952530fa968d 1512 break;
tmulrooney 23:952530fa968d 1513 default:
tmulrooney 23:952530fa968d 1514 break;
tmulrooney 23:952530fa968d 1515 }
tmulrooney 23:952530fa968d 1516 }
tmulrooney 23:952530fa968d 1517
tmulrooney 23:952530fa968d 1518 void SX1272::OnDio3Irq( void )
tmulrooney 23:952530fa968d 1519 {
tmulrooney 23:952530fa968d 1520 debug("OnDio3Irq\r\n");
tmulrooney 23:952530fa968d 1521 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 1522 {
tmulrooney 23:952530fa968d 1523 case MODEM_FSK:
tmulrooney 23:952530fa968d 1524 break;
tmulrooney 23:952530fa968d 1525 case MODEM_LORA:
tmulrooney 23:952530fa968d 1526 if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
tmulrooney 23:952530fa968d 1527 {
tmulrooney 23:952530fa968d 1528 // Clear Irq
tmulrooney 23:952530fa968d 1529 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
tmulrooney 23:952530fa968d 1530 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
tmulrooney 23:952530fa968d 1531 {
tmulrooney 23:952530fa968d 1532 this->RadioEvents->CadDone( true );
tmulrooney 23:952530fa968d 1533 }
tmulrooney 23:952530fa968d 1534 }
tmulrooney 23:952530fa968d 1535 else
tmulrooney 23:952530fa968d 1536 {
tmulrooney 23:952530fa968d 1537 // Clear Irq
tmulrooney 23:952530fa968d 1538 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
tmulrooney 23:952530fa968d 1539 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
tmulrooney 23:952530fa968d 1540 {
tmulrooney 23:952530fa968d 1541 this->RadioEvents->CadDone( false );
tmulrooney 23:952530fa968d 1542 }
tmulrooney 23:952530fa968d 1543 }
tmulrooney 23:952530fa968d 1544 break;
tmulrooney 23:952530fa968d 1545 default:
tmulrooney 23:952530fa968d 1546 break;
tmulrooney 23:952530fa968d 1547 }
tmulrooney 23:952530fa968d 1548 }
tmulrooney 23:952530fa968d 1549
tmulrooney 23:952530fa968d 1550 void SX1272::OnDio4Irq( void )
tmulrooney 23:952530fa968d 1551 {
tmulrooney 23:952530fa968d 1552 debug("OnDio4Irq\r\n");
tmulrooney 23:952530fa968d 1553 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 1554 {
tmulrooney 23:952530fa968d 1555 case MODEM_FSK:
tmulrooney 23:952530fa968d 1556 {
tmulrooney 23:952530fa968d 1557 if( this->settings.FskPacketHandler.PreambleDetected == false )
tmulrooney 23:952530fa968d 1558 {
tmulrooney 23:952530fa968d 1559 this->settings.FskPacketHandler.PreambleDetected = true;
tmulrooney 23:952530fa968d 1560 }
tmulrooney 23:952530fa968d 1561 }
tmulrooney 23:952530fa968d 1562 break;
tmulrooney 23:952530fa968d 1563 case MODEM_LORA:
tmulrooney 23:952530fa968d 1564 break;
tmulrooney 23:952530fa968d 1565 default:
tmulrooney 23:952530fa968d 1566 break;
tmulrooney 23:952530fa968d 1567 }
tmulrooney 23:952530fa968d 1568 }
tmulrooney 23:952530fa968d 1569
tmulrooney 23:952530fa968d 1570 void SX1272::OnDio5Irq( void )
tmulrooney 23:952530fa968d 1571 {
tmulrooney 23:952530fa968d 1572 debug("OnDio5Irq\r\n");
tmulrooney 23:952530fa968d 1573 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 1574 {
tmulrooney 23:952530fa968d 1575 case MODEM_FSK:
tmulrooney 23:952530fa968d 1576 break;
tmulrooney 23:952530fa968d 1577 case MODEM_LORA:
tmulrooney 23:952530fa968d 1578 break;
tmulrooney 23:952530fa968d 1579 default:
tmulrooney 23:952530fa968d 1580 break;
tmulrooney 23:952530fa968d 1581 }
tmulrooney 23:952530fa968d 1582 }