Timothy Mulrooney / SX1272Libx

test

Dependents:   LoRaWAN-lmic-app_tjm

Fork of SX1276Lib by Semtech

sx1272/sx1272.cpp@25:856779ac8921, 2016-02-25 (annotated)

Committer:
tmulrooney
Date:
Thu Feb 25 21:28:39 2016 +0000
Revision:
25:856779ac8921
Parent:
24:54935d8f4b9e 
first successful join

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tmulrooney 23:952530fa968d 1 /*
tmulrooney 23:952530fa968d 2 / _____) _ | |
tmulrooney 23:952530fa968d 3 ( (____ _____ ____ _| |_ _____ ____| |__
tmulrooney 23:952530fa968d 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
tmulrooney 23:952530fa968d 5 _____) ) ____| | | || |_| ____( (___| | | |
tmulrooney 23:952530fa968d 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
tmulrooney 23:952530fa968d 7 (C) 2014 Semtech
tmulrooney 23:952530fa968d 8
tmulrooney 23:952530fa968d 9 Description: Actual implementation of a SX1272 radio, inherits Radio
tmulrooney 23:952530fa968d 10
tmulrooney 23:952530fa968d 11 License: Revised BSD License, see LICENSE.TXT file include in the project
tmulrooney 23:952530fa968d 12
tmulrooney 23:952530fa968d 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
tmulrooney 23:952530fa968d 14 */
tmulrooney 23:952530fa968d 15 #include "sx1272.h"
tmulrooney 23:952530fa968d 16 #include "debug.h"
tmulrooney 23:952530fa968d 17
tmulrooney 23:952530fa968d 18 const FskBandwidth_t SX1272::FskBandwidths[] =
tmulrooney 23:952530fa968d 19 {
tmulrooney 23:952530fa968d 20 { 2600 , 0x17 },
tmulrooney 23:952530fa968d 21 { 3100 , 0x0F },
tmulrooney 23:952530fa968d 22 { 3900 , 0x07 },
tmulrooney 23:952530fa968d 23 { 5200 , 0x16 },
tmulrooney 23:952530fa968d 24 { 6300 , 0x0E },
tmulrooney 23:952530fa968d 25 { 7800 , 0x06 },
tmulrooney 23:952530fa968d 26 { 10400 , 0x15 },
tmulrooney 23:952530fa968d 27 { 12500 , 0x0D },
tmulrooney 23:952530fa968d 28 { 15600 , 0x05 },
tmulrooney 23:952530fa968d 29 { 20800 , 0x14 },
tmulrooney 23:952530fa968d 30 { 25000 , 0x0C },
tmulrooney 23:952530fa968d 31 { 31300 , 0x04 },
tmulrooney 23:952530fa968d 32 { 41700 , 0x13 },
tmulrooney 23:952530fa968d 33 { 50000 , 0x0B },
tmulrooney 23:952530fa968d 34 { 62500 , 0x03 },
tmulrooney 23:952530fa968d 35 { 83333 , 0x12 },
tmulrooney 23:952530fa968d 36 { 100000, 0x0A },
tmulrooney 23:952530fa968d 37 { 125000, 0x02 },
tmulrooney 23:952530fa968d 38 { 166700, 0x11 },
tmulrooney 23:952530fa968d 39 { 200000, 0x09 },
tmulrooney 23:952530fa968d 40 { 250000, 0x01 },
tmulrooney 23:952530fa968d 41 { 300000, 0x00 }, // Invalid Badwidth
tmulrooney 23:952530fa968d 42 };
tmulrooney 23:952530fa968d 43
tmulrooney 23:952530fa968d 44 SX1272::SX1272( RadioEvents_t *events,
tmulrooney 23:952530fa968d 45 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
tmulrooney 23:952530fa968d 46 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
tmulrooney 23:952530fa968d 47 : Radio( events ),
tmulrooney 23:952530fa968d 48 // spi( mosi, miso, sclk ),
tmulrooney 23:952530fa968d 49 // nss( nss ),
tmulrooney 23:952530fa968d 50 spi( PTD6, PTD7, PTD5 ),
tmulrooney 23:952530fa968d 51 nss( PTD4 ),
tmulrooney 23:952530fa968d 52 reset( reset ),
tmulrooney 25:856779ac8921 53 dio0( PTC2 ), dio1( PTB1 ), dio2( PTC3 ), dio3( PTB0 ), dio4( PTC4 ), dio5( PTC1 ),
tmulrooney 23:952530fa968d 54 isRadioActive( false )
tmulrooney 23:952530fa968d 55 {
tmulrooney 23:952530fa968d 56 debug("SX1272 constructor\r\n");
tmulrooney 23:952530fa968d 57 wait_ms( 10 );
tmulrooney 23:952530fa968d 58 this->rxTx = 0;
tmulrooney 23:952530fa968d 59 this->rxBuffer = new uint8_t[RX_BUFFER_SIZE];
tmulrooney 23:952530fa968d 60 previousOpMode = RF_OPMODE_STANDBY;
tmulrooney 23:952530fa968d 61
tmulrooney 23:952530fa968d 62 this->RadioEvents = events;
tmulrooney 23:952530fa968d 63
tmulrooney 23:952530fa968d 64 this->dioIrq = new DioIrqHandler[6];
tmulrooney 23:952530fa968d 65
tmulrooney 23:952530fa968d 66 this->dioIrq[0] = &SX1272::OnDio0Irq;
tmulrooney 23:952530fa968d 67 this->dioIrq[1] = &SX1272::OnDio1Irq;
tmulrooney 23:952530fa968d 68 this->dioIrq[2] = &SX1272::OnDio2Irq;
tmulrooney 23:952530fa968d 69 this->dioIrq[3] = &SX1272::OnDio3Irq;
tmulrooney 23:952530fa968d 70 this->dioIrq[4] = &SX1272::OnDio4Irq;
tmulrooney 23:952530fa968d 71 this->dioIrq[5] = NULL;
tmulrooney 23:952530fa968d 72
tmulrooney 23:952530fa968d 73 this->settings.State = RF_IDLE;
tmulrooney 23:952530fa968d 74 }
tmulrooney 23:952530fa968d 75
tmulrooney 23:952530fa968d 76 SX1272::~SX1272( )
tmulrooney 23:952530fa968d 77 {
tmulrooney 23:952530fa968d 78 debug("SX1272x destructor\r\n");
tmulrooney 23:952530fa968d 79 delete this->rxBuffer;
tmulrooney 23:952530fa968d 80 delete this->dioIrq;
tmulrooney 23:952530fa968d 81 }
tmulrooney 23:952530fa968d 82
tmulrooney 23:952530fa968d 83 void SX1272::Init( RadioEvents_t *events )
tmulrooney 23:952530fa968d 84 {
tmulrooney 23:952530fa968d 85 debug("SX1272 Init\r\n");
tmulrooney 23:952530fa968d 86 this->RadioEvents = events;
tmulrooney 23:952530fa968d 87 }
tmulrooney 23:952530fa968d 88
tmulrooney 23:952530fa968d 89 RadioState SX1272::GetStatus( void )
tmulrooney 23:952530fa968d 90 {
tmulrooney 23:952530fa968d 91 debug("GetStatus\r\n");
tmulrooney 23:952530fa968d 92 return this->settings.State;
tmulrooney 23:952530fa968d 93 }
tmulrooney 23:952530fa968d 94
tmulrooney 23:952530fa968d 95 void SX1272::SetChannel( uint32_t freq )
tmulrooney 23:952530fa968d 96 {
tmulrooney 25:856779ac8921 97 // debug_val("SetChannel enter ",freq);
tmulrooney 23:952530fa968d 98 this->settings.Channel = freq;
tmulrooney 23:952530fa968d 99 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
tmulrooney 23:952530fa968d 100 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
tmulrooney 23:952530fa968d 101 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
tmulrooney 23:952530fa968d 102 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
tmulrooney 23:952530fa968d 103 }
tmulrooney 23:952530fa968d 104
tmulrooney 23:952530fa968d 105 bool SX1272::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh )
tmulrooney 23:952530fa968d 106 {
tmulrooney 23:952530fa968d 107 debug("IsChannelFree\r\n");
tmulrooney 23:952530fa968d 108 int16_t rssi = 0;
tmulrooney 23:952530fa968d 109
tmulrooney 23:952530fa968d 110 SetModem( modem );
tmulrooney 23:952530fa968d 111
tmulrooney 23:952530fa968d 112 SetChannel( freq );
tmulrooney 23:952530fa968d 113
tmulrooney 23:952530fa968d 114 SetOpMode( RF_OPMODE_RECEIVER );
tmulrooney 23:952530fa968d 115
tmulrooney 23:952530fa968d 116 wait_ms( 1 );
tmulrooney 23:952530fa968d 117
tmulrooney 23:952530fa968d 118 rssi = GetRssi( modem );
tmulrooney 23:952530fa968d 119
tmulrooney 23:952530fa968d 120 Sleep( );
tmulrooney 23:952530fa968d 121
tmulrooney 23:952530fa968d 122 if( rssi > rssiThresh )
tmulrooney 23:952530fa968d 123 {
tmulrooney 23:952530fa968d 124 return false;
tmulrooney 23:952530fa968d 125 }
tmulrooney 23:952530fa968d 126 return true;
tmulrooney 23:952530fa968d 127 }
tmulrooney 23:952530fa968d 128
tmulrooney 23:952530fa968d 129 uint32_t SX1272::Random( void )
tmulrooney 23:952530fa968d 130 {
tmulrooney 23:952530fa968d 131 debug("Random\r\n");
tmulrooney 23:952530fa968d 132 uint8_t i;
tmulrooney 23:952530fa968d 133 uint32_t rnd = 0;
tmulrooney 23:952530fa968d 134
tmulrooney 23:952530fa968d 135 /*
tmulrooney 23:952530fa968d 136 * Radio setup for random number generation
tmulrooney 23:952530fa968d 137 */
tmulrooney 23:952530fa968d 138 // Set LoRa modem ON
tmulrooney 23:952530fa968d 139 SetModem( MODEM_LORA );
tmulrooney 23:952530fa968d 140
tmulrooney 23:952530fa968d 141 // Disable LoRa modem interrupts
tmulrooney 23:952530fa968d 142 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
tmulrooney 23:952530fa968d 143 RFLR_IRQFLAGS_RXDONE |
tmulrooney 23:952530fa968d 144 RFLR_IRQFLAGS_PAYLOADCRCERROR |
tmulrooney 23:952530fa968d 145 RFLR_IRQFLAGS_VALIDHEADER |
tmulrooney 23:952530fa968d 146 RFLR_IRQFLAGS_TXDONE |
tmulrooney 23:952530fa968d 147 RFLR_IRQFLAGS_CADDONE |
tmulrooney 23:952530fa968d 148 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
tmulrooney 23:952530fa968d 149 RFLR_IRQFLAGS_CADDETECTED );
tmulrooney 23:952530fa968d 150
tmulrooney 23:952530fa968d 151 // Set radio in continuous reception
tmulrooney 23:952530fa968d 152 SetOpMode( RF_OPMODE_RECEIVER );
tmulrooney 23:952530fa968d 153
tmulrooney 23:952530fa968d 154 for( i = 0; i < 32; i++ )
tmulrooney 23:952530fa968d 155 {
tmulrooney 23:952530fa968d 156 wait_ms( 1 );
tmulrooney 23:952530fa968d 157 // Unfiltered RSSI value reading. Only takes the LSB value
tmulrooney 23:952530fa968d 158 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
tmulrooney 23:952530fa968d 159 }
tmulrooney 23:952530fa968d 160
tmulrooney 23:952530fa968d 161 Sleep( );
tmulrooney 23:952530fa968d 162
tmulrooney 23:952530fa968d 163 return rnd;
tmulrooney 23:952530fa968d 164 }
tmulrooney 23:952530fa968d 165
tmulrooney 23:952530fa968d 166 /*!
tmulrooney 23:952530fa968d 167 * Performs the Rx chain calibration for LF and HF bands
tmulrooney 23:952530fa968d 168 * \remark Must be called just after the reset so all registers are at their
tmulrooney 23:952530fa968d 169 * default values
tmulrooney 23:952530fa968d 170 */
tmulrooney 23:952530fa968d 171 void SX1272::RxChainCalibration( void )
tmulrooney 23:952530fa968d 172 {
tmulrooney 23:952530fa968d 173 debug("RxChainCalibration enter\r\n");
tmulrooney 23:952530fa968d 174 uint8_t regPaConfigInitVal;
tmulrooney 23:952530fa968d 175 uint32_t initialFreq;
tmulrooney 23:952530fa968d 176
tmulrooney 23:952530fa968d 177 // Save context
tmulrooney 23:952530fa968d 178 regPaConfigInitVal = this->Read( REG_PACONFIG );
tmulrooney 23:952530fa968d 179 initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) |
tmulrooney 23:952530fa968d 180 ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) |
tmulrooney 23:952530fa968d 181 ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
tmulrooney 23:952530fa968d 182 debug("Initial Freq: %d\r\n", initialFreq);
tmulrooney 23:952530fa968d 183
tmulrooney 23:952530fa968d 184 // Cut the PA just in case, RFO output, power = -1 dBm
tmulrooney 23:952530fa968d 185 this->Write( REG_PACONFIG, 0x00 );
tmulrooney 23:952530fa968d 186
tmulrooney 23:952530fa968d 187 // Launch Rx chain calibration for LF band
tmulrooney 23:952530fa968d 188 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
tmulrooney 23:952530fa968d 189 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
tmulrooney 23:952530fa968d 190 {
tmulrooney 23:952530fa968d 191 }
tmulrooney 23:952530fa968d 192
tmulrooney 23:952530fa968d 193 // Sets a Frequency in HF band
tmulrooney 23:952530fa968d 194 SetChannel( 868000000 );
tmulrooney 23:952530fa968d 195
tmulrooney 23:952530fa968d 196 // Launch Rx chain calibration for HF band
tmulrooney 23:952530fa968d 197 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
tmulrooney 23:952530fa968d 198 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
tmulrooney 23:952530fa968d 199 {
tmulrooney 23:952530fa968d 200 }
tmulrooney 23:952530fa968d 201
tmulrooney 23:952530fa968d 202 // Restore context
tmulrooney 23:952530fa968d 203 this->Write( REG_PACONFIG, regPaConfigInitVal );
tmulrooney 23:952530fa968d 204 SetChannel( initialFreq );
tmulrooney 23:952530fa968d 205 }
tmulrooney 23:952530fa968d 206
tmulrooney 23:952530fa968d 207 /*!
tmulrooney 23:952530fa968d 208 * Returns the known FSK bandwidth registers value
tmulrooney 23:952530fa968d 209 *
tmulrooney 23:952530fa968d 210 * \param [IN] bandwidth Bandwidth value in Hz
tmulrooney 23:952530fa968d 211 * \retval regValue Bandwidth register value.
tmulrooney 23:952530fa968d 212 */
tmulrooney 23:952530fa968d 213 uint8_t SX1272::GetFskBandwidthRegValue( uint32_t bandwidth )
tmulrooney 23:952530fa968d 214 {
tmulrooney 23:952530fa968d 215 debug("GetFskBandwidthRegValue\r\n");
tmulrooney 23:952530fa968d 216 uint8_t i;
tmulrooney 23:952530fa968d 217
tmulrooney 23:952530fa968d 218 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
tmulrooney 23:952530fa968d 219 {
tmulrooney 23:952530fa968d 220 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
tmulrooney 23:952530fa968d 221 {
tmulrooney 23:952530fa968d 222 return FskBandwidths[i].RegValue;
tmulrooney 23:952530fa968d 223 }
tmulrooney 23:952530fa968d 224 }
tmulrooney 23:952530fa968d 225 // ERROR: Value not found
tmulrooney 23:952530fa968d 226 while( 1 );
tmulrooney 23:952530fa968d 227 }
tmulrooney 23:952530fa968d 228
tmulrooney 23:952530fa968d 229 void SX1272::SetRxConfig( RadioModems_t modem, uint32_t bandwidth,
tmulrooney 23:952530fa968d 230 uint32_t datarate, uint8_t coderate,
tmulrooney 23:952530fa968d 231 uint32_t bandwidthAfc, uint16_t preambleLen,
tmulrooney 23:952530fa968d 232 uint16_t symbTimeout, bool fixLen,
tmulrooney 23:952530fa968d 233 uint8_t payloadLen,
tmulrooney 23:952530fa968d 234 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
tmulrooney 23:952530fa968d 235 bool iqInverted, bool rxContinuous )
tmulrooney 23:952530fa968d 236 {
tmulrooney 23:952530fa968d 237 debug("SetRxConfig enter\r\n");
tmulrooney 23:952530fa968d 238 SetModem( modem );
tmulrooney 23:952530fa968d 239
tmulrooney 23:952530fa968d 240 switch( modem )
tmulrooney 23:952530fa968d 241 {
tmulrooney 23:952530fa968d 242 case MODEM_FSK:
tmulrooney 23:952530fa968d 243 {
tmulrooney 23:952530fa968d 244 this->settings.Fsk.Bandwidth = bandwidth;
tmulrooney 23:952530fa968d 245 this->settings.Fsk.Datarate = datarate;
tmulrooney 23:952530fa968d 246 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
tmulrooney 23:952530fa968d 247 this->settings.Fsk.FixLen = fixLen;
tmulrooney 23:952530fa968d 248 this->settings.Fsk.PayloadLen = payloadLen;
tmulrooney 23:952530fa968d 249 this->settings.Fsk.CrcOn = crcOn;
tmulrooney 23:952530fa968d 250 this->settings.Fsk.IqInverted = iqInverted;
tmulrooney 23:952530fa968d 251 this->settings.Fsk.RxContinuous = rxContinuous;
tmulrooney 23:952530fa968d 252 this->settings.Fsk.PreambleLen = preambleLen;
tmulrooney 23:952530fa968d 253
tmulrooney 23:952530fa968d 254 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
tmulrooney 23:952530fa968d 255 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
tmulrooney 23:952530fa968d 256 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
tmulrooney 23:952530fa968d 257
tmulrooney 23:952530fa968d 258 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
tmulrooney 23:952530fa968d 259 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
tmulrooney 23:952530fa968d 260
tmulrooney 23:952530fa968d 261 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
tmulrooney 23:952530fa968d 262 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
tmulrooney 23:952530fa968d 263
tmulrooney 23:952530fa968d 264 if( fixLen == 1 )
tmulrooney 23:952530fa968d 265 {
tmulrooney 23:952530fa968d 266 Write( REG_PAYLOADLENGTH, payloadLen );
tmulrooney 23:952530fa968d 267 }
tmulrooney 23:952530fa968d 268
tmulrooney 23:952530fa968d 269 Write( REG_PACKETCONFIG1,
tmulrooney 23:952530fa968d 270 ( Read( REG_PACKETCONFIG1 ) &
tmulrooney 23:952530fa968d 271 RF_PACKETCONFIG1_CRC_MASK &
tmulrooney 23:952530fa968d 272 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
tmulrooney 23:952530fa968d 273 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
tmulrooney 23:952530fa968d 274 ( crcOn << 4 ) );
tmulrooney 23:952530fa968d 275 }
tmulrooney 23:952530fa968d 276 break;
tmulrooney 23:952530fa968d 277 case MODEM_LORA:
tmulrooney 23:952530fa968d 278 {
tmulrooney 23:952530fa968d 279 if( bandwidth > 2 )
tmulrooney 23:952530fa968d 280 {
tmulrooney 23:952530fa968d 281 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
tmulrooney 23:952530fa968d 282 while( 1 );
tmulrooney 23:952530fa968d 283 }
tmulrooney 23:952530fa968d 284 bandwidth += 7;
tmulrooney 23:952530fa968d 285 this->settings.LoRa.Bandwidth = bandwidth;
tmulrooney 23:952530fa968d 286 this->settings.LoRa.Datarate = datarate;
tmulrooney 23:952530fa968d 287 this->settings.LoRa.Coderate = coderate;
tmulrooney 23:952530fa968d 288 this->settings.LoRa.PreambleLen = preambleLen;
tmulrooney 23:952530fa968d 289 this->settings.LoRa.FixLen = fixLen;
tmulrooney 23:952530fa968d 290 this->settings.LoRa.PayloadLen = payloadLen;
tmulrooney 23:952530fa968d 291 this->settings.LoRa.CrcOn = crcOn;
tmulrooney 23:952530fa968d 292 this->settings.LoRa.FreqHopOn = freqHopOn;
tmulrooney 23:952530fa968d 293 this->settings.LoRa.HopPeriod = hopPeriod;
tmulrooney 23:952530fa968d 294 this->settings.LoRa.IqInverted = iqInverted;
tmulrooney 23:952530fa968d 295 this->settings.LoRa.RxContinuous = rxContinuous;
tmulrooney 23:952530fa968d 296
tmulrooney 23:952530fa968d 297 if( datarate > 12 )
tmulrooney 23:952530fa968d 298 {
tmulrooney 23:952530fa968d 299 datarate = 12;
tmulrooney 23:952530fa968d 300 }
tmulrooney 23:952530fa968d 301 else if( datarate < 6 )
tmulrooney 23:952530fa968d 302 {
tmulrooney 23:952530fa968d 303 datarate = 6;
tmulrooney 23:952530fa968d 304 }
tmulrooney 23:952530fa968d 305
tmulrooney 23:952530fa968d 306 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
tmulrooney 23:952530fa968d 307 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
tmulrooney 23:952530fa968d 308 {
tmulrooney 23:952530fa968d 309 this->settings.LoRa.LowDatarateOptimize = 0x01;
tmulrooney 23:952530fa968d 310 }
tmulrooney 23:952530fa968d 311 else
tmulrooney 23:952530fa968d 312 {
tmulrooney 23:952530fa968d 313 this->settings.LoRa.LowDatarateOptimize = 0x00;
tmulrooney 23:952530fa968d 314 }
tmulrooney 23:952530fa968d 315
tmulrooney 23:952530fa968d 316 Write( REG_LR_MODEMCONFIG1,
tmulrooney 23:952530fa968d 317 ( Read( REG_LR_MODEMCONFIG1 ) &
tmulrooney 23:952530fa968d 318 RFLR_MODEMCONFIG1_BW_MASK &
tmulrooney 23:952530fa968d 319 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
tmulrooney 23:952530fa968d 320 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
tmulrooney 23:952530fa968d 321 ( bandwidth << 4 ) | ( coderate << 1 ) |
tmulrooney 23:952530fa968d 322 fixLen );
tmulrooney 23:952530fa968d 323
tmulrooney 23:952530fa968d 324 Write( REG_LR_MODEMCONFIG2,
tmulrooney 23:952530fa968d 325 ( Read( REG_LR_MODEMCONFIG2 ) &
tmulrooney 23:952530fa968d 326 RFLR_MODEMCONFIG2_SF_MASK &
tmulrooney 23:952530fa968d 327 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
tmulrooney 23:952530fa968d 328 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
tmulrooney 23:952530fa968d 329 ( datarate << 4 ) | ( crcOn << 2 ) |
tmulrooney 23:952530fa968d 330 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
tmulrooney 23:952530fa968d 331
tmulrooney 23:952530fa968d 332 Write( REG_LR_MODEMCONFIG3,
tmulrooney 23:952530fa968d 333 ( Read( REG_LR_MODEMCONFIG3 ) &
tmulrooney 23:952530fa968d 334 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
tmulrooney 23:952530fa968d 335 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
tmulrooney 23:952530fa968d 336
tmulrooney 23:952530fa968d 337 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
tmulrooney 23:952530fa968d 338
tmulrooney 23:952530fa968d 339 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
tmulrooney 23:952530fa968d 340 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
tmulrooney 23:952530fa968d 341
tmulrooney 23:952530fa968d 342 if( fixLen == 1 )
tmulrooney 23:952530fa968d 343 {
tmulrooney 23:952530fa968d 344 Write( REG_LR_PAYLOADLENGTH, payloadLen );
tmulrooney 23:952530fa968d 345 }
tmulrooney 23:952530fa968d 346
tmulrooney 23:952530fa968d 347 if( this->settings.LoRa.FreqHopOn == true )
tmulrooney 23:952530fa968d 348 {
tmulrooney 23:952530fa968d 349 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
tmulrooney 23:952530fa968d 350 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
tmulrooney 23:952530fa968d 351 }
tmulrooney 23:952530fa968d 352
tmulrooney 23:952530fa968d 353 if( ( bandwidth == 9 ) && ( RF_MID_BAND_THRESH ) )
tmulrooney 23:952530fa968d 354 {
tmulrooney 23:952530fa968d 355 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
tmulrooney 23:952530fa968d 356 Write( REG_LR_TEST36, 0x02 );
tmulrooney 23:952530fa968d 357 Write( REG_LR_TEST3A, 0x64 );
tmulrooney 23:952530fa968d 358 }
tmulrooney 23:952530fa968d 359 else if( bandwidth == 9 )
tmulrooney 23:952530fa968d 360 {
tmulrooney 23:952530fa968d 361 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
tmulrooney 23:952530fa968d 362 Write( REG_LR_TEST36, 0x02 );
tmulrooney 23:952530fa968d 363 Write( REG_LR_TEST3A, 0x7F );
tmulrooney 23:952530fa968d 364 }
tmulrooney 23:952530fa968d 365 else
tmulrooney 23:952530fa968d 366 {
tmulrooney 23:952530fa968d 367 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
tmulrooney 23:952530fa968d 368 Write( REG_LR_TEST36, 0x03 );
tmulrooney 23:952530fa968d 369 }
tmulrooney 23:952530fa968d 370
tmulrooney 23:952530fa968d 371 if( datarate == 6 )
tmulrooney 23:952530fa968d 372 {
tmulrooney 23:952530fa968d 373 Write( REG_LR_DETECTOPTIMIZE,
tmulrooney 23:952530fa968d 374 ( Read( REG_LR_DETECTOPTIMIZE ) &
tmulrooney 23:952530fa968d 375 RFLR_DETECTIONOPTIMIZE_MASK ) |
tmulrooney 23:952530fa968d 376 RFLR_DETECTIONOPTIMIZE_SF6 );
tmulrooney 23:952530fa968d 377 Write( REG_LR_DETECTIONTHRESHOLD,
tmulrooney 23:952530fa968d 378 RFLR_DETECTIONTHRESH_SF6 );
tmulrooney 23:952530fa968d 379 }
tmulrooney 23:952530fa968d 380 else
tmulrooney 23:952530fa968d 381 {
tmulrooney 23:952530fa968d 382 Write( REG_LR_DETECTOPTIMIZE,
tmulrooney 23:952530fa968d 383 ( Read( REG_LR_DETECTOPTIMIZE ) &
tmulrooney 23:952530fa968d 384 RFLR_DETECTIONOPTIMIZE_MASK ) |
tmulrooney 23:952530fa968d 385 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
tmulrooney 23:952530fa968d 386 Write( REG_LR_DETECTIONTHRESHOLD,
tmulrooney 23:952530fa968d 387 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
tmulrooney 23:952530fa968d 388 }
tmulrooney 23:952530fa968d 389 }
tmulrooney 23:952530fa968d 390 break;
tmulrooney 23:952530fa968d 391 }
tmulrooney 23:952530fa968d 392 }
tmulrooney 23:952530fa968d 393
tmulrooney 23:952530fa968d 394 void SX1272::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
tmulrooney 23:952530fa968d 395 uint32_t bandwidth, uint32_t datarate,
tmulrooney 23:952530fa968d 396 uint8_t coderate, uint16_t preambleLen,
tmulrooney 23:952530fa968d 397 bool fixLen, bool crcOn, bool freqHopOn,
tmulrooney 23:952530fa968d 398 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
tmulrooney 23:952530fa968d 399 {
tmulrooney 23:952530fa968d 400 debug("SetTxConfig enter\r\n");
tmulrooney 23:952530fa968d 401 debug("modem: %d power: %d fdev: %d\r\n",modem,power,fdev);
tmulrooney 23:952530fa968d 402 debug("bandwidth: %d datarate:%d\r\n",bandwidth,datarate);
tmulrooney 23:952530fa968d 403 debug("timeout: %d\r\n",timeout);
tmulrooney 23:952530fa968d 404 uint8_t paConfig = 0;
tmulrooney 23:952530fa968d 405 uint8_t paDac = 0;
tmulrooney 23:952530fa968d 406
tmulrooney 23:952530fa968d 407 SetModem( modem );
tmulrooney 23:952530fa968d 408
tmulrooney 23:952530fa968d 409 paConfig = Read( REG_PACONFIG );
tmulrooney 23:952530fa968d 410 paDac = Read( REG_PADAC );
tmulrooney 23:952530fa968d 411
tmulrooney 23:952530fa968d 412 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
tmulrooney 23:952530fa968d 413 paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
tmulrooney 23:952530fa968d 414
tmulrooney 23:952530fa968d 415 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
tmulrooney 23:952530fa968d 416 {
tmulrooney 23:952530fa968d 417 if( power > 17 )
tmulrooney 23:952530fa968d 418 {
tmulrooney 23:952530fa968d 419 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
tmulrooney 23:952530fa968d 420 }
tmulrooney 23:952530fa968d 421 else
tmulrooney 23:952530fa968d 422 {
tmulrooney 23:952530fa968d 423 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
tmulrooney 23:952530fa968d 424 }
tmulrooney 23:952530fa968d 425 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
tmulrooney 23:952530fa968d 426 {
tmulrooney 23:952530fa968d 427 if( power < 5 )
tmulrooney 23:952530fa968d 428 {
tmulrooney 23:952530fa968d 429 power = 5;
tmulrooney 23:952530fa968d 430 }
tmulrooney 23:952530fa968d 431 if( power > 20 )
tmulrooney 23:952530fa968d 432 {
tmulrooney 23:952530fa968d 433 power = 20;
tmulrooney 23:952530fa968d 434 }
tmulrooney 23:952530fa968d 435 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
tmulrooney 23:952530fa968d 436 }
tmulrooney 23:952530fa968d 437 else
tmulrooney 23:952530fa968d 438 {
tmulrooney 23:952530fa968d 439 if( power < 2 )
tmulrooney 23:952530fa968d 440 {
tmulrooney 23:952530fa968d 441 power = 2;
tmulrooney 23:952530fa968d 442 }
tmulrooney 23:952530fa968d 443 if( power > 17 )
tmulrooney 23:952530fa968d 444 {
tmulrooney 23:952530fa968d 445 power = 17;
tmulrooney 23:952530fa968d 446 }
tmulrooney 23:952530fa968d 447 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
tmulrooney 23:952530fa968d 448 }
tmulrooney 23:952530fa968d 449 }
tmulrooney 23:952530fa968d 450 else
tmulrooney 23:952530fa968d 451 {
tmulrooney 23:952530fa968d 452 if( power < -1 )
tmulrooney 23:952530fa968d 453 {
tmulrooney 23:952530fa968d 454 power = -1;
tmulrooney 23:952530fa968d 455 }
tmulrooney 23:952530fa968d 456 if( power > 14 )
tmulrooney 23:952530fa968d 457 {
tmulrooney 23:952530fa968d 458 power = 14;
tmulrooney 23:952530fa968d 459 }
tmulrooney 23:952530fa968d 460 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
tmulrooney 23:952530fa968d 461 }
tmulrooney 23:952530fa968d 462 Write( REG_PACONFIG, paConfig );
tmulrooney 23:952530fa968d 463 Write( REG_PADAC, paDac );
tmulrooney 23:952530fa968d 464
tmulrooney 23:952530fa968d 465 switch( modem )
tmulrooney 23:952530fa968d 466 {
tmulrooney 23:952530fa968d 467 case MODEM_FSK:
tmulrooney 23:952530fa968d 468 {
tmulrooney 23:952530fa968d 469 this->settings.Fsk.Power = power;
tmulrooney 23:952530fa968d 470 this->settings.Fsk.Fdev = fdev;
tmulrooney 23:952530fa968d 471 this->settings.Fsk.Bandwidth = bandwidth;
tmulrooney 23:952530fa968d 472 this->settings.Fsk.Datarate = datarate;
tmulrooney 23:952530fa968d 473 this->settings.Fsk.PreambleLen = preambleLen;
tmulrooney 23:952530fa968d 474 this->settings.Fsk.FixLen = fixLen;
tmulrooney 23:952530fa968d 475 this->settings.Fsk.CrcOn = crcOn;
tmulrooney 23:952530fa968d 476 this->settings.Fsk.IqInverted = iqInverted;
tmulrooney 23:952530fa968d 477 this->settings.Fsk.TxTimeout = timeout;
tmulrooney 23:952530fa968d 478
tmulrooney 23:952530fa968d 479 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
tmulrooney 23:952530fa968d 480 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
tmulrooney 23:952530fa968d 481 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
tmulrooney 23:952530fa968d 482
tmulrooney 23:952530fa968d 483 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
tmulrooney 23:952530fa968d 484 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
tmulrooney 23:952530fa968d 485 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
tmulrooney 23:952530fa968d 486
tmulrooney 23:952530fa968d 487 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
tmulrooney 23:952530fa968d 488 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
tmulrooney 23:952530fa968d 489
tmulrooney 23:952530fa968d 490 Write( REG_PACKETCONFIG1,
tmulrooney 23:952530fa968d 491 ( Read( REG_PACKETCONFIG1 ) &
tmulrooney 23:952530fa968d 492 RF_PACKETCONFIG1_CRC_MASK &
tmulrooney 23:952530fa968d 493 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
tmulrooney 23:952530fa968d 494 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
tmulrooney 23:952530fa968d 495 ( crcOn << 4 ) );
tmulrooney 23:952530fa968d 496
tmulrooney 23:952530fa968d 497 }
tmulrooney 23:952530fa968d 498 break;
tmulrooney 23:952530fa968d 499 case MODEM_LORA:
tmulrooney 23:952530fa968d 500 {
tmulrooney 23:952530fa968d 501 this->settings.LoRa.Power = power;
tmulrooney 23:952530fa968d 502 if( bandwidth > 2 )
tmulrooney 23:952530fa968d 503 {
tmulrooney 23:952530fa968d 504 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
tmulrooney 23:952530fa968d 505 while( 1 );
tmulrooney 23:952530fa968d 506 }
tmulrooney 23:952530fa968d 507 bandwidth += 7;
tmulrooney 23:952530fa968d 508 this->settings.LoRa.Bandwidth = bandwidth;
tmulrooney 23:952530fa968d 509 this->settings.LoRa.Datarate = datarate;
tmulrooney 23:952530fa968d 510 this->settings.LoRa.Coderate = coderate;
tmulrooney 23:952530fa968d 511 this->settings.LoRa.PreambleLen = preambleLen;
tmulrooney 23:952530fa968d 512 this->settings.LoRa.FixLen = fixLen;
tmulrooney 23:952530fa968d 513 this->settings.LoRa.FreqHopOn = freqHopOn;
tmulrooney 23:952530fa968d 514 this->settings.LoRa.HopPeriod = hopPeriod;
tmulrooney 23:952530fa968d 515 this->settings.LoRa.CrcOn = crcOn;
tmulrooney 23:952530fa968d 516 this->settings.LoRa.IqInverted = iqInverted;
tmulrooney 23:952530fa968d 517 this->settings.LoRa.TxTimeout = timeout;
tmulrooney 23:952530fa968d 518
tmulrooney 23:952530fa968d 519 if( datarate > 12 )
tmulrooney 23:952530fa968d 520 {
tmulrooney 23:952530fa968d 521 datarate = 12;
tmulrooney 23:952530fa968d 522 }
tmulrooney 23:952530fa968d 523 else if( datarate < 6 )
tmulrooney 23:952530fa968d 524 {
tmulrooney 23:952530fa968d 525 datarate = 6;
tmulrooney 23:952530fa968d 526 }
tmulrooney 23:952530fa968d 527 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
tmulrooney 23:952530fa968d 528 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
tmulrooney 23:952530fa968d 529 {
tmulrooney 23:952530fa968d 530 this->settings.LoRa.LowDatarateOptimize = 0x01;
tmulrooney 23:952530fa968d 531 }
tmulrooney 23:952530fa968d 532 else
tmulrooney 23:952530fa968d 533 {
tmulrooney 23:952530fa968d 534 this->settings.LoRa.LowDatarateOptimize = 0x00;
tmulrooney 23:952530fa968d 535 }
tmulrooney 23:952530fa968d 536
tmulrooney 23:952530fa968d 537 if( this->settings.LoRa.FreqHopOn == true )
tmulrooney 23:952530fa968d 538 {
tmulrooney 23:952530fa968d 539 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
tmulrooney 23:952530fa968d 540 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
tmulrooney 23:952530fa968d 541 }
tmulrooney 23:952530fa968d 542
tmulrooney 23:952530fa968d 543 Write( REG_LR_MODEMCONFIG1,
tmulrooney 23:952530fa968d 544 ( Read( REG_LR_MODEMCONFIG1 ) &
tmulrooney 23:952530fa968d 545 RFLR_MODEMCONFIG1_BW_MASK &
tmulrooney 23:952530fa968d 546 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
tmulrooney 23:952530fa968d 547 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
tmulrooney 23:952530fa968d 548 ( bandwidth << 4 ) | ( coderate << 1 ) |
tmulrooney 23:952530fa968d 549 fixLen );
tmulrooney 23:952530fa968d 550
tmulrooney 23:952530fa968d 551 Write( REG_LR_MODEMCONFIG2,
tmulrooney 23:952530fa968d 552 ( Read( REG_LR_MODEMCONFIG2 ) &
tmulrooney 23:952530fa968d 553 RFLR_MODEMCONFIG2_SF_MASK &
tmulrooney 23:952530fa968d 554 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) |
tmulrooney 23:952530fa968d 555 ( datarate << 4 ) | ( crcOn << 2 ) );
tmulrooney 23:952530fa968d 556
tmulrooney 23:952530fa968d 557 Write( REG_LR_MODEMCONFIG3,
tmulrooney 23:952530fa968d 558 ( Read( REG_LR_MODEMCONFIG3 ) &
tmulrooney 23:952530fa968d 559 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
tmulrooney 23:952530fa968d 560 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
tmulrooney 23:952530fa968d 561
tmulrooney 23:952530fa968d 562 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
tmulrooney 23:952530fa968d 563 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
tmulrooney 23:952530fa968d 564
tmulrooney 23:952530fa968d 565 if( datarate == 6 )
tmulrooney 23:952530fa968d 566 {
tmulrooney 23:952530fa968d 567 Write( REG_LR_DETECTOPTIMIZE,
tmulrooney 23:952530fa968d 568 ( Read( REG_LR_DETECTOPTIMIZE ) &
tmulrooney 23:952530fa968d 569 RFLR_DETECTIONOPTIMIZE_MASK ) |
tmulrooney 23:952530fa968d 570 RFLR_DETECTIONOPTIMIZE_SF6 );
tmulrooney 23:952530fa968d 571 Write( REG_LR_DETECTIONTHRESHOLD,
tmulrooney 23:952530fa968d 572 RFLR_DETECTIONTHRESH_SF6 );
tmulrooney 23:952530fa968d 573 }
tmulrooney 23:952530fa968d 574 else
tmulrooney 23:952530fa968d 575 {
tmulrooney 23:952530fa968d 576 Write( REG_LR_DETECTOPTIMIZE,
tmulrooney 23:952530fa968d 577 ( Read( REG_LR_DETECTOPTIMIZE ) &
tmulrooney 23:952530fa968d 578 RFLR_DETECTIONOPTIMIZE_MASK ) |
tmulrooney 23:952530fa968d 579 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
tmulrooney 23:952530fa968d 580 Write( REG_LR_DETECTIONTHRESHOLD,
tmulrooney 23:952530fa968d 581 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
tmulrooney 23:952530fa968d 582 }
tmulrooney 23:952530fa968d 583 }
tmulrooney 23:952530fa968d 584 break;
tmulrooney 23:952530fa968d 585 }
tmulrooney 23:952530fa968d 586 }
tmulrooney 23:952530fa968d 587
tmulrooney 23:952530fa968d 588 double SX1272::TimeOnAir( RadioModems_t modem, uint8_t pktLen )
tmulrooney 23:952530fa968d 589 {
tmulrooney 23:952530fa968d 590 debug("TimeOnAir\r\n");
tmulrooney 23:952530fa968d 591 uint32_t airTime = 0;
tmulrooney 23:952530fa968d 592
tmulrooney 23:952530fa968d 593 switch( modem )
tmulrooney 23:952530fa968d 594 {
tmulrooney 23:952530fa968d 595 case MODEM_FSK:
tmulrooney 23:952530fa968d 596 {
tmulrooney 23:952530fa968d 597 airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen +
tmulrooney 23:952530fa968d 598 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
tmulrooney 23:952530fa968d 599 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
tmulrooney 23:952530fa968d 600 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
tmulrooney 23:952530fa968d 601 pktLen +
tmulrooney 23:952530fa968d 602 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
tmulrooney 23:952530fa968d 603 this->settings.Fsk.Datarate ) * 1e6 );
tmulrooney 23:952530fa968d 604 }
tmulrooney 23:952530fa968d 605 break;
tmulrooney 23:952530fa968d 606 case MODEM_LORA:
tmulrooney 23:952530fa968d 607 {
tmulrooney 23:952530fa968d 608 double bw = 0.0;
tmulrooney 23:952530fa968d 609 // REMARK: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
tmulrooney 23:952530fa968d 610 switch( this->settings.LoRa.Bandwidth )
tmulrooney 23:952530fa968d 611 {
tmulrooney 23:952530fa968d 612 //case 0: // 7.8 kHz
tmulrooney 23:952530fa968d 613 // bw = 78e2;
tmulrooney 23:952530fa968d 614 // break;
tmulrooney 23:952530fa968d 615 //case 1: // 10.4 kHz
tmulrooney 23:952530fa968d 616 // bw = 104e2;
tmulrooney 23:952530fa968d 617 // break;
tmulrooney 23:952530fa968d 618 //case 2: // 15.6 kHz
tmulrooney 23:952530fa968d 619 // bw = 156e2;
tmulrooney 23:952530fa968d 620 // break;
tmulrooney 23:952530fa968d 621 //case 3: // 20.8 kHz
tmulrooney 23:952530fa968d 622 // bw = 208e2;
tmulrooney 23:952530fa968d 623 // break;
tmulrooney 23:952530fa968d 624 //case 4: // 31.2 kHz
tmulrooney 23:952530fa968d 625 // bw = 312e2;
tmulrooney 23:952530fa968d 626 // break;
tmulrooney 23:952530fa968d 627 //case 5: // 41.4 kHz
tmulrooney 23:952530fa968d 628 // bw = 414e2;
tmulrooney 23:952530fa968d 629 // break;
tmulrooney 23:952530fa968d 630 //case 6: // 62.5 kHz
tmulrooney 23:952530fa968d 631 // bw = 625e2;
tmulrooney 23:952530fa968d 632 // break;
tmulrooney 23:952530fa968d 633 case 7: // 125 kHz
tmulrooney 23:952530fa968d 634 bw = 125e3;
tmulrooney 23:952530fa968d 635 break;
tmulrooney 23:952530fa968d 636 case 8: // 250 kHz
tmulrooney 23:952530fa968d 637 bw = 250e3;
tmulrooney 23:952530fa968d 638 break;
tmulrooney 23:952530fa968d 639 case 9: // 500 kHz
tmulrooney 23:952530fa968d 640 bw = 500e3;
tmulrooney 23:952530fa968d 641 break;
tmulrooney 23:952530fa968d 642 }
tmulrooney 23:952530fa968d 643
tmulrooney 23:952530fa968d 644 // Symbol rate : time for one symbol (secs)
tmulrooney 23:952530fa968d 645 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
tmulrooney 23:952530fa968d 646 double ts = 1 / rs;
tmulrooney 23:952530fa968d 647 // time of preamble
tmulrooney 23:952530fa968d 648 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
tmulrooney 23:952530fa968d 649 // Symbol length of payload and time
tmulrooney 23:952530fa968d 650 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
tmulrooney 23:952530fa968d 651 28 + 16 * this->settings.LoRa.CrcOn -
tmulrooney 23:952530fa968d 652 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
tmulrooney 23:952530fa968d 653 ( double )( 4 * this->settings.LoRa.Datarate -
tmulrooney 23:952530fa968d 654 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) *
tmulrooney 23:952530fa968d 655 ( this->settings.LoRa.Coderate + 4 );
tmulrooney 23:952530fa968d 656 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
tmulrooney 23:952530fa968d 657 double tPayload = nPayload * ts;
tmulrooney 23:952530fa968d 658 // Time on air
tmulrooney 23:952530fa968d 659 double tOnAir = tPreamble + tPayload;
tmulrooney 23:952530fa968d 660 // return us secs
tmulrooney 23:952530fa968d 661 airTime = floor( tOnAir * 1e6 + 0.999 );
tmulrooney 23:952530fa968d 662 }
tmulrooney 23:952530fa968d 663 break;
tmulrooney 23:952530fa968d 664 }
tmulrooney 23:952530fa968d 665 return airTime;
tmulrooney 23:952530fa968d 666 }
tmulrooney 23:952530fa968d 667
tmulrooney 23:952530fa968d 668 void SX1272::Send( uint8_t *buffer, uint8_t size )
tmulrooney 23:952530fa968d 669 {
tmulrooney 23:952530fa968d 670 debug("Send\r\n");
tmulrooney 23:952530fa968d 671 uint32_t txTimeout = 0;
tmulrooney 23:952530fa968d 672
tmulrooney 23:952530fa968d 673 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 674 {
tmulrooney 23:952530fa968d 675 case MODEM_FSK:
tmulrooney 23:952530fa968d 676 {
tmulrooney 23:952530fa968d 677 this->settings.FskPacketHandler.NbBytes = 0;
tmulrooney 23:952530fa968d 678 this->settings.FskPacketHandler.Size = size;
tmulrooney 23:952530fa968d 679
tmulrooney 23:952530fa968d 680 if( this->settings.Fsk.FixLen == false )
tmulrooney 23:952530fa968d 681 {
tmulrooney 23:952530fa968d 682 WriteFifo( ( uint8_t* )&size, 1 );
tmulrooney 23:952530fa968d 683 }
tmulrooney 23:952530fa968d 684 else
tmulrooney 23:952530fa968d 685 {
tmulrooney 23:952530fa968d 686 Write( REG_PAYLOADLENGTH, size );
tmulrooney 23:952530fa968d 687 }
tmulrooney 23:952530fa968d 688
tmulrooney 23:952530fa968d 689 if( ( size > 0 ) && ( size <= 64 ) )
tmulrooney 23:952530fa968d 690 {
tmulrooney 23:952530fa968d 691 this->settings.FskPacketHandler.ChunkSize = size;
tmulrooney 23:952530fa968d 692 }
tmulrooney 23:952530fa968d 693 else
tmulrooney 23:952530fa968d 694 {
tmulrooney 23:952530fa968d 695 this->settings.FskPacketHandler.ChunkSize = 32;
tmulrooney 23:952530fa968d 696 }
tmulrooney 23:952530fa968d 697
tmulrooney 23:952530fa968d 698 // Write payload buffer
tmulrooney 23:952530fa968d 699 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
tmulrooney 23:952530fa968d 700 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
tmulrooney 23:952530fa968d 701 txTimeout = this->settings.Fsk.TxTimeout;
tmulrooney 23:952530fa968d 702 }
tmulrooney 23:952530fa968d 703 break;
tmulrooney 23:952530fa968d 704 case MODEM_LORA:
tmulrooney 23:952530fa968d 705 {
tmulrooney 23:952530fa968d 706 if( this->settings.LoRa.IqInverted == true )
tmulrooney 23:952530fa968d 707 {
tmulrooney 23:952530fa968d 708 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
tmulrooney 23:952530fa968d 709 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
tmulrooney 23:952530fa968d 710 }
tmulrooney 23:952530fa968d 711 else
tmulrooney 23:952530fa968d 712 {
tmulrooney 23:952530fa968d 713 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
tmulrooney 23:952530fa968d 714 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
tmulrooney 23:952530fa968d 715 }
tmulrooney 23:952530fa968d 716
tmulrooney 23:952530fa968d 717 this->settings.LoRaPacketHandler.Size = size;
tmulrooney 23:952530fa968d 718
tmulrooney 23:952530fa968d 719 // Initializes the payload size
tmulrooney 23:952530fa968d 720 Write( REG_LR_PAYLOADLENGTH, size );
tmulrooney 23:952530fa968d 721
tmulrooney 23:952530fa968d 722 // Full buffer used for Tx
tmulrooney 23:952530fa968d 723 Write( REG_LR_FIFOTXBASEADDR, 0 );
tmulrooney 23:952530fa968d 724 Write( REG_LR_FIFOADDRPTR, 0 );
tmulrooney 23:952530fa968d 725
tmulrooney 23:952530fa968d 726 // FIFO operations can not take place in Sleep mode
tmulrooney 23:952530fa968d 727 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
tmulrooney 23:952530fa968d 728 {
tmulrooney 23:952530fa968d 729 Standby( );
tmulrooney 23:952530fa968d 730 wait_ms( 1 );
tmulrooney 23:952530fa968d 731 }
tmulrooney 23:952530fa968d 732 // Write payload buffer
tmulrooney 23:952530fa968d 733 WriteFifo( buffer, size );
tmulrooney 23:952530fa968d 734 txTimeout = this->settings.LoRa.TxTimeout;
tmulrooney 23:952530fa968d 735 }
tmulrooney 23:952530fa968d 736 break;
tmulrooney 23:952530fa968d 737 }
tmulrooney 23:952530fa968d 738
tmulrooney 23:952530fa968d 739 Tx( txTimeout );
tmulrooney 23:952530fa968d 740 }
tmulrooney 23:952530fa968d 741
tmulrooney 23:952530fa968d 742 void SX1272::Sleep( void )
tmulrooney 23:952530fa968d 743 {
tmulrooney 23:952530fa968d 744 debug("Sleep\r\n");
tmulrooney 23:952530fa968d 745 txTimeoutTimer.detach( );
tmulrooney 23:952530fa968d 746 rxTimeoutTimer.detach( );
tmulrooney 23:952530fa968d 747
tmulrooney 23:952530fa968d 748 SetOpMode( RF_OPMODE_SLEEP );
tmulrooney 23:952530fa968d 749 this->settings.State = RF_IDLE;
tmulrooney 23:952530fa968d 750 }
tmulrooney 23:952530fa968d 751
tmulrooney 23:952530fa968d 752 void SX1272::Standby( void )
tmulrooney 23:952530fa968d 753 {
tmulrooney 23:952530fa968d 754 debug("Standby\r\n");
tmulrooney 23:952530fa968d 755 txTimeoutTimer.detach( );
tmulrooney 23:952530fa968d 756 rxTimeoutTimer.detach( );
tmulrooney 23:952530fa968d 757
tmulrooney 23:952530fa968d 758 SetOpMode( RF_OPMODE_STANDBY );
tmulrooney 23:952530fa968d 759 this->settings.State = RF_IDLE;
tmulrooney 23:952530fa968d 760 }
tmulrooney 23:952530fa968d 761
tmulrooney 23:952530fa968d 762 void SX1272::Rx( uint32_t timeout )
tmulrooney 23:952530fa968d 763 {
tmulrooney 23:952530fa968d 764 debug("Rx enter %d\r\n",timeout);
tmulrooney 23:952530fa968d 765 bool rxContinuous = false;
tmulrooney 23:952530fa968d 766
tmulrooney 23:952530fa968d 767 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 768 {
tmulrooney 23:952530fa968d 769 case MODEM_FSK:
tmulrooney 23:952530fa968d 770 {
tmulrooney 23:952530fa968d 771 rxContinuous = this->settings.Fsk.RxContinuous;
tmulrooney 23:952530fa968d 772
tmulrooney 23:952530fa968d 773 // DIO0=PayloadReady
tmulrooney 23:952530fa968d 774 // DIO1=FifoLevel
tmulrooney 23:952530fa968d 775 // DIO2=SyncAddr
tmulrooney 23:952530fa968d 776 // DIO3=FifoEmpty
tmulrooney 23:952530fa968d 777 // DIO4=Preamble
tmulrooney 23:952530fa968d 778 // DIO5=ModeReady
tmulrooney 23:952530fa968d 779 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
tmulrooney 23:952530fa968d 780 RF_DIOMAPPING1_DIO2_MASK ) |
tmulrooney 23:952530fa968d 781 RF_DIOMAPPING1_DIO0_00 |
tmulrooney 23:952530fa968d 782 RF_DIOMAPPING1_DIO2_11 );
tmulrooney 23:952530fa968d 783
tmulrooney 23:952530fa968d 784 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
tmulrooney 23:952530fa968d 785 RF_DIOMAPPING2_MAP_MASK ) |
tmulrooney 23:952530fa968d 786 RF_DIOMAPPING2_DIO4_11 |
tmulrooney 23:952530fa968d 787 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
tmulrooney 23:952530fa968d 788
tmulrooney 23:952530fa968d 789 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
tmulrooney 23:952530fa968d 790
tmulrooney 23:952530fa968d 791 this->settings.FskPacketHandler.PreambleDetected = false;
tmulrooney 23:952530fa968d 792 this->settings.FskPacketHandler.SyncWordDetected = false;
tmulrooney 23:952530fa968d 793 this->settings.FskPacketHandler.NbBytes = 0;
tmulrooney 23:952530fa968d 794 this->settings.FskPacketHandler.Size = 0;
tmulrooney 23:952530fa968d 795 }
tmulrooney 23:952530fa968d 796 break;
tmulrooney 23:952530fa968d 797 case MODEM_LORA:
tmulrooney 23:952530fa968d 798 {
tmulrooney 23:952530fa968d 799 if( this->settings.LoRa.IqInverted == true )
tmulrooney 23:952530fa968d 800 {
tmulrooney 23:952530fa968d 801 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
tmulrooney 23:952530fa968d 802 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
tmulrooney 23:952530fa968d 803 }
tmulrooney 23:952530fa968d 804 else
tmulrooney 23:952530fa968d 805 {
tmulrooney 23:952530fa968d 806 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
tmulrooney 23:952530fa968d 807 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
tmulrooney 23:952530fa968d 808 }
tmulrooney 23:952530fa968d 809
tmulrooney 23:952530fa968d 810
tmulrooney 23:952530fa968d 811 // ERRATA 2.3 - Receiver Spurious Reception of a LoRa Signal
tmulrooney 23:952530fa968d 812 if( this->settings.LoRa.Bandwidth < 9 )
tmulrooney 23:952530fa968d 813 {
tmulrooney 23:952530fa968d 814 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) & 0x7F );
tmulrooney 23:952530fa968d 815 Write( REG_LR_TEST30, 0x00 );
tmulrooney 23:952530fa968d 816 switch( this->settings.LoRa.Bandwidth )
tmulrooney 23:952530fa968d 817 {
tmulrooney 23:952530fa968d 818 case 0: // 7.8 kHz
tmulrooney 23:952530fa968d 819 Write( REG_LR_TEST2F, 0x48 );
tmulrooney 23:952530fa968d 820 SetChannel(this->settings.Channel + 7.81e3 );
tmulrooney 23:952530fa968d 821 break;
tmulrooney 23:952530fa968d 822 case 1: // 10.4 kHz
tmulrooney 23:952530fa968d 823 Write( REG_LR_TEST2F, 0x44 );
tmulrooney 23:952530fa968d 824 SetChannel(this->settings.Channel + 10.42e3 );
tmulrooney 23:952530fa968d 825 break;
tmulrooney 23:952530fa968d 826 case 2: // 15.6 kHz
tmulrooney 23:952530fa968d 827 Write( REG_LR_TEST2F, 0x44 );
tmulrooney 23:952530fa968d 828 SetChannel(this->settings.Channel + 15.62e3 );
tmulrooney 23:952530fa968d 829 break;
tmulrooney 23:952530fa968d 830 case 3: // 20.8 kHz
tmulrooney 23:952530fa968d 831 Write( REG_LR_TEST2F, 0x44 );
tmulrooney 23:952530fa968d 832 SetChannel(this->settings.Channel + 20.83e3 );
tmulrooney 23:952530fa968d 833 break;
tmulrooney 23:952530fa968d 834 case 4: // 31.2 kHz
tmulrooney 23:952530fa968d 835 Write( REG_LR_TEST2F, 0x44 );
tmulrooney 23:952530fa968d 836 SetChannel(this->settings.Channel + 31.25e3 );
tmulrooney 23:952530fa968d 837 break;
tmulrooney 23:952530fa968d 838 case 5: // 41.4 kHz
tmulrooney 23:952530fa968d 839 Write( REG_LR_TEST2F, 0x44 );
tmulrooney 23:952530fa968d 840 SetChannel(this->settings.Channel + 41.67e3 );
tmulrooney 23:952530fa968d 841 break;
tmulrooney 23:952530fa968d 842 case 6: // 62.5 kHz
tmulrooney 23:952530fa968d 843 Write( REG_LR_TEST2F, 0x40 );
tmulrooney 23:952530fa968d 844 break;
tmulrooney 23:952530fa968d 845 case 7: // 125 kHz
tmulrooney 23:952530fa968d 846 Write( REG_LR_TEST2F, 0x40 );
tmulrooney 23:952530fa968d 847 break;
tmulrooney 23:952530fa968d 848 case 8: // 250 kHz
tmulrooney 23:952530fa968d 849 Write( REG_LR_TEST2F, 0x40 );
tmulrooney 23:952530fa968d 850 break;
tmulrooney 23:952530fa968d 851 }
tmulrooney 23:952530fa968d 852 }
tmulrooney 23:952530fa968d 853 else
tmulrooney 23:952530fa968d 854 {
tmulrooney 23:952530fa968d 855 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) | 0x80 );
tmulrooney 23:952530fa968d 856 }
tmulrooney 23:952530fa968d 857 this->settings.LoRa.RxContinuous = true; /* *********** added for test TJM **********/
tmulrooney 23:952530fa968d 858 rxContinuous = this->settings.LoRa.RxContinuous;
tmulrooney 23:952530fa968d 859
tmulrooney 23:952530fa968d 860 if( this->settings.LoRa.FreqHopOn == true )
tmulrooney 23:952530fa968d 861 {
tmulrooney 23:952530fa968d 862 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
tmulrooney 23:952530fa968d 863 //RFLR_IRQFLAGS_RXDONE |
tmulrooney 23:952530fa968d 864 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
tmulrooney 23:952530fa968d 865 RFLR_IRQFLAGS_VALIDHEADER |
tmulrooney 23:952530fa968d 866 RFLR_IRQFLAGS_TXDONE |
tmulrooney 23:952530fa968d 867 RFLR_IRQFLAGS_CADDONE |
tmulrooney 23:952530fa968d 868 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
tmulrooney 23:952530fa968d 869 RFLR_IRQFLAGS_CADDETECTED );
tmulrooney 23:952530fa968d 870
tmulrooney 23:952530fa968d 871 // DIO0=RxDone, DIO2=FhssChangeChannel
tmulrooney 23:952530fa968d 872 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
tmulrooney 23:952530fa968d 873 }
tmulrooney 23:952530fa968d 874 else
tmulrooney 23:952530fa968d 875 {
tmulrooney 23:952530fa968d 876 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
tmulrooney 23:952530fa968d 877 //RFLR_IRQFLAGS_RXDONE |
tmulrooney 23:952530fa968d 878 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
tmulrooney 23:952530fa968d 879 RFLR_IRQFLAGS_VALIDHEADER |
tmulrooney 23:952530fa968d 880 RFLR_IRQFLAGS_TXDONE |
tmulrooney 23:952530fa968d 881 RFLR_IRQFLAGS_CADDONE |
tmulrooney 23:952530fa968d 882 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
tmulrooney 23:952530fa968d 883 RFLR_IRQFLAGS_CADDETECTED );
tmulrooney 23:952530fa968d 884
tmulrooney 23:952530fa968d 885 // DIO0=RxDone
tmulrooney 23:952530fa968d 886 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
tmulrooney 23:952530fa968d 887 }
tmulrooney 23:952530fa968d 888 Write( REG_LR_FIFORXBASEADDR, 0 );
tmulrooney 23:952530fa968d 889 Write( REG_LR_FIFOADDRPTR, 0 );
tmulrooney 23:952530fa968d 890 }
tmulrooney 23:952530fa968d 891 break;
tmulrooney 23:952530fa968d 892 }
tmulrooney 23:952530fa968d 893
tmulrooney 23:952530fa968d 894 memset( rxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
tmulrooney 23:952530fa968d 895
tmulrooney 23:952530fa968d 896 this->settings.State = RF_RX_RUNNING;
tmulrooney 23:952530fa968d 897 if( timeout != 0 )
tmulrooney 23:952530fa968d 898 {
tmulrooney 23:952530fa968d 899 rxTimeoutTimer.attach_us( this, &SX1272::OnTimeoutIrq, timeout );
tmulrooney 23:952530fa968d 900 }
tmulrooney 23:952530fa968d 901
tmulrooney 23:952530fa968d 902 if( this->settings.Modem == MODEM_FSK )
tmulrooney 23:952530fa968d 903 {
tmulrooney 23:952530fa968d 904 SetOpMode( RF_OPMODE_RECEIVER );
tmulrooney 23:952530fa968d 905
tmulrooney 23:952530fa968d 906 if( rxContinuous == false )
tmulrooney 23:952530fa968d 907 {
tmulrooney 23:952530fa968d 908 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
tmulrooney 23:952530fa968d 909 ( ( Read( REG_SYNCCONFIG ) &
tmulrooney 23:952530fa968d 910 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
tmulrooney 23:952530fa968d 911 1.0 ) + 10.0 ) /
tmulrooney 23:952530fa968d 912 ( double )this->settings.Fsk.Datarate ) * 1e6 );
tmulrooney 23:952530fa968d 913 }
tmulrooney 23:952530fa968d 914 }
tmulrooney 23:952530fa968d 915 else
tmulrooney 23:952530fa968d 916 {
tmulrooney 23:952530fa968d 917 debug("rxContinuous %d\r\n",rxContinuous);
tmulrooney 23:952530fa968d 918 if( rxContinuous == true )
tmulrooney 23:952530fa968d 919 {
tmulrooney 23:952530fa968d 920 SetOpMode( RFLR_OPMODE_RECEIVER );
tmulrooney 23:952530fa968d 921 }
tmulrooney 23:952530fa968d 922 else
tmulrooney 23:952530fa968d 923 {
tmulrooney 23:952530fa968d 924 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
tmulrooney 23:952530fa968d 925 }
tmulrooney 23:952530fa968d 926 }
tmulrooney 23:952530fa968d 927 }
tmulrooney 23:952530fa968d 928
tmulrooney 23:952530fa968d 929 void SX1272::Tx( uint32_t timeout )
tmulrooney 23:952530fa968d 930 {
tmulrooney 23:952530fa968d 931 debug("Tx enter\r\n");
tmulrooney 23:952530fa968d 932
tmulrooney 23:952530fa968d 933 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 934 {
tmulrooney 23:952530fa968d 935 case MODEM_FSK:
tmulrooney 23:952530fa968d 936 {
tmulrooney 23:952530fa968d 937 // DIO0=PacketSent
tmulrooney 23:952530fa968d 938 // DIO1=FifoLevel
tmulrooney 23:952530fa968d 939 // DIO2=FifoFull
tmulrooney 23:952530fa968d 940 // DIO3=FifoEmpty
tmulrooney 23:952530fa968d 941 // DIO4=LowBat
tmulrooney 23:952530fa968d 942 // DIO5=ModeReady
tmulrooney 23:952530fa968d 943 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
tmulrooney 23:952530fa968d 944 RF_DIOMAPPING1_DIO2_MASK ) );
tmulrooney 23:952530fa968d 945
tmulrooney 23:952530fa968d 946 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
tmulrooney 23:952530fa968d 947 RF_DIOMAPPING2_MAP_MASK ) );
tmulrooney 23:952530fa968d 948 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
tmulrooney 23:952530fa968d 949 }
tmulrooney 23:952530fa968d 950 break;
tmulrooney 23:952530fa968d 951 case MODEM_LORA:
tmulrooney 23:952530fa968d 952 {
tmulrooney 23:952530fa968d 953 if( this->settings.LoRa.FreqHopOn == true )
tmulrooney 23:952530fa968d 954 {
tmulrooney 23:952530fa968d 955 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
tmulrooney 23:952530fa968d 956 RFLR_IRQFLAGS_RXDONE |
tmulrooney 23:952530fa968d 957 RFLR_IRQFLAGS_PAYLOADCRCERROR |
tmulrooney 23:952530fa968d 958 RFLR_IRQFLAGS_VALIDHEADER |
tmulrooney 23:952530fa968d 959 //RFLR_IRQFLAGS_TXDONE |
tmulrooney 23:952530fa968d 960 RFLR_IRQFLAGS_CADDONE |
tmulrooney 23:952530fa968d 961 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
tmulrooney 23:952530fa968d 962 RFLR_IRQFLAGS_CADDETECTED );
tmulrooney 23:952530fa968d 963
tmulrooney 23:952530fa968d 964 // DIO0=TxDone, DIO2=FhssChangeChannel
tmulrooney 23:952530fa968d 965 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
tmulrooney 23:952530fa968d 966 }
tmulrooney 23:952530fa968d 967 else
tmulrooney 23:952530fa968d 968 {
tmulrooney 23:952530fa968d 969 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
tmulrooney 23:952530fa968d 970 RFLR_IRQFLAGS_RXDONE |
tmulrooney 23:952530fa968d 971 RFLR_IRQFLAGS_PAYLOADCRCERROR |
tmulrooney 23:952530fa968d 972 RFLR_IRQFLAGS_VALIDHEADER |
tmulrooney 23:952530fa968d 973 //RFLR_IRQFLAGS_TXDONE |
tmulrooney 23:952530fa968d 974 RFLR_IRQFLAGS_CADDONE |
tmulrooney 23:952530fa968d 975 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
tmulrooney 23:952530fa968d 976 RFLR_IRQFLAGS_CADDETECTED );
tmulrooney 23:952530fa968d 977
tmulrooney 23:952530fa968d 978 // DIO0=TxDone
tmulrooney 23:952530fa968d 979 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
tmulrooney 23:952530fa968d 980 }
tmulrooney 23:952530fa968d 981 }
tmulrooney 23:952530fa968d 982 break;
tmulrooney 23:952530fa968d 983 }
tmulrooney 23:952530fa968d 984
tmulrooney 23:952530fa968d 985 this->settings.State = RF_TX_RUNNING;
tmulrooney 23:952530fa968d 986 txTimeoutTimer.attach_us( this, &SX1272::OnTimeoutIrq, timeout );
tmulrooney 23:952530fa968d 987 SetOpMode( RF_OPMODE_TRANSMITTER );
tmulrooney 23:952530fa968d 988 }
tmulrooney 23:952530fa968d 989
tmulrooney 23:952530fa968d 990 void SX1272::StartCad( void )
tmulrooney 23:952530fa968d 991 {
tmulrooney 23:952530fa968d 992 debug("StartCad\r\n");
tmulrooney 23:952530fa968d 993 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 994 {
tmulrooney 23:952530fa968d 995 case MODEM_FSK:
tmulrooney 23:952530fa968d 996 {
tmulrooney 23:952530fa968d 997
tmulrooney 23:952530fa968d 998 }
tmulrooney 23:952530fa968d 999 break;
tmulrooney 23:952530fa968d 1000 case MODEM_LORA:
tmulrooney 23:952530fa968d 1001 {
tmulrooney 23:952530fa968d 1002 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
tmulrooney 23:952530fa968d 1003 RFLR_IRQFLAGS_RXDONE |
tmulrooney 23:952530fa968d 1004 RFLR_IRQFLAGS_PAYLOADCRCERROR |
tmulrooney 23:952530fa968d 1005 RFLR_IRQFLAGS_VALIDHEADER |
tmulrooney 23:952530fa968d 1006 RFLR_IRQFLAGS_TXDONE |
tmulrooney 23:952530fa968d 1007 //RFLR_IRQFLAGS_CADDONE |
tmulrooney 23:952530fa968d 1008 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
tmulrooney 23:952530fa968d 1009 //RFLR_IRQFLAGS_CADDETECTED
tmulrooney 23:952530fa968d 1010 );
tmulrooney 23:952530fa968d 1011
tmulrooney 23:952530fa968d 1012 // DIO3=CADDone
tmulrooney 23:952530fa968d 1013 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
tmulrooney 23:952530fa968d 1014
tmulrooney 23:952530fa968d 1015 this->settings.State = RF_CAD;
tmulrooney 23:952530fa968d 1016 SetOpMode( RFLR_OPMODE_CAD );
tmulrooney 23:952530fa968d 1017 }
tmulrooney 23:952530fa968d 1018 break;
tmulrooney 23:952530fa968d 1019 default:
tmulrooney 23:952530fa968d 1020 break;
tmulrooney 23:952530fa968d 1021 }
tmulrooney 23:952530fa968d 1022 }
tmulrooney 23:952530fa968d 1023
tmulrooney 23:952530fa968d 1024 int16_t SX1272::GetRssi( RadioModems_t modem )
tmulrooney 23:952530fa968d 1025 {
tmulrooney 23:952530fa968d 1026 debug("GetRssi\r\n");
tmulrooney 23:952530fa968d 1027 int16_t rssi = 0;
tmulrooney 23:952530fa968d 1028
tmulrooney 23:952530fa968d 1029 switch( modem )
tmulrooney 23:952530fa968d 1030 {
tmulrooney 23:952530fa968d 1031 case MODEM_FSK:
tmulrooney 23:952530fa968d 1032 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
tmulrooney 23:952530fa968d 1033 break;
tmulrooney 23:952530fa968d 1034 case MODEM_LORA:
tmulrooney 23:952530fa968d 1035 if( this->settings.Channel > RF_MID_BAND_THRESH )
tmulrooney 23:952530fa968d 1036 {
tmulrooney 23:952530fa968d 1037 rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE );
tmulrooney 23:952530fa968d 1038 }
tmulrooney 23:952530fa968d 1039 else
tmulrooney 23:952530fa968d 1040 {
tmulrooney 23:952530fa968d 1041 rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE );
tmulrooney 23:952530fa968d 1042 }
tmulrooney 23:952530fa968d 1043 break;
tmulrooney 23:952530fa968d 1044 default:
tmulrooney 23:952530fa968d 1045 rssi = -1;
tmulrooney 23:952530fa968d 1046 break;
tmulrooney 23:952530fa968d 1047 }
tmulrooney 23:952530fa968d 1048 return rssi;
tmulrooney 23:952530fa968d 1049 }
tmulrooney 23:952530fa968d 1050
tmulrooney 23:952530fa968d 1051 void SX1272::SetOpMode( uint8_t opMode )
tmulrooney 23:952530fa968d 1052 {
tmulrooney 23:952530fa968d 1053 debug("SetOpMode enter %02X\r\n",opMode);
tmulrooney 23:952530fa968d 1054 if( opMode != previousOpMode )
tmulrooney 23:952530fa968d 1055 {
tmulrooney 23:952530fa968d 1056 previousOpMode = opMode;
tmulrooney 23:952530fa968d 1057 if( opMode == RF_OPMODE_SLEEP )
tmulrooney 23:952530fa968d 1058 {
tmulrooney 23:952530fa968d 1059 SetAntSwLowPower( true );
tmulrooney 23:952530fa968d 1060 }
tmulrooney 23:952530fa968d 1061 else
tmulrooney 23:952530fa968d 1062 {
tmulrooney 23:952530fa968d 1063 SetAntSwLowPower( false );
tmulrooney 23:952530fa968d 1064 if( opMode == RF_OPMODE_TRANSMITTER )
tmulrooney 23:952530fa968d 1065 {
tmulrooney 23:952530fa968d 1066 SetAntSw( 1 );
tmulrooney 23:952530fa968d 1067 }
tmulrooney 23:952530fa968d 1068 else
tmulrooney 23:952530fa968d 1069 {
tmulrooney 23:952530fa968d 1070 SetAntSw( 0 );
tmulrooney 23:952530fa968d 1071 }
tmulrooney 23:952530fa968d 1072 }
tmulrooney 23:952530fa968d 1073 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
tmulrooney 23:952530fa968d 1074 }
tmulrooney 23:952530fa968d 1075 }
tmulrooney 23:952530fa968d 1076
tmulrooney 23:952530fa968d 1077 void SX1272::SetModem( RadioModems_t modem )
tmulrooney 23:952530fa968d 1078 {
tmulrooney 23:952530fa968d 1079 debug("SetModem enter %d\r\n",modem);
tmulrooney 23:952530fa968d 1080 if( this->settings.Modem == modem )
tmulrooney 23:952530fa968d 1081 {
tmulrooney 23:952530fa968d 1082 return;
tmulrooney 23:952530fa968d 1083 }
tmulrooney 23:952530fa968d 1084
tmulrooney 23:952530fa968d 1085 this->settings.Modem = modem;
tmulrooney 23:952530fa968d 1086 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 1087 {
tmulrooney 23:952530fa968d 1088 default:
tmulrooney 23:952530fa968d 1089 case MODEM_FSK:
tmulrooney 23:952530fa968d 1090 SetOpMode( RF_OPMODE_SLEEP );
tmulrooney 23:952530fa968d 1091 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
tmulrooney 23:952530fa968d 1092
tmulrooney 23:952530fa968d 1093 Write( REG_DIOMAPPING1, 0x00 );
tmulrooney 23:952530fa968d 1094 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
tmulrooney 23:952530fa968d 1095 break;
tmulrooney 23:952530fa968d 1096 case MODEM_LORA:
tmulrooney 23:952530fa968d 1097 SetOpMode( RF_OPMODE_SLEEP );
tmulrooney 23:952530fa968d 1098 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
tmulrooney 23:952530fa968d 1099
tmulrooney 23:952530fa968d 1100 Write( REG_DIOMAPPING1, 0x00 );
tmulrooney 23:952530fa968d 1101 Write( REG_DIOMAPPING2, 0x00 );
tmulrooney 23:952530fa968d 1102 break;
tmulrooney 23:952530fa968d 1103 }
tmulrooney 23:952530fa968d 1104 }
tmulrooney 23:952530fa968d 1105
tmulrooney 23:952530fa968d 1106 void SX1272::SetMaxPayloadLength( RadioModems_t modem, uint8_t max )
tmulrooney 23:952530fa968d 1107 {
tmulrooney 23:952530fa968d 1108 debug("SetMaxPayloadLength\r\n");
tmulrooney 23:952530fa968d 1109 this->SetModem( modem );
tmulrooney 23:952530fa968d 1110
tmulrooney 23:952530fa968d 1111 switch( modem )
tmulrooney 23:952530fa968d 1112 {
tmulrooney 23:952530fa968d 1113 case MODEM_FSK:
tmulrooney 23:952530fa968d 1114 if( this->settings.Fsk.FixLen == false )
tmulrooney 23:952530fa968d 1115 {
tmulrooney 23:952530fa968d 1116 this->Write( REG_PAYLOADLENGTH, max );
tmulrooney 23:952530fa968d 1117 }
tmulrooney 23:952530fa968d 1118 break;
tmulrooney 23:952530fa968d 1119 case MODEM_LORA:
tmulrooney 23:952530fa968d 1120 this->Write( REG_LR_PAYLOADMAXLENGTH, max );
tmulrooney 23:952530fa968d 1121 break;
tmulrooney 23:952530fa968d 1122 }
tmulrooney 23:952530fa968d 1123 }
tmulrooney 23:952530fa968d 1124
tmulrooney 23:952530fa968d 1125 void SX1272::OnTimeoutIrq( void )
tmulrooney 23:952530fa968d 1126 {
tmulrooney 23:952530fa968d 1127 debug("OnTimeoutIrq\r\n");
tmulrooney 23:952530fa968d 1128 switch( this->settings.State )
tmulrooney 23:952530fa968d 1129 {
tmulrooney 23:952530fa968d 1130 case RF_RX_RUNNING:
tmulrooney 23:952530fa968d 1131 if( this->settings.Modem == MODEM_FSK )
tmulrooney 23:952530fa968d 1132 {
tmulrooney 23:952530fa968d 1133 this->settings.FskPacketHandler.PreambleDetected = false;
tmulrooney 23:952530fa968d 1134 this->settings.FskPacketHandler.SyncWordDetected = false;
tmulrooney 23:952530fa968d 1135 this->settings.FskPacketHandler.NbBytes = 0;
tmulrooney 23:952530fa968d 1136 this->settings.FskPacketHandler.Size = 0;
tmulrooney 23:952530fa968d 1137
tmulrooney 23:952530fa968d 1138 // Clear Irqs
tmulrooney 23:952530fa968d 1139 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
tmulrooney 23:952530fa968d 1140 RF_IRQFLAGS1_PREAMBLEDETECT |
tmulrooney 23:952530fa968d 1141 RF_IRQFLAGS1_SYNCADDRESSMATCH );
tmulrooney 23:952530fa968d 1142 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
tmulrooney 23:952530fa968d 1143
tmulrooney 23:952530fa968d 1144 if( this->settings.Fsk.RxContinuous == true )
tmulrooney 23:952530fa968d 1145 {
tmulrooney 23:952530fa968d 1146 // Continuous mode restart Rx chain
tmulrooney 23:952530fa968d 1147 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
tmulrooney 23:952530fa968d 1148 }
tmulrooney 23:952530fa968d 1149 else
tmulrooney 23:952530fa968d 1150 {
tmulrooney 23:952530fa968d 1151 this->settings.State = RF_IDLE;
tmulrooney 23:952530fa968d 1152 rxTimeoutSyncWord.detach( );
tmulrooney 23:952530fa968d 1153 }
tmulrooney 23:952530fa968d 1154 }
tmulrooney 23:952530fa968d 1155 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
tmulrooney 23:952530fa968d 1156 {
tmulrooney 23:952530fa968d 1157 this->RadioEvents->RxTimeout( );
tmulrooney 23:952530fa968d 1158 }
tmulrooney 23:952530fa968d 1159 break;
tmulrooney 23:952530fa968d 1160 case RF_TX_RUNNING:
tmulrooney 23:952530fa968d 1161 this->settings.State = RF_IDLE;
tmulrooney 23:952530fa968d 1162 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxTimeout != NULL ) )
tmulrooney 23:952530fa968d 1163 {
tmulrooney 23:952530fa968d 1164 this->RadioEvents->TxTimeout( );
tmulrooney 23:952530fa968d 1165 }
tmulrooney 23:952530fa968d 1166 break;
tmulrooney 23:952530fa968d 1167 default:
tmulrooney 23:952530fa968d 1168 break;
tmulrooney 23:952530fa968d 1169 }
tmulrooney 23:952530fa968d 1170 }
tmulrooney 23:952530fa968d 1171
tmulrooney 23:952530fa968d 1172 void SX1272::OnDio0Irq( void )
tmulrooney 23:952530fa968d 1173 {
tmulrooney 25:856779ac8921 1174 // debug_str("OnDio0Irq\r\n");
tmulrooney 23:952530fa968d 1175 volatile uint8_t irqFlags = 0;
tmulrooney 23:952530fa968d 1176
tmulrooney 23:952530fa968d 1177 switch( this->settings.State )
tmulrooney 23:952530fa968d 1178 {
tmulrooney 23:952530fa968d 1179 case RF_RX_RUNNING:
tmulrooney 23:952530fa968d 1180 //TimerStop( &RxTimeoutTimer );
tmulrooney 23:952530fa968d 1181 // RxDone interrupt
tmulrooney 23:952530fa968d 1182 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 1183 {
tmulrooney 23:952530fa968d 1184 case MODEM_FSK:
tmulrooney 23:952530fa968d 1185 if( this->settings.Fsk.CrcOn == true )
tmulrooney 23:952530fa968d 1186 {
tmulrooney 23:952530fa968d 1187 irqFlags = Read( REG_IRQFLAGS2 );
tmulrooney 23:952530fa968d 1188 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
tmulrooney 23:952530fa968d 1189 {
tmulrooney 23:952530fa968d 1190 // Clear Irqs
tmulrooney 23:952530fa968d 1191 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
tmulrooney 23:952530fa968d 1192 RF_IRQFLAGS1_PREAMBLEDETECT |
tmulrooney 23:952530fa968d 1193 RF_IRQFLAGS1_SYNCADDRESSMATCH );
tmulrooney 23:952530fa968d 1194 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
tmulrooney 23:952530fa968d 1195
tmulrooney 23:952530fa968d 1196 if( this->settings.Fsk.RxContinuous == false )
tmulrooney 23:952530fa968d 1197 {
tmulrooney 23:952530fa968d 1198 this->settings.State = RF_IDLE;
tmulrooney 23:952530fa968d 1199 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
tmulrooney 23:952530fa968d 1200 ( ( Read( REG_SYNCCONFIG ) &
tmulrooney 23:952530fa968d 1201 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
tmulrooney 23:952530fa968d 1202 1.0 ) + 10.0 ) /
tmulrooney 23:952530fa968d 1203 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
tmulrooney 23:952530fa968d 1204 }
tmulrooney 23:952530fa968d 1205 else
tmulrooney 23:952530fa968d 1206 {
tmulrooney 23:952530fa968d 1207 // Continuous mode restart Rx chain
tmulrooney 23:952530fa968d 1208 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
tmulrooney 23:952530fa968d 1209 }
tmulrooney 23:952530fa968d 1210 rxTimeoutTimer.detach( );
tmulrooney 23:952530fa968d 1211
tmulrooney 23:952530fa968d 1212 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
tmulrooney 23:952530fa968d 1213 {
tmulrooney 23:952530fa968d 1214 this->RadioEvents->RxError( );
tmulrooney 23:952530fa968d 1215 }
tmulrooney 23:952530fa968d 1216 this->settings.FskPacketHandler.PreambleDetected = false;
tmulrooney 23:952530fa968d 1217 this->settings.FskPacketHandler.SyncWordDetected = false;
tmulrooney 23:952530fa968d 1218 this->settings.FskPacketHandler.NbBytes = 0;
tmulrooney 23:952530fa968d 1219 this->settings.FskPacketHandler.Size = 0;
tmulrooney 23:952530fa968d 1220 break;
tmulrooney 23:952530fa968d 1221 }
tmulrooney 23:952530fa968d 1222 }
tmulrooney 23:952530fa968d 1223
tmulrooney 23:952530fa968d 1224 // Read received packet size
tmulrooney 23:952530fa968d 1225 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
tmulrooney 23:952530fa968d 1226 {
tmulrooney 23:952530fa968d 1227 if( this->settings.Fsk.FixLen == false )
tmulrooney 23:952530fa968d 1228 {
tmulrooney 23:952530fa968d 1229 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
tmulrooney 23:952530fa968d 1230 }
tmulrooney 23:952530fa968d 1231 else
tmulrooney 23:952530fa968d 1232 {
tmulrooney 23:952530fa968d 1233 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
tmulrooney 23:952530fa968d 1234 }
tmulrooney 23:952530fa968d 1235 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:952530fa968d 1236 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:952530fa968d 1237 }
tmulrooney 23:952530fa968d 1238 else
tmulrooney 23:952530fa968d 1239 {
tmulrooney 23:952530fa968d 1240 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:952530fa968d 1241 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:952530fa968d 1242 }
tmulrooney 23:952530fa968d 1243
tmulrooney 23:952530fa968d 1244 if( this->settings.Fsk.RxContinuous == false )
tmulrooney 23:952530fa968d 1245 {
tmulrooney 23:952530fa968d 1246 this->settings.State = RF_IDLE;
tmulrooney 23:952530fa968d 1247 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
tmulrooney 23:952530fa968d 1248 ( ( Read( REG_SYNCCONFIG ) &
tmulrooney 23:952530fa968d 1249 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
tmulrooney 23:952530fa968d 1250 1.0 ) + 10.0 ) /
tmulrooney 23:952530fa968d 1251 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
tmulrooney 23:952530fa968d 1252 }
tmulrooney 23:952530fa968d 1253 else
tmulrooney 23:952530fa968d 1254 {
tmulrooney 23:952530fa968d 1255 // Continuous mode restart Rx chain
tmulrooney 23:952530fa968d 1256 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
tmulrooney 23:952530fa968d 1257 }
tmulrooney 23:952530fa968d 1258 rxTimeoutTimer.detach( );
tmulrooney 23:952530fa968d 1259
tmulrooney 23:952530fa968d 1260 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
tmulrooney 23:952530fa968d 1261 {
tmulrooney 23:952530fa968d 1262 this->RadioEvents->RxDone( rxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
tmulrooney 23:952530fa968d 1263 }
tmulrooney 23:952530fa968d 1264 this->settings.FskPacketHandler.PreambleDetected = false;
tmulrooney 23:952530fa968d 1265 this->settings.FskPacketHandler.SyncWordDetected = false;
tmulrooney 23:952530fa968d 1266 this->settings.FskPacketHandler.NbBytes = 0;
tmulrooney 23:952530fa968d 1267 this->settings.FskPacketHandler.Size = 0;
tmulrooney 23:952530fa968d 1268 break;
tmulrooney 23:952530fa968d 1269 case MODEM_LORA:
tmulrooney 23:952530fa968d 1270 {
tmulrooney 23:952530fa968d 1271 int8_t snr = 0;
tmulrooney 23:952530fa968d 1272
tmulrooney 23:952530fa968d 1273 // Clear Irq
tmulrooney 23:952530fa968d 1274 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
tmulrooney 23:952530fa968d 1275
tmulrooney 23:952530fa968d 1276 irqFlags = Read( REG_LR_IRQFLAGS );
tmulrooney 23:952530fa968d 1277 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
tmulrooney 23:952530fa968d 1278 {
tmulrooney 23:952530fa968d 1279 // Clear Irq
tmulrooney 23:952530fa968d 1280 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
tmulrooney 23:952530fa968d 1281
tmulrooney 23:952530fa968d 1282 if( this->settings.LoRa.RxContinuous == false )
tmulrooney 23:952530fa968d 1283 {
tmulrooney 23:952530fa968d 1284 this->settings.State = RF_IDLE;
tmulrooney 23:952530fa968d 1285 }
tmulrooney 23:952530fa968d 1286 rxTimeoutTimer.detach( );
tmulrooney 23:952530fa968d 1287
tmulrooney 23:952530fa968d 1288 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
tmulrooney 23:952530fa968d 1289 {
tmulrooney 23:952530fa968d 1290 this->RadioEvents->RxError( );
tmulrooney 23:952530fa968d 1291 }
tmulrooney 23:952530fa968d 1292 break;
tmulrooney 23:952530fa968d 1293 }
tmulrooney 23:952530fa968d 1294
tmulrooney 23:952530fa968d 1295 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
tmulrooney 23:952530fa968d 1296 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
tmulrooney 23:952530fa968d 1297 {
tmulrooney 23:952530fa968d 1298 // Invert and divide by 4
tmulrooney 23:952530fa968d 1299 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
tmulrooney 23:952530fa968d 1300 snr = -snr;
tmulrooney 23:952530fa968d 1301 }
tmulrooney 23:952530fa968d 1302 else
tmulrooney 23:952530fa968d 1303 {
tmulrooney 23:952530fa968d 1304 // Divide by 4
tmulrooney 23:952530fa968d 1305 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
tmulrooney 23:952530fa968d 1306 }
tmulrooney 23:952530fa968d 1307
tmulrooney 23:952530fa968d 1308 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
tmulrooney 23:952530fa968d 1309 if( snr < 0 )
tmulrooney 23:952530fa968d 1310 {
tmulrooney 23:952530fa968d 1311 if( this->settings.Channel > RF_MID_BAND_THRESH )
tmulrooney 23:952530fa968d 1312 {
tmulrooney 23:952530fa968d 1313 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) +
tmulrooney 23:952530fa968d 1314 snr;
tmulrooney 23:952530fa968d 1315 }
tmulrooney 23:952530fa968d 1316 else
tmulrooney 23:952530fa968d 1317 {
tmulrooney 23:952530fa968d 1318 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) +
tmulrooney 23:952530fa968d 1319 snr;
tmulrooney 23:952530fa968d 1320 }
tmulrooney 23:952530fa968d 1321 }
tmulrooney 23:952530fa968d 1322 else
tmulrooney 23:952530fa968d 1323 {
tmulrooney 23:952530fa968d 1324 if( this->settings.Channel > RF_MID_BAND_THRESH )
tmulrooney 23:952530fa968d 1325 {
tmulrooney 23:952530fa968d 1326 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 );
tmulrooney 23:952530fa968d 1327 }
tmulrooney 23:952530fa968d 1328 else
tmulrooney 23:952530fa968d 1329 {
tmulrooney 23:952530fa968d 1330 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 );
tmulrooney 23:952530fa968d 1331 }
tmulrooney 23:952530fa968d 1332 }
tmulrooney 23:952530fa968d 1333
tmulrooney 23:952530fa968d 1334 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
tmulrooney 23:952530fa968d 1335 ReadFifo( rxBuffer, this->settings.LoRaPacketHandler.Size );
tmulrooney 23:952530fa968d 1336
tmulrooney 23:952530fa968d 1337 if( this->settings.LoRa.RxContinuous == false )
tmulrooney 23:952530fa968d 1338 {
tmulrooney 23:952530fa968d 1339 this->settings.State = RF_IDLE;
tmulrooney 23:952530fa968d 1340 }
tmulrooney 23:952530fa968d 1341 rxTimeoutTimer.detach( );
tmulrooney 23:952530fa968d 1342
tmulrooney 23:952530fa968d 1343 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
tmulrooney 23:952530fa968d 1344 {
tmulrooney 23:952530fa968d 1345 this->RadioEvents->RxDone( rxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
tmulrooney 23:952530fa968d 1346 }
tmulrooney 23:952530fa968d 1347 }
tmulrooney 23:952530fa968d 1348 break;
tmulrooney 23:952530fa968d 1349 default:
tmulrooney 23:952530fa968d 1350 break;
tmulrooney 23:952530fa968d 1351 }
tmulrooney 23:952530fa968d 1352 break;
tmulrooney 23:952530fa968d 1353 case RF_TX_RUNNING:
tmulrooney 23:952530fa968d 1354 txTimeoutTimer.detach( );
tmulrooney 23:952530fa968d 1355 // TxDone interrupt
tmulrooney 23:952530fa968d 1356 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 1357 {
tmulrooney 23:952530fa968d 1358 case MODEM_LORA:
tmulrooney 23:952530fa968d 1359 // Clear Irq
tmulrooney 23:952530fa968d 1360 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
tmulrooney 23:952530fa968d 1361 // Intentional fall through
tmulrooney 23:952530fa968d 1362 case MODEM_FSK:
tmulrooney 23:952530fa968d 1363 default:
tmulrooney 23:952530fa968d 1364 this->settings.State = RF_IDLE;
tmulrooney 23:952530fa968d 1365 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) )
tmulrooney 23:952530fa968d 1366 {
tmulrooney 23:952530fa968d 1367 this->RadioEvents->TxDone( );
tmulrooney 23:952530fa968d 1368 }
tmulrooney 23:952530fa968d 1369 break;
tmulrooney 23:952530fa968d 1370 }
tmulrooney 23:952530fa968d 1371 break;
tmulrooney 23:952530fa968d 1372 default:
tmulrooney 23:952530fa968d 1373 break;
tmulrooney 23:952530fa968d 1374 }
tmulrooney 23:952530fa968d 1375 }
tmulrooney 23:952530fa968d 1376
tmulrooney 23:952530fa968d 1377 void SX1272::OnDio1Irq( void )
tmulrooney 23:952530fa968d 1378 {
tmulrooney 25:856779ac8921 1379 // debug_str("OnDio1Irq\r\n");
tmulrooney 23:952530fa968d 1380 switch( this->settings.State )
tmulrooney 23:952530fa968d 1381 {
tmulrooney 23:952530fa968d 1382 case RF_RX_RUNNING:
tmulrooney 23:952530fa968d 1383 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 1384 {
tmulrooney 23:952530fa968d 1385 case MODEM_FSK:
tmulrooney 23:952530fa968d 1386 // FifoLevel interrupt
tmulrooney 23:952530fa968d 1387 // Read received packet size
tmulrooney 23:952530fa968d 1388 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
tmulrooney 23:952530fa968d 1389 {
tmulrooney 23:952530fa968d 1390 if( this->settings.Fsk.FixLen == false )
tmulrooney 23:952530fa968d 1391 {
tmulrooney 23:952530fa968d 1392 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
tmulrooney 23:952530fa968d 1393 }
tmulrooney 23:952530fa968d 1394 else
tmulrooney 23:952530fa968d 1395 {
tmulrooney 23:952530fa968d 1396 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
tmulrooney 23:952530fa968d 1397 }
tmulrooney 23:952530fa968d 1398 }
tmulrooney 23:952530fa968d 1399
tmulrooney 23:952530fa968d 1400 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
tmulrooney 23:952530fa968d 1401 {
tmulrooney 23:952530fa968d 1402 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
tmulrooney 23:952530fa968d 1403 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
tmulrooney 23:952530fa968d 1404 }
tmulrooney 23:952530fa968d 1405 else
tmulrooney 23:952530fa968d 1406 {
tmulrooney 23:952530fa968d 1407 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:952530fa968d 1408 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:952530fa968d 1409 }
tmulrooney 23:952530fa968d 1410 break;
tmulrooney 23:952530fa968d 1411 case MODEM_LORA:
tmulrooney 23:952530fa968d 1412 // Sync time out
tmulrooney 23:952530fa968d 1413 rxTimeoutTimer.detach( );
tmulrooney 23:952530fa968d 1414 this->settings.State = RF_IDLE;
tmulrooney 23:952530fa968d 1415 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
tmulrooney 23:952530fa968d 1416 {
tmulrooney 23:952530fa968d 1417 this->RadioEvents->RxTimeout( );
tmulrooney 23:952530fa968d 1418 }
tmulrooney 23:952530fa968d 1419 break;
tmulrooney 23:952530fa968d 1420 default:
tmulrooney 23:952530fa968d 1421 break;
tmulrooney 23:952530fa968d 1422 }
tmulrooney 23:952530fa968d 1423 break;
tmulrooney 23:952530fa968d 1424 case RF_TX_RUNNING:
tmulrooney 23:952530fa968d 1425 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 1426 {
tmulrooney 23:952530fa968d 1427 case MODEM_FSK:
tmulrooney 23:952530fa968d 1428 // FifoLevel interrupt
tmulrooney 23:952530fa968d 1429 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
tmulrooney 23:952530fa968d 1430 {
tmulrooney 23:952530fa968d 1431 WriteFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
tmulrooney 23:952530fa968d 1432 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
tmulrooney 23:952530fa968d 1433 }
tmulrooney 23:952530fa968d 1434 else
tmulrooney 23:952530fa968d 1435 {
tmulrooney 23:952530fa968d 1436 // Write the last chunk of data
tmulrooney 23:952530fa968d 1437 WriteFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
tmulrooney 23:952530fa968d 1438 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
tmulrooney 23:952530fa968d 1439 }
tmulrooney 23:952530fa968d 1440 break;
tmulrooney 23:952530fa968d 1441 case MODEM_LORA:
tmulrooney 23:952530fa968d 1442 break;
tmulrooney 23:952530fa968d 1443 default:
tmulrooney 23:952530fa968d 1444 break;
tmulrooney 23:952530fa968d 1445 }
tmulrooney 23:952530fa968d 1446 break;
tmulrooney 23:952530fa968d 1447 default:
tmulrooney 23:952530fa968d 1448 break;
tmulrooney 23:952530fa968d 1449 }
tmulrooney 23:952530fa968d 1450 }
tmulrooney 23:952530fa968d 1451
tmulrooney 23:952530fa968d 1452 void SX1272::OnDio2Irq( void )
tmulrooney 23:952530fa968d 1453 {
tmulrooney 25:856779ac8921 1454 debug_str("OnDio2Irq\r\n");
tmulrooney 23:952530fa968d 1455 switch( this->settings.State )
tmulrooney 23:952530fa968d 1456 {
tmulrooney 23:952530fa968d 1457 case RF_RX_RUNNING:
tmulrooney 23:952530fa968d 1458 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 1459 {
tmulrooney 23:952530fa968d 1460 case MODEM_FSK:
tmulrooney 23:952530fa968d 1461 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
tmulrooney 23:952530fa968d 1462 {
tmulrooney 23:952530fa968d 1463 rxTimeoutSyncWord.detach( );
tmulrooney 23:952530fa968d 1464
tmulrooney 23:952530fa968d 1465 this->settings.FskPacketHandler.SyncWordDetected = true;
tmulrooney 23:952530fa968d 1466
tmulrooney 23:952530fa968d 1467 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
tmulrooney 23:952530fa968d 1468
tmulrooney 23:952530fa968d 1469 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
tmulrooney 23:952530fa968d 1470 ( uint16_t )Read( REG_AFCLSB ) ) *
tmulrooney 23:952530fa968d 1471 ( double )FREQ_STEP;
tmulrooney 23:952530fa968d 1472 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
tmulrooney 23:952530fa968d 1473 }
tmulrooney 23:952530fa968d 1474 break;
tmulrooney 23:952530fa968d 1475 case MODEM_LORA:
tmulrooney 23:952530fa968d 1476 if( this->settings.LoRa.FreqHopOn == true )
tmulrooney 23:952530fa968d 1477 {
tmulrooney 23:952530fa968d 1478 // Clear Irq
tmulrooney 23:952530fa968d 1479 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
tmulrooney 23:952530fa968d 1480
tmulrooney 23:952530fa968d 1481 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
tmulrooney 23:952530fa968d 1482 {
tmulrooney 23:952530fa968d 1483 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
tmulrooney 23:952530fa968d 1484 }
tmulrooney 23:952530fa968d 1485 }
tmulrooney 23:952530fa968d 1486 break;
tmulrooney 23:952530fa968d 1487 default:
tmulrooney 23:952530fa968d 1488 break;
tmulrooney 23:952530fa968d 1489 }
tmulrooney 23:952530fa968d 1490 break;
tmulrooney 23:952530fa968d 1491 case RF_TX_RUNNING:
tmulrooney 23:952530fa968d 1492 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 1493 {
tmulrooney 23:952530fa968d 1494 case MODEM_FSK:
tmulrooney 23:952530fa968d 1495 break;
tmulrooney 23:952530fa968d 1496 case MODEM_LORA:
tmulrooney 23:952530fa968d 1497 if( this->settings.LoRa.FreqHopOn == true )
tmulrooney 23:952530fa968d 1498 {
tmulrooney 23:952530fa968d 1499 // Clear Irq
tmulrooney 23:952530fa968d 1500 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
tmulrooney 23:952530fa968d 1501
tmulrooney 23:952530fa968d 1502 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
tmulrooney 23:952530fa968d 1503 {
tmulrooney 23:952530fa968d 1504 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
tmulrooney 23:952530fa968d 1505 }
tmulrooney 23:952530fa968d 1506 }
tmulrooney 23:952530fa968d 1507 break;
tmulrooney 23:952530fa968d 1508 default:
tmulrooney 23:952530fa968d 1509 break;
tmulrooney 23:952530fa968d 1510 }
tmulrooney 23:952530fa968d 1511 break;
tmulrooney 23:952530fa968d 1512 default:
tmulrooney 23:952530fa968d 1513 break;
tmulrooney 23:952530fa968d 1514 }
tmulrooney 23:952530fa968d 1515 }
tmulrooney 23:952530fa968d 1516
tmulrooney 23:952530fa968d 1517 void SX1272::OnDio3Irq( void )
tmulrooney 23:952530fa968d 1518 {
tmulrooney 25:856779ac8921 1519 // debug_str("OnDio3Irq\r\n");
tmulrooney 23:952530fa968d 1520 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 1521 {
tmulrooney 23:952530fa968d 1522 case MODEM_FSK:
tmulrooney 23:952530fa968d 1523 break;
tmulrooney 23:952530fa968d 1524 case MODEM_LORA:
tmulrooney 23:952530fa968d 1525 if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
tmulrooney 23:952530fa968d 1526 {
tmulrooney 23:952530fa968d 1527 // Clear Irq
tmulrooney 23:952530fa968d 1528 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
tmulrooney 23:952530fa968d 1529 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
tmulrooney 23:952530fa968d 1530 {
tmulrooney 23:952530fa968d 1531 this->RadioEvents->CadDone( true );
tmulrooney 23:952530fa968d 1532 }
tmulrooney 23:952530fa968d 1533 }
tmulrooney 23:952530fa968d 1534 else
tmulrooney 23:952530fa968d 1535 {
tmulrooney 23:952530fa968d 1536 // Clear Irq
tmulrooney 23:952530fa968d 1537 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
tmulrooney 23:952530fa968d 1538 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
tmulrooney 23:952530fa968d 1539 {
tmulrooney 23:952530fa968d 1540 this->RadioEvents->CadDone( false );
tmulrooney 23:952530fa968d 1541 }
tmulrooney 23:952530fa968d 1542 }
tmulrooney 23:952530fa968d 1543 break;
tmulrooney 23:952530fa968d 1544 default:
tmulrooney 23:952530fa968d 1545 break;
tmulrooney 23:952530fa968d 1546 }
tmulrooney 23:952530fa968d 1547 }
tmulrooney 23:952530fa968d 1548
tmulrooney 23:952530fa968d 1549 void SX1272::OnDio4Irq( void )
tmulrooney 23:952530fa968d 1550 {
tmulrooney 25:856779ac8921 1551 // debug_str("OnDio4Irq\r\n");
tmulrooney 23:952530fa968d 1552 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 1553 {
tmulrooney 23:952530fa968d 1554 case MODEM_FSK:
tmulrooney 23:952530fa968d 1555 {
tmulrooney 23:952530fa968d 1556 if( this->settings.FskPacketHandler.PreambleDetected == false )
tmulrooney 23:952530fa968d 1557 {
tmulrooney 23:952530fa968d 1558 this->settings.FskPacketHandler.PreambleDetected = true;
tmulrooney 23:952530fa968d 1559 }
tmulrooney 23:952530fa968d 1560 }
tmulrooney 23:952530fa968d 1561 break;
tmulrooney 23:952530fa968d 1562 case MODEM_LORA:
tmulrooney 23:952530fa968d 1563 break;
tmulrooney 23:952530fa968d 1564 default:
tmulrooney 23:952530fa968d 1565 break;
tmulrooney 23:952530fa968d 1566 }
tmulrooney 23:952530fa968d 1567 }
tmulrooney 23:952530fa968d 1568
tmulrooney 23:952530fa968d 1569 void SX1272::OnDio5Irq( void )
tmulrooney 23:952530fa968d 1570 {
tmulrooney 25:856779ac8921 1571 // debug_str("OnDio5Irq\r\n");
tmulrooney 23:952530fa968d 1572 switch( this->settings.Modem )
tmulrooney 23:952530fa968d 1573 {
tmulrooney 23:952530fa968d 1574 case MODEM_FSK:
tmulrooney 23:952530fa968d 1575 break;
tmulrooney 23:952530fa968d 1576 case MODEM_LORA:
tmulrooney 23:952530fa968d 1577 break;
tmulrooney 23:952530fa968d 1578 default:
tmulrooney 23:952530fa968d 1579 break;
tmulrooney 23:952530fa968d 1580 }
tmulrooney 23:952530fa968d 1581 }