round-robin-rtos - Round robin Scheduler

Users » timexton » Code » round-robin-rtos

Tim Exton-McGuinness / Mbed 2 deprecated round-robin-rtos

Round robin Scheduler

LPC17xx.h@0:cf2d4c337b6f, 2010-09-09 (annotated)

Committer:: timexton
Date:: Thu Sep 09 14:09:14 2010 +0000
Revision:: 0:cf2d4c337b6f

Who changed what in which revision?

User	Revision	Line number	New contents of line
timexton	0:cf2d4c337b6f	1	/************************************************************************//
timexton	0:cf2d4c337b6f	2	* @file LPC17xx.h
timexton	0:cf2d4c337b6f	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
timexton	0:cf2d4c337b6f	4	* NXP LPC17xx Device Series
timexton	0:cf2d4c337b6f	5	* @version V1.07
timexton	0:cf2d4c337b6f	6	* @date 19. October 2009
timexton	0:cf2d4c337b6f	7	*
timexton	0:cf2d4c337b6f	8	* @note
timexton	0:cf2d4c337b6f	9	* Copyright (C) 2009 ARM Limited. All rights reserved.
timexton	0:cf2d4c337b6f	10	*
timexton	0:cf2d4c337b6f	11	* @par
timexton	0:cf2d4c337b6f	12	* ARM Limited (ARM) is supplying this software for use with Cortex-M
timexton	0:cf2d4c337b6f	13	* processor based microcontrollers. This file can be freely distributed
timexton	0:cf2d4c337b6f	14	* within development tools that are supporting such ARM based processors.
timexton	0:cf2d4c337b6f	15	*
timexton	0:cf2d4c337b6f	16	* @par
timexton	0:cf2d4c337b6f	17	* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
timexton	0:cf2d4c337b6f	18	* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
timexton	0:cf2d4c337b6f	19	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
timexton	0:cf2d4c337b6f	20	* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
timexton	0:cf2d4c337b6f	21	* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
timexton	0:cf2d4c337b6f	22	*
timexton	0:cf2d4c337b6f	23	******************************************************************************/
timexton	0:cf2d4c337b6f	24
timexton	0:cf2d4c337b6f	25
timexton	0:cf2d4c337b6f	26	#ifndef __LPC17xx_H__
timexton	0:cf2d4c337b6f	27	#define __LPC17xx_H__
timexton	0:cf2d4c337b6f	28
timexton	0:cf2d4c337b6f	29	/*
timexton	0:cf2d4c337b6f	30	* ==========================================================================
timexton	0:cf2d4c337b6f	31	* ---------- Interrupt Number Definition -----------------------------------
timexton	0:cf2d4c337b6f	32	* ==========================================================================
timexton	0:cf2d4c337b6f	33	*/
timexton	0:cf2d4c337b6f	34
timexton	0:cf2d4c337b6f	35	typedef enum IRQn
timexton	0:cf2d4c337b6f	36	{
timexton	0:cf2d4c337b6f	37	/**** Cortex-M3 Processor Exceptions Numbers *************************************************/
timexton	0:cf2d4c337b6f	38	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
timexton	0:cf2d4c337b6f	39	MemoryManagement_IRQn = -12, /!< 4 Cortex-M3 Memory Management Interrupt /
timexton	0:cf2d4c337b6f	40	BusFault_IRQn = -11, /!< 5 Cortex-M3 Bus Fault Interrupt /
timexton	0:cf2d4c337b6f	41	UsageFault_IRQn = -10, /!< 6 Cortex-M3 Usage Fault Interrupt /
timexton	0:cf2d4c337b6f	42	SVCall_IRQn = -5, /!< 11 Cortex-M3 SV Call Interrupt /
timexton	0:cf2d4c337b6f	43	DebugMonitor_IRQn = -4, /!< 12 Cortex-M3 Debug Monitor Interrupt /
timexton	0:cf2d4c337b6f	44	PendSV_IRQn = -2, /!< 14 Cortex-M3 Pend SV Interrupt /
timexton	0:cf2d4c337b6f	45	SysTick_IRQn = -1, /!< 15 Cortex-M3 System Tick Interrupt /
timexton	0:cf2d4c337b6f	46
timexton	0:cf2d4c337b6f	47	/**** LPC17xx Specific Interrupt Numbers *****************************************************/
timexton	0:cf2d4c337b6f	48	WDT_IRQn = 0, /!< Watchdog Timer Interrupt /
timexton	0:cf2d4c337b6f	49	TIMER0_IRQn = 1, /!< Timer0 Interrupt /
timexton	0:cf2d4c337b6f	50	TIMER1_IRQn = 2, /!< Timer1 Interrupt /
timexton	0:cf2d4c337b6f	51	TIMER2_IRQn = 3, /!< Timer2 Interrupt /
timexton	0:cf2d4c337b6f	52	TIMER3_IRQn = 4, /!< Timer3 Interrupt /
timexton	0:cf2d4c337b6f	53	UART0_IRQn = 5, /!< UART0 Interrupt /
timexton	0:cf2d4c337b6f	54	UART1_IRQn = 6, /!< UART1 Interrupt /
timexton	0:cf2d4c337b6f	55	UART2_IRQn = 7, /!< UART2 Interrupt /
timexton	0:cf2d4c337b6f	56	UART3_IRQn = 8, /!< UART3 Interrupt /
timexton	0:cf2d4c337b6f	57	PWM1_IRQn = 9, /!< PWM1 Interrupt /
timexton	0:cf2d4c337b6f	58	I2C0_IRQn = 10, /!< I2C0 Interrupt /
timexton	0:cf2d4c337b6f	59	I2C1_IRQn = 11, /!< I2C1 Interrupt /
timexton	0:cf2d4c337b6f	60	I2C2_IRQn = 12, /!< I2C2 Interrupt /
timexton	0:cf2d4c337b6f	61	SPI_IRQn = 13, /!< SPI Interrupt /
timexton	0:cf2d4c337b6f	62	SSP0_IRQn = 14, /!< SSP0 Interrupt /
timexton	0:cf2d4c337b6f	63	SSP1_IRQn = 15, /!< SSP1 Interrupt /
timexton	0:cf2d4c337b6f	64	PLL0_IRQn = 16, /!< PLL0 Lock (Main PLL) Interrupt /
timexton	0:cf2d4c337b6f	65	RTC_IRQn = 17, /!< Real Time Clock Interrupt /
timexton	0:cf2d4c337b6f	66	EINT0_IRQn = 18, /!< External Interrupt 0 Interrupt /
timexton	0:cf2d4c337b6f	67	EINT1_IRQn = 19, /!< External Interrupt 1 Interrupt /
timexton	0:cf2d4c337b6f	68	EINT2_IRQn = 20, /!< External Interrupt 2 Interrupt /
timexton	0:cf2d4c337b6f	69	EINT3_IRQn = 21, /!< External Interrupt 3 Interrupt /
timexton	0:cf2d4c337b6f	70	ADC_IRQn = 22, /!< A/D Converter Interrupt /
timexton	0:cf2d4c337b6f	71	BOD_IRQn = 23, /!< Brown-Out Detect Interrupt /
timexton	0:cf2d4c337b6f	72	USB_IRQn = 24, /!< USB Interrupt /
timexton	0:cf2d4c337b6f	73	CAN_IRQn = 25, /!< CAN Interrupt /
timexton	0:cf2d4c337b6f	74	DMA_IRQn = 26, /!< General Purpose DMA Interrupt /
timexton	0:cf2d4c337b6f	75	I2S_IRQn = 27, /!< I2S Interrupt /
timexton	0:cf2d4c337b6f	76	ENET_IRQn = 28, /!< Ethernet Interrupt /
timexton	0:cf2d4c337b6f	77	RIT_IRQn = 29, /!< Repetitive Interrupt Timer Interrupt /
timexton	0:cf2d4c337b6f	78	MCPWM_IRQn = 30, /!< Motor Control PWM Interrupt /
timexton	0:cf2d4c337b6f	79	QEI_IRQn = 31, /!< Quadrature Encoder Interface Interrupt /
timexton	0:cf2d4c337b6f	80	PLL1_IRQn = 32, /!< PLL1 Lock (USB PLL) Interrupt /
timexton	0:cf2d4c337b6f	81	} IRQn_Type;
timexton	0:cf2d4c337b6f	82
timexton	0:cf2d4c337b6f	83
timexton	0:cf2d4c337b6f	84	/*
timexton	0:cf2d4c337b6f	85	* ==========================================================================
timexton	0:cf2d4c337b6f	86	* ----------- Processor and Core Peripheral Section ------------------------
timexton	0:cf2d4c337b6f	87	* ==========================================================================
timexton	0:cf2d4c337b6f	88	*/
timexton	0:cf2d4c337b6f	89
timexton	0:cf2d4c337b6f	90	/* Configuration of the Cortex-M3 Processor and Core Peripherals */
timexton	0:cf2d4c337b6f	91	#define __MPU_PRESENT 1 /!< MPU present or not /
timexton	0:cf2d4c337b6f	92	#define __NVIC_PRIO_BITS 5 /!< Number of Bits used for Priority Levels /
timexton	0:cf2d4c337b6f	93	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
timexton	0:cf2d4c337b6f	94
timexton	0:cf2d4c337b6f	95
timexton	0:cf2d4c337b6f	96	#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
timexton	0:cf2d4c337b6f	97	#include "system_LPC17xx.h" /* System Header */
timexton	0:cf2d4c337b6f	98
timexton	0:cf2d4c337b6f	99
timexton	0:cf2d4c337b6f	100	/******************************************************************************/
timexton	0:cf2d4c337b6f	101	/* Device Specific Peripheral registers structures */
timexton	0:cf2d4c337b6f	102	/******************************************************************************/
timexton	0:cf2d4c337b6f	103
timexton	0:cf2d4c337b6f	104	#if defined ( __CC_ARM )
timexton	0:cf2d4c337b6f	105	#pragma anon_unions
timexton	0:cf2d4c337b6f	106	#endif
timexton	0:cf2d4c337b6f	107
timexton	0:cf2d4c337b6f	108	/------------- System Control (SC) ------------------------------------------/
timexton	0:cf2d4c337b6f	109	typedef struct
timexton	0:cf2d4c337b6f	110	{
timexton	0:cf2d4c337b6f	111	__IO uint32_t FLASHCFG; /* Flash Accelerator Module */
timexton	0:cf2d4c337b6f	112	uint32_t RESERVED0[31];
timexton	0:cf2d4c337b6f	113	__IO uint32_t PLL0CON; /* Clocking and Power Control */
timexton	0:cf2d4c337b6f	114	__IO uint32_t PLL0CFG;
timexton	0:cf2d4c337b6f	115	__I uint32_t PLL0STAT;
timexton	0:cf2d4c337b6f	116	__O uint32_t PLL0FEED;
timexton	0:cf2d4c337b6f	117	uint32_t RESERVED1[4];
timexton	0:cf2d4c337b6f	118	__IO uint32_t PLL1CON;
timexton	0:cf2d4c337b6f	119	__IO uint32_t PLL1CFG;
timexton	0:cf2d4c337b6f	120	__I uint32_t PLL1STAT;
timexton	0:cf2d4c337b6f	121	__O uint32_t PLL1FEED;
timexton	0:cf2d4c337b6f	122	uint32_t RESERVED2[4];
timexton	0:cf2d4c337b6f	123	__IO uint32_t PCON;
timexton	0:cf2d4c337b6f	124	__IO uint32_t PCONP;
timexton	0:cf2d4c337b6f	125	uint32_t RESERVED3[15];
timexton	0:cf2d4c337b6f	126	__IO uint32_t CCLKCFG;
timexton	0:cf2d4c337b6f	127	__IO uint32_t USBCLKCFG;
timexton	0:cf2d4c337b6f	128	__IO uint32_t CLKSRCSEL;
timexton	0:cf2d4c337b6f	129	uint32_t RESERVED4[12];
timexton	0:cf2d4c337b6f	130	__IO uint32_t EXTINT; /* External Interrupts */
timexton	0:cf2d4c337b6f	131	uint32_t RESERVED5;
timexton	0:cf2d4c337b6f	132	__IO uint32_t EXTMODE;
timexton	0:cf2d4c337b6f	133	__IO uint32_t EXTPOLAR;
timexton	0:cf2d4c337b6f	134	uint32_t RESERVED6[12];
timexton	0:cf2d4c337b6f	135	__IO uint32_t RSID; /* Reset */
timexton	0:cf2d4c337b6f	136	uint32_t RESERVED7[7];
timexton	0:cf2d4c337b6f	137	__IO uint32_t SCS; /* Syscon Miscellaneous Registers */
timexton	0:cf2d4c337b6f	138	__IO uint32_t IRCTRIM; /* Clock Dividers */
timexton	0:cf2d4c337b6f	139	__IO uint32_t PCLKSEL0;
timexton	0:cf2d4c337b6f	140	__IO uint32_t PCLKSEL1;
timexton	0:cf2d4c337b6f	141	uint32_t RESERVED8[4];
timexton	0:cf2d4c337b6f	142	__IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
timexton	0:cf2d4c337b6f	143	__IO uint32_t DMAREQSEL;
timexton	0:cf2d4c337b6f	144	__IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
timexton	0:cf2d4c337b6f	145	} LPC_SC_TypeDef;
timexton	0:cf2d4c337b6f	146
timexton	0:cf2d4c337b6f	147	/------------- Pin Connect Block (PINCON) -----------------------------------/
timexton	0:cf2d4c337b6f	148	typedef struct
timexton	0:cf2d4c337b6f	149	{
timexton	0:cf2d4c337b6f	150	__IO uint32_t PINSEL0;
timexton	0:cf2d4c337b6f	151	__IO uint32_t PINSEL1;
timexton	0:cf2d4c337b6f	152	__IO uint32_t PINSEL2;
timexton	0:cf2d4c337b6f	153	__IO uint32_t PINSEL3;
timexton	0:cf2d4c337b6f	154	__IO uint32_t PINSEL4;
timexton	0:cf2d4c337b6f	155	__IO uint32_t PINSEL5;
timexton	0:cf2d4c337b6f	156	__IO uint32_t PINSEL6;
timexton	0:cf2d4c337b6f	157	__IO uint32_t PINSEL7;
timexton	0:cf2d4c337b6f	158	__IO uint32_t PINSEL8;
timexton	0:cf2d4c337b6f	159	__IO uint32_t PINSEL9;
timexton	0:cf2d4c337b6f	160	__IO uint32_t PINSEL10;
timexton	0:cf2d4c337b6f	161	uint32_t RESERVED0[5];
timexton	0:cf2d4c337b6f	162	__IO uint32_t PINMODE0;
timexton	0:cf2d4c337b6f	163	__IO uint32_t PINMODE1;
timexton	0:cf2d4c337b6f	164	__IO uint32_t PINMODE2;
timexton	0:cf2d4c337b6f	165	__IO uint32_t PINMODE3;
timexton	0:cf2d4c337b6f	166	__IO uint32_t PINMODE4;
timexton	0:cf2d4c337b6f	167	__IO uint32_t PINMODE5;
timexton	0:cf2d4c337b6f	168	__IO uint32_t PINMODE6;
timexton	0:cf2d4c337b6f	169	__IO uint32_t PINMODE7;
timexton	0:cf2d4c337b6f	170	__IO uint32_t PINMODE8;
timexton	0:cf2d4c337b6f	171	__IO uint32_t PINMODE9;
timexton	0:cf2d4c337b6f	172	__IO uint32_t PINMODE_OD0;
timexton	0:cf2d4c337b6f	173	__IO uint32_t PINMODE_OD1;
timexton	0:cf2d4c337b6f	174	__IO uint32_t PINMODE_OD2;
timexton	0:cf2d4c337b6f	175	__IO uint32_t PINMODE_OD3;
timexton	0:cf2d4c337b6f	176	__IO uint32_t PINMODE_OD4;
timexton	0:cf2d4c337b6f	177	__IO uint32_t I2CPADCFG;
timexton	0:cf2d4c337b6f	178	} LPC_PINCON_TypeDef;
timexton	0:cf2d4c337b6f	179
timexton	0:cf2d4c337b6f	180	/------------- General Purpose Input/Output (GPIO) --------------------------/
timexton	0:cf2d4c337b6f	181	typedef struct
timexton	0:cf2d4c337b6f	182	{
timexton	0:cf2d4c337b6f	183	union {
timexton	0:cf2d4c337b6f	184	__IO uint32_t FIODIR;
timexton	0:cf2d4c337b6f	185	struct {
timexton	0:cf2d4c337b6f	186	__IO uint16_t FIODIRL;
timexton	0:cf2d4c337b6f	187	__IO uint16_t FIODIRH;
timexton	0:cf2d4c337b6f	188	};
timexton	0:cf2d4c337b6f	189	struct {
timexton	0:cf2d4c337b6f	190	__IO uint8_t FIODIR0;
timexton	0:cf2d4c337b6f	191	__IO uint8_t FIODIR1;
timexton	0:cf2d4c337b6f	192	__IO uint8_t FIODIR2;
timexton	0:cf2d4c337b6f	193	__IO uint8_t FIODIR3;
timexton	0:cf2d4c337b6f	194	};
timexton	0:cf2d4c337b6f	195	};
timexton	0:cf2d4c337b6f	196	uint32_t RESERVED0[3];
timexton	0:cf2d4c337b6f	197	union {
timexton	0:cf2d4c337b6f	198	__IO uint32_t FIOMASK;
timexton	0:cf2d4c337b6f	199	struct {
timexton	0:cf2d4c337b6f	200	__IO uint16_t FIOMASKL;
timexton	0:cf2d4c337b6f	201	__IO uint16_t FIOMASKH;
timexton	0:cf2d4c337b6f	202	};
timexton	0:cf2d4c337b6f	203	struct {
timexton	0:cf2d4c337b6f	204	__IO uint8_t FIOMASK0;
timexton	0:cf2d4c337b6f	205	__IO uint8_t FIOMASK1;
timexton	0:cf2d4c337b6f	206	__IO uint8_t FIOMASK2;
timexton	0:cf2d4c337b6f	207	__IO uint8_t FIOMASK3;
timexton	0:cf2d4c337b6f	208	};
timexton	0:cf2d4c337b6f	209	};
timexton	0:cf2d4c337b6f	210	union {
timexton	0:cf2d4c337b6f	211	__IO uint32_t FIOPIN;
timexton	0:cf2d4c337b6f	212	struct {
timexton	0:cf2d4c337b6f	213	__IO uint16_t FIOPINL;
timexton	0:cf2d4c337b6f	214	__IO uint16_t FIOPINH;
timexton	0:cf2d4c337b6f	215	};
timexton	0:cf2d4c337b6f	216	struct {
timexton	0:cf2d4c337b6f	217	__IO uint8_t FIOPIN0;
timexton	0:cf2d4c337b6f	218	__IO uint8_t FIOPIN1;
timexton	0:cf2d4c337b6f	219	__IO uint8_t FIOPIN2;
timexton	0:cf2d4c337b6f	220	__IO uint8_t FIOPIN3;
timexton	0:cf2d4c337b6f	221	};
timexton	0:cf2d4c337b6f	222	};
timexton	0:cf2d4c337b6f	223	union {
timexton	0:cf2d4c337b6f	224	__IO uint32_t FIOSET;
timexton	0:cf2d4c337b6f	225	struct {
timexton	0:cf2d4c337b6f	226	__IO uint16_t FIOSETL;
timexton	0:cf2d4c337b6f	227	__IO uint16_t FIOSETH;
timexton	0:cf2d4c337b6f	228	};
timexton	0:cf2d4c337b6f	229	struct {
timexton	0:cf2d4c337b6f	230	__IO uint8_t FIOSET0;
timexton	0:cf2d4c337b6f	231	__IO uint8_t FIOSET1;
timexton	0:cf2d4c337b6f	232	__IO uint8_t FIOSET2;
timexton	0:cf2d4c337b6f	233	__IO uint8_t FIOSET3;
timexton	0:cf2d4c337b6f	234	};
timexton	0:cf2d4c337b6f	235	};
timexton	0:cf2d4c337b6f	236	union {
timexton	0:cf2d4c337b6f	237	__O uint32_t FIOCLR;
timexton	0:cf2d4c337b6f	238	struct {
timexton	0:cf2d4c337b6f	239	__O uint16_t FIOCLRL;
timexton	0:cf2d4c337b6f	240	__O uint16_t FIOCLRH;
timexton	0:cf2d4c337b6f	241	};
timexton	0:cf2d4c337b6f	242	struct {
timexton	0:cf2d4c337b6f	243	__O uint8_t FIOCLR0;
timexton	0:cf2d4c337b6f	244	__O uint8_t FIOCLR1;
timexton	0:cf2d4c337b6f	245	__O uint8_t FIOCLR2;
timexton	0:cf2d4c337b6f	246	__O uint8_t FIOCLR3;
timexton	0:cf2d4c337b6f	247	};
timexton	0:cf2d4c337b6f	248	};
timexton	0:cf2d4c337b6f	249	} LPC_GPIO_TypeDef;
timexton	0:cf2d4c337b6f	250
timexton	0:cf2d4c337b6f	251	typedef struct
timexton	0:cf2d4c337b6f	252	{
timexton	0:cf2d4c337b6f	253	__I uint32_t IntStatus;
timexton	0:cf2d4c337b6f	254	__I uint32_t IO0IntStatR;
timexton	0:cf2d4c337b6f	255	__I uint32_t IO0IntStatF;
timexton	0:cf2d4c337b6f	256	__O uint32_t IO0IntClr;
timexton	0:cf2d4c337b6f	257	__IO uint32_t IO0IntEnR;
timexton	0:cf2d4c337b6f	258	__IO uint32_t IO0IntEnF;
timexton	0:cf2d4c337b6f	259	uint32_t RESERVED0[3];
timexton	0:cf2d4c337b6f	260	__I uint32_t IO2IntStatR;
timexton	0:cf2d4c337b6f	261	__I uint32_t IO2IntStatF;
timexton	0:cf2d4c337b6f	262	__O uint32_t IO2IntClr;
timexton	0:cf2d4c337b6f	263	__IO uint32_t IO2IntEnR;
timexton	0:cf2d4c337b6f	264	__IO uint32_t IO2IntEnF;
timexton	0:cf2d4c337b6f	265	} LPC_GPIOINT_TypeDef;
timexton	0:cf2d4c337b6f	266
timexton	0:cf2d4c337b6f	267	/------------- Timer (TIM) --------------------------------------------------/
timexton	0:cf2d4c337b6f	268	typedef struct
timexton	0:cf2d4c337b6f	269	{
timexton	0:cf2d4c337b6f	270	__IO uint32_t IR;
timexton	0:cf2d4c337b6f	271	__IO uint32_t TCR;
timexton	0:cf2d4c337b6f	272	__IO uint32_t TC;
timexton	0:cf2d4c337b6f	273	__IO uint32_t PR;
timexton	0:cf2d4c337b6f	274	__IO uint32_t PC;
timexton	0:cf2d4c337b6f	275	__IO uint32_t MCR;
timexton	0:cf2d4c337b6f	276	__IO uint32_t MR0;
timexton	0:cf2d4c337b6f	277	__IO uint32_t MR1;
timexton	0:cf2d4c337b6f	278	__IO uint32_t MR2;
timexton	0:cf2d4c337b6f	279	__IO uint32_t MR3;
timexton	0:cf2d4c337b6f	280	__IO uint32_t CCR;
timexton	0:cf2d4c337b6f	281	__I uint32_t CR0;
timexton	0:cf2d4c337b6f	282	__I uint32_t CR1;
timexton	0:cf2d4c337b6f	283	uint32_t RESERVED0[2];
timexton	0:cf2d4c337b6f	284	__IO uint32_t EMR;
timexton	0:cf2d4c337b6f	285	uint32_t RESERVED1[12];
timexton	0:cf2d4c337b6f	286	__IO uint32_t CTCR;
timexton	0:cf2d4c337b6f	287	} LPC_TIM_TypeDef;
timexton	0:cf2d4c337b6f	288
timexton	0:cf2d4c337b6f	289	/------------- Pulse-Width Modulation (PWM) ---------------------------------/
timexton	0:cf2d4c337b6f	290	typedef struct
timexton	0:cf2d4c337b6f	291	{
timexton	0:cf2d4c337b6f	292	__IO uint32_t IR;
timexton	0:cf2d4c337b6f	293	__IO uint32_t TCR;
timexton	0:cf2d4c337b6f	294	__IO uint32_t TC;
timexton	0:cf2d4c337b6f	295	__IO uint32_t PR;
timexton	0:cf2d4c337b6f	296	__IO uint32_t PC;
timexton	0:cf2d4c337b6f	297	__IO uint32_t MCR;
timexton	0:cf2d4c337b6f	298	__IO uint32_t MR0;
timexton	0:cf2d4c337b6f	299	__IO uint32_t MR1;
timexton	0:cf2d4c337b6f	300	__IO uint32_t MR2;
timexton	0:cf2d4c337b6f	301	__IO uint32_t MR3;
timexton	0:cf2d4c337b6f	302	__IO uint32_t CCR;
timexton	0:cf2d4c337b6f	303	__I uint32_t CR0;
timexton	0:cf2d4c337b6f	304	__I uint32_t CR1;
timexton	0:cf2d4c337b6f	305	__I uint32_t CR2;
timexton	0:cf2d4c337b6f	306	__I uint32_t CR3;
timexton	0:cf2d4c337b6f	307	uint32_t RESERVED0;
timexton	0:cf2d4c337b6f	308	__IO uint32_t MR4;
timexton	0:cf2d4c337b6f	309	__IO uint32_t MR5;
timexton	0:cf2d4c337b6f	310	__IO uint32_t MR6;
timexton	0:cf2d4c337b6f	311	__IO uint32_t PCR;
timexton	0:cf2d4c337b6f	312	__IO uint32_t LER;
timexton	0:cf2d4c337b6f	313	uint32_t RESERVED1[7];
timexton	0:cf2d4c337b6f	314	__IO uint32_t CTCR;
timexton	0:cf2d4c337b6f	315	} LPC_PWM_TypeDef;
timexton	0:cf2d4c337b6f	316
timexton	0:cf2d4c337b6f	317	/------------- Universal Asynchronous Receiver Transmitter (UART) -----------/
timexton	0:cf2d4c337b6f	318	typedef struct
timexton	0:cf2d4c337b6f	319	{
timexton	0:cf2d4c337b6f	320	union {
timexton	0:cf2d4c337b6f	321	__I uint8_t RBR;
timexton	0:cf2d4c337b6f	322	__O uint8_t THR;
timexton	0:cf2d4c337b6f	323	__IO uint8_t DLL;
timexton	0:cf2d4c337b6f	324	uint32_t RESERVED0;
timexton	0:cf2d4c337b6f	325	};
timexton	0:cf2d4c337b6f	326	union {
timexton	0:cf2d4c337b6f	327	__IO uint8_t DLM;
timexton	0:cf2d4c337b6f	328	__IO uint32_t IER;
timexton	0:cf2d4c337b6f	329	};
timexton	0:cf2d4c337b6f	330	union {
timexton	0:cf2d4c337b6f	331	__I uint32_t IIR;
timexton	0:cf2d4c337b6f	332	__O uint8_t FCR;
timexton	0:cf2d4c337b6f	333	};
timexton	0:cf2d4c337b6f	334	__IO uint8_t LCR;
timexton	0:cf2d4c337b6f	335	uint8_t RESERVED1[7];
timexton	0:cf2d4c337b6f	336	__I uint8_t LSR;
timexton	0:cf2d4c337b6f	337	uint8_t RESERVED2[7];
timexton	0:cf2d4c337b6f	338	__IO uint8_t SCR;
timexton	0:cf2d4c337b6f	339	uint8_t RESERVED3[3];
timexton	0:cf2d4c337b6f	340	__IO uint32_t ACR;
timexton	0:cf2d4c337b6f	341	__IO uint8_t ICR;
timexton	0:cf2d4c337b6f	342	uint8_t RESERVED4[3];
timexton	0:cf2d4c337b6f	343	__IO uint8_t FDR;
timexton	0:cf2d4c337b6f	344	uint8_t RESERVED5[7];
timexton	0:cf2d4c337b6f	345	__IO uint8_t TER;
timexton	0:cf2d4c337b6f	346	uint8_t RESERVED6[39];
timexton	0:cf2d4c337b6f	347	__I uint8_t FIFOLVL;
timexton	0:cf2d4c337b6f	348	} LPC_UART_TypeDef;
timexton	0:cf2d4c337b6f	349
timexton	0:cf2d4c337b6f	350	typedef struct
timexton	0:cf2d4c337b6f	351	{
timexton	0:cf2d4c337b6f	352	union {
timexton	0:cf2d4c337b6f	353	__I uint8_t RBR;
timexton	0:cf2d4c337b6f	354	__O uint8_t THR;
timexton	0:cf2d4c337b6f	355	__IO uint8_t DLL;
timexton	0:cf2d4c337b6f	356	uint32_t RESERVED0;
timexton	0:cf2d4c337b6f	357	};
timexton	0:cf2d4c337b6f	358	union {
timexton	0:cf2d4c337b6f	359	__IO uint8_t DLM;
timexton	0:cf2d4c337b6f	360	__IO uint32_t IER;
timexton	0:cf2d4c337b6f	361	};
timexton	0:cf2d4c337b6f	362	union {
timexton	0:cf2d4c337b6f	363	__I uint32_t IIR;
timexton	0:cf2d4c337b6f	364	__O uint8_t FCR;
timexton	0:cf2d4c337b6f	365	};
timexton	0:cf2d4c337b6f	366	__IO uint8_t LCR;
timexton	0:cf2d4c337b6f	367	uint8_t RESERVED1[7];
timexton	0:cf2d4c337b6f	368	__I uint8_t LSR;
timexton	0:cf2d4c337b6f	369	uint8_t RESERVED2[7];
timexton	0:cf2d4c337b6f	370	__IO uint8_t SCR;
timexton	0:cf2d4c337b6f	371	uint8_t RESERVED3[3];
timexton	0:cf2d4c337b6f	372	__IO uint32_t ACR;
timexton	0:cf2d4c337b6f	373	__IO uint8_t ICR;
timexton	0:cf2d4c337b6f	374	uint8_t RESERVED4[3];
timexton	0:cf2d4c337b6f	375	__IO uint8_t FDR;
timexton	0:cf2d4c337b6f	376	uint8_t RESERVED5[7];
timexton	0:cf2d4c337b6f	377	__IO uint8_t TER;
timexton	0:cf2d4c337b6f	378	uint8_t RESERVED6[39];
timexton	0:cf2d4c337b6f	379	__I uint8_t FIFOLVL;
timexton	0:cf2d4c337b6f	380	} LPC_UART0_TypeDef;
timexton	0:cf2d4c337b6f	381
timexton	0:cf2d4c337b6f	382	typedef struct
timexton	0:cf2d4c337b6f	383	{
timexton	0:cf2d4c337b6f	384	union {
timexton	0:cf2d4c337b6f	385	__I uint8_t RBR;
timexton	0:cf2d4c337b6f	386	__O uint8_t THR;
timexton	0:cf2d4c337b6f	387	__IO uint8_t DLL;
timexton	0:cf2d4c337b6f	388	uint32_t RESERVED0;
timexton	0:cf2d4c337b6f	389	};
timexton	0:cf2d4c337b6f	390	union {
timexton	0:cf2d4c337b6f	391	__IO uint8_t DLM;
timexton	0:cf2d4c337b6f	392	__IO uint32_t IER;
timexton	0:cf2d4c337b6f	393	};
timexton	0:cf2d4c337b6f	394	union {
timexton	0:cf2d4c337b6f	395	__I uint32_t IIR;
timexton	0:cf2d4c337b6f	396	__O uint8_t FCR;
timexton	0:cf2d4c337b6f	397	};
timexton	0:cf2d4c337b6f	398	__IO uint8_t LCR;
timexton	0:cf2d4c337b6f	399	uint8_t RESERVED1[3];
timexton	0:cf2d4c337b6f	400	__IO uint8_t MCR;
timexton	0:cf2d4c337b6f	401	uint8_t RESERVED2[3];
timexton	0:cf2d4c337b6f	402	__I uint8_t LSR;
timexton	0:cf2d4c337b6f	403	uint8_t RESERVED3[3];
timexton	0:cf2d4c337b6f	404	__I uint8_t MSR;
timexton	0:cf2d4c337b6f	405	uint8_t RESERVED4[3];
timexton	0:cf2d4c337b6f	406	__IO uint8_t SCR;
timexton	0:cf2d4c337b6f	407	uint8_t RESERVED5[3];
timexton	0:cf2d4c337b6f	408	__IO uint32_t ACR;
timexton	0:cf2d4c337b6f	409	uint32_t RESERVED6;
timexton	0:cf2d4c337b6f	410	__IO uint32_t FDR;
timexton	0:cf2d4c337b6f	411	uint32_t RESERVED7;
timexton	0:cf2d4c337b6f	412	__IO uint8_t TER;
timexton	0:cf2d4c337b6f	413	uint8_t RESERVED8[27];
timexton	0:cf2d4c337b6f	414	__IO uint8_t RS485CTRL;
timexton	0:cf2d4c337b6f	415	uint8_t RESERVED9[3];
timexton	0:cf2d4c337b6f	416	__IO uint8_t ADRMATCH;
timexton	0:cf2d4c337b6f	417	uint8_t RESERVED10[3];
timexton	0:cf2d4c337b6f	418	__IO uint8_t RS485DLY;
timexton	0:cf2d4c337b6f	419	uint8_t RESERVED11[3];
timexton	0:cf2d4c337b6f	420	__I uint8_t FIFOLVL;
timexton	0:cf2d4c337b6f	421	} LPC_UART1_TypeDef;
timexton	0:cf2d4c337b6f	422
timexton	0:cf2d4c337b6f	423	/------------- Serial Peripheral Interface (SPI) ----------------------------/
timexton	0:cf2d4c337b6f	424	typedef struct
timexton	0:cf2d4c337b6f	425	{
timexton	0:cf2d4c337b6f	426	__IO uint32_t SPCR;
timexton	0:cf2d4c337b6f	427	__I uint32_t SPSR;
timexton	0:cf2d4c337b6f	428	__IO uint32_t SPDR;
timexton	0:cf2d4c337b6f	429	__IO uint32_t SPCCR;
timexton	0:cf2d4c337b6f	430	uint32_t RESERVED0[3];
timexton	0:cf2d4c337b6f	431	__IO uint32_t SPINT;
timexton	0:cf2d4c337b6f	432	} LPC_SPI_TypeDef;
timexton	0:cf2d4c337b6f	433
timexton	0:cf2d4c337b6f	434	/------------- Synchronous Serial Communication (SSP) -----------------------/
timexton	0:cf2d4c337b6f	435	typedef struct
timexton	0:cf2d4c337b6f	436	{
timexton	0:cf2d4c337b6f	437	__IO uint32_t CR0;
timexton	0:cf2d4c337b6f	438	__IO uint32_t CR1;
timexton	0:cf2d4c337b6f	439	__IO uint32_t DR;
timexton	0:cf2d4c337b6f	440	__I uint32_t SR;
timexton	0:cf2d4c337b6f	441	__IO uint32_t CPSR;
timexton	0:cf2d4c337b6f	442	__IO uint32_t IMSC;
timexton	0:cf2d4c337b6f	443	__IO uint32_t RIS;
timexton	0:cf2d4c337b6f	444	__IO uint32_t MIS;
timexton	0:cf2d4c337b6f	445	__IO uint32_t ICR;
timexton	0:cf2d4c337b6f	446	__IO uint32_t DMACR;
timexton	0:cf2d4c337b6f	447	} LPC_SSP_TypeDef;
timexton	0:cf2d4c337b6f	448
timexton	0:cf2d4c337b6f	449	/------------- Inter-Integrated Circuit (I2C) -------------------------------/
timexton	0:cf2d4c337b6f	450	typedef struct
timexton	0:cf2d4c337b6f	451	{
timexton	0:cf2d4c337b6f	452	__IO uint32_t I2CONSET;
timexton	0:cf2d4c337b6f	453	__I uint32_t I2STAT;
timexton	0:cf2d4c337b6f	454	__IO uint32_t I2DAT;
timexton	0:cf2d4c337b6f	455	__IO uint32_t I2ADR0;
timexton	0:cf2d4c337b6f	456	__IO uint32_t I2SCLH;
timexton	0:cf2d4c337b6f	457	__IO uint32_t I2SCLL;
timexton	0:cf2d4c337b6f	458	__O uint32_t I2CONCLR;
timexton	0:cf2d4c337b6f	459	__IO uint32_t MMCTRL;
timexton	0:cf2d4c337b6f	460	__IO uint32_t I2ADR1;
timexton	0:cf2d4c337b6f	461	__IO uint32_t I2ADR2;
timexton	0:cf2d4c337b6f	462	__IO uint32_t I2ADR3;
timexton	0:cf2d4c337b6f	463	__I uint32_t I2DATA_BUFFER;
timexton	0:cf2d4c337b6f	464	__IO uint32_t I2MASK0;
timexton	0:cf2d4c337b6f	465	__IO uint32_t I2MASK1;
timexton	0:cf2d4c337b6f	466	__IO uint32_t I2MASK2;
timexton	0:cf2d4c337b6f	467	__IO uint32_t I2MASK3;
timexton	0:cf2d4c337b6f	468	} LPC_I2C_TypeDef;
timexton	0:cf2d4c337b6f	469
timexton	0:cf2d4c337b6f	470	/------------- Inter IC Sound (I2S) -----------------------------------------/
timexton	0:cf2d4c337b6f	471	typedef struct
timexton	0:cf2d4c337b6f	472	{
timexton	0:cf2d4c337b6f	473	__IO uint32_t I2SDAO;
timexton	0:cf2d4c337b6f	474	__IO uint32_t I2SDAI;
timexton	0:cf2d4c337b6f	475	__O uint32_t I2STXFIFO;
timexton	0:cf2d4c337b6f	476	__I uint32_t I2SRXFIFO;
timexton	0:cf2d4c337b6f	477	__I uint32_t I2SSTATE;
timexton	0:cf2d4c337b6f	478	__IO uint32_t I2SDMA1;
timexton	0:cf2d4c337b6f	479	__IO uint32_t I2SDMA2;
timexton	0:cf2d4c337b6f	480	__IO uint32_t I2SIRQ;
timexton	0:cf2d4c337b6f	481	__IO uint32_t I2STXRATE;
timexton	0:cf2d4c337b6f	482	__IO uint32_t I2SRXRATE;
timexton	0:cf2d4c337b6f	483	__IO uint32_t I2STXBITRATE;
timexton	0:cf2d4c337b6f	484	__IO uint32_t I2SRXBITRATE;
timexton	0:cf2d4c337b6f	485	__IO uint32_t I2STXMODE;
timexton	0:cf2d4c337b6f	486	__IO uint32_t I2SRXMODE;
timexton	0:cf2d4c337b6f	487	} LPC_I2S_TypeDef;
timexton	0:cf2d4c337b6f	488
timexton	0:cf2d4c337b6f	489	/------------- Repetitive Interrupt Timer (RIT) -----------------------------/
timexton	0:cf2d4c337b6f	490	typedef struct
timexton	0:cf2d4c337b6f	491	{
timexton	0:cf2d4c337b6f	492	__IO uint32_t RICOMPVAL;
timexton	0:cf2d4c337b6f	493	__IO uint32_t RIMASK;
timexton	0:cf2d4c337b6f	494	__IO uint8_t RICTRL;
timexton	0:cf2d4c337b6f	495	uint8_t RESERVED0[3];
timexton	0:cf2d4c337b6f	496	__IO uint32_t RICOUNTER;
timexton	0:cf2d4c337b6f	497	} LPC_RIT_TypeDef;
timexton	0:cf2d4c337b6f	498
timexton	0:cf2d4c337b6f	499	/------------- Real-Time Clock (RTC) ----------------------------------------/
timexton	0:cf2d4c337b6f	500	typedef struct
timexton	0:cf2d4c337b6f	501	{
timexton	0:cf2d4c337b6f	502	__IO uint8_t ILR;
timexton	0:cf2d4c337b6f	503	uint8_t RESERVED0[7];
timexton	0:cf2d4c337b6f	504	__IO uint8_t CCR;
timexton	0:cf2d4c337b6f	505	uint8_t RESERVED1[3];
timexton	0:cf2d4c337b6f	506	__IO uint8_t CIIR;
timexton	0:cf2d4c337b6f	507	uint8_t RESERVED2[3];
timexton	0:cf2d4c337b6f	508	__IO uint8_t AMR;
timexton	0:cf2d4c337b6f	509	uint8_t RESERVED3[3];
timexton	0:cf2d4c337b6f	510	__I uint32_t CTIME0;
timexton	0:cf2d4c337b6f	511	__I uint32_t CTIME1;
timexton	0:cf2d4c337b6f	512	__I uint32_t CTIME2;
timexton	0:cf2d4c337b6f	513	__IO uint8_t SEC;
timexton	0:cf2d4c337b6f	514	uint8_t RESERVED4[3];
timexton	0:cf2d4c337b6f	515	__IO uint8_t MIN;
timexton	0:cf2d4c337b6f	516	uint8_t RESERVED5[3];
timexton	0:cf2d4c337b6f	517	__IO uint8_t HOUR;
timexton	0:cf2d4c337b6f	518	uint8_t RESERVED6[3];
timexton	0:cf2d4c337b6f	519	__IO uint8_t DOM;
timexton	0:cf2d4c337b6f	520	uint8_t RESERVED7[3];
timexton	0:cf2d4c337b6f	521	__IO uint8_t DOW;
timexton	0:cf2d4c337b6f	522	uint8_t RESERVED8[3];
timexton	0:cf2d4c337b6f	523	__IO uint16_t DOY;
timexton	0:cf2d4c337b6f	524	uint16_t RESERVED9;
timexton	0:cf2d4c337b6f	525	__IO uint8_t MONTH;
timexton	0:cf2d4c337b6f	526	uint8_t RESERVED10[3];
timexton	0:cf2d4c337b6f	527	__IO uint16_t YEAR;
timexton	0:cf2d4c337b6f	528	uint16_t RESERVED11;
timexton	0:cf2d4c337b6f	529	__IO uint32_t CALIBRATION;
timexton	0:cf2d4c337b6f	530	__IO uint32_t GPREG0;
timexton	0:cf2d4c337b6f	531	__IO uint32_t GPREG1;
timexton	0:cf2d4c337b6f	532	__IO uint32_t GPREG2;
timexton	0:cf2d4c337b6f	533	__IO uint32_t GPREG3;
timexton	0:cf2d4c337b6f	534	__IO uint32_t GPREG4;
timexton	0:cf2d4c337b6f	535	__IO uint8_t RTC_AUXEN;
timexton	0:cf2d4c337b6f	536	uint8_t RESERVED12[3];
timexton	0:cf2d4c337b6f	537	__IO uint8_t RTC_AUX;
timexton	0:cf2d4c337b6f	538	uint8_t RESERVED13[3];
timexton	0:cf2d4c337b6f	539	__IO uint8_t ALSEC;
timexton	0:cf2d4c337b6f	540	uint8_t RESERVED14[3];
timexton	0:cf2d4c337b6f	541	__IO uint8_t ALMIN;
timexton	0:cf2d4c337b6f	542	uint8_t RESERVED15[3];
timexton	0:cf2d4c337b6f	543	__IO uint8_t ALHOUR;
timexton	0:cf2d4c337b6f	544	uint8_t RESERVED16[3];
timexton	0:cf2d4c337b6f	545	__IO uint8_t ALDOM;
timexton	0:cf2d4c337b6f	546	uint8_t RESERVED17[3];
timexton	0:cf2d4c337b6f	547	__IO uint8_t ALDOW;
timexton	0:cf2d4c337b6f	548	uint8_t RESERVED18[3];
timexton	0:cf2d4c337b6f	549	__IO uint16_t ALDOY;
timexton	0:cf2d4c337b6f	550	uint16_t RESERVED19;
timexton	0:cf2d4c337b6f	551	__IO uint8_t ALMON;
timexton	0:cf2d4c337b6f	552	uint8_t RESERVED20[3];
timexton	0:cf2d4c337b6f	553	__IO uint16_t ALYEAR;
timexton	0:cf2d4c337b6f	554	uint16_t RESERVED21;
timexton	0:cf2d4c337b6f	555	} LPC_RTC_TypeDef;
timexton	0:cf2d4c337b6f	556
timexton	0:cf2d4c337b6f	557	/------------- Watchdog Timer (WDT) -----------------------------------------/
timexton	0:cf2d4c337b6f	558	typedef struct
timexton	0:cf2d4c337b6f	559	{
timexton	0:cf2d4c337b6f	560	__IO uint8_t WDMOD;
timexton	0:cf2d4c337b6f	561	uint8_t RESERVED0[3];
timexton	0:cf2d4c337b6f	562	__IO uint32_t WDTC;
timexton	0:cf2d4c337b6f	563	__O uint8_t WDFEED;
timexton	0:cf2d4c337b6f	564	uint8_t RESERVED1[3];
timexton	0:cf2d4c337b6f	565	__I uint32_t WDTV;
timexton	0:cf2d4c337b6f	566	__IO uint32_t WDCLKSEL;
timexton	0:cf2d4c337b6f	567	} LPC_WDT_TypeDef;
timexton	0:cf2d4c337b6f	568
timexton	0:cf2d4c337b6f	569	/------------- Analog-to-Digital Converter (ADC) ----------------------------/
timexton	0:cf2d4c337b6f	570	typedef struct
timexton	0:cf2d4c337b6f	571	{
timexton	0:cf2d4c337b6f	572	__IO uint32_t ADCR;
timexton	0:cf2d4c337b6f	573	__IO uint32_t ADGDR;
timexton	0:cf2d4c337b6f	574	uint32_t RESERVED0;
timexton	0:cf2d4c337b6f	575	__IO uint32_t ADINTEN;
timexton	0:cf2d4c337b6f	576	__I uint32_t ADDR0;
timexton	0:cf2d4c337b6f	577	__I uint32_t ADDR1;
timexton	0:cf2d4c337b6f	578	__I uint32_t ADDR2;
timexton	0:cf2d4c337b6f	579	__I uint32_t ADDR3;
timexton	0:cf2d4c337b6f	580	__I uint32_t ADDR4;
timexton	0:cf2d4c337b6f	581	__I uint32_t ADDR5;
timexton	0:cf2d4c337b6f	582	__I uint32_t ADDR6;
timexton	0:cf2d4c337b6f	583	__I uint32_t ADDR7;
timexton	0:cf2d4c337b6f	584	__I uint32_t ADSTAT;
timexton	0:cf2d4c337b6f	585	__IO uint32_t ADTRM;
timexton	0:cf2d4c337b6f	586	} LPC_ADC_TypeDef;
timexton	0:cf2d4c337b6f	587
timexton	0:cf2d4c337b6f	588	/------------- Digital-to-Analog Converter (DAC) ----------------------------/
timexton	0:cf2d4c337b6f	589	typedef struct
timexton	0:cf2d4c337b6f	590	{
timexton	0:cf2d4c337b6f	591	__IO uint32_t DACR;
timexton	0:cf2d4c337b6f	592	__IO uint32_t DACCTRL;
timexton	0:cf2d4c337b6f	593	__IO uint16_t DACCNTVAL;
timexton	0:cf2d4c337b6f	594	} LPC_DAC_TypeDef;
timexton	0:cf2d4c337b6f	595
timexton	0:cf2d4c337b6f	596	/------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------/
timexton	0:cf2d4c337b6f	597	typedef struct
timexton	0:cf2d4c337b6f	598	{
timexton	0:cf2d4c337b6f	599	__I uint32_t MCCON;
timexton	0:cf2d4c337b6f	600	__O uint32_t MCCON_SET;
timexton	0:cf2d4c337b6f	601	__O uint32_t MCCON_CLR;
timexton	0:cf2d4c337b6f	602	__I uint32_t MCCAPCON;
timexton	0:cf2d4c337b6f	603	__O uint32_t MCCAPCON_SET;
timexton	0:cf2d4c337b6f	604	__O uint32_t MCCAPCON_CLR;
timexton	0:cf2d4c337b6f	605	__IO uint32_t MCTIM0;
timexton	0:cf2d4c337b6f	606	__IO uint32_t MCTIM1;
timexton	0:cf2d4c337b6f	607	__IO uint32_t MCTIM2;
timexton	0:cf2d4c337b6f	608	__IO uint32_t MCPER0;
timexton	0:cf2d4c337b6f	609	__IO uint32_t MCPER1;
timexton	0:cf2d4c337b6f	610	__IO uint32_t MCPER2;
timexton	0:cf2d4c337b6f	611	__IO uint32_t MCPW0;
timexton	0:cf2d4c337b6f	612	__IO uint32_t MCPW1;
timexton	0:cf2d4c337b6f	613	__IO uint32_t MCPW2;
timexton	0:cf2d4c337b6f	614	__IO uint32_t MCDEADTIME;
timexton	0:cf2d4c337b6f	615	__IO uint32_t MCCCP;
timexton	0:cf2d4c337b6f	616	__IO uint32_t MCCR0;
timexton	0:cf2d4c337b6f	617	__IO uint32_t MCCR1;
timexton	0:cf2d4c337b6f	618	__IO uint32_t MCCR2;
timexton	0:cf2d4c337b6f	619	__I uint32_t MCINTEN;
timexton	0:cf2d4c337b6f	620	__O uint32_t MCINTEN_SET;
timexton	0:cf2d4c337b6f	621	__O uint32_t MCINTEN_CLR;
timexton	0:cf2d4c337b6f	622	__I uint32_t MCCNTCON;
timexton	0:cf2d4c337b6f	623	__O uint32_t MCCNTCON_SET;
timexton	0:cf2d4c337b6f	624	__O uint32_t MCCNTCON_CLR;
timexton	0:cf2d4c337b6f	625	__I uint32_t MCINTFLAG;
timexton	0:cf2d4c337b6f	626	__O uint32_t MCINTFLAG_SET;
timexton	0:cf2d4c337b6f	627	__O uint32_t MCINTFLAG_CLR;
timexton	0:cf2d4c337b6f	628	__O uint32_t MCCAP_CLR;
timexton	0:cf2d4c337b6f	629	} LPC_MCPWM_TypeDef;
timexton	0:cf2d4c337b6f	630
timexton	0:cf2d4c337b6f	631	/------------- Quadrature Encoder Interface (QEI) ---------------------------/
timexton	0:cf2d4c337b6f	632	typedef struct
timexton	0:cf2d4c337b6f	633	{
timexton	0:cf2d4c337b6f	634	__O uint32_t QEICON;
timexton	0:cf2d4c337b6f	635	__I uint32_t QEISTAT;
timexton	0:cf2d4c337b6f	636	__IO uint32_t QEICONF;
timexton	0:cf2d4c337b6f	637	__I uint32_t QEIPOS;
timexton	0:cf2d4c337b6f	638	__IO uint32_t QEIMAXPOS;
timexton	0:cf2d4c337b6f	639	__IO uint32_t CMPOS0;
timexton	0:cf2d4c337b6f	640	__IO uint32_t CMPOS1;
timexton	0:cf2d4c337b6f	641	__IO uint32_t CMPOS2;
timexton	0:cf2d4c337b6f	642	__I uint32_t INXCNT;
timexton	0:cf2d4c337b6f	643	__IO uint32_t INXCMP;
timexton	0:cf2d4c337b6f	644	__IO uint32_t QEILOAD;
timexton	0:cf2d4c337b6f	645	__I uint32_t QEITIME;
timexton	0:cf2d4c337b6f	646	__I uint32_t QEIVEL;
timexton	0:cf2d4c337b6f	647	__I uint32_t QEICAP;
timexton	0:cf2d4c337b6f	648	__IO uint32_t VELCOMP;
timexton	0:cf2d4c337b6f	649	__IO uint32_t FILTER;
timexton	0:cf2d4c337b6f	650	uint32_t RESERVED0[998];
timexton	0:cf2d4c337b6f	651	__O uint32_t QEIIEC;
timexton	0:cf2d4c337b6f	652	__O uint32_t QEIIES;
timexton	0:cf2d4c337b6f	653	__I uint32_t QEIINTSTAT;
timexton	0:cf2d4c337b6f	654	__I uint32_t QEIIE;
timexton	0:cf2d4c337b6f	655	__O uint32_t QEICLR;
timexton	0:cf2d4c337b6f	656	__O uint32_t QEISET;
timexton	0:cf2d4c337b6f	657	} LPC_QEI_TypeDef;
timexton	0:cf2d4c337b6f	658
timexton	0:cf2d4c337b6f	659	/------------- Controller Area Network (CAN) --------------------------------/
timexton	0:cf2d4c337b6f	660	typedef struct
timexton	0:cf2d4c337b6f	661	{
timexton	0:cf2d4c337b6f	662	__IO uint32_t mask[512]; /* ID Masks */
timexton	0:cf2d4c337b6f	663	} LPC_CANAF_RAM_TypeDef;
timexton	0:cf2d4c337b6f	664
timexton	0:cf2d4c337b6f	665	typedef struct /* Acceptance Filter Registers */
timexton	0:cf2d4c337b6f	666	{
timexton	0:cf2d4c337b6f	667	__IO uint32_t AFMR;
timexton	0:cf2d4c337b6f	668	__IO uint32_t SFF_sa;
timexton	0:cf2d4c337b6f	669	__IO uint32_t SFF_GRP_sa;
timexton	0:cf2d4c337b6f	670	__IO uint32_t EFF_sa;
timexton	0:cf2d4c337b6f	671	__IO uint32_t EFF_GRP_sa;
timexton	0:cf2d4c337b6f	672	__IO uint32_t ENDofTable;
timexton	0:cf2d4c337b6f	673	__I uint32_t LUTerrAd;
timexton	0:cf2d4c337b6f	674	__I uint32_t LUTerr;
timexton	0:cf2d4c337b6f	675	__IO uint32_t FCANIE;
timexton	0:cf2d4c337b6f	676	__IO uint32_t FCANIC0;
timexton	0:cf2d4c337b6f	677	__IO uint32_t FCANIC1;
timexton	0:cf2d4c337b6f	678	} LPC_CANAF_TypeDef;
timexton	0:cf2d4c337b6f	679
timexton	0:cf2d4c337b6f	680	typedef struct /* Central Registers */
timexton	0:cf2d4c337b6f	681	{
timexton	0:cf2d4c337b6f	682	__I uint32_t CANTxSR;
timexton	0:cf2d4c337b6f	683	__I uint32_t CANRxSR;
timexton	0:cf2d4c337b6f	684	__I uint32_t CANMSR;
timexton	0:cf2d4c337b6f	685	} LPC_CANCR_TypeDef;
timexton	0:cf2d4c337b6f	686
timexton	0:cf2d4c337b6f	687	typedef struct /* Controller Registers */
timexton	0:cf2d4c337b6f	688	{
timexton	0:cf2d4c337b6f	689	__IO uint32_t MOD;
timexton	0:cf2d4c337b6f	690	__O uint32_t CMR;
timexton	0:cf2d4c337b6f	691	__IO uint32_t GSR;
timexton	0:cf2d4c337b6f	692	__I uint32_t ICR;
timexton	0:cf2d4c337b6f	693	__IO uint32_t IER;
timexton	0:cf2d4c337b6f	694	__IO uint32_t BTR;
timexton	0:cf2d4c337b6f	695	__IO uint32_t EWL;
timexton	0:cf2d4c337b6f	696	__I uint32_t SR;
timexton	0:cf2d4c337b6f	697	__IO uint32_t RFS;
timexton	0:cf2d4c337b6f	698	__IO uint32_t RID;
timexton	0:cf2d4c337b6f	699	__IO uint32_t RDA;
timexton	0:cf2d4c337b6f	700	__IO uint32_t RDB;
timexton	0:cf2d4c337b6f	701	__IO uint32_t TFI1;
timexton	0:cf2d4c337b6f	702	__IO uint32_t TID1;
timexton	0:cf2d4c337b6f	703	__IO uint32_t TDA1;
timexton	0:cf2d4c337b6f	704	__IO uint32_t TDB1;
timexton	0:cf2d4c337b6f	705	__IO uint32_t TFI2;
timexton	0:cf2d4c337b6f	706	__IO uint32_t TID2;
timexton	0:cf2d4c337b6f	707	__IO uint32_t TDA2;
timexton	0:cf2d4c337b6f	708	__IO uint32_t TDB2;
timexton	0:cf2d4c337b6f	709	__IO uint32_t TFI3;
timexton	0:cf2d4c337b6f	710	__IO uint32_t TID3;
timexton	0:cf2d4c337b6f	711	__IO uint32_t TDA3;
timexton	0:cf2d4c337b6f	712	__IO uint32_t TDB3;
timexton	0:cf2d4c337b6f	713	} LPC_CAN_TypeDef;
timexton	0:cf2d4c337b6f	714
timexton	0:cf2d4c337b6f	715	/------------- General Purpose Direct Memory Access (GPDMA) -----------------/
timexton	0:cf2d4c337b6f	716	typedef struct /* Common Registers */
timexton	0:cf2d4c337b6f	717	{
timexton	0:cf2d4c337b6f	718	__I uint32_t DMACIntStat;
timexton	0:cf2d4c337b6f	719	__I uint32_t DMACIntTCStat;
timexton	0:cf2d4c337b6f	720	__O uint32_t DMACIntTCClear;
timexton	0:cf2d4c337b6f	721	__I uint32_t DMACIntErrStat;
timexton	0:cf2d4c337b6f	722	__O uint32_t DMACIntErrClr;
timexton	0:cf2d4c337b6f	723	__I uint32_t DMACRawIntTCStat;
timexton	0:cf2d4c337b6f	724	__I uint32_t DMACRawIntErrStat;
timexton	0:cf2d4c337b6f	725	__I uint32_t DMACEnbldChns;
timexton	0:cf2d4c337b6f	726	__IO uint32_t DMACSoftBReq;
timexton	0:cf2d4c337b6f	727	__IO uint32_t DMACSoftSReq;
timexton	0:cf2d4c337b6f	728	__IO uint32_t DMACSoftLBReq;
timexton	0:cf2d4c337b6f	729	__IO uint32_t DMACSoftLSReq;
timexton	0:cf2d4c337b6f	730	__IO uint32_t DMACConfig;
timexton	0:cf2d4c337b6f	731	__IO uint32_t DMACSync;
timexton	0:cf2d4c337b6f	732	} LPC_GPDMA_TypeDef;
timexton	0:cf2d4c337b6f	733
timexton	0:cf2d4c337b6f	734	typedef struct /* Channel Registers */
timexton	0:cf2d4c337b6f	735	{
timexton	0:cf2d4c337b6f	736	__IO uint32_t DMACCSrcAddr;
timexton	0:cf2d4c337b6f	737	__IO uint32_t DMACCDestAddr;
timexton	0:cf2d4c337b6f	738	__IO uint32_t DMACCLLI;
timexton	0:cf2d4c337b6f	739	__IO uint32_t DMACCControl;
timexton	0:cf2d4c337b6f	740	__IO uint32_t DMACCConfig;
timexton	0:cf2d4c337b6f	741	} LPC_GPDMACH_TypeDef;
timexton	0:cf2d4c337b6f	742
timexton	0:cf2d4c337b6f	743	/------------- Universal Serial Bus (USB) -----------------------------------/
timexton	0:cf2d4c337b6f	744	typedef struct
timexton	0:cf2d4c337b6f	745	{
timexton	0:cf2d4c337b6f	746	__I uint32_t HcRevision; /* USB Host Registers */
timexton	0:cf2d4c337b6f	747	__IO uint32_t HcControl;
timexton	0:cf2d4c337b6f	748	__IO uint32_t HcCommandStatus;
timexton	0:cf2d4c337b6f	749	__IO uint32_t HcInterruptStatus;
timexton	0:cf2d4c337b6f	750	__IO uint32_t HcInterruptEnable;
timexton	0:cf2d4c337b6f	751	__IO uint32_t HcInterruptDisable;
timexton	0:cf2d4c337b6f	752	__IO uint32_t HcHCCA;
timexton	0:cf2d4c337b6f	753	__I uint32_t HcPeriodCurrentED;
timexton	0:cf2d4c337b6f	754	__IO uint32_t HcControlHeadED;
timexton	0:cf2d4c337b6f	755	__IO uint32_t HcControlCurrentED;
timexton	0:cf2d4c337b6f	756	__IO uint32_t HcBulkHeadED;
timexton	0:cf2d4c337b6f	757	__IO uint32_t HcBulkCurrentED;
timexton	0:cf2d4c337b6f	758	__I uint32_t HcDoneHead;
timexton	0:cf2d4c337b6f	759	__IO uint32_t HcFmInterval;
timexton	0:cf2d4c337b6f	760	__I uint32_t HcFmRemaining;
timexton	0:cf2d4c337b6f	761	__I uint32_t HcFmNumber;
timexton	0:cf2d4c337b6f	762	__IO uint32_t HcPeriodicStart;
timexton	0:cf2d4c337b6f	763	__IO uint32_t HcLSTreshold;
timexton	0:cf2d4c337b6f	764	__IO uint32_t HcRhDescriptorA;
timexton	0:cf2d4c337b6f	765	__IO uint32_t HcRhDescriptorB;
timexton	0:cf2d4c337b6f	766	__IO uint32_t HcRhStatus;
timexton	0:cf2d4c337b6f	767	__IO uint32_t HcRhPortStatus1;
timexton	0:cf2d4c337b6f	768	__IO uint32_t HcRhPortStatus2;
timexton	0:cf2d4c337b6f	769	uint32_t RESERVED0[40];
timexton	0:cf2d4c337b6f	770	__I uint32_t Module_ID;
timexton	0:cf2d4c337b6f	771
timexton	0:cf2d4c337b6f	772	__I uint32_t OTGIntSt; /* USB On-The-Go Registers */
timexton	0:cf2d4c337b6f	773	__IO uint32_t OTGIntEn;
timexton	0:cf2d4c337b6f	774	__O uint32_t OTGIntSet;
timexton	0:cf2d4c337b6f	775	__O uint32_t OTGIntClr;
timexton	0:cf2d4c337b6f	776	__IO uint32_t OTGStCtrl;
timexton	0:cf2d4c337b6f	777	__IO uint32_t OTGTmr;
timexton	0:cf2d4c337b6f	778	uint32_t RESERVED1[58];
timexton	0:cf2d4c337b6f	779
timexton	0:cf2d4c337b6f	780	__I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
timexton	0:cf2d4c337b6f	781	__IO uint32_t USBDevIntEn;
timexton	0:cf2d4c337b6f	782	__O uint32_t USBDevIntClr;
timexton	0:cf2d4c337b6f	783	__O uint32_t USBDevIntSet;
timexton	0:cf2d4c337b6f	784
timexton	0:cf2d4c337b6f	785	__O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
timexton	0:cf2d4c337b6f	786	__I uint32_t USBCmdData;
timexton	0:cf2d4c337b6f	787
timexton	0:cf2d4c337b6f	788	__I uint32_t USBRxData; /* USB Device Transfer Registers */
timexton	0:cf2d4c337b6f	789	__O uint32_t USBTxData;
timexton	0:cf2d4c337b6f	790	__I uint32_t USBRxPLen;
timexton	0:cf2d4c337b6f	791	__O uint32_t USBTxPLen;
timexton	0:cf2d4c337b6f	792	__IO uint32_t USBCtrl;
timexton	0:cf2d4c337b6f	793	__O uint32_t USBDevIntPri;
timexton	0:cf2d4c337b6f	794
timexton	0:cf2d4c337b6f	795	__I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
timexton	0:cf2d4c337b6f	796	__IO uint32_t USBEpIntEn;
timexton	0:cf2d4c337b6f	797	__O uint32_t USBEpIntClr;
timexton	0:cf2d4c337b6f	798	__O uint32_t USBEpIntSet;
timexton	0:cf2d4c337b6f	799	__O uint32_t USBEpIntPri;
timexton	0:cf2d4c337b6f	800
timexton	0:cf2d4c337b6f	801	__IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
timexton	0:cf2d4c337b6f	802	__O uint32_t USBEpInd;
timexton	0:cf2d4c337b6f	803	__IO uint32_t USBMaxPSize;
timexton	0:cf2d4c337b6f	804
timexton	0:cf2d4c337b6f	805	__I uint32_t USBDMARSt; /* USB Device DMA Registers */
timexton	0:cf2d4c337b6f	806	__O uint32_t USBDMARClr;
timexton	0:cf2d4c337b6f	807	__O uint32_t USBDMARSet;
timexton	0:cf2d4c337b6f	808	uint32_t RESERVED2[9];
timexton	0:cf2d4c337b6f	809	__IO uint32_t USBUDCAH;
timexton	0:cf2d4c337b6f	810	__I uint32_t USBEpDMASt;
timexton	0:cf2d4c337b6f	811	__O uint32_t USBEpDMAEn;
timexton	0:cf2d4c337b6f	812	__O uint32_t USBEpDMADis;
timexton	0:cf2d4c337b6f	813	__I uint32_t USBDMAIntSt;
timexton	0:cf2d4c337b6f	814	__IO uint32_t USBDMAIntEn;
timexton	0:cf2d4c337b6f	815	uint32_t RESERVED3[2];
timexton	0:cf2d4c337b6f	816	__I uint32_t USBEoTIntSt;
timexton	0:cf2d4c337b6f	817	__O uint32_t USBEoTIntClr;
timexton	0:cf2d4c337b6f	818	__O uint32_t USBEoTIntSet;
timexton	0:cf2d4c337b6f	819	__I uint32_t USBNDDRIntSt;
timexton	0:cf2d4c337b6f	820	__O uint32_t USBNDDRIntClr;
timexton	0:cf2d4c337b6f	821	__O uint32_t USBNDDRIntSet;
timexton	0:cf2d4c337b6f	822	__I uint32_t USBSysErrIntSt;
timexton	0:cf2d4c337b6f	823	__O uint32_t USBSysErrIntClr;
timexton	0:cf2d4c337b6f	824	__O uint32_t USBSysErrIntSet;
timexton	0:cf2d4c337b6f	825	uint32_t RESERVED4[15];
timexton	0:cf2d4c337b6f	826
timexton	0:cf2d4c337b6f	827	__I uint32_t I2C_RX; /* USB OTG I2C Registers */
timexton	0:cf2d4c337b6f	828	__O uint32_t I2C_WO;
timexton	0:cf2d4c337b6f	829	__I uint32_t I2C_STS;
timexton	0:cf2d4c337b6f	830	__IO uint32_t I2C_CTL;
timexton	0:cf2d4c337b6f	831	__IO uint32_t I2C_CLKHI;
timexton	0:cf2d4c337b6f	832	__O uint32_t I2C_CLKLO;
timexton	0:cf2d4c337b6f	833	uint32_t RESERVED5[823];
timexton	0:cf2d4c337b6f	834
timexton	0:cf2d4c337b6f	835	union {
timexton	0:cf2d4c337b6f	836	__IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
timexton	0:cf2d4c337b6f	837	__IO uint32_t OTGClkCtrl;
timexton	0:cf2d4c337b6f	838	};
timexton	0:cf2d4c337b6f	839	union {
timexton	0:cf2d4c337b6f	840	__I uint32_t USBClkSt;
timexton	0:cf2d4c337b6f	841	__I uint32_t OTGClkSt;
timexton	0:cf2d4c337b6f	842	};
timexton	0:cf2d4c337b6f	843	} LPC_USB_TypeDef;
timexton	0:cf2d4c337b6f	844
timexton	0:cf2d4c337b6f	845	/------------- Ethernet Media Access Controller (EMAC) ----------------------/
timexton	0:cf2d4c337b6f	846	typedef struct
timexton	0:cf2d4c337b6f	847	{
timexton	0:cf2d4c337b6f	848	__IO uint32_t MAC1; /* MAC Registers */
timexton	0:cf2d4c337b6f	849	__IO uint32_t MAC2;
timexton	0:cf2d4c337b6f	850	__IO uint32_t IPGT;
timexton	0:cf2d4c337b6f	851	__IO uint32_t IPGR;
timexton	0:cf2d4c337b6f	852	__IO uint32_t CLRT;
timexton	0:cf2d4c337b6f	853	__IO uint32_t MAXF;
timexton	0:cf2d4c337b6f	854	__IO uint32_t SUPP;
timexton	0:cf2d4c337b6f	855	__IO uint32_t TEST;
timexton	0:cf2d4c337b6f	856	__IO uint32_t MCFG;
timexton	0:cf2d4c337b6f	857	__IO uint32_t MCMD;
timexton	0:cf2d4c337b6f	858	__IO uint32_t MADR;
timexton	0:cf2d4c337b6f	859	__O uint32_t MWTD;
timexton	0:cf2d4c337b6f	860	__I uint32_t MRDD;
timexton	0:cf2d4c337b6f	861	__I uint32_t MIND;
timexton	0:cf2d4c337b6f	862	uint32_t RESERVED0[2];
timexton	0:cf2d4c337b6f	863	__IO uint32_t SA0;
timexton	0:cf2d4c337b6f	864	__IO uint32_t SA1;
timexton	0:cf2d4c337b6f	865	__IO uint32_t SA2;
timexton	0:cf2d4c337b6f	866	uint32_t RESERVED1[45];
timexton	0:cf2d4c337b6f	867	__IO uint32_t Command; /* Control Registers */
timexton	0:cf2d4c337b6f	868	__I uint32_t Status;
timexton	0:cf2d4c337b6f	869	__IO uint32_t RxDescriptor;
timexton	0:cf2d4c337b6f	870	__IO uint32_t RxStatus;
timexton	0:cf2d4c337b6f	871	__IO uint32_t RxDescriptorNumber;
timexton	0:cf2d4c337b6f	872	__I uint32_t RxProduceIndex;
timexton	0:cf2d4c337b6f	873	__IO uint32_t RxConsumeIndex;
timexton	0:cf2d4c337b6f	874	__IO uint32_t TxDescriptor;
timexton	0:cf2d4c337b6f	875	__IO uint32_t TxStatus;
timexton	0:cf2d4c337b6f	876	__IO uint32_t TxDescriptorNumber;
timexton	0:cf2d4c337b6f	877	__IO uint32_t TxProduceIndex;
timexton	0:cf2d4c337b6f	878	__I uint32_t TxConsumeIndex;
timexton	0:cf2d4c337b6f	879	uint32_t RESERVED2[10];
timexton	0:cf2d4c337b6f	880	__I uint32_t TSV0;
timexton	0:cf2d4c337b6f	881	__I uint32_t TSV1;
timexton	0:cf2d4c337b6f	882	__I uint32_t RSV;
timexton	0:cf2d4c337b6f	883	uint32_t RESERVED3[3];
timexton	0:cf2d4c337b6f	884	__IO uint32_t FlowControlCounter;
timexton	0:cf2d4c337b6f	885	__I uint32_t FlowControlStatus;
timexton	0:cf2d4c337b6f	886	uint32_t RESERVED4[34];
timexton	0:cf2d4c337b6f	887	__IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
timexton	0:cf2d4c337b6f	888	__IO uint32_t RxFilterWoLStatus;
timexton	0:cf2d4c337b6f	889	__IO uint32_t RxFilterWoLClear;
timexton	0:cf2d4c337b6f	890	uint32_t RESERVED5;
timexton	0:cf2d4c337b6f	891	__IO uint32_t HashFilterL;
timexton	0:cf2d4c337b6f	892	__IO uint32_t HashFilterH;
timexton	0:cf2d4c337b6f	893	uint32_t RESERVED6[882];
timexton	0:cf2d4c337b6f	894	__I uint32_t IntStatus; /* Module Control Registers */
timexton	0:cf2d4c337b6f	895	__IO uint32_t IntEnable;
timexton	0:cf2d4c337b6f	896	__O uint32_t IntClear;
timexton	0:cf2d4c337b6f	897	__O uint32_t IntSet;
timexton	0:cf2d4c337b6f	898	uint32_t RESERVED7;
timexton	0:cf2d4c337b6f	899	__IO uint32_t PowerDown;
timexton	0:cf2d4c337b6f	900	uint32_t RESERVED8;
timexton	0:cf2d4c337b6f	901	__IO uint32_t Module_ID;
timexton	0:cf2d4c337b6f	902	} LPC_EMAC_TypeDef;
timexton	0:cf2d4c337b6f	903
timexton	0:cf2d4c337b6f	904	#if defined ( __CC_ARM )
timexton	0:cf2d4c337b6f	905	#pragma no_anon_unions
timexton	0:cf2d4c337b6f	906	#endif
timexton	0:cf2d4c337b6f	907
timexton	0:cf2d4c337b6f	908
timexton	0:cf2d4c337b6f	909	/******************************************************************************/
timexton	0:cf2d4c337b6f	910	/* Peripheral memory map */
timexton	0:cf2d4c337b6f	911	/******************************************************************************/
timexton	0:cf2d4c337b6f	912	/* Base addresses */
timexton	0:cf2d4c337b6f	913	#define LPC_FLASH_BASE (0x00000000UL)
timexton	0:cf2d4c337b6f	914	#define LPC_RAM_BASE (0x10000000UL)
timexton	0:cf2d4c337b6f	915	#define LPC_GPIO_BASE (0x2009C000UL)
timexton	0:cf2d4c337b6f	916	#define LPC_APB0_BASE (0x40000000UL)
timexton	0:cf2d4c337b6f	917	#define LPC_APB1_BASE (0x40080000UL)
timexton	0:cf2d4c337b6f	918	#define LPC_AHB_BASE (0x50000000UL)
timexton	0:cf2d4c337b6f	919	#define LPC_CM3_BASE (0xE0000000UL)
timexton	0:cf2d4c337b6f	920
timexton	0:cf2d4c337b6f	921	/* APB0 peripherals */
timexton	0:cf2d4c337b6f	922	#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
timexton	0:cf2d4c337b6f	923	#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
timexton	0:cf2d4c337b6f	924	#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
timexton	0:cf2d4c337b6f	925	#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
timexton	0:cf2d4c337b6f	926	#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
timexton	0:cf2d4c337b6f	927	#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
timexton	0:cf2d4c337b6f	928	#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
timexton	0:cf2d4c337b6f	929	#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
timexton	0:cf2d4c337b6f	930	#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
timexton	0:cf2d4c337b6f	931	#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
timexton	0:cf2d4c337b6f	932	#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
timexton	0:cf2d4c337b6f	933	#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
timexton	0:cf2d4c337b6f	934	#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
timexton	0:cf2d4c337b6f	935	#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
timexton	0:cf2d4c337b6f	936	#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
timexton	0:cf2d4c337b6f	937	#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
timexton	0:cf2d4c337b6f	938	#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
timexton	0:cf2d4c337b6f	939	#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
timexton	0:cf2d4c337b6f	940	#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
timexton	0:cf2d4c337b6f	941
timexton	0:cf2d4c337b6f	942	/* APB1 peripherals */
timexton	0:cf2d4c337b6f	943	#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
timexton	0:cf2d4c337b6f	944	#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
timexton	0:cf2d4c337b6f	945	#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
timexton	0:cf2d4c337b6f	946	#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
timexton	0:cf2d4c337b6f	947	#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
timexton	0:cf2d4c337b6f	948	#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
timexton	0:cf2d4c337b6f	949	#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
timexton	0:cf2d4c337b6f	950	#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
timexton	0:cf2d4c337b6f	951	#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
timexton	0:cf2d4c337b6f	952	#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
timexton	0:cf2d4c337b6f	953	#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
timexton	0:cf2d4c337b6f	954	#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
timexton	0:cf2d4c337b6f	955
timexton	0:cf2d4c337b6f	956	/* AHB peripherals */
timexton	0:cf2d4c337b6f	957	#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
timexton	0:cf2d4c337b6f	958	#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
timexton	0:cf2d4c337b6f	959	#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
timexton	0:cf2d4c337b6f	960	#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
timexton	0:cf2d4c337b6f	961	#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
timexton	0:cf2d4c337b6f	962	#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
timexton	0:cf2d4c337b6f	963	#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
timexton	0:cf2d4c337b6f	964	#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
timexton	0:cf2d4c337b6f	965	#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
timexton	0:cf2d4c337b6f	966	#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
timexton	0:cf2d4c337b6f	967	#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
timexton	0:cf2d4c337b6f	968
timexton	0:cf2d4c337b6f	969	/* GPIOs */
timexton	0:cf2d4c337b6f	970	#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
timexton	0:cf2d4c337b6f	971	#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
timexton	0:cf2d4c337b6f	972	#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
timexton	0:cf2d4c337b6f	973	#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
timexton	0:cf2d4c337b6f	974	#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
timexton	0:cf2d4c337b6f	975
timexton	0:cf2d4c337b6f	976
timexton	0:cf2d4c337b6f	977	/******************************************************************************/
timexton	0:cf2d4c337b6f	978	/* Peripheral declaration */
timexton	0:cf2d4c337b6f	979	/******************************************************************************/
timexton	0:cf2d4c337b6f	980	#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
timexton	0:cf2d4c337b6f	981	#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
timexton	0:cf2d4c337b6f	982	#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
timexton	0:cf2d4c337b6f	983	#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
timexton	0:cf2d4c337b6f	984	#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
timexton	0:cf2d4c337b6f	985	#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
timexton	0:cf2d4c337b6f	986	#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
timexton	0:cf2d4c337b6f	987	#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
timexton	0:cf2d4c337b6f	988	#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
timexton	0:cf2d4c337b6f	989	#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
timexton	0:cf2d4c337b6f	990	#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
timexton	0:cf2d4c337b6f	991	#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
timexton	0:cf2d4c337b6f	992	#define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
timexton	0:cf2d4c337b6f	993	#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
timexton	0:cf2d4c337b6f	994	#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
timexton	0:cf2d4c337b6f	995	#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
timexton	0:cf2d4c337b6f	996	#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
timexton	0:cf2d4c337b6f	997	#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
timexton	0:cf2d4c337b6f	998	#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
timexton	0:cf2d4c337b6f	999	#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
timexton	0:cf2d4c337b6f	1000	#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
timexton	0:cf2d4c337b6f	1001	#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
timexton	0:cf2d4c337b6f	1002	#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
timexton	0:cf2d4c337b6f	1003	#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
timexton	0:cf2d4c337b6f	1004	#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
timexton	0:cf2d4c337b6f	1005	#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
timexton	0:cf2d4c337b6f	1006	#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
timexton	0:cf2d4c337b6f	1007	#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
timexton	0:cf2d4c337b6f	1008	#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
timexton	0:cf2d4c337b6f	1009	#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
timexton	0:cf2d4c337b6f	1010	#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
timexton	0:cf2d4c337b6f	1011	#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
timexton	0:cf2d4c337b6f	1012	#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
timexton	0:cf2d4c337b6f	1013	#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
timexton	0:cf2d4c337b6f	1014	#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
timexton	0:cf2d4c337b6f	1015	#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
timexton	0:cf2d4c337b6f	1016	#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
timexton	0:cf2d4c337b6f	1017	#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
timexton	0:cf2d4c337b6f	1018	#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
timexton	0:cf2d4c337b6f	1019	#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
timexton	0:cf2d4c337b6f	1020	#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
timexton	0:cf2d4c337b6f	1021	#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
timexton	0:cf2d4c337b6f	1022	#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
timexton	0:cf2d4c337b6f	1023	#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
timexton	0:cf2d4c337b6f	1024	#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
timexton	0:cf2d4c337b6f	1025	#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
timexton	0:cf2d4c337b6f	1026	#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
timexton	0:cf2d4c337b6f	1027
timexton	0:cf2d4c337b6f	1028	#endif // __LPC17xx_H__

Repository toolbox

Export to desktop IDE

Build repository

Repository details

Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	09 Sep 2010
Imports:	30
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	3

LPC17xx.h@0:cf2d4c337b6f, 2010-09-09 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning