tim004 tim004
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LV2_Zadatak2_Tim004
Sumejja Porča Ediba Žugor
main.cpp@1:7663761e3c44, 2014-03-10 (annotated)
- Committer:
- tim004
- Date:
- Mon Mar 10 18:47:21 2014 +0000
- Revision:
- 1:7663761e3c44
- Parent:
- 0:1d6871f4478c
LV2_Zadatak2_Tim004;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
tim004 | 0:1d6871f4478c | 1 | #include "mbed.h" |
tim004 | 0:1d6871f4478c | 2 | BusOut myleds (dp23,dp24,dp25,dp26,dp27,dp5,dp6,dp28); |
tim004 | 0:1d6871f4478c | 3 | DigitalIn t1 (dp1); |
tim004 | 0:1d6871f4478c | 4 | DigitalIn t2(dp2); |
tim004 | 0:1d6871f4478c | 5 | bool t1_pret, t2_pret; |
tim004 | 0:1d6871f4478c | 6 | void povecaj(); |
tim004 | 0:1d6871f4478c | 7 | void smanji(); |
tim004 | 0:1d6871f4478c | 8 | |
tim004 | 0:1d6871f4478c | 9 | DigitalOut enable(dp14); //kom |
tim004 | 0:1d6871f4478c | 10 | int i; |
tim004 | 0:1d6871f4478c | 11 | |
tim004 | 0:1d6871f4478c | 12 | void povecaj() |
tim004 | 0:1d6871f4478c | 13 | { |
tim004 | 1:7663761e3c44 | 14 | i++; |
tim004 | 0:1d6871f4478c | 15 | myleds=i%256; |
tim004 | 1:7663761e3c44 | 16 | |
tim004 | 0:1d6871f4478c | 17 | } |
tim004 | 1:7663761e3c44 | 18 | |
tim004 | 0:1d6871f4478c | 19 | |
tim004 | 0:1d6871f4478c | 20 | void smanji(){ |
tim004 | 1:7663761e3c44 | 21 | i--; |
tim004 | 0:1d6871f4478c | 22 | myleds=i%256; |
tim004 | 1:7663761e3c44 | 23 | |
tim004 | 1:7663761e3c44 | 24 | |
tim004 | 0:1d6871f4478c | 25 | if ( i < 0 ) |
tim004 | 0:1d6871f4478c | 26 | i = 255; |
tim004 | 0:1d6871f4478c | 27 | |
tim004 | 0:1d6871f4478c | 28 | } |
tim004 | 0:1d6871f4478c | 29 | int main() { |
tim004 | 0:1d6871f4478c | 30 | myleds = 0; |
tim004 | 0:1d6871f4478c | 31 | i=0; |
tim004 | 0:1d6871f4478c | 32 | enable=0; |
tim004 | 0:1d6871f4478c | 33 | t1_pret = 0; |
tim004 | 0:1d6871f4478c | 34 | t2_pret = 0; |
tim004 | 0:1d6871f4478c | 35 | while(1) { |
tim004 | 1:7663761e3c44 | 36 | if (t1==1 && t1_pret==0) |
tim004 | 1:7663761e3c44 | 37 | for( int j = 0; j <= 300; j++) |
tim004 | 0:1d6871f4478c | 38 | { |
tim004 | 0:1d6871f4478c | 39 | if(t1 == 0) |
tim004 | 0:1d6871f4478c | 40 | { |
tim004 | 0:1d6871f4478c | 41 | break; |
tim004 | 0:1d6871f4478c | 42 | } |
tim004 | 1:7663761e3c44 | 43 | if ( j == 300) |
tim004 | 0:1d6871f4478c | 44 | { |
tim004 | 0:1d6871f4478c | 45 | t1_pret = 1; |
tim004 | 0:1d6871f4478c | 46 | povecaj(); |
tim004 | 0:1d6871f4478c | 47 | } |
tim004 | 0:1d6871f4478c | 48 | } |
tim004 | 1:7663761e3c44 | 49 | if ( t1 == 0 && t1_pret == 1 ) |
tim004 | 1:7663761e3c44 | 50 | { |
tim004 | 1:7663761e3c44 | 51 | for( int j = 0; j <= 300; j++) |
tim004 | 1:7663761e3c44 | 52 | { if(t1 == 1) |
tim004 | 1:7663761e3c44 | 53 | { |
tim004 | 1:7663761e3c44 | 54 | break; |
tim004 | 1:7663761e3c44 | 55 | } |
tim004 | 1:7663761e3c44 | 56 | if ( j == 300) |
tim004 | 1:7663761e3c44 | 57 | { |
tim004 | 1:7663761e3c44 | 58 | t1_pret = 0; |
tim004 | 1:7663761e3c44 | 59 | |
tim004 | 1:7663761e3c44 | 60 | } |
tim004 | 1:7663761e3c44 | 61 | } |
tim004 | 1:7663761e3c44 | 62 | } |
tim004 | 0:1d6871f4478c | 63 | |
tim004 | 1:7663761e3c44 | 64 | if (t2 == 1 && t2_pret == 0) |
tim004 | 1:7663761e3c44 | 65 | for( int j = 0; j <= 300; j++) |
tim004 | 0:1d6871f4478c | 66 | { |
tim004 | 0:1d6871f4478c | 67 | if(t2 == 0) |
tim004 | 0:1d6871f4478c | 68 | { |
tim004 | 0:1d6871f4478c | 69 | break; |
tim004 | 0:1d6871f4478c | 70 | } |
tim004 | 1:7663761e3c44 | 71 | if ( j == 300) |
tim004 | 0:1d6871f4478c | 72 | { |
tim004 | 0:1d6871f4478c | 73 | t2_pret = 1; |
tim004 | 0:1d6871f4478c | 74 | smanji(); |
tim004 | 0:1d6871f4478c | 75 | } |
tim004 | 0:1d6871f4478c | 76 | } |
tim004 | 1:7663761e3c44 | 77 | if (t2 == 0 && t2_pret == 1) |
tim004 | 1:7663761e3c44 | 78 | for( int j = 0; j <= 300; j++) |
tim004 | 1:7663761e3c44 | 79 | { |
tim004 | 1:7663761e3c44 | 80 | if(t2 == 1) |
tim004 | 1:7663761e3c44 | 81 | { |
tim004 | 1:7663761e3c44 | 82 | break; |
tim004 | 1:7663761e3c44 | 83 | } |
tim004 | 1:7663761e3c44 | 84 | if ( j == 300) |
tim004 | 1:7663761e3c44 | 85 | { |
tim004 | 1:7663761e3c44 | 86 | t2_pret = 0; |
tim004 | 1:7663761e3c44 | 87 | } |
tim004 | 1:7663761e3c44 | 88 | } |
tim004 | 0:1d6871f4478c | 89 | |
tim004 | 0:1d6871f4478c | 90 | } |
tim004 | 0:1d6871f4478c | 91 | } |