Diff: export/iar/iar_definitions.json

Revision:

31:182518299918

diff -r f12ce67666d0 -r 182518299918 export/iar/iar_definitions.json
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/export/iar/iar_definitions.json	Wed Jan 04 11:58:24 2017 -0600
@@ -0,0 +1,161 @@
+{
+    "STM32L476VG": {
+        "OGChipSelectEditMenu": "STM32L476VG\tST STM32L476VG"
+    },
+    "LPC11U24FBD48/401": {
+        "OGChipSelectEditMenu": "LPC11U24FBD64_401\tNXP LPC11U24FBD64_401"
+    },
+    "STM32F334R8": {
+        "OGChipSelectEditMenu": "STM32F334x8\tST STM32F334x8"
+    },
+    "STM32F302R8": {
+        "OGChipSelectEditMenu": "STM32F302x8\tST STM32F302x8"
+    },
+    "EFM32LG990F256": {
+        "OGChipSelectEditMenu": "EFM32LG990F256\tSiliconLaboratories EFM32LG990F256"
+    },
+    "STM32F042K6": {
+        "OGChipSelectEditMenu": "STM32F042x6\tST STM32F042x6"
+    },
+    "STM32L476RG": {
+        "OGChipSelectEditMenu": "STM32L476RG\tST STM32L476RG"
+    },
+    "STM32L011K4": {
+        "OGChipSelectEditMenu": "STM32L011x4\tST STM32L011x4"
+    },
+    "EFM32WG990F256": {
+        "OGChipSelectEditMenu": "EFM32WG990F256\tSiliconLaboratories EFM32WG990F256"
+    },
+    "STM32F401RE": {
+        "OGChipSelectEditMenu": "STM32F401xE\tST STM32F401xE"
+    },
+    "STM32F070RB": {
+        "OGChipSelectEditMenu": "STM32F070RB\tST STM32F070RB"
+    },
+    "MK64FN1M0xxx12": {
+        "OGChipSelectEditMenu": "MK64FN1M0xxx12\tFreescale MK64FN1M0xxx12"
+    },
+    "STM32F072RB": {
+        "OGChipSelectEditMenu": "STM32F072RB\tST STM32F072RB"
+    },
+    "nRF51822_xxAA": {
+        "OGChipSelectEditMenu": "nRF51822-QFAA\tNordicSemi nRF51822-QFAA"
+    },
+    "EFM32GG990F1024": {
+        "OGChipSelectEditMenu": "EFM32GG990F1024\tSiliconLaboratories EFM32GG990F1024"
+    },
+    "MKL46Z256xxx4": {
+        "OGChipSelectEditMenu": "MKL46Z256xxx4\tFreescale MKL46Z256xxx4"
+    },
+    "STM32F030R8": {
+        "OGChipSelectEditMenu": "STM32F030x8\tST STM32F030x8"
+    },
+    "EFM32ZG222F32": {
+        "OGChipSelectEditMenu": "EFM32ZG220F32\tSiliconLaboratories EFM32ZG220F32"
+    },
+    "STM32F303RE": {
+        "OGChipSelectEditMenu": "STM32F303xE\tST STM32F303xE"
+    },
+    "STM32L152RE": {
+        "OGChipSelectEditMenu": "STM32L152xE\tST STM32L152xE"
+    },
+    "STM32F439ZI": {
+        "OGChipSelectEditMenu": "STM32F439ZI\tST STM32F439ZI"
+    },
+    "LPC1768": {
+        "OGChipSelectEditMenu": "LPC1768\tNXP LPC1768"
+    },
+    "STM32F446RE": {
+        "OGChipSelectEditMenu": "STM32F446RE\tST STM32F446RE"
+    },
+    "STM32L073RZ": {
+        "OGChipSelectEditMenu": "STM32L073RZ\tST STM32L073RZ"
+    },
+    "STM32F746ZG": {
+        "OGChipSelectEditMenu": "STM32F746ZG\tST STM32F746ZG",
+        "GBECoreSlave": 41,
+        "CoreVariant": 41,
+        "FPU2": 6,
+        "NrRegs": 1
+    },
+    "MKL43Z256xxx4": {
+        "OGChipSelectEditMenu": "MKL43Z256xxx4\tFreescale MKL43Z256xxx4"
+    },
+    "LPC812M101JDH20": {
+        "OGChipSelectEditMenu": "LPC812M101\tNXP LPC812M101"
+    },
+    "STM32F746NG": {
+        "OGChipSelectEditMenu": "STM32F746NG\tST STM32F746NG",
+        "GBECoreSlave": 41,
+        "CoreVariant": 41,
+        "FPU2": 6,
+        "NrRegs": 1
+    },
+    "STM32F411RE": {
+        "OGChipSelectEditMenu": "STM32F411RE\tST STM32F411RE"
+    },
+    "STM32L053C8": {
+        "OGChipSelectEditMenu": "STM32L053x8\tST STM32L053x8"
+    },
+    "STM32L031K6": {
+        "OGChipSelectEditMenu": "STM32L031x6\tST STM32L031x6"
+    },
+    "EFM32HG322F64": {
+        "OGChipSelectEditMenu": "EFM32HG322F64\tSiliconLaboratories EFM32HG322F64"
+    },
+    "MK20DX256xxx7": {
+        "OGChipSelectEditMenu": "MK20DX256xxx7\tFreescale MK20DX256xxx7"
+    },
+    "STM32F446ZE": {
+        "OGChipSelectEditMenu": "STM32F446ZE\tST STM32F446ZE"
+    },
+    "MK22DN512xxx5": {
+        "OGChipSelectEditMenu": "MK22FN512xxx12\tFreescale MK22FN512xxx12"
+    },
+    "STM32F303K8": {
+        "OGChipSelectEditMenu": "STM32F303x8\tST STM32F303x8"
+    },
+    "STM32F405RG": {
+        "OGChipSelectEditMenu": "STM32F405RG\tST STM32F405RG"
+    },
+    "MK20DX128xxx5": {
+        "OGChipSelectEditMenu": "MK20DX128xxx5\tFreescale MK20DX128xxx5"
+    },
+    "MKL25Z128xxx4": {
+        "OGChipSelectEditMenu": "MKL25Z128xxx4\tFreescale MKL25Z128xxx4"
+    },
+    "STM32F429ZI": {
+        "OGChipSelectEditMenu": "STM32F429ZI\tST STM32F429ZI"
+    },
+    "STM32F103RB": {
+        "OGChipSelectEditMenu": "STM32F103xB\tST STM32F103xB"
+    },
+    "STM32F091RC": {
+        "OGChipSelectEditMenu": "STM32F091RC\tST STM32F091RC"
+    },
+    "r7s721001": {
+        "OGChipSelectEditMenu": "R7S721001\tRenesas R7S721001",
+        "CoreVariant": 37,
+        "GFPUCoreSlave": 37,
+        "GBECoreSlave": 37,
+        "NEON":1
+    },
+    "MKL05Z32xxx4": {
+        "OGChipSelectEditMenu": "MKL05Z32xxx4\tFreescale MKL05Z32xxx4"
+    },
+    "STM32F031K6": {
+        "OGChipSelectEditMenu": "STM32F031x6\tST STM32F031x6"
+    },
+    "max326000x85": {
+        "OGChipSelectEditMenu": "MAX32600x85\tMaxim MAX32600x85"
+    },
+    "STM32F407VG": {
+        "OGChipSelectEditMenu": "STM32F407VG\tST STM32F407VG"
+    },
+    "nRF52832_xxAA":{
+        "OGChipSelectEditMenu": "nRF52832-xxAA\tNordicSemi nRF52832-xxAA"
+    },
+    "NCS36510":{
+        "OGChipSelectEditMenu": "NCS36510\tONSemiconductor NCS36510"
+    }
+}