bugfixes and reduced version for disco board only
Dependents: Scope DISCO-F746NG_Sinewave DISCO-F746NG_Sweep DISCO-F746NG_Oscilloscope ... more
Fork of BSP_DISCO_F746NG_patch by
stm32746g_discovery_qspi.c@1:e8fac4061a5b, 2015-11-02 (annotated)
- Committer:
- NirT
- Date:
- Mon Nov 02 23:35:17 2015 +0000
- Revision:
- 1:e8fac4061a5b
Error: Incomplete type is not allowed in "patch/LwIP/src/include/lwip/dhcp.h", Line: 83, Col: 4; ; and more like this.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
NirT | 1:e8fac4061a5b | 1 | /** |
NirT | 1:e8fac4061a5b | 2 | ****************************************************************************** |
NirT | 1:e8fac4061a5b | 3 | * @file stm32746g_discovery_qspi.c |
NirT | 1:e8fac4061a5b | 4 | * @author MCD Application Team |
NirT | 1:e8fac4061a5b | 5 | * @version V1.0.0 |
NirT | 1:e8fac4061a5b | 6 | * @date 25-June-2015 |
NirT | 1:e8fac4061a5b | 7 | * @brief This file includes a standard driver for the N25Q128A QSPI |
NirT | 1:e8fac4061a5b | 8 | * memory mounted on STM32746G-Discovery board. |
NirT | 1:e8fac4061a5b | 9 | @verbatim |
NirT | 1:e8fac4061a5b | 10 | ============================================================================== |
NirT | 1:e8fac4061a5b | 11 | ##### How to use this driver ##### |
NirT | 1:e8fac4061a5b | 12 | ============================================================================== |
NirT | 1:e8fac4061a5b | 13 | [..] |
NirT | 1:e8fac4061a5b | 14 | (#) This driver is used to drive the N25Q128A QSPI external |
NirT | 1:e8fac4061a5b | 15 | memory mounted on STM32746G-Discovery board. |
NirT | 1:e8fac4061a5b | 16 | |
NirT | 1:e8fac4061a5b | 17 | (#) This driver need a specific component driver (N25Q128A) to be included with. |
NirT | 1:e8fac4061a5b | 18 | |
NirT | 1:e8fac4061a5b | 19 | (#) Initialization steps: |
NirT | 1:e8fac4061a5b | 20 | (++) Initialize the QPSI external memory using the BSP_QSPI_Init() function. This |
NirT | 1:e8fac4061a5b | 21 | function includes the MSP layer hardware resources initialization and the |
NirT | 1:e8fac4061a5b | 22 | QSPI interface with the external memory. |
NirT | 1:e8fac4061a5b | 23 | |
NirT | 1:e8fac4061a5b | 24 | (#) QSPI memory operations |
NirT | 1:e8fac4061a5b | 25 | (++) QSPI memory can be accessed with read/write operations once it is |
NirT | 1:e8fac4061a5b | 26 | initialized. |
NirT | 1:e8fac4061a5b | 27 | Read/write operation can be performed with AHB access using the functions |
NirT | 1:e8fac4061a5b | 28 | BSP_QSPI_Read()/BSP_QSPI_Write(). |
NirT | 1:e8fac4061a5b | 29 | (++) The function BSP_QSPI_GetInfo() returns the configuration of the QSPI memory. |
NirT | 1:e8fac4061a5b | 30 | (see the QSPI memory data sheet) |
NirT | 1:e8fac4061a5b | 31 | (++) Perform erase block operation using the function BSP_QSPI_Erase_Block() and by |
NirT | 1:e8fac4061a5b | 32 | specifying the block address. You can perform an erase operation of the whole |
NirT | 1:e8fac4061a5b | 33 | chip by calling the function BSP_QSPI_Erase_Chip(). |
NirT | 1:e8fac4061a5b | 34 | (++) The function BSP_QSPI_GetStatus() returns the current status of the QSPI memory. |
NirT | 1:e8fac4061a5b | 35 | (see the QSPI memory data sheet) |
NirT | 1:e8fac4061a5b | 36 | @endverbatim |
NirT | 1:e8fac4061a5b | 37 | ****************************************************************************** |
NirT | 1:e8fac4061a5b | 38 | * @attention |
NirT | 1:e8fac4061a5b | 39 | * |
NirT | 1:e8fac4061a5b | 40 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
NirT | 1:e8fac4061a5b | 41 | * |
NirT | 1:e8fac4061a5b | 42 | * Redistribution and use in source and binary forms, with or without modification, |
NirT | 1:e8fac4061a5b | 43 | * are permitted provided that the following conditions are met: |
NirT | 1:e8fac4061a5b | 44 | * 1. Redistributions of source code must retain the above copyright notice, |
NirT | 1:e8fac4061a5b | 45 | * this list of conditions and the following disclaimer. |
NirT | 1:e8fac4061a5b | 46 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
NirT | 1:e8fac4061a5b | 47 | * this list of conditions and the following disclaimer in the documentation |
NirT | 1:e8fac4061a5b | 48 | * and/or other materials provided with the distribution. |
NirT | 1:e8fac4061a5b | 49 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
NirT | 1:e8fac4061a5b | 50 | * may be used to endorse or promote products derived from this software |
NirT | 1:e8fac4061a5b | 51 | * without specific prior written permission. |
NirT | 1:e8fac4061a5b | 52 | * |
NirT | 1:e8fac4061a5b | 53 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
NirT | 1:e8fac4061a5b | 54 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
NirT | 1:e8fac4061a5b | 55 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
NirT | 1:e8fac4061a5b | 56 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
NirT | 1:e8fac4061a5b | 57 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
NirT | 1:e8fac4061a5b | 58 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
NirT | 1:e8fac4061a5b | 59 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
NirT | 1:e8fac4061a5b | 60 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
NirT | 1:e8fac4061a5b | 61 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
NirT | 1:e8fac4061a5b | 62 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
NirT | 1:e8fac4061a5b | 63 | * |
NirT | 1:e8fac4061a5b | 64 | ****************************************************************************** |
NirT | 1:e8fac4061a5b | 65 | */ |
NirT | 1:e8fac4061a5b | 66 | |
NirT | 1:e8fac4061a5b | 67 | /* Includes ------------------------------------------------------------------*/ |
NirT | 1:e8fac4061a5b | 68 | #include "stm32746g_discovery_qspi.h" |
NirT | 1:e8fac4061a5b | 69 | |
NirT | 1:e8fac4061a5b | 70 | /** @addtogroup BSP |
NirT | 1:e8fac4061a5b | 71 | * @{ |
NirT | 1:e8fac4061a5b | 72 | */ |
NirT | 1:e8fac4061a5b | 73 | |
NirT | 1:e8fac4061a5b | 74 | /** @addtogroup STM32746G_DISCOVERY |
NirT | 1:e8fac4061a5b | 75 | * @{ |
NirT | 1:e8fac4061a5b | 76 | */ |
NirT | 1:e8fac4061a5b | 77 | |
NirT | 1:e8fac4061a5b | 78 | /** @defgroup STM32746G_DISCOVERY_QSPI STM32746G-Discovery QSPI |
NirT | 1:e8fac4061a5b | 79 | * @{ |
NirT | 1:e8fac4061a5b | 80 | */ |
NirT | 1:e8fac4061a5b | 81 | |
NirT | 1:e8fac4061a5b | 82 | |
NirT | 1:e8fac4061a5b | 83 | /* Private variables ---------------------------------------------------------*/ |
NirT | 1:e8fac4061a5b | 84 | |
NirT | 1:e8fac4061a5b | 85 | /** @defgroup STM32746G_DISCOVERY_QSPI_Private_Variables STM32746G_DISCOVERY QSPI Private Variables |
NirT | 1:e8fac4061a5b | 86 | * @{ |
NirT | 1:e8fac4061a5b | 87 | */ |
NirT | 1:e8fac4061a5b | 88 | QSPI_HandleTypeDef QSPIHandle; |
NirT | 1:e8fac4061a5b | 89 | |
NirT | 1:e8fac4061a5b | 90 | /** |
NirT | 1:e8fac4061a5b | 91 | * @} |
NirT | 1:e8fac4061a5b | 92 | */ |
NirT | 1:e8fac4061a5b | 93 | |
NirT | 1:e8fac4061a5b | 94 | |
NirT | 1:e8fac4061a5b | 95 | |
NirT | 1:e8fac4061a5b | 96 | /* Private functions ---------------------------------------------------------*/ |
NirT | 1:e8fac4061a5b | 97 | |
NirT | 1:e8fac4061a5b | 98 | /** @defgroup STM32746G_DISCOVERY_QSPI_Private_Functions STM32746G_DISCOVERY QSPI Private Functions |
NirT | 1:e8fac4061a5b | 99 | * @{ |
NirT | 1:e8fac4061a5b | 100 | */ |
NirT | 1:e8fac4061a5b | 101 | static uint8_t QSPI_ResetMemory (QSPI_HandleTypeDef *hqspi); |
NirT | 1:e8fac4061a5b | 102 | static uint8_t QSPI_DummyCyclesCfg (QSPI_HandleTypeDef *hqspi); |
NirT | 1:e8fac4061a5b | 103 | static uint8_t QSPI_WriteEnable (QSPI_HandleTypeDef *hqspi); |
NirT | 1:e8fac4061a5b | 104 | static uint8_t QSPI_AutoPollingMemReady (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); |
NirT | 1:e8fac4061a5b | 105 | |
NirT | 1:e8fac4061a5b | 106 | /** |
NirT | 1:e8fac4061a5b | 107 | * @} |
NirT | 1:e8fac4061a5b | 108 | */ |
NirT | 1:e8fac4061a5b | 109 | |
NirT | 1:e8fac4061a5b | 110 | /** @defgroup STM32746G_DISCOVERY_QSPI_Exported_Functions STM32746G_DISCOVERY QSPI Exported Functions |
NirT | 1:e8fac4061a5b | 111 | * @{ |
NirT | 1:e8fac4061a5b | 112 | */ |
NirT | 1:e8fac4061a5b | 113 | |
NirT | 1:e8fac4061a5b | 114 | /** |
NirT | 1:e8fac4061a5b | 115 | * @brief Initializes the QSPI interface. |
NirT | 1:e8fac4061a5b | 116 | * @retval QSPI memory status |
NirT | 1:e8fac4061a5b | 117 | */ |
NirT | 1:e8fac4061a5b | 118 | uint8_t BSP_QSPI_Init(void) |
NirT | 1:e8fac4061a5b | 119 | { |
NirT | 1:e8fac4061a5b | 120 | QSPIHandle.Instance = QUADSPI; |
NirT | 1:e8fac4061a5b | 121 | |
NirT | 1:e8fac4061a5b | 122 | /* Call the DeInit function to reset the driver */ |
NirT | 1:e8fac4061a5b | 123 | if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK) |
NirT | 1:e8fac4061a5b | 124 | { |
NirT | 1:e8fac4061a5b | 125 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 126 | } |
NirT | 1:e8fac4061a5b | 127 | |
NirT | 1:e8fac4061a5b | 128 | /* System level initialization */ |
NirT | 1:e8fac4061a5b | 129 | BSP_QSPI_MspInit(&QSPIHandle, NULL); |
NirT | 1:e8fac4061a5b | 130 | |
NirT | 1:e8fac4061a5b | 131 | /* QSPI initialization */ |
NirT | 1:e8fac4061a5b | 132 | QSPIHandle.Init.ClockPrescaler = 1; /* QSPI freq = 216 MHz/(1+1) = 108 Mhz */ |
NirT | 1:e8fac4061a5b | 133 | QSPIHandle.Init.FifoThreshold = 4; |
NirT | 1:e8fac4061a5b | 134 | QSPIHandle.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE; |
NirT | 1:e8fac4061a5b | 135 | QSPIHandle.Init.FlashSize = POSITION_VAL(N25Q128A_FLASH_SIZE) - 1; |
NirT | 1:e8fac4061a5b | 136 | QSPIHandle.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_2_CYCLE; |
NirT | 1:e8fac4061a5b | 137 | QSPIHandle.Init.ClockMode = QSPI_CLOCK_MODE_0; |
NirT | 1:e8fac4061a5b | 138 | QSPIHandle.Init.FlashID = QSPI_FLASH_ID_1; |
NirT | 1:e8fac4061a5b | 139 | QSPIHandle.Init.DualFlash = QSPI_DUALFLASH_DISABLE; |
NirT | 1:e8fac4061a5b | 140 | |
NirT | 1:e8fac4061a5b | 141 | if (HAL_QSPI_Init(&QSPIHandle) != HAL_OK) |
NirT | 1:e8fac4061a5b | 142 | { |
NirT | 1:e8fac4061a5b | 143 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 144 | } |
NirT | 1:e8fac4061a5b | 145 | |
NirT | 1:e8fac4061a5b | 146 | /* QSPI memory reset */ |
NirT | 1:e8fac4061a5b | 147 | if (QSPI_ResetMemory(&QSPIHandle) != QSPI_OK) |
NirT | 1:e8fac4061a5b | 148 | { |
NirT | 1:e8fac4061a5b | 149 | return QSPI_NOT_SUPPORTED; |
NirT | 1:e8fac4061a5b | 150 | } |
NirT | 1:e8fac4061a5b | 151 | |
NirT | 1:e8fac4061a5b | 152 | /* Configuration of the dummy cycles on QSPI memory side */ |
NirT | 1:e8fac4061a5b | 153 | if (QSPI_DummyCyclesCfg(&QSPIHandle) != QSPI_OK) |
NirT | 1:e8fac4061a5b | 154 | { |
NirT | 1:e8fac4061a5b | 155 | return QSPI_NOT_SUPPORTED; |
NirT | 1:e8fac4061a5b | 156 | } |
NirT | 1:e8fac4061a5b | 157 | |
NirT | 1:e8fac4061a5b | 158 | return QSPI_OK; |
NirT | 1:e8fac4061a5b | 159 | } |
NirT | 1:e8fac4061a5b | 160 | |
NirT | 1:e8fac4061a5b | 161 | /** |
NirT | 1:e8fac4061a5b | 162 | * @brief De-Initializes the QSPI interface. |
NirT | 1:e8fac4061a5b | 163 | * @retval QSPI memory status |
NirT | 1:e8fac4061a5b | 164 | */ |
NirT | 1:e8fac4061a5b | 165 | uint8_t BSP_QSPI_DeInit(void) |
NirT | 1:e8fac4061a5b | 166 | { |
NirT | 1:e8fac4061a5b | 167 | QSPIHandle.Instance = QUADSPI; |
NirT | 1:e8fac4061a5b | 168 | |
NirT | 1:e8fac4061a5b | 169 | /* Call the DeInit function to reset the driver */ |
NirT | 1:e8fac4061a5b | 170 | if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK) |
NirT | 1:e8fac4061a5b | 171 | { |
NirT | 1:e8fac4061a5b | 172 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 173 | } |
NirT | 1:e8fac4061a5b | 174 | |
NirT | 1:e8fac4061a5b | 175 | /* System level De-initialization */ |
NirT | 1:e8fac4061a5b | 176 | BSP_QSPI_MspDeInit(&QSPIHandle, NULL); |
NirT | 1:e8fac4061a5b | 177 | |
NirT | 1:e8fac4061a5b | 178 | return QSPI_OK; |
NirT | 1:e8fac4061a5b | 179 | } |
NirT | 1:e8fac4061a5b | 180 | |
NirT | 1:e8fac4061a5b | 181 | /** |
NirT | 1:e8fac4061a5b | 182 | * @brief Reads an amount of data from the QSPI memory. |
NirT | 1:e8fac4061a5b | 183 | * @param pData: Pointer to data to be read |
NirT | 1:e8fac4061a5b | 184 | * @param ReadAddr: Read start address |
NirT | 1:e8fac4061a5b | 185 | * @param Size: Size of data to read |
NirT | 1:e8fac4061a5b | 186 | * @retval QSPI memory status |
NirT | 1:e8fac4061a5b | 187 | */ |
NirT | 1:e8fac4061a5b | 188 | uint8_t BSP_QSPI_Read(uint8_t* pData, uint32_t ReadAddr, uint32_t Size) |
NirT | 1:e8fac4061a5b | 189 | { |
NirT | 1:e8fac4061a5b | 190 | QSPI_CommandTypeDef s_command; |
NirT | 1:e8fac4061a5b | 191 | |
NirT | 1:e8fac4061a5b | 192 | /* Initialize the read command */ |
NirT | 1:e8fac4061a5b | 193 | s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
NirT | 1:e8fac4061a5b | 194 | s_command.Instruction = QUAD_INOUT_FAST_READ_CMD; |
NirT | 1:e8fac4061a5b | 195 | s_command.AddressMode = QSPI_ADDRESS_4_LINES; |
NirT | 1:e8fac4061a5b | 196 | s_command.AddressSize = QSPI_ADDRESS_24_BITS; |
NirT | 1:e8fac4061a5b | 197 | s_command.Address = ReadAddr; |
NirT | 1:e8fac4061a5b | 198 | s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
NirT | 1:e8fac4061a5b | 199 | s_command.DataMode = QSPI_DATA_4_LINES; |
NirT | 1:e8fac4061a5b | 200 | s_command.DummyCycles = N25Q128A_DUMMY_CYCLES_READ_QUAD; |
NirT | 1:e8fac4061a5b | 201 | s_command.NbData = Size; |
NirT | 1:e8fac4061a5b | 202 | s_command.DdrMode = QSPI_DDR_MODE_DISABLE; |
NirT | 1:e8fac4061a5b | 203 | s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
NirT | 1:e8fac4061a5b | 204 | s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
NirT | 1:e8fac4061a5b | 205 | |
NirT | 1:e8fac4061a5b | 206 | /* Configure the command */ |
NirT | 1:e8fac4061a5b | 207 | if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
NirT | 1:e8fac4061a5b | 208 | { |
NirT | 1:e8fac4061a5b | 209 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 210 | } |
NirT | 1:e8fac4061a5b | 211 | |
NirT | 1:e8fac4061a5b | 212 | /* Reception of the data */ |
NirT | 1:e8fac4061a5b | 213 | if (HAL_QSPI_Receive(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
NirT | 1:e8fac4061a5b | 214 | { |
NirT | 1:e8fac4061a5b | 215 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 216 | } |
NirT | 1:e8fac4061a5b | 217 | |
NirT | 1:e8fac4061a5b | 218 | return QSPI_OK; |
NirT | 1:e8fac4061a5b | 219 | } |
NirT | 1:e8fac4061a5b | 220 | |
NirT | 1:e8fac4061a5b | 221 | /** |
NirT | 1:e8fac4061a5b | 222 | * @brief Writes an amount of data to the QSPI memory. |
NirT | 1:e8fac4061a5b | 223 | * @param pData: Pointer to data to be written |
NirT | 1:e8fac4061a5b | 224 | * @param WriteAddr: Write start address |
NirT | 1:e8fac4061a5b | 225 | * @param Size: Size of data to write |
NirT | 1:e8fac4061a5b | 226 | * @retval QSPI memory status |
NirT | 1:e8fac4061a5b | 227 | */ |
NirT | 1:e8fac4061a5b | 228 | uint8_t BSP_QSPI_Write(uint8_t* pData, uint32_t WriteAddr, uint32_t Size) |
NirT | 1:e8fac4061a5b | 229 | { |
NirT | 1:e8fac4061a5b | 230 | QSPI_CommandTypeDef s_command; |
NirT | 1:e8fac4061a5b | 231 | uint32_t end_addr, current_size, current_addr; |
NirT | 1:e8fac4061a5b | 232 | |
NirT | 1:e8fac4061a5b | 233 | /* Calculation of the size between the write address and the end of the page */ |
NirT | 1:e8fac4061a5b | 234 | current_addr = 0; |
NirT | 1:e8fac4061a5b | 235 | |
NirT | 1:e8fac4061a5b | 236 | while (current_addr <= WriteAddr) |
NirT | 1:e8fac4061a5b | 237 | { |
NirT | 1:e8fac4061a5b | 238 | current_addr += N25Q128A_PAGE_SIZE; |
NirT | 1:e8fac4061a5b | 239 | } |
NirT | 1:e8fac4061a5b | 240 | current_size = current_addr - WriteAddr; |
NirT | 1:e8fac4061a5b | 241 | |
NirT | 1:e8fac4061a5b | 242 | /* Check if the size of the data is less than the remaining place in the page */ |
NirT | 1:e8fac4061a5b | 243 | if (current_size > Size) |
NirT | 1:e8fac4061a5b | 244 | { |
NirT | 1:e8fac4061a5b | 245 | current_size = Size; |
NirT | 1:e8fac4061a5b | 246 | } |
NirT | 1:e8fac4061a5b | 247 | |
NirT | 1:e8fac4061a5b | 248 | /* Initialize the adress variables */ |
NirT | 1:e8fac4061a5b | 249 | current_addr = WriteAddr; |
NirT | 1:e8fac4061a5b | 250 | end_addr = WriteAddr + Size; |
NirT | 1:e8fac4061a5b | 251 | |
NirT | 1:e8fac4061a5b | 252 | /* Initialize the program command */ |
NirT | 1:e8fac4061a5b | 253 | s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
NirT | 1:e8fac4061a5b | 254 | s_command.Instruction = EXT_QUAD_IN_FAST_PROG_CMD; |
NirT | 1:e8fac4061a5b | 255 | s_command.AddressMode = QSPI_ADDRESS_4_LINES; |
NirT | 1:e8fac4061a5b | 256 | s_command.AddressSize = QSPI_ADDRESS_24_BITS; |
NirT | 1:e8fac4061a5b | 257 | s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
NirT | 1:e8fac4061a5b | 258 | s_command.DataMode = QSPI_DATA_4_LINES; |
NirT | 1:e8fac4061a5b | 259 | s_command.DummyCycles = 0; |
NirT | 1:e8fac4061a5b | 260 | s_command.DdrMode = QSPI_DDR_MODE_DISABLE; |
NirT | 1:e8fac4061a5b | 261 | s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
NirT | 1:e8fac4061a5b | 262 | s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
NirT | 1:e8fac4061a5b | 263 | |
NirT | 1:e8fac4061a5b | 264 | /* Perform the write page by page */ |
NirT | 1:e8fac4061a5b | 265 | do |
NirT | 1:e8fac4061a5b | 266 | { |
NirT | 1:e8fac4061a5b | 267 | s_command.Address = current_addr; |
NirT | 1:e8fac4061a5b | 268 | s_command.NbData = current_size; |
NirT | 1:e8fac4061a5b | 269 | |
NirT | 1:e8fac4061a5b | 270 | /* Enable write operations */ |
NirT | 1:e8fac4061a5b | 271 | if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK) |
NirT | 1:e8fac4061a5b | 272 | { |
NirT | 1:e8fac4061a5b | 273 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 274 | } |
NirT | 1:e8fac4061a5b | 275 | |
NirT | 1:e8fac4061a5b | 276 | /* Configure the command */ |
NirT | 1:e8fac4061a5b | 277 | if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
NirT | 1:e8fac4061a5b | 278 | { |
NirT | 1:e8fac4061a5b | 279 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 280 | } |
NirT | 1:e8fac4061a5b | 281 | |
NirT | 1:e8fac4061a5b | 282 | /* Transmission of the data */ |
NirT | 1:e8fac4061a5b | 283 | if (HAL_QSPI_Transmit(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
NirT | 1:e8fac4061a5b | 284 | { |
NirT | 1:e8fac4061a5b | 285 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 286 | } |
NirT | 1:e8fac4061a5b | 287 | |
NirT | 1:e8fac4061a5b | 288 | /* Configure automatic polling mode to wait for end of program */ |
NirT | 1:e8fac4061a5b | 289 | if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK) |
NirT | 1:e8fac4061a5b | 290 | { |
NirT | 1:e8fac4061a5b | 291 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 292 | } |
NirT | 1:e8fac4061a5b | 293 | |
NirT | 1:e8fac4061a5b | 294 | /* Update the address and size variables for next page programming */ |
NirT | 1:e8fac4061a5b | 295 | current_addr += current_size; |
NirT | 1:e8fac4061a5b | 296 | pData += current_size; |
NirT | 1:e8fac4061a5b | 297 | current_size = ((current_addr + N25Q128A_PAGE_SIZE) > end_addr) ? (end_addr - current_addr) : N25Q128A_PAGE_SIZE; |
NirT | 1:e8fac4061a5b | 298 | } while (current_addr < end_addr); |
NirT | 1:e8fac4061a5b | 299 | |
NirT | 1:e8fac4061a5b | 300 | return QSPI_OK; |
NirT | 1:e8fac4061a5b | 301 | } |
NirT | 1:e8fac4061a5b | 302 | |
NirT | 1:e8fac4061a5b | 303 | /** |
NirT | 1:e8fac4061a5b | 304 | * @brief Erases the specified block of the QSPI memory. |
NirT | 1:e8fac4061a5b | 305 | * @param BlockAddress: Block address to erase |
NirT | 1:e8fac4061a5b | 306 | * @retval QSPI memory status |
NirT | 1:e8fac4061a5b | 307 | */ |
NirT | 1:e8fac4061a5b | 308 | uint8_t BSP_QSPI_Erase_Block(uint32_t BlockAddress) |
NirT | 1:e8fac4061a5b | 309 | { |
NirT | 1:e8fac4061a5b | 310 | QSPI_CommandTypeDef s_command; |
NirT | 1:e8fac4061a5b | 311 | |
NirT | 1:e8fac4061a5b | 312 | /* Initialize the erase command */ |
NirT | 1:e8fac4061a5b | 313 | s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
NirT | 1:e8fac4061a5b | 314 | s_command.Instruction = SUBSECTOR_ERASE_CMD; |
NirT | 1:e8fac4061a5b | 315 | s_command.AddressMode = QSPI_ADDRESS_1_LINE; |
NirT | 1:e8fac4061a5b | 316 | s_command.AddressSize = QSPI_ADDRESS_24_BITS; |
NirT | 1:e8fac4061a5b | 317 | s_command.Address = BlockAddress; |
NirT | 1:e8fac4061a5b | 318 | s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
NirT | 1:e8fac4061a5b | 319 | s_command.DataMode = QSPI_DATA_NONE; |
NirT | 1:e8fac4061a5b | 320 | s_command.DummyCycles = 0; |
NirT | 1:e8fac4061a5b | 321 | s_command.DdrMode = QSPI_DDR_MODE_DISABLE; |
NirT | 1:e8fac4061a5b | 322 | s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
NirT | 1:e8fac4061a5b | 323 | s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
NirT | 1:e8fac4061a5b | 324 | |
NirT | 1:e8fac4061a5b | 325 | /* Enable write operations */ |
NirT | 1:e8fac4061a5b | 326 | if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK) |
NirT | 1:e8fac4061a5b | 327 | { |
NirT | 1:e8fac4061a5b | 328 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 329 | } |
NirT | 1:e8fac4061a5b | 330 | |
NirT | 1:e8fac4061a5b | 331 | /* Send the command */ |
NirT | 1:e8fac4061a5b | 332 | if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
NirT | 1:e8fac4061a5b | 333 | { |
NirT | 1:e8fac4061a5b | 334 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 335 | } |
NirT | 1:e8fac4061a5b | 336 | |
NirT | 1:e8fac4061a5b | 337 | /* Configure automatic polling mode to wait for end of erase */ |
NirT | 1:e8fac4061a5b | 338 | if (QSPI_AutoPollingMemReady(&QSPIHandle, N25Q128A_SUBSECTOR_ERASE_MAX_TIME) != QSPI_OK) |
NirT | 1:e8fac4061a5b | 339 | { |
NirT | 1:e8fac4061a5b | 340 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 341 | } |
NirT | 1:e8fac4061a5b | 342 | |
NirT | 1:e8fac4061a5b | 343 | return QSPI_OK; |
NirT | 1:e8fac4061a5b | 344 | } |
NirT | 1:e8fac4061a5b | 345 | |
NirT | 1:e8fac4061a5b | 346 | /** |
NirT | 1:e8fac4061a5b | 347 | * @brief Erases the entire QSPI memory. |
NirT | 1:e8fac4061a5b | 348 | * @retval QSPI memory status |
NirT | 1:e8fac4061a5b | 349 | */ |
NirT | 1:e8fac4061a5b | 350 | uint8_t BSP_QSPI_Erase_Chip(void) |
NirT | 1:e8fac4061a5b | 351 | { |
NirT | 1:e8fac4061a5b | 352 | QSPI_CommandTypeDef s_command; |
NirT | 1:e8fac4061a5b | 353 | |
NirT | 1:e8fac4061a5b | 354 | /* Initialize the erase command */ |
NirT | 1:e8fac4061a5b | 355 | s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
NirT | 1:e8fac4061a5b | 356 | s_command.Instruction = BULK_ERASE_CMD; |
NirT | 1:e8fac4061a5b | 357 | s_command.AddressMode = QSPI_ADDRESS_NONE; |
NirT | 1:e8fac4061a5b | 358 | s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
NirT | 1:e8fac4061a5b | 359 | s_command.DataMode = QSPI_DATA_NONE; |
NirT | 1:e8fac4061a5b | 360 | s_command.DummyCycles = 0; |
NirT | 1:e8fac4061a5b | 361 | s_command.DdrMode = QSPI_DDR_MODE_DISABLE; |
NirT | 1:e8fac4061a5b | 362 | s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
NirT | 1:e8fac4061a5b | 363 | s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
NirT | 1:e8fac4061a5b | 364 | |
NirT | 1:e8fac4061a5b | 365 | /* Enable write operations */ |
NirT | 1:e8fac4061a5b | 366 | if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK) |
NirT | 1:e8fac4061a5b | 367 | { |
NirT | 1:e8fac4061a5b | 368 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 369 | } |
NirT | 1:e8fac4061a5b | 370 | |
NirT | 1:e8fac4061a5b | 371 | /* Send the command */ |
NirT | 1:e8fac4061a5b | 372 | if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
NirT | 1:e8fac4061a5b | 373 | { |
NirT | 1:e8fac4061a5b | 374 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 375 | } |
NirT | 1:e8fac4061a5b | 376 | |
NirT | 1:e8fac4061a5b | 377 | /* Configure automatic polling mode to wait for end of erase */ |
NirT | 1:e8fac4061a5b | 378 | if (QSPI_AutoPollingMemReady(&QSPIHandle, N25Q128A_BULK_ERASE_MAX_TIME) != QSPI_OK) |
NirT | 1:e8fac4061a5b | 379 | { |
NirT | 1:e8fac4061a5b | 380 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 381 | } |
NirT | 1:e8fac4061a5b | 382 | |
NirT | 1:e8fac4061a5b | 383 | return QSPI_OK; |
NirT | 1:e8fac4061a5b | 384 | } |
NirT | 1:e8fac4061a5b | 385 | |
NirT | 1:e8fac4061a5b | 386 | /** |
NirT | 1:e8fac4061a5b | 387 | * @brief Reads current status of the QSPI memory. |
NirT | 1:e8fac4061a5b | 388 | * @retval QSPI memory status |
NirT | 1:e8fac4061a5b | 389 | */ |
NirT | 1:e8fac4061a5b | 390 | uint8_t BSP_QSPI_GetStatus(void) |
NirT | 1:e8fac4061a5b | 391 | { |
NirT | 1:e8fac4061a5b | 392 | QSPI_CommandTypeDef s_command; |
NirT | 1:e8fac4061a5b | 393 | uint8_t reg; |
NirT | 1:e8fac4061a5b | 394 | |
NirT | 1:e8fac4061a5b | 395 | /* Initialize the read flag status register command */ |
NirT | 1:e8fac4061a5b | 396 | s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
NirT | 1:e8fac4061a5b | 397 | s_command.Instruction = READ_FLAG_STATUS_REG_CMD; |
NirT | 1:e8fac4061a5b | 398 | s_command.AddressMode = QSPI_ADDRESS_NONE; |
NirT | 1:e8fac4061a5b | 399 | s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
NirT | 1:e8fac4061a5b | 400 | s_command.DataMode = QSPI_DATA_1_LINE; |
NirT | 1:e8fac4061a5b | 401 | s_command.DummyCycles = 0; |
NirT | 1:e8fac4061a5b | 402 | s_command.NbData = 1; |
NirT | 1:e8fac4061a5b | 403 | s_command.DdrMode = QSPI_DDR_MODE_DISABLE; |
NirT | 1:e8fac4061a5b | 404 | s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
NirT | 1:e8fac4061a5b | 405 | s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
NirT | 1:e8fac4061a5b | 406 | |
NirT | 1:e8fac4061a5b | 407 | /* Configure the command */ |
NirT | 1:e8fac4061a5b | 408 | if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
NirT | 1:e8fac4061a5b | 409 | { |
NirT | 1:e8fac4061a5b | 410 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 411 | } |
NirT | 1:e8fac4061a5b | 412 | |
NirT | 1:e8fac4061a5b | 413 | /* Reception of the data */ |
NirT | 1:e8fac4061a5b | 414 | if (HAL_QSPI_Receive(&QSPIHandle, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
NirT | 1:e8fac4061a5b | 415 | { |
NirT | 1:e8fac4061a5b | 416 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 417 | } |
NirT | 1:e8fac4061a5b | 418 | |
NirT | 1:e8fac4061a5b | 419 | /* Check the value of the register */ |
NirT | 1:e8fac4061a5b | 420 | if ((reg & (N25Q128A_FSR_PRERR | N25Q128A_FSR_VPPERR | N25Q128A_FSR_PGERR | N25Q128A_FSR_ERERR)) != 0) |
NirT | 1:e8fac4061a5b | 421 | { |
NirT | 1:e8fac4061a5b | 422 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 423 | } |
NirT | 1:e8fac4061a5b | 424 | else if ((reg & (N25Q128A_FSR_PGSUS | N25Q128A_FSR_ERSUS)) != 0) |
NirT | 1:e8fac4061a5b | 425 | { |
NirT | 1:e8fac4061a5b | 426 | return QSPI_SUSPENDED; |
NirT | 1:e8fac4061a5b | 427 | } |
NirT | 1:e8fac4061a5b | 428 | else if ((reg & N25Q128A_FSR_READY) != 0) |
NirT | 1:e8fac4061a5b | 429 | { |
NirT | 1:e8fac4061a5b | 430 | return QSPI_OK; |
NirT | 1:e8fac4061a5b | 431 | } |
NirT | 1:e8fac4061a5b | 432 | else |
NirT | 1:e8fac4061a5b | 433 | { |
NirT | 1:e8fac4061a5b | 434 | return QSPI_BUSY; |
NirT | 1:e8fac4061a5b | 435 | } |
NirT | 1:e8fac4061a5b | 436 | } |
NirT | 1:e8fac4061a5b | 437 | |
NirT | 1:e8fac4061a5b | 438 | /** |
NirT | 1:e8fac4061a5b | 439 | * @brief Return the configuration of the QSPI memory. |
NirT | 1:e8fac4061a5b | 440 | * @param pInfo: pointer on the configuration structure |
NirT | 1:e8fac4061a5b | 441 | * @retval QSPI memory status |
NirT | 1:e8fac4061a5b | 442 | */ |
NirT | 1:e8fac4061a5b | 443 | uint8_t BSP_QSPI_GetInfo(QSPI_Info* pInfo) |
NirT | 1:e8fac4061a5b | 444 | { |
NirT | 1:e8fac4061a5b | 445 | /* Configure the structure with the memory configuration */ |
NirT | 1:e8fac4061a5b | 446 | pInfo->FlashSize = N25Q128A_FLASH_SIZE; |
NirT | 1:e8fac4061a5b | 447 | pInfo->EraseSectorSize = N25Q128A_SUBSECTOR_SIZE; |
NirT | 1:e8fac4061a5b | 448 | pInfo->EraseSectorsNumber = (N25Q128A_FLASH_SIZE/N25Q128A_SUBSECTOR_SIZE); |
NirT | 1:e8fac4061a5b | 449 | pInfo->ProgPageSize = N25Q128A_PAGE_SIZE; |
NirT | 1:e8fac4061a5b | 450 | pInfo->ProgPagesNumber = (N25Q128A_FLASH_SIZE/N25Q128A_PAGE_SIZE); |
NirT | 1:e8fac4061a5b | 451 | |
NirT | 1:e8fac4061a5b | 452 | return QSPI_OK; |
NirT | 1:e8fac4061a5b | 453 | } |
NirT | 1:e8fac4061a5b | 454 | |
NirT | 1:e8fac4061a5b | 455 | /** |
NirT | 1:e8fac4061a5b | 456 | * @brief Configure the QSPI in memory-mapped mode |
NirT | 1:e8fac4061a5b | 457 | * @retval QSPI memory status |
NirT | 1:e8fac4061a5b | 458 | */ |
NirT | 1:e8fac4061a5b | 459 | uint8_t BSP_QSPI_MemoryMappedMode(void) |
NirT | 1:e8fac4061a5b | 460 | { |
NirT | 1:e8fac4061a5b | 461 | QSPI_CommandTypeDef s_command; |
NirT | 1:e8fac4061a5b | 462 | QSPI_MemoryMappedTypeDef s_mem_mapped_cfg; |
NirT | 1:e8fac4061a5b | 463 | |
NirT | 1:e8fac4061a5b | 464 | /* Configure the command for the read instruction */ |
NirT | 1:e8fac4061a5b | 465 | s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
NirT | 1:e8fac4061a5b | 466 | s_command.Instruction = QUAD_INOUT_FAST_READ_CMD; |
NirT | 1:e8fac4061a5b | 467 | s_command.AddressMode = QSPI_ADDRESS_4_LINES; |
NirT | 1:e8fac4061a5b | 468 | s_command.AddressSize = QSPI_ADDRESS_24_BITS; |
NirT | 1:e8fac4061a5b | 469 | s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
NirT | 1:e8fac4061a5b | 470 | s_command.DataMode = QSPI_DATA_4_LINES; |
NirT | 1:e8fac4061a5b | 471 | s_command.DummyCycles = N25Q128A_DUMMY_CYCLES_READ_QUAD; |
NirT | 1:e8fac4061a5b | 472 | s_command.DdrMode = QSPI_DDR_MODE_DISABLE; |
NirT | 1:e8fac4061a5b | 473 | s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
NirT | 1:e8fac4061a5b | 474 | s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
NirT | 1:e8fac4061a5b | 475 | |
NirT | 1:e8fac4061a5b | 476 | /* Configure the memory mapped mode */ |
NirT | 1:e8fac4061a5b | 477 | s_mem_mapped_cfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_ENABLE; |
NirT | 1:e8fac4061a5b | 478 | s_mem_mapped_cfg.TimeOutPeriod = 1; |
NirT | 1:e8fac4061a5b | 479 | |
NirT | 1:e8fac4061a5b | 480 | if (HAL_QSPI_MemoryMapped(&QSPIHandle, &s_command, &s_mem_mapped_cfg) != HAL_OK) |
NirT | 1:e8fac4061a5b | 481 | { |
NirT | 1:e8fac4061a5b | 482 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 483 | } |
NirT | 1:e8fac4061a5b | 484 | |
NirT | 1:e8fac4061a5b | 485 | return QSPI_OK; |
NirT | 1:e8fac4061a5b | 486 | } |
NirT | 1:e8fac4061a5b | 487 | |
NirT | 1:e8fac4061a5b | 488 | /** |
NirT | 1:e8fac4061a5b | 489 | * @} |
NirT | 1:e8fac4061a5b | 490 | */ |
NirT | 1:e8fac4061a5b | 491 | |
NirT | 1:e8fac4061a5b | 492 | /** @addtogroup STM32746G_DISCOVERY_QSPI_Private_Functions |
NirT | 1:e8fac4061a5b | 493 | * @{ |
NirT | 1:e8fac4061a5b | 494 | */ |
NirT | 1:e8fac4061a5b | 495 | |
NirT | 1:e8fac4061a5b | 496 | /** |
NirT | 1:e8fac4061a5b | 497 | * @brief QSPI MSP Initialization |
NirT | 1:e8fac4061a5b | 498 | * This function configures the hardware resources used in this example: |
NirT | 1:e8fac4061a5b | 499 | * - Peripheral's clock enable |
NirT | 1:e8fac4061a5b | 500 | * - Peripheral's GPIO Configuration |
NirT | 1:e8fac4061a5b | 501 | * - NVIC configuration for QSPI interrupt |
NirT | 1:e8fac4061a5b | 502 | * @retval None |
NirT | 1:e8fac4061a5b | 503 | */ |
NirT | 1:e8fac4061a5b | 504 | __weak void BSP_QSPI_MspInit(QSPI_HandleTypeDef *hqspi, void *Params) |
NirT | 1:e8fac4061a5b | 505 | { |
NirT | 1:e8fac4061a5b | 506 | GPIO_InitTypeDef gpio_init_structure; |
NirT | 1:e8fac4061a5b | 507 | |
NirT | 1:e8fac4061a5b | 508 | /*##-1- Enable peripherals and GPIO Clocks #################################*/ |
NirT | 1:e8fac4061a5b | 509 | /* Enable the QuadSPI memory interface clock */ |
NirT | 1:e8fac4061a5b | 510 | QSPI_CLK_ENABLE(); |
NirT | 1:e8fac4061a5b | 511 | /* Reset the QuadSPI memory interface */ |
NirT | 1:e8fac4061a5b | 512 | QSPI_FORCE_RESET(); |
NirT | 1:e8fac4061a5b | 513 | QSPI_RELEASE_RESET(); |
NirT | 1:e8fac4061a5b | 514 | /* Enable GPIO clocks */ |
NirT | 1:e8fac4061a5b | 515 | QSPI_CS_GPIO_CLK_ENABLE(); |
NirT | 1:e8fac4061a5b | 516 | QSPI_CLK_GPIO_CLK_ENABLE(); |
NirT | 1:e8fac4061a5b | 517 | QSPI_D0_GPIO_CLK_ENABLE(); |
NirT | 1:e8fac4061a5b | 518 | QSPI_D1_GPIO_CLK_ENABLE(); |
NirT | 1:e8fac4061a5b | 519 | QSPI_D2_GPIO_CLK_ENABLE(); |
NirT | 1:e8fac4061a5b | 520 | QSPI_D3_GPIO_CLK_ENABLE(); |
NirT | 1:e8fac4061a5b | 521 | |
NirT | 1:e8fac4061a5b | 522 | /*##-2- Configure peripheral GPIO ##########################################*/ |
NirT | 1:e8fac4061a5b | 523 | /* QSPI CS GPIO pin configuration */ |
NirT | 1:e8fac4061a5b | 524 | gpio_init_structure.Pin = QSPI_CS_PIN; |
NirT | 1:e8fac4061a5b | 525 | gpio_init_structure.Mode = GPIO_MODE_AF_PP; |
NirT | 1:e8fac4061a5b | 526 | gpio_init_structure.Pull = GPIO_PULLUP; |
NirT | 1:e8fac4061a5b | 527 | gpio_init_structure.Speed = GPIO_SPEED_HIGH; |
NirT | 1:e8fac4061a5b | 528 | gpio_init_structure.Alternate = GPIO_AF10_QUADSPI; |
NirT | 1:e8fac4061a5b | 529 | HAL_GPIO_Init(QSPI_CS_GPIO_PORT, &gpio_init_structure); |
NirT | 1:e8fac4061a5b | 530 | |
NirT | 1:e8fac4061a5b | 531 | /* QSPI CLK GPIO pin configuration */ |
NirT | 1:e8fac4061a5b | 532 | gpio_init_structure.Pin = QSPI_CLK_PIN; |
NirT | 1:e8fac4061a5b | 533 | gpio_init_structure.Pull = GPIO_NOPULL; |
NirT | 1:e8fac4061a5b | 534 | gpio_init_structure.Alternate = GPIO_AF9_QUADSPI; |
NirT | 1:e8fac4061a5b | 535 | HAL_GPIO_Init(QSPI_CLK_GPIO_PORT, &gpio_init_structure); |
NirT | 1:e8fac4061a5b | 536 | |
NirT | 1:e8fac4061a5b | 537 | /* QSPI D0 GPIO pin configuration */ |
NirT | 1:e8fac4061a5b | 538 | gpio_init_structure.Pin = QSPI_D0_PIN; |
NirT | 1:e8fac4061a5b | 539 | gpio_init_structure.Alternate = GPIO_AF9_QUADSPI; |
NirT | 1:e8fac4061a5b | 540 | HAL_GPIO_Init(QSPI_D0_GPIO_PORT, &gpio_init_structure); |
NirT | 1:e8fac4061a5b | 541 | |
NirT | 1:e8fac4061a5b | 542 | /* QSPI D1 GPIO pin configuration */ |
NirT | 1:e8fac4061a5b | 543 | gpio_init_structure.Pin = QSPI_D1_PIN; |
NirT | 1:e8fac4061a5b | 544 | gpio_init_structure.Alternate = GPIO_AF9_QUADSPI; |
NirT | 1:e8fac4061a5b | 545 | HAL_GPIO_Init(QSPI_D1_GPIO_PORT, &gpio_init_structure); |
NirT | 1:e8fac4061a5b | 546 | |
NirT | 1:e8fac4061a5b | 547 | /* QSPI D2 GPIO pin configuration */ |
NirT | 1:e8fac4061a5b | 548 | gpio_init_structure.Pin = QSPI_D2_PIN; |
NirT | 1:e8fac4061a5b | 549 | gpio_init_structure.Alternate = GPIO_AF9_QUADSPI; |
NirT | 1:e8fac4061a5b | 550 | HAL_GPIO_Init(QSPI_D2_GPIO_PORT, &gpio_init_structure); |
NirT | 1:e8fac4061a5b | 551 | |
NirT | 1:e8fac4061a5b | 552 | /* QSPI D3 GPIO pin configuration */ |
NirT | 1:e8fac4061a5b | 553 | gpio_init_structure.Pin = QSPI_D3_PIN; |
NirT | 1:e8fac4061a5b | 554 | gpio_init_structure.Alternate = GPIO_AF9_QUADSPI; |
NirT | 1:e8fac4061a5b | 555 | HAL_GPIO_Init(QSPI_D3_GPIO_PORT, &gpio_init_structure); |
NirT | 1:e8fac4061a5b | 556 | |
NirT | 1:e8fac4061a5b | 557 | /*##-3- Configure the NVIC for QSPI #########################################*/ |
NirT | 1:e8fac4061a5b | 558 | /* NVIC configuration for QSPI interrupt */ |
NirT | 1:e8fac4061a5b | 559 | HAL_NVIC_SetPriority(QUADSPI_IRQn, 0x0F, 0); |
NirT | 1:e8fac4061a5b | 560 | HAL_NVIC_EnableIRQ(QUADSPI_IRQn); |
NirT | 1:e8fac4061a5b | 561 | } |
NirT | 1:e8fac4061a5b | 562 | |
NirT | 1:e8fac4061a5b | 563 | /** |
NirT | 1:e8fac4061a5b | 564 | * @brief QSPI MSP De-Initialization |
NirT | 1:e8fac4061a5b | 565 | * This function frees the hardware resources used in this example: |
NirT | 1:e8fac4061a5b | 566 | * - Disable the Peripheral's clock |
NirT | 1:e8fac4061a5b | 567 | * - Revert GPIO and NVIC configuration to their default state |
NirT | 1:e8fac4061a5b | 568 | * @retval None |
NirT | 1:e8fac4061a5b | 569 | */ |
NirT | 1:e8fac4061a5b | 570 | __weak void BSP_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi, void *Params) |
NirT | 1:e8fac4061a5b | 571 | { |
NirT | 1:e8fac4061a5b | 572 | /*##-1- Disable the NVIC for QSPI ###########################################*/ |
NirT | 1:e8fac4061a5b | 573 | HAL_NVIC_DisableIRQ(QUADSPI_IRQn); |
NirT | 1:e8fac4061a5b | 574 | |
NirT | 1:e8fac4061a5b | 575 | /*##-2- Disable peripherals and GPIO Clocks ################################*/ |
NirT | 1:e8fac4061a5b | 576 | /* De-Configure QSPI pins */ |
NirT | 1:e8fac4061a5b | 577 | HAL_GPIO_DeInit(QSPI_CS_GPIO_PORT, QSPI_CS_PIN); |
NirT | 1:e8fac4061a5b | 578 | HAL_GPIO_DeInit(QSPI_CLK_GPIO_PORT, QSPI_CLK_PIN); |
NirT | 1:e8fac4061a5b | 579 | HAL_GPIO_DeInit(QSPI_D0_GPIO_PORT, QSPI_D0_PIN); |
NirT | 1:e8fac4061a5b | 580 | HAL_GPIO_DeInit(QSPI_D1_GPIO_PORT, QSPI_D1_PIN); |
NirT | 1:e8fac4061a5b | 581 | HAL_GPIO_DeInit(QSPI_D2_GPIO_PORT, QSPI_D2_PIN); |
NirT | 1:e8fac4061a5b | 582 | HAL_GPIO_DeInit(QSPI_D3_GPIO_PORT, QSPI_D3_PIN); |
NirT | 1:e8fac4061a5b | 583 | |
NirT | 1:e8fac4061a5b | 584 | /*##-3- Reset peripherals ##################################################*/ |
NirT | 1:e8fac4061a5b | 585 | /* Reset the QuadSPI memory interface */ |
NirT | 1:e8fac4061a5b | 586 | QSPI_FORCE_RESET(); |
NirT | 1:e8fac4061a5b | 587 | QSPI_RELEASE_RESET(); |
NirT | 1:e8fac4061a5b | 588 | |
NirT | 1:e8fac4061a5b | 589 | /* Disable the QuadSPI memory interface clock */ |
NirT | 1:e8fac4061a5b | 590 | QSPI_CLK_DISABLE(); |
NirT | 1:e8fac4061a5b | 591 | } |
NirT | 1:e8fac4061a5b | 592 | |
NirT | 1:e8fac4061a5b | 593 | /** |
NirT | 1:e8fac4061a5b | 594 | * @brief This function reset the QSPI memory. |
NirT | 1:e8fac4061a5b | 595 | * @param hqspi: QSPI handle |
NirT | 1:e8fac4061a5b | 596 | * @retval None |
NirT | 1:e8fac4061a5b | 597 | */ |
NirT | 1:e8fac4061a5b | 598 | static uint8_t QSPI_ResetMemory(QSPI_HandleTypeDef *hqspi) |
NirT | 1:e8fac4061a5b | 599 | { |
NirT | 1:e8fac4061a5b | 600 | QSPI_CommandTypeDef s_command; |
NirT | 1:e8fac4061a5b | 601 | |
NirT | 1:e8fac4061a5b | 602 | /* Initialize the reset enable command */ |
NirT | 1:e8fac4061a5b | 603 | s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
NirT | 1:e8fac4061a5b | 604 | s_command.Instruction = RESET_ENABLE_CMD; |
NirT | 1:e8fac4061a5b | 605 | s_command.AddressMode = QSPI_ADDRESS_NONE; |
NirT | 1:e8fac4061a5b | 606 | s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
NirT | 1:e8fac4061a5b | 607 | s_command.DataMode = QSPI_DATA_NONE; |
NirT | 1:e8fac4061a5b | 608 | s_command.DummyCycles = 0; |
NirT | 1:e8fac4061a5b | 609 | s_command.DdrMode = QSPI_DDR_MODE_DISABLE; |
NirT | 1:e8fac4061a5b | 610 | s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
NirT | 1:e8fac4061a5b | 611 | s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
NirT | 1:e8fac4061a5b | 612 | |
NirT | 1:e8fac4061a5b | 613 | /* Send the command */ |
NirT | 1:e8fac4061a5b | 614 | if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
NirT | 1:e8fac4061a5b | 615 | { |
NirT | 1:e8fac4061a5b | 616 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 617 | } |
NirT | 1:e8fac4061a5b | 618 | |
NirT | 1:e8fac4061a5b | 619 | /* Send the reset memory command */ |
NirT | 1:e8fac4061a5b | 620 | s_command.Instruction = RESET_MEMORY_CMD; |
NirT | 1:e8fac4061a5b | 621 | if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
NirT | 1:e8fac4061a5b | 622 | { |
NirT | 1:e8fac4061a5b | 623 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 624 | } |
NirT | 1:e8fac4061a5b | 625 | |
NirT | 1:e8fac4061a5b | 626 | /* Configure automatic polling mode to wait the memory is ready */ |
NirT | 1:e8fac4061a5b | 627 | if (QSPI_AutoPollingMemReady(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK) |
NirT | 1:e8fac4061a5b | 628 | { |
NirT | 1:e8fac4061a5b | 629 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 630 | } |
NirT | 1:e8fac4061a5b | 631 | |
NirT | 1:e8fac4061a5b | 632 | return QSPI_OK; |
NirT | 1:e8fac4061a5b | 633 | } |
NirT | 1:e8fac4061a5b | 634 | |
NirT | 1:e8fac4061a5b | 635 | /** |
NirT | 1:e8fac4061a5b | 636 | * @brief This function configure the dummy cycles on memory side. |
NirT | 1:e8fac4061a5b | 637 | * @param hqspi: QSPI handle |
NirT | 1:e8fac4061a5b | 638 | * @retval None |
NirT | 1:e8fac4061a5b | 639 | */ |
NirT | 1:e8fac4061a5b | 640 | static uint8_t QSPI_DummyCyclesCfg(QSPI_HandleTypeDef *hqspi) |
NirT | 1:e8fac4061a5b | 641 | { |
NirT | 1:e8fac4061a5b | 642 | QSPI_CommandTypeDef s_command; |
NirT | 1:e8fac4061a5b | 643 | uint8_t reg; |
NirT | 1:e8fac4061a5b | 644 | |
NirT | 1:e8fac4061a5b | 645 | /* Initialize the read volatile configuration register command */ |
NirT | 1:e8fac4061a5b | 646 | s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
NirT | 1:e8fac4061a5b | 647 | s_command.Instruction = READ_VOL_CFG_REG_CMD; |
NirT | 1:e8fac4061a5b | 648 | s_command.AddressMode = QSPI_ADDRESS_NONE; |
NirT | 1:e8fac4061a5b | 649 | s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
NirT | 1:e8fac4061a5b | 650 | s_command.DataMode = QSPI_DATA_1_LINE; |
NirT | 1:e8fac4061a5b | 651 | s_command.DummyCycles = 0; |
NirT | 1:e8fac4061a5b | 652 | s_command.NbData = 1; |
NirT | 1:e8fac4061a5b | 653 | s_command.DdrMode = QSPI_DDR_MODE_DISABLE; |
NirT | 1:e8fac4061a5b | 654 | s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
NirT | 1:e8fac4061a5b | 655 | s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
NirT | 1:e8fac4061a5b | 656 | |
NirT | 1:e8fac4061a5b | 657 | /* Configure the command */ |
NirT | 1:e8fac4061a5b | 658 | if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
NirT | 1:e8fac4061a5b | 659 | { |
NirT | 1:e8fac4061a5b | 660 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 661 | } |
NirT | 1:e8fac4061a5b | 662 | |
NirT | 1:e8fac4061a5b | 663 | /* Reception of the data */ |
NirT | 1:e8fac4061a5b | 664 | if (HAL_QSPI_Receive(hqspi, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
NirT | 1:e8fac4061a5b | 665 | { |
NirT | 1:e8fac4061a5b | 666 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 667 | } |
NirT | 1:e8fac4061a5b | 668 | |
NirT | 1:e8fac4061a5b | 669 | /* Enable write operations */ |
NirT | 1:e8fac4061a5b | 670 | if (QSPI_WriteEnable(hqspi) != QSPI_OK) |
NirT | 1:e8fac4061a5b | 671 | { |
NirT | 1:e8fac4061a5b | 672 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 673 | } |
NirT | 1:e8fac4061a5b | 674 | |
NirT | 1:e8fac4061a5b | 675 | /* Update volatile configuration register (with new dummy cycles) */ |
NirT | 1:e8fac4061a5b | 676 | s_command.Instruction = WRITE_VOL_CFG_REG_CMD; |
NirT | 1:e8fac4061a5b | 677 | MODIFY_REG(reg, N25Q128A_VCR_NB_DUMMY, (N25Q128A_DUMMY_CYCLES_READ_QUAD << POSITION_VAL(N25Q128A_VCR_NB_DUMMY))); |
NirT | 1:e8fac4061a5b | 678 | |
NirT | 1:e8fac4061a5b | 679 | /* Configure the write volatile configuration register command */ |
NirT | 1:e8fac4061a5b | 680 | if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
NirT | 1:e8fac4061a5b | 681 | { |
NirT | 1:e8fac4061a5b | 682 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 683 | } |
NirT | 1:e8fac4061a5b | 684 | |
NirT | 1:e8fac4061a5b | 685 | /* Transmission of the data */ |
NirT | 1:e8fac4061a5b | 686 | if (HAL_QSPI_Transmit(hqspi, ®, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
NirT | 1:e8fac4061a5b | 687 | { |
NirT | 1:e8fac4061a5b | 688 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 689 | } |
NirT | 1:e8fac4061a5b | 690 | |
NirT | 1:e8fac4061a5b | 691 | return QSPI_OK; |
NirT | 1:e8fac4061a5b | 692 | } |
NirT | 1:e8fac4061a5b | 693 | |
NirT | 1:e8fac4061a5b | 694 | /** |
NirT | 1:e8fac4061a5b | 695 | * @brief This function send a Write Enable and wait it is effective. |
NirT | 1:e8fac4061a5b | 696 | * @param hqspi: QSPI handle |
NirT | 1:e8fac4061a5b | 697 | * @retval None |
NirT | 1:e8fac4061a5b | 698 | */ |
NirT | 1:e8fac4061a5b | 699 | static uint8_t QSPI_WriteEnable(QSPI_HandleTypeDef *hqspi) |
NirT | 1:e8fac4061a5b | 700 | { |
NirT | 1:e8fac4061a5b | 701 | QSPI_CommandTypeDef s_command; |
NirT | 1:e8fac4061a5b | 702 | QSPI_AutoPollingTypeDef s_config; |
NirT | 1:e8fac4061a5b | 703 | |
NirT | 1:e8fac4061a5b | 704 | /* Enable write operations */ |
NirT | 1:e8fac4061a5b | 705 | s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
NirT | 1:e8fac4061a5b | 706 | s_command.Instruction = WRITE_ENABLE_CMD; |
NirT | 1:e8fac4061a5b | 707 | s_command.AddressMode = QSPI_ADDRESS_NONE; |
NirT | 1:e8fac4061a5b | 708 | s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
NirT | 1:e8fac4061a5b | 709 | s_command.DataMode = QSPI_DATA_NONE; |
NirT | 1:e8fac4061a5b | 710 | s_command.DummyCycles = 0; |
NirT | 1:e8fac4061a5b | 711 | s_command.DdrMode = QSPI_DDR_MODE_DISABLE; |
NirT | 1:e8fac4061a5b | 712 | s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
NirT | 1:e8fac4061a5b | 713 | s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
NirT | 1:e8fac4061a5b | 714 | |
NirT | 1:e8fac4061a5b | 715 | if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
NirT | 1:e8fac4061a5b | 716 | { |
NirT | 1:e8fac4061a5b | 717 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 718 | } |
NirT | 1:e8fac4061a5b | 719 | |
NirT | 1:e8fac4061a5b | 720 | /* Configure automatic polling mode to wait for write enabling */ |
NirT | 1:e8fac4061a5b | 721 | s_config.Match = N25Q128A_SR_WREN; |
NirT | 1:e8fac4061a5b | 722 | s_config.Mask = N25Q128A_SR_WREN; |
NirT | 1:e8fac4061a5b | 723 | s_config.MatchMode = QSPI_MATCH_MODE_AND; |
NirT | 1:e8fac4061a5b | 724 | s_config.StatusBytesSize = 1; |
NirT | 1:e8fac4061a5b | 725 | s_config.Interval = 0x10; |
NirT | 1:e8fac4061a5b | 726 | s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; |
NirT | 1:e8fac4061a5b | 727 | |
NirT | 1:e8fac4061a5b | 728 | s_command.Instruction = READ_STATUS_REG_CMD; |
NirT | 1:e8fac4061a5b | 729 | s_command.DataMode = QSPI_DATA_1_LINE; |
NirT | 1:e8fac4061a5b | 730 | |
NirT | 1:e8fac4061a5b | 731 | if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) |
NirT | 1:e8fac4061a5b | 732 | { |
NirT | 1:e8fac4061a5b | 733 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 734 | } |
NirT | 1:e8fac4061a5b | 735 | |
NirT | 1:e8fac4061a5b | 736 | return QSPI_OK; |
NirT | 1:e8fac4061a5b | 737 | } |
NirT | 1:e8fac4061a5b | 738 | |
NirT | 1:e8fac4061a5b | 739 | /** |
NirT | 1:e8fac4061a5b | 740 | * @brief This function read the SR of the memory and wait the EOP. |
NirT | 1:e8fac4061a5b | 741 | * @param hqspi: QSPI handle |
NirT | 1:e8fac4061a5b | 742 | * @param Timeout |
NirT | 1:e8fac4061a5b | 743 | * @retval None |
NirT | 1:e8fac4061a5b | 744 | */ |
NirT | 1:e8fac4061a5b | 745 | static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) |
NirT | 1:e8fac4061a5b | 746 | { |
NirT | 1:e8fac4061a5b | 747 | QSPI_CommandTypeDef s_command; |
NirT | 1:e8fac4061a5b | 748 | QSPI_AutoPollingTypeDef s_config; |
NirT | 1:e8fac4061a5b | 749 | |
NirT | 1:e8fac4061a5b | 750 | /* Configure automatic polling mode to wait for memory ready */ |
NirT | 1:e8fac4061a5b | 751 | s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE; |
NirT | 1:e8fac4061a5b | 752 | s_command.Instruction = READ_STATUS_REG_CMD; |
NirT | 1:e8fac4061a5b | 753 | s_command.AddressMode = QSPI_ADDRESS_NONE; |
NirT | 1:e8fac4061a5b | 754 | s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE; |
NirT | 1:e8fac4061a5b | 755 | s_command.DataMode = QSPI_DATA_1_LINE; |
NirT | 1:e8fac4061a5b | 756 | s_command.DummyCycles = 0; |
NirT | 1:e8fac4061a5b | 757 | s_command.DdrMode = QSPI_DDR_MODE_DISABLE; |
NirT | 1:e8fac4061a5b | 758 | s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY; |
NirT | 1:e8fac4061a5b | 759 | s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD; |
NirT | 1:e8fac4061a5b | 760 | |
NirT | 1:e8fac4061a5b | 761 | s_config.Match = 0; |
NirT | 1:e8fac4061a5b | 762 | s_config.Mask = N25Q128A_SR_WIP; |
NirT | 1:e8fac4061a5b | 763 | s_config.MatchMode = QSPI_MATCH_MODE_AND; |
NirT | 1:e8fac4061a5b | 764 | s_config.StatusBytesSize = 1; |
NirT | 1:e8fac4061a5b | 765 | s_config.Interval = 0x10; |
NirT | 1:e8fac4061a5b | 766 | s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE; |
NirT | 1:e8fac4061a5b | 767 | |
NirT | 1:e8fac4061a5b | 768 | if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, Timeout) != HAL_OK) |
NirT | 1:e8fac4061a5b | 769 | { |
NirT | 1:e8fac4061a5b | 770 | return QSPI_ERROR; |
NirT | 1:e8fac4061a5b | 771 | } |
NirT | 1:e8fac4061a5b | 772 | |
NirT | 1:e8fac4061a5b | 773 | return QSPI_OK; |
NirT | 1:e8fac4061a5b | 774 | } |
NirT | 1:e8fac4061a5b | 775 | /** |
NirT | 1:e8fac4061a5b | 776 | * @} |
NirT | 1:e8fac4061a5b | 777 | */ |
NirT | 1:e8fac4061a5b | 778 | |
NirT | 1:e8fac4061a5b | 779 | /** |
NirT | 1:e8fac4061a5b | 780 | * @} |
NirT | 1:e8fac4061a5b | 781 | */ |
NirT | 1:e8fac4061a5b | 782 | |
NirT | 1:e8fac4061a5b | 783 | /** |
NirT | 1:e8fac4061a5b | 784 | * @} |
NirT | 1:e8fac4061a5b | 785 | */ |
NirT | 1:e8fac4061a5b | 786 | |
NirT | 1:e8fac4061a5b | 787 | /** |
NirT | 1:e8fac4061a5b | 788 | * @} |
NirT | 1:e8fac4061a5b | 789 | */ |
NirT | 1:e8fac4061a5b | 790 | |
NirT | 1:e8fac4061a5b | 791 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
NirT | 1:e8fac4061a5b | 792 | |
NirT | 1:e8fac4061a5b | 793 |