bugfixes and reduced version for disco board only
Dependents: Scope DISCO-F746NG_Sinewave DISCO-F746NG_Sweep DISCO-F746NG_Oscilloscope ... more
Fork of BSP_DISCO_F746NG_patch by
stm32746g_discovery_eeprom.c@1:e8fac4061a5b, 2015-11-02 (annotated)
- Committer:
- NirT
- Date:
- Mon Nov 02 23:35:17 2015 +0000
- Revision:
- 1:e8fac4061a5b
Error: Incomplete type is not allowed in "patch/LwIP/src/include/lwip/dhcp.h", Line: 83, Col: 4; ; and more like this.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
NirT | 1:e8fac4061a5b | 1 | /** |
NirT | 1:e8fac4061a5b | 2 | ****************************************************************************** |
NirT | 1:e8fac4061a5b | 3 | * @file stm32746g_discovery_eeprom.c |
NirT | 1:e8fac4061a5b | 4 | * @author MCD Application Team |
NirT | 1:e8fac4061a5b | 5 | * @version V1.0.0 |
NirT | 1:e8fac4061a5b | 6 | * @date 25-June-2015 |
NirT | 1:e8fac4061a5b | 7 | * @brief This file provides a set of functions needed to manage an I2C M24LR64 |
NirT | 1:e8fac4061a5b | 8 | * EEPROM memory. |
NirT | 1:e8fac4061a5b | 9 | @verbatim |
NirT | 1:e8fac4061a5b | 10 | To be able to use this driver, the switch EE_M24LR64 must be defined |
NirT | 1:e8fac4061a5b | 11 | in your toolchain compiler preprocessor |
NirT | 1:e8fac4061a5b | 12 | |
NirT | 1:e8fac4061a5b | 13 | =================================================================== |
NirT | 1:e8fac4061a5b | 14 | Notes: |
NirT | 1:e8fac4061a5b | 15 | - The I2C EEPROM memory (M24LR64) is available on separate daughter |
NirT | 1:e8fac4061a5b | 16 | board ANT7-M24LR-A, which is not provided with the STM32746G_DISCOVERY |
NirT | 1:e8fac4061a5b | 17 | board. |
NirT | 1:e8fac4061a5b | 18 | To use this driver you have to connect the ANT7-M24LR-A to CN3 |
NirT | 1:e8fac4061a5b | 19 | connector of STM32746G_DISCOVERY board. |
NirT | 1:e8fac4061a5b | 20 | =================================================================== |
NirT | 1:e8fac4061a5b | 21 | |
NirT | 1:e8fac4061a5b | 22 | It implements a high level communication layer for read and write |
NirT | 1:e8fac4061a5b | 23 | from/to this memory. The needed STM32F7xx hardware resources (I2C and |
NirT | 1:e8fac4061a5b | 24 | GPIO) are defined in stm32746g_discovery.h file, and the initialization is |
NirT | 1:e8fac4061a5b | 25 | performed in EEPROM_IO_Init() function declared in stm32746g_discovery.c |
NirT | 1:e8fac4061a5b | 26 | file. |
NirT | 1:e8fac4061a5b | 27 | You can easily tailor this driver to any other development board, |
NirT | 1:e8fac4061a5b | 28 | by just adapting the defines for hardware resources and |
NirT | 1:e8fac4061a5b | 29 | EEPROM_IO_Init() function. |
NirT | 1:e8fac4061a5b | 30 | |
NirT | 1:e8fac4061a5b | 31 | @note In this driver, basic read and write functions (BSP_EEPROM_ReadBuffer() |
NirT | 1:e8fac4061a5b | 32 | and BSP_EEPROM_WritePage()) use DMA mode to perform the data |
NirT | 1:e8fac4061a5b | 33 | transfer to/from EEPROM memory. |
NirT | 1:e8fac4061a5b | 34 | |
NirT | 1:e8fac4061a5b | 35 | @note Regarding BSP_EEPROM_WritePage(), it is an optimized function to perform |
NirT | 1:e8fac4061a5b | 36 | small write (less than 1 page) BUT the number of bytes (combined to write start address) must not |
NirT | 1:e8fac4061a5b | 37 | cross the EEPROM page boundary. This function can only writes into |
NirT | 1:e8fac4061a5b | 38 | the boundaries of an EEPROM page. |
NirT | 1:e8fac4061a5b | 39 | This function doesn't check on boundaries condition (in this driver |
NirT | 1:e8fac4061a5b | 40 | the function BSP_EEPROM_WriteBuffer() which calls BSP_EEPROM_WritePage() is |
NirT | 1:e8fac4061a5b | 41 | responsible of checking on Page boundaries). |
NirT | 1:e8fac4061a5b | 42 | |
NirT | 1:e8fac4061a5b | 43 | |
NirT | 1:e8fac4061a5b | 44 | +-----------------------------------------------------------------+ |
NirT | 1:e8fac4061a5b | 45 | | Pin assignment for M24LR64 EEPROM | |
NirT | 1:e8fac4061a5b | 46 | +---------------------------------------+-----------+-------------+ |
NirT | 1:e8fac4061a5b | 47 | | STM32F7xx I2C Pins | EEPROM | Pin | |
NirT | 1:e8fac4061a5b | 48 | +---------------------------------------+-----------+-------------+ |
NirT | 1:e8fac4061a5b | 49 | | . | E0(GND) | 1 (0V) | |
NirT | 1:e8fac4061a5b | 50 | | . | AC0 | 2 | |
NirT | 1:e8fac4061a5b | 51 | | . | AC1 | 3 | |
NirT | 1:e8fac4061a5b | 52 | | . | VSS | 4 (0V) | |
NirT | 1:e8fac4061a5b | 53 | | SDA | SDA | 5 | |
NirT | 1:e8fac4061a5b | 54 | | SCL | SCL | 6 | |
NirT | 1:e8fac4061a5b | 55 | | . | E1(GND) | 7 (0V) | |
NirT | 1:e8fac4061a5b | 56 | | . | VDD | 8 (3.3V) | |
NirT | 1:e8fac4061a5b | 57 | +---------------------------------------+-----------+-------------+ |
NirT | 1:e8fac4061a5b | 58 | @endverbatim |
NirT | 1:e8fac4061a5b | 59 | ****************************************************************************** |
NirT | 1:e8fac4061a5b | 60 | * @attention |
NirT | 1:e8fac4061a5b | 61 | * |
NirT | 1:e8fac4061a5b | 62 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
NirT | 1:e8fac4061a5b | 63 | * |
NirT | 1:e8fac4061a5b | 64 | * Redistribution and use in source and binary forms, with or without modification, |
NirT | 1:e8fac4061a5b | 65 | * are permitted provided that the following conditions are met: |
NirT | 1:e8fac4061a5b | 66 | * 1. Redistributions of source code must retain the above copyright notice, |
NirT | 1:e8fac4061a5b | 67 | * this list of conditions and the following disclaimer. |
NirT | 1:e8fac4061a5b | 68 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
NirT | 1:e8fac4061a5b | 69 | * this list of conditions and the following disclaimer in the documentation |
NirT | 1:e8fac4061a5b | 70 | * and/or other materials provided with the distribution. |
NirT | 1:e8fac4061a5b | 71 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
NirT | 1:e8fac4061a5b | 72 | * may be used to endorse or promote products derived from this software |
NirT | 1:e8fac4061a5b | 73 | * without specific prior written permission. |
NirT | 1:e8fac4061a5b | 74 | * |
NirT | 1:e8fac4061a5b | 75 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
NirT | 1:e8fac4061a5b | 76 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
NirT | 1:e8fac4061a5b | 77 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
NirT | 1:e8fac4061a5b | 78 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
NirT | 1:e8fac4061a5b | 79 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
NirT | 1:e8fac4061a5b | 80 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
NirT | 1:e8fac4061a5b | 81 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
NirT | 1:e8fac4061a5b | 82 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
NirT | 1:e8fac4061a5b | 83 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
NirT | 1:e8fac4061a5b | 84 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
NirT | 1:e8fac4061a5b | 85 | * |
NirT | 1:e8fac4061a5b | 86 | ****************************************************************************** |
NirT | 1:e8fac4061a5b | 87 | */ |
NirT | 1:e8fac4061a5b | 88 | /* Includes ------------------------------------------------------------------*/ |
NirT | 1:e8fac4061a5b | 89 | #include "stm32746g_discovery_eeprom.h" |
NirT | 1:e8fac4061a5b | 90 | |
NirT | 1:e8fac4061a5b | 91 | /** @addtogroup BSP |
NirT | 1:e8fac4061a5b | 92 | * @{ |
NirT | 1:e8fac4061a5b | 93 | */ |
NirT | 1:e8fac4061a5b | 94 | |
NirT | 1:e8fac4061a5b | 95 | /** @addtogroup STM32746G_DISCOVERY |
NirT | 1:e8fac4061a5b | 96 | * @{ |
NirT | 1:e8fac4061a5b | 97 | */ |
NirT | 1:e8fac4061a5b | 98 | |
NirT | 1:e8fac4061a5b | 99 | /** @addtogroup STM32746G_DISCOVERY_EEPROM |
NirT | 1:e8fac4061a5b | 100 | * @brief This file includes the I2C EEPROM driver of STM32746G-Discovery board. |
NirT | 1:e8fac4061a5b | 101 | * @{ |
NirT | 1:e8fac4061a5b | 102 | */ |
NirT | 1:e8fac4061a5b | 103 | |
NirT | 1:e8fac4061a5b | 104 | /** @defgroup STM32746G_DISCOVERY_EEPROM_Private_Types STM32746G_DISCOVERY_EEPROM Private Types |
NirT | 1:e8fac4061a5b | 105 | * @{ |
NirT | 1:e8fac4061a5b | 106 | */ |
NirT | 1:e8fac4061a5b | 107 | /** |
NirT | 1:e8fac4061a5b | 108 | * @} |
NirT | 1:e8fac4061a5b | 109 | */ |
NirT | 1:e8fac4061a5b | 110 | |
NirT | 1:e8fac4061a5b | 111 | /** @defgroup STM32746G_DISCOVERY_EEPROM_Private_Defines STM32746G_DISCOVERY_EEPROM Private Defines |
NirT | 1:e8fac4061a5b | 112 | * @{ |
NirT | 1:e8fac4061a5b | 113 | */ |
NirT | 1:e8fac4061a5b | 114 | /** |
NirT | 1:e8fac4061a5b | 115 | * @} |
NirT | 1:e8fac4061a5b | 116 | */ |
NirT | 1:e8fac4061a5b | 117 | |
NirT | 1:e8fac4061a5b | 118 | /** @defgroup STM32746G_DISCOVERY_EEPROM_Private_Macros STM32746G_DISCOVERY_EEPROM Private Macros |
NirT | 1:e8fac4061a5b | 119 | * @{ |
NirT | 1:e8fac4061a5b | 120 | */ |
NirT | 1:e8fac4061a5b | 121 | /** |
NirT | 1:e8fac4061a5b | 122 | * @} |
NirT | 1:e8fac4061a5b | 123 | */ |
NirT | 1:e8fac4061a5b | 124 | |
NirT | 1:e8fac4061a5b | 125 | /** @defgroup STM32746G_DISCOVERY_EEPROM_Private_Variables STM32746G_DISCOVERY_EEPROM Private Variables |
NirT | 1:e8fac4061a5b | 126 | * @{ |
NirT | 1:e8fac4061a5b | 127 | */ |
NirT | 1:e8fac4061a5b | 128 | __IO uint16_t EEPROMAddress = 0; |
NirT | 1:e8fac4061a5b | 129 | __IO uint16_t EEPROMDataRead; |
NirT | 1:e8fac4061a5b | 130 | __IO uint8_t EEPROMDataWrite; |
NirT | 1:e8fac4061a5b | 131 | /** |
NirT | 1:e8fac4061a5b | 132 | * @} |
NirT | 1:e8fac4061a5b | 133 | */ |
NirT | 1:e8fac4061a5b | 134 | |
NirT | 1:e8fac4061a5b | 135 | /** @defgroup STM32746G_DISCOVERY_EEPROM_Private_Function_Prototypes STM32746G_DISCOVERY_EEPROM Private Function Prototypes |
NirT | 1:e8fac4061a5b | 136 | * @{ |
NirT | 1:e8fac4061a5b | 137 | */ |
NirT | 1:e8fac4061a5b | 138 | /** |
NirT | 1:e8fac4061a5b | 139 | * @} |
NirT | 1:e8fac4061a5b | 140 | */ |
NirT | 1:e8fac4061a5b | 141 | |
NirT | 1:e8fac4061a5b | 142 | /** @defgroup STM32746G_DISCOVERY_EEPROM_Exported_Functions STM32746G_DISCOVERY_EEPROM Exported Functions |
NirT | 1:e8fac4061a5b | 143 | * @{ |
NirT | 1:e8fac4061a5b | 144 | */ |
NirT | 1:e8fac4061a5b | 145 | |
NirT | 1:e8fac4061a5b | 146 | /** |
NirT | 1:e8fac4061a5b | 147 | * @brief Initializes peripherals used by the I2C EEPROM driver. |
NirT | 1:e8fac4061a5b | 148 | * |
NirT | 1:e8fac4061a5b | 149 | * @note There are 2 different versions of M24LR64 (A01 & A02). |
NirT | 1:e8fac4061a5b | 150 | * Then try to connect on 1st one (EEPROM_I2C_ADDRESS_A01) |
NirT | 1:e8fac4061a5b | 151 | * and if problem, check the 2nd one (EEPROM_I2C_ADDRESS_A02) |
NirT | 1:e8fac4061a5b | 152 | * @retval EEPROM_OK (0) if operation is correctly performed, else return value |
NirT | 1:e8fac4061a5b | 153 | * different from EEPROM_OK (0) |
NirT | 1:e8fac4061a5b | 154 | */ |
NirT | 1:e8fac4061a5b | 155 | uint32_t BSP_EEPROM_Init(void) |
NirT | 1:e8fac4061a5b | 156 | { |
NirT | 1:e8fac4061a5b | 157 | /* I2C Initialization */ |
NirT | 1:e8fac4061a5b | 158 | EEPROM_IO_Init(); |
NirT | 1:e8fac4061a5b | 159 | |
NirT | 1:e8fac4061a5b | 160 | /* Select the EEPROM address for A01 and check if OK */ |
NirT | 1:e8fac4061a5b | 161 | EEPROMAddress = EEPROM_I2C_ADDRESS_A01; |
NirT | 1:e8fac4061a5b | 162 | if(EEPROM_IO_IsDeviceReady(EEPROMAddress, EEPROM_MAX_TRIALS) != HAL_OK) |
NirT | 1:e8fac4061a5b | 163 | { |
NirT | 1:e8fac4061a5b | 164 | /* Select the EEPROM address for A02 and check if OK */ |
NirT | 1:e8fac4061a5b | 165 | EEPROMAddress = EEPROM_I2C_ADDRESS_A02; |
NirT | 1:e8fac4061a5b | 166 | if(EEPROM_IO_IsDeviceReady(EEPROMAddress, EEPROM_MAX_TRIALS) != HAL_OK) |
NirT | 1:e8fac4061a5b | 167 | { |
NirT | 1:e8fac4061a5b | 168 | return EEPROM_FAIL; |
NirT | 1:e8fac4061a5b | 169 | } |
NirT | 1:e8fac4061a5b | 170 | } |
NirT | 1:e8fac4061a5b | 171 | return EEPROM_OK; |
NirT | 1:e8fac4061a5b | 172 | } |
NirT | 1:e8fac4061a5b | 173 | |
NirT | 1:e8fac4061a5b | 174 | /** |
NirT | 1:e8fac4061a5b | 175 | * @brief DeInitializes the EEPROM. |
NirT | 1:e8fac4061a5b | 176 | * @retval EEPROM state |
NirT | 1:e8fac4061a5b | 177 | */ |
NirT | 1:e8fac4061a5b | 178 | uint8_t BSP_EEPROM_DeInit(void) |
NirT | 1:e8fac4061a5b | 179 | { |
NirT | 1:e8fac4061a5b | 180 | /* I2C won't be disabled because common to other functionalities */ |
NirT | 1:e8fac4061a5b | 181 | return EEPROM_OK; |
NirT | 1:e8fac4061a5b | 182 | } |
NirT | 1:e8fac4061a5b | 183 | |
NirT | 1:e8fac4061a5b | 184 | /** |
NirT | 1:e8fac4061a5b | 185 | * @brief Reads a block of data from the EEPROM. |
NirT | 1:e8fac4061a5b | 186 | * @param pBuffer: pointer to the buffer that receives the data read from |
NirT | 1:e8fac4061a5b | 187 | * the EEPROM. |
NirT | 1:e8fac4061a5b | 188 | * @param ReadAddr: EEPROM's internal address to start reading from. |
NirT | 1:e8fac4061a5b | 189 | * @param NumByteToRead: pointer to the variable holding number of bytes to |
NirT | 1:e8fac4061a5b | 190 | * be read from the EEPROM. |
NirT | 1:e8fac4061a5b | 191 | * |
NirT | 1:e8fac4061a5b | 192 | * @note The variable pointed by NumByteToRead is reset to 0 when all the |
NirT | 1:e8fac4061a5b | 193 | * data are read from the EEPROM. Application should monitor this |
NirT | 1:e8fac4061a5b | 194 | * variable in order know when the transfer is complete. |
NirT | 1:e8fac4061a5b | 195 | * |
NirT | 1:e8fac4061a5b | 196 | * @retval EEPROM_OK (0) if operation is correctly performed, else return value |
NirT | 1:e8fac4061a5b | 197 | * different from EEPROM_OK (0) or the timeout user callback. |
NirT | 1:e8fac4061a5b | 198 | */ |
NirT | 1:e8fac4061a5b | 199 | uint32_t BSP_EEPROM_ReadBuffer(uint8_t* pBuffer, uint16_t ReadAddr, uint16_t* NumByteToRead) |
NirT | 1:e8fac4061a5b | 200 | { |
NirT | 1:e8fac4061a5b | 201 | uint32_t buffersize = *NumByteToRead; |
NirT | 1:e8fac4061a5b | 202 | |
NirT | 1:e8fac4061a5b | 203 | /* Set the pointer to the Number of data to be read. This pointer will be used |
NirT | 1:e8fac4061a5b | 204 | by the DMA Transfer Completer interrupt Handler in order to reset the |
NirT | 1:e8fac4061a5b | 205 | variable to 0. User should check on this variable in order to know if the |
NirT | 1:e8fac4061a5b | 206 | DMA transfer has been complete or not. */ |
NirT | 1:e8fac4061a5b | 207 | EEPROMDataRead = *NumByteToRead; |
NirT | 1:e8fac4061a5b | 208 | |
NirT | 1:e8fac4061a5b | 209 | if(EEPROM_IO_ReadData(EEPROMAddress, ReadAddr, pBuffer, buffersize) != HAL_OK) |
NirT | 1:e8fac4061a5b | 210 | { |
NirT | 1:e8fac4061a5b | 211 | BSP_EEPROM_TIMEOUT_UserCallback(); |
NirT | 1:e8fac4061a5b | 212 | return EEPROM_FAIL; |
NirT | 1:e8fac4061a5b | 213 | } |
NirT | 1:e8fac4061a5b | 214 | |
NirT | 1:e8fac4061a5b | 215 | /* If all operations OK, return EEPROM_OK (0) */ |
NirT | 1:e8fac4061a5b | 216 | return EEPROM_OK; |
NirT | 1:e8fac4061a5b | 217 | } |
NirT | 1:e8fac4061a5b | 218 | |
NirT | 1:e8fac4061a5b | 219 | /** |
NirT | 1:e8fac4061a5b | 220 | * @brief Writes more than one byte to the EEPROM with a single WRITE cycle. |
NirT | 1:e8fac4061a5b | 221 | * |
NirT | 1:e8fac4061a5b | 222 | * @note The number of bytes (combined to write start address) must not |
NirT | 1:e8fac4061a5b | 223 | * cross the EEPROM page boundary. This function can only write into |
NirT | 1:e8fac4061a5b | 224 | * the boundaries of an EEPROM page. |
NirT | 1:e8fac4061a5b | 225 | * This function doesn't check on boundaries condition (in this driver |
NirT | 1:e8fac4061a5b | 226 | * the function BSP_EEPROM_WriteBuffer() which calls BSP_EEPROM_WritePage() is |
NirT | 1:e8fac4061a5b | 227 | * responsible of checking on Page boundaries). |
NirT | 1:e8fac4061a5b | 228 | * |
NirT | 1:e8fac4061a5b | 229 | * @param pBuffer: pointer to the buffer containing the data to be written to |
NirT | 1:e8fac4061a5b | 230 | * the EEPROM. |
NirT | 1:e8fac4061a5b | 231 | * @param WriteAddr: EEPROM's internal address to write to. |
NirT | 1:e8fac4061a5b | 232 | * @param NumByteToWrite: pointer to the variable holding number of bytes to |
NirT | 1:e8fac4061a5b | 233 | * be written into the EEPROM. |
NirT | 1:e8fac4061a5b | 234 | * |
NirT | 1:e8fac4061a5b | 235 | * @note The variable pointed by NumByteToWrite is reset to 0 when all the |
NirT | 1:e8fac4061a5b | 236 | * data are written to the EEPROM. Application should monitor this |
NirT | 1:e8fac4061a5b | 237 | * variable in order know when the transfer is complete. |
NirT | 1:e8fac4061a5b | 238 | * |
NirT | 1:e8fac4061a5b | 239 | * @note This function just configure the communication and enable the DMA |
NirT | 1:e8fac4061a5b | 240 | * channel to transfer data. Meanwhile, the user application may perform |
NirT | 1:e8fac4061a5b | 241 | * other tasks in parallel. |
NirT | 1:e8fac4061a5b | 242 | * |
NirT | 1:e8fac4061a5b | 243 | * @retval EEPROM_OK (0) if operation is correctly performed, else return value |
NirT | 1:e8fac4061a5b | 244 | * different from EEPROM_OK (0) or the timeout user callback. |
NirT | 1:e8fac4061a5b | 245 | */ |
NirT | 1:e8fac4061a5b | 246 | uint32_t BSP_EEPROM_WritePage(uint8_t* pBuffer, uint16_t WriteAddr, uint8_t* NumByteToWrite) |
NirT | 1:e8fac4061a5b | 247 | { |
NirT | 1:e8fac4061a5b | 248 | uint32_t buffersize = *NumByteToWrite; |
NirT | 1:e8fac4061a5b | 249 | uint32_t status = EEPROM_OK; |
NirT | 1:e8fac4061a5b | 250 | |
NirT | 1:e8fac4061a5b | 251 | /* Set the pointer to the Number of data to be written. This pointer will be used |
NirT | 1:e8fac4061a5b | 252 | by the DMA Transfer Completer interrupt Handler in order to reset the |
NirT | 1:e8fac4061a5b | 253 | variable to 0. User should check on this variable in order to know if the |
NirT | 1:e8fac4061a5b | 254 | DMA transfer has been complete or not. */ |
NirT | 1:e8fac4061a5b | 255 | EEPROMDataWrite = *NumByteToWrite; |
NirT | 1:e8fac4061a5b | 256 | |
NirT | 1:e8fac4061a5b | 257 | if(EEPROM_IO_WriteData(EEPROMAddress, WriteAddr, pBuffer, buffersize) != HAL_OK) |
NirT | 1:e8fac4061a5b | 258 | { |
NirT | 1:e8fac4061a5b | 259 | BSP_EEPROM_TIMEOUT_UserCallback(); |
NirT | 1:e8fac4061a5b | 260 | status = EEPROM_FAIL; |
NirT | 1:e8fac4061a5b | 261 | } |
NirT | 1:e8fac4061a5b | 262 | |
NirT | 1:e8fac4061a5b | 263 | if(BSP_EEPROM_WaitEepromStandbyState() != EEPROM_OK) |
NirT | 1:e8fac4061a5b | 264 | { |
NirT | 1:e8fac4061a5b | 265 | return EEPROM_FAIL; |
NirT | 1:e8fac4061a5b | 266 | } |
NirT | 1:e8fac4061a5b | 267 | |
NirT | 1:e8fac4061a5b | 268 | /* If all operations OK, return EEPROM_OK (0) */ |
NirT | 1:e8fac4061a5b | 269 | return status; |
NirT | 1:e8fac4061a5b | 270 | } |
NirT | 1:e8fac4061a5b | 271 | |
NirT | 1:e8fac4061a5b | 272 | /** |
NirT | 1:e8fac4061a5b | 273 | * @brief Writes buffer of data to the I2C EEPROM. |
NirT | 1:e8fac4061a5b | 274 | * @param pBuffer: pointer to the buffer containing the data to be written |
NirT | 1:e8fac4061a5b | 275 | * to the EEPROM. |
NirT | 1:e8fac4061a5b | 276 | * @param WriteAddr: EEPROM's internal address to write to. |
NirT | 1:e8fac4061a5b | 277 | * @param NumByteToWrite: number of bytes to write to the EEPROM. |
NirT | 1:e8fac4061a5b | 278 | * @retval EEPROM_OK (0) if operation is correctly performed, else return value |
NirT | 1:e8fac4061a5b | 279 | * different from EEPROM_OK (0) or the timeout user callback. |
NirT | 1:e8fac4061a5b | 280 | */ |
NirT | 1:e8fac4061a5b | 281 | uint32_t BSP_EEPROM_WriteBuffer(uint8_t *pBuffer, uint16_t WriteAddr, uint16_t NumByteToWrite) |
NirT | 1:e8fac4061a5b | 282 | { |
NirT | 1:e8fac4061a5b | 283 | uint16_t numofpage = 0, numofsingle = 0, count = 0; |
NirT | 1:e8fac4061a5b | 284 | uint16_t addr = 0; |
NirT | 1:e8fac4061a5b | 285 | uint8_t dataindex = 0; |
NirT | 1:e8fac4061a5b | 286 | uint32_t status = EEPROM_OK; |
NirT | 1:e8fac4061a5b | 287 | |
NirT | 1:e8fac4061a5b | 288 | addr = WriteAddr % EEPROM_PAGESIZE; |
NirT | 1:e8fac4061a5b | 289 | count = EEPROM_PAGESIZE - addr; |
NirT | 1:e8fac4061a5b | 290 | numofpage = NumByteToWrite / EEPROM_PAGESIZE; |
NirT | 1:e8fac4061a5b | 291 | numofsingle = NumByteToWrite % EEPROM_PAGESIZE; |
NirT | 1:e8fac4061a5b | 292 | |
NirT | 1:e8fac4061a5b | 293 | /* If WriteAddr is EEPROM_PAGESIZE aligned */ |
NirT | 1:e8fac4061a5b | 294 | if(addr == 0) |
NirT | 1:e8fac4061a5b | 295 | { |
NirT | 1:e8fac4061a5b | 296 | /* If NumByteToWrite < EEPROM_PAGESIZE */ |
NirT | 1:e8fac4061a5b | 297 | if(numofpage == 0) |
NirT | 1:e8fac4061a5b | 298 | { |
NirT | 1:e8fac4061a5b | 299 | /* Store the number of data to be written */ |
NirT | 1:e8fac4061a5b | 300 | dataindex = numofsingle; |
NirT | 1:e8fac4061a5b | 301 | /* Start writing data */ |
NirT | 1:e8fac4061a5b | 302 | status = BSP_EEPROM_WritePage(pBuffer, WriteAddr, (uint8_t*)(&dataindex)); |
NirT | 1:e8fac4061a5b | 303 | if(status != EEPROM_OK) |
NirT | 1:e8fac4061a5b | 304 | { |
NirT | 1:e8fac4061a5b | 305 | return status; |
NirT | 1:e8fac4061a5b | 306 | } |
NirT | 1:e8fac4061a5b | 307 | } |
NirT | 1:e8fac4061a5b | 308 | /* If NumByteToWrite > EEPROM_PAGESIZE */ |
NirT | 1:e8fac4061a5b | 309 | else |
NirT | 1:e8fac4061a5b | 310 | { |
NirT | 1:e8fac4061a5b | 311 | while(numofpage--) |
NirT | 1:e8fac4061a5b | 312 | { |
NirT | 1:e8fac4061a5b | 313 | /* Store the number of data to be written */ |
NirT | 1:e8fac4061a5b | 314 | dataindex = EEPROM_PAGESIZE; |
NirT | 1:e8fac4061a5b | 315 | status = BSP_EEPROM_WritePage(pBuffer, WriteAddr, (uint8_t*)(&dataindex)); |
NirT | 1:e8fac4061a5b | 316 | if(status != EEPROM_OK) |
NirT | 1:e8fac4061a5b | 317 | { |
NirT | 1:e8fac4061a5b | 318 | return status; |
NirT | 1:e8fac4061a5b | 319 | } |
NirT | 1:e8fac4061a5b | 320 | |
NirT | 1:e8fac4061a5b | 321 | WriteAddr += EEPROM_PAGESIZE; |
NirT | 1:e8fac4061a5b | 322 | pBuffer += EEPROM_PAGESIZE; |
NirT | 1:e8fac4061a5b | 323 | } |
NirT | 1:e8fac4061a5b | 324 | |
NirT | 1:e8fac4061a5b | 325 | if(numofsingle!=0) |
NirT | 1:e8fac4061a5b | 326 | { |
NirT | 1:e8fac4061a5b | 327 | /* Store the number of data to be written */ |
NirT | 1:e8fac4061a5b | 328 | dataindex = numofsingle; |
NirT | 1:e8fac4061a5b | 329 | status = BSP_EEPROM_WritePage(pBuffer, WriteAddr, (uint8_t*)(&dataindex)); |
NirT | 1:e8fac4061a5b | 330 | if(status != EEPROM_OK) |
NirT | 1:e8fac4061a5b | 331 | { |
NirT | 1:e8fac4061a5b | 332 | return status; |
NirT | 1:e8fac4061a5b | 333 | } |
NirT | 1:e8fac4061a5b | 334 | } |
NirT | 1:e8fac4061a5b | 335 | } |
NirT | 1:e8fac4061a5b | 336 | } |
NirT | 1:e8fac4061a5b | 337 | /* If WriteAddr is not EEPROM_PAGESIZE aligned */ |
NirT | 1:e8fac4061a5b | 338 | else |
NirT | 1:e8fac4061a5b | 339 | { |
NirT | 1:e8fac4061a5b | 340 | /* If NumByteToWrite < EEPROM_PAGESIZE */ |
NirT | 1:e8fac4061a5b | 341 | if(numofpage== 0) |
NirT | 1:e8fac4061a5b | 342 | { |
NirT | 1:e8fac4061a5b | 343 | /* If the number of data to be written is more than the remaining space |
NirT | 1:e8fac4061a5b | 344 | in the current page: */ |
NirT | 1:e8fac4061a5b | 345 | if(NumByteToWrite > count) |
NirT | 1:e8fac4061a5b | 346 | { |
NirT | 1:e8fac4061a5b | 347 | /* Store the number of data to be written */ |
NirT | 1:e8fac4061a5b | 348 | dataindex = count; |
NirT | 1:e8fac4061a5b | 349 | /* Write the data contained in same page */ |
NirT | 1:e8fac4061a5b | 350 | status = BSP_EEPROM_WritePage(pBuffer, WriteAddr, (uint8_t*)(&dataindex)); |
NirT | 1:e8fac4061a5b | 351 | if(status != EEPROM_OK) |
NirT | 1:e8fac4061a5b | 352 | { |
NirT | 1:e8fac4061a5b | 353 | return status; |
NirT | 1:e8fac4061a5b | 354 | } |
NirT | 1:e8fac4061a5b | 355 | |
NirT | 1:e8fac4061a5b | 356 | /* Store the number of data to be written */ |
NirT | 1:e8fac4061a5b | 357 | dataindex = (NumByteToWrite - count); |
NirT | 1:e8fac4061a5b | 358 | /* Write the remaining data in the following page */ |
NirT | 1:e8fac4061a5b | 359 | status = BSP_EEPROM_WritePage((uint8_t*)(pBuffer + count), (WriteAddr + count), (uint8_t*)(&dataindex)); |
NirT | 1:e8fac4061a5b | 360 | if(status != EEPROM_OK) |
NirT | 1:e8fac4061a5b | 361 | { |
NirT | 1:e8fac4061a5b | 362 | return status; |
NirT | 1:e8fac4061a5b | 363 | } |
NirT | 1:e8fac4061a5b | 364 | } |
NirT | 1:e8fac4061a5b | 365 | else |
NirT | 1:e8fac4061a5b | 366 | { |
NirT | 1:e8fac4061a5b | 367 | /* Store the number of data to be written */ |
NirT | 1:e8fac4061a5b | 368 | dataindex = numofsingle; |
NirT | 1:e8fac4061a5b | 369 | status = BSP_EEPROM_WritePage(pBuffer, WriteAddr, (uint8_t*)(&dataindex)); |
NirT | 1:e8fac4061a5b | 370 | if(status != EEPROM_OK) |
NirT | 1:e8fac4061a5b | 371 | { |
NirT | 1:e8fac4061a5b | 372 | return status; |
NirT | 1:e8fac4061a5b | 373 | } |
NirT | 1:e8fac4061a5b | 374 | } |
NirT | 1:e8fac4061a5b | 375 | } |
NirT | 1:e8fac4061a5b | 376 | /* If NumByteToWrite > EEPROM_PAGESIZE */ |
NirT | 1:e8fac4061a5b | 377 | else |
NirT | 1:e8fac4061a5b | 378 | { |
NirT | 1:e8fac4061a5b | 379 | NumByteToWrite -= count; |
NirT | 1:e8fac4061a5b | 380 | numofpage = NumByteToWrite / EEPROM_PAGESIZE; |
NirT | 1:e8fac4061a5b | 381 | numofsingle = NumByteToWrite % EEPROM_PAGESIZE; |
NirT | 1:e8fac4061a5b | 382 | |
NirT | 1:e8fac4061a5b | 383 | if(count != 0) |
NirT | 1:e8fac4061a5b | 384 | { |
NirT | 1:e8fac4061a5b | 385 | /* Store the number of data to be written */ |
NirT | 1:e8fac4061a5b | 386 | dataindex = count; |
NirT | 1:e8fac4061a5b | 387 | status = BSP_EEPROM_WritePage(pBuffer, WriteAddr, (uint8_t*)(&dataindex)); |
NirT | 1:e8fac4061a5b | 388 | if(status != EEPROM_OK) |
NirT | 1:e8fac4061a5b | 389 | { |
NirT | 1:e8fac4061a5b | 390 | return status; |
NirT | 1:e8fac4061a5b | 391 | } |
NirT | 1:e8fac4061a5b | 392 | WriteAddr += count; |
NirT | 1:e8fac4061a5b | 393 | pBuffer += count; |
NirT | 1:e8fac4061a5b | 394 | } |
NirT | 1:e8fac4061a5b | 395 | |
NirT | 1:e8fac4061a5b | 396 | while(numofpage--) |
NirT | 1:e8fac4061a5b | 397 | { |
NirT | 1:e8fac4061a5b | 398 | /* Store the number of data to be written */ |
NirT | 1:e8fac4061a5b | 399 | dataindex = EEPROM_PAGESIZE; |
NirT | 1:e8fac4061a5b | 400 | status = BSP_EEPROM_WritePage(pBuffer, WriteAddr, (uint8_t*)(&dataindex)); |
NirT | 1:e8fac4061a5b | 401 | if(status != EEPROM_OK) |
NirT | 1:e8fac4061a5b | 402 | { |
NirT | 1:e8fac4061a5b | 403 | return status; |
NirT | 1:e8fac4061a5b | 404 | } |
NirT | 1:e8fac4061a5b | 405 | WriteAddr += EEPROM_PAGESIZE; |
NirT | 1:e8fac4061a5b | 406 | pBuffer += EEPROM_PAGESIZE; |
NirT | 1:e8fac4061a5b | 407 | } |
NirT | 1:e8fac4061a5b | 408 | if(numofsingle != 0) |
NirT | 1:e8fac4061a5b | 409 | { |
NirT | 1:e8fac4061a5b | 410 | /* Store the number of data to be written */ |
NirT | 1:e8fac4061a5b | 411 | dataindex = numofsingle; |
NirT | 1:e8fac4061a5b | 412 | status = BSP_EEPROM_WritePage(pBuffer, WriteAddr, (uint8_t*)(&dataindex)); |
NirT | 1:e8fac4061a5b | 413 | if(status != EEPROM_OK) |
NirT | 1:e8fac4061a5b | 414 | { |
NirT | 1:e8fac4061a5b | 415 | return status; |
NirT | 1:e8fac4061a5b | 416 | } |
NirT | 1:e8fac4061a5b | 417 | } |
NirT | 1:e8fac4061a5b | 418 | } |
NirT | 1:e8fac4061a5b | 419 | } |
NirT | 1:e8fac4061a5b | 420 | |
NirT | 1:e8fac4061a5b | 421 | /* If all operations OK, return EEPROM_OK (0) */ |
NirT | 1:e8fac4061a5b | 422 | return EEPROM_OK; |
NirT | 1:e8fac4061a5b | 423 | } |
NirT | 1:e8fac4061a5b | 424 | |
NirT | 1:e8fac4061a5b | 425 | /** |
NirT | 1:e8fac4061a5b | 426 | * @brief Wait for EEPROM Standby state. |
NirT | 1:e8fac4061a5b | 427 | * |
NirT | 1:e8fac4061a5b | 428 | * @note This function allows to wait and check that EEPROM has finished the |
NirT | 1:e8fac4061a5b | 429 | * last operation. It is mostly used after Write operation: after receiving |
NirT | 1:e8fac4061a5b | 430 | * the buffer to be written, the EEPROM may need additional time to actually |
NirT | 1:e8fac4061a5b | 431 | * perform the write operation. During this time, it doesn't answer to |
NirT | 1:e8fac4061a5b | 432 | * I2C packets addressed to it. Once the write operation is complete |
NirT | 1:e8fac4061a5b | 433 | * the EEPROM responds to its address. |
NirT | 1:e8fac4061a5b | 434 | * |
NirT | 1:e8fac4061a5b | 435 | * @retval EEPROM_OK (0) if operation is correctly performed, else return value |
NirT | 1:e8fac4061a5b | 436 | * different from EEPROM_OK (0) or the timeout user callback. |
NirT | 1:e8fac4061a5b | 437 | */ |
NirT | 1:e8fac4061a5b | 438 | uint32_t BSP_EEPROM_WaitEepromStandbyState(void) |
NirT | 1:e8fac4061a5b | 439 | { |
NirT | 1:e8fac4061a5b | 440 | /* Check if the maximum allowed number of trials has bee reached */ |
NirT | 1:e8fac4061a5b | 441 | if(EEPROM_IO_IsDeviceReady(EEPROMAddress, EEPROM_MAX_TRIALS) != HAL_OK) |
NirT | 1:e8fac4061a5b | 442 | { |
NirT | 1:e8fac4061a5b | 443 | /* If the maximum number of trials has been reached, exit the function */ |
NirT | 1:e8fac4061a5b | 444 | BSP_EEPROM_TIMEOUT_UserCallback(); |
NirT | 1:e8fac4061a5b | 445 | return EEPROM_TIMEOUT; |
NirT | 1:e8fac4061a5b | 446 | } |
NirT | 1:e8fac4061a5b | 447 | return EEPROM_OK; |
NirT | 1:e8fac4061a5b | 448 | } |
NirT | 1:e8fac4061a5b | 449 | |
NirT | 1:e8fac4061a5b | 450 | /** |
NirT | 1:e8fac4061a5b | 451 | * @brief Basic management of the timeout situation. |
NirT | 1:e8fac4061a5b | 452 | * @retval None |
NirT | 1:e8fac4061a5b | 453 | */ |
NirT | 1:e8fac4061a5b | 454 | __weak void BSP_EEPROM_TIMEOUT_UserCallback(void) |
NirT | 1:e8fac4061a5b | 455 | { |
NirT | 1:e8fac4061a5b | 456 | } |
NirT | 1:e8fac4061a5b | 457 | |
NirT | 1:e8fac4061a5b | 458 | /** |
NirT | 1:e8fac4061a5b | 459 | * @} |
NirT | 1:e8fac4061a5b | 460 | */ |
NirT | 1:e8fac4061a5b | 461 | |
NirT | 1:e8fac4061a5b | 462 | /** |
NirT | 1:e8fac4061a5b | 463 | * @} |
NirT | 1:e8fac4061a5b | 464 | */ |
NirT | 1:e8fac4061a5b | 465 | |
NirT | 1:e8fac4061a5b | 466 | /** |
NirT | 1:e8fac4061a5b | 467 | * @} |
NirT | 1:e8fac4061a5b | 468 | */ |
NirT | 1:e8fac4061a5b | 469 | |
NirT | 1:e8fac4061a5b | 470 | /** |
NirT | 1:e8fac4061a5b | 471 | * @} |
NirT | 1:e8fac4061a5b | 472 | */ |
NirT | 1:e8fac4061a5b | 473 | |
NirT | 1:e8fac4061a5b | 474 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
NirT | 1:e8fac4061a5b | 475 |