The SZ / BSP_DISCO_F746NG_patch_fixed

bugfixes and reduced version for disco board only

Dependents:   Scope DISCO-F746NG_Sinewave DISCO-F746NG_Sweep DISCO-F746NG_Oscilloscope ... more

Fork of BSP_DISCO_F746NG_patch by Nirvana Jay

stm32746g_discovery_qspi.h@7:a4e658110084, 2016-01-31 (annotated)

Committer:
the_sz
Date:
Sun Jan 31 17:45:21 2016 +0000
Revision:
7:a4e658110084
Parent:
1:e8fac4061a5b 
remove debug line

Who changed what in which revision?

UserRevisionLine numberNew contents of line
NirT 1:e8fac4061a5b 1 /**
NirT 1:e8fac4061a5b 2 ******************************************************************************
NirT 1:e8fac4061a5b 3 * @file stm32746g_discovery_qspi.h
NirT 1:e8fac4061a5b 4 * @author MCD Application Team
NirT 1:e8fac4061a5b 5 * @version V1.0.0
NirT 1:e8fac4061a5b 6 * @date 25-June-2015
NirT 1:e8fac4061a5b 7 * @brief This file contains the common defines and functions prototypes for
NirT 1:e8fac4061a5b 8 * the stm32746g_discovery_qspi.c driver.
NirT 1:e8fac4061a5b 9 ******************************************************************************
NirT 1:e8fac4061a5b 10 * @attention
NirT 1:e8fac4061a5b 11 *
NirT 1:e8fac4061a5b 12 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
NirT 1:e8fac4061a5b 13 *
NirT 1:e8fac4061a5b 14 * Redistribution and use in source and binary forms, with or without modification,
NirT 1:e8fac4061a5b 15 * are permitted provided that the following conditions are met:
NirT 1:e8fac4061a5b 16 * 1. Redistributions of source code must retain the above copyright notice,
NirT 1:e8fac4061a5b 17 * this list of conditions and the following disclaimer.
NirT 1:e8fac4061a5b 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
NirT 1:e8fac4061a5b 19 * this list of conditions and the following disclaimer in the documentation
NirT 1:e8fac4061a5b 20 * and/or other materials provided with the distribution.
NirT 1:e8fac4061a5b 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
NirT 1:e8fac4061a5b 22 * may be used to endorse or promote products derived from this software
NirT 1:e8fac4061a5b 23 * without specific prior written permission.
NirT 1:e8fac4061a5b 24 *
NirT 1:e8fac4061a5b 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
NirT 1:e8fac4061a5b 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
NirT 1:e8fac4061a5b 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
NirT 1:e8fac4061a5b 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
NirT 1:e8fac4061a5b 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
NirT 1:e8fac4061a5b 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
NirT 1:e8fac4061a5b 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
NirT 1:e8fac4061a5b 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
NirT 1:e8fac4061a5b 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
NirT 1:e8fac4061a5b 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
NirT 1:e8fac4061a5b 35 *
NirT 1:e8fac4061a5b 36 ******************************************************************************
NirT 1:e8fac4061a5b 37 */
NirT 1:e8fac4061a5b 38
NirT 1:e8fac4061a5b 39 /** @addtogroup BSP
NirT 1:e8fac4061a5b 40 * @{
NirT 1:e8fac4061a5b 41 */
NirT 1:e8fac4061a5b 42
NirT 1:e8fac4061a5b 43 /** @addtogroup STM32746G_DISCOVERY
NirT 1:e8fac4061a5b 44 * @{
NirT 1:e8fac4061a5b 45 */
NirT 1:e8fac4061a5b 46
NirT 1:e8fac4061a5b 47 /* Define to prevent recursive inclusion -------------------------------------*/
NirT 1:e8fac4061a5b 48 #ifndef __STM32746G_DISCOVERY_QSPI_H
NirT 1:e8fac4061a5b 49 #define __STM32746G_DISCOVERY_QSPI_H
NirT 1:e8fac4061a5b 50
NirT 1:e8fac4061a5b 51 #ifdef __cplusplus
NirT 1:e8fac4061a5b 52 extern "C" {
NirT 1:e8fac4061a5b 53 #endif
NirT 1:e8fac4061a5b 54
NirT 1:e8fac4061a5b 55 /* Includes ------------------------------------------------------------------*/
NirT 1:e8fac4061a5b 56 #include "stm32f7xx_hal.h"
NirT 1:e8fac4061a5b 57 #include "../Components/n25q128a/n25q128a.h"
NirT 1:e8fac4061a5b 58
NirT 1:e8fac4061a5b 59 /** @addtogroup STM32746G_DISCOVERY_QSPI
NirT 1:e8fac4061a5b 60 * @{
NirT 1:e8fac4061a5b 61 */
NirT 1:e8fac4061a5b 62
NirT 1:e8fac4061a5b 63
NirT 1:e8fac4061a5b 64 /* Exported constants --------------------------------------------------------*/
NirT 1:e8fac4061a5b 65 /** @defgroup STM32746G_DISCOVERY_QSPI_Exported_Constants STM32746G_DISCOVERY_QSPI Exported Constants
NirT 1:e8fac4061a5b 66 * @{
NirT 1:e8fac4061a5b 67 */
NirT 1:e8fac4061a5b 68 /* QSPI Error codes */
NirT 1:e8fac4061a5b 69 #define QSPI_OK ((uint8_t)0x00)
NirT 1:e8fac4061a5b 70 #define QSPI_ERROR ((uint8_t)0x01)
NirT 1:e8fac4061a5b 71 #define QSPI_BUSY ((uint8_t)0x02)
NirT 1:e8fac4061a5b 72 #define QSPI_NOT_SUPPORTED ((uint8_t)0x04)
NirT 1:e8fac4061a5b 73 #define QSPI_SUSPENDED ((uint8_t)0x08)
NirT 1:e8fac4061a5b 74
NirT 1:e8fac4061a5b 75
NirT 1:e8fac4061a5b 76 /* Definition for QSPI clock resources */
NirT 1:e8fac4061a5b 77 #define QSPI_CLK_ENABLE() __HAL_RCC_QSPI_CLK_ENABLE()
NirT 1:e8fac4061a5b 78 #define QSPI_CLK_DISABLE() __HAL_RCC_QSPI_CLK_DISABLE()
NirT 1:e8fac4061a5b 79 #define QSPI_CS_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
NirT 1:e8fac4061a5b 80 #define QSPI_CLK_GPIO_CLK_ENABLE() __HAL_RCC_GPIOB_CLK_ENABLE()
NirT 1:e8fac4061a5b 81 #define QSPI_D0_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
NirT 1:e8fac4061a5b 82 #define QSPI_D1_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
NirT 1:e8fac4061a5b 83 #define QSPI_D2_GPIO_CLK_ENABLE() __HAL_RCC_GPIOE_CLK_ENABLE()
NirT 1:e8fac4061a5b 84 #define QSPI_D3_GPIO_CLK_ENABLE() __HAL_RCC_GPIOD_CLK_ENABLE()
NirT 1:e8fac4061a5b 85
NirT 1:e8fac4061a5b 86 #define QSPI_FORCE_RESET() __HAL_RCC_QSPI_FORCE_RESET()
NirT 1:e8fac4061a5b 87 #define QSPI_RELEASE_RESET() __HAL_RCC_QSPI_RELEASE_RESET()
NirT 1:e8fac4061a5b 88
NirT 1:e8fac4061a5b 89 /* Definition for QSPI Pins */
NirT 1:e8fac4061a5b 90 #define QSPI_CS_PIN GPIO_PIN_6
NirT 1:e8fac4061a5b 91 #define QSPI_CS_GPIO_PORT GPIOB
NirT 1:e8fac4061a5b 92 #define QSPI_CLK_PIN GPIO_PIN_2
NirT 1:e8fac4061a5b 93 #define QSPI_CLK_GPIO_PORT GPIOB
NirT 1:e8fac4061a5b 94 #define QSPI_D0_PIN GPIO_PIN_11
NirT 1:e8fac4061a5b 95 #define QSPI_D0_GPIO_PORT GPIOD
NirT 1:e8fac4061a5b 96 #define QSPI_D1_PIN GPIO_PIN_12
NirT 1:e8fac4061a5b 97 #define QSPI_D1_GPIO_PORT GPIOD
NirT 1:e8fac4061a5b 98 #define QSPI_D2_PIN GPIO_PIN_2
NirT 1:e8fac4061a5b 99 #define QSPI_D2_GPIO_PORT GPIOE
NirT 1:e8fac4061a5b 100 #define QSPI_D3_PIN GPIO_PIN_13
NirT 1:e8fac4061a5b 101 #define QSPI_D3_GPIO_PORT GPIOD
NirT 1:e8fac4061a5b 102
NirT 1:e8fac4061a5b 103 /* N25Q128A13EF840E Micron memory */
NirT 1:e8fac4061a5b 104 /* Size of the flash */
NirT 1:e8fac4061a5b 105 #define QSPI_FLASH_SIZE 23 /* Address bus width to access whole memory space */
NirT 1:e8fac4061a5b 106 #define QSPI_PAGE_SIZE 256
NirT 1:e8fac4061a5b 107
NirT 1:e8fac4061a5b 108 /**
NirT 1:e8fac4061a5b 109 * @}
NirT 1:e8fac4061a5b 110 */
NirT 1:e8fac4061a5b 111
NirT 1:e8fac4061a5b 112 /* Exported types ------------------------------------------------------------*/
NirT 1:e8fac4061a5b 113 /** @defgroup STM32746G_DISCOVERY_QSPI_Exported_Types STM32746G_DISCOVERY_QSPI Exported Types
NirT 1:e8fac4061a5b 114 * @{
NirT 1:e8fac4061a5b 115 */
NirT 1:e8fac4061a5b 116 /* QSPI Info */
NirT 1:e8fac4061a5b 117 typedef struct {
NirT 1:e8fac4061a5b 118 uint32_t FlashSize; /*!< Size of the flash */
NirT 1:e8fac4061a5b 119 uint32_t EraseSectorSize; /*!< Size of sectors for the erase operation */
NirT 1:e8fac4061a5b 120 uint32_t EraseSectorsNumber; /*!< Number of sectors for the erase operation */
NirT 1:e8fac4061a5b 121 uint32_t ProgPageSize; /*!< Size of pages for the program operation */
NirT 1:e8fac4061a5b 122 uint32_t ProgPagesNumber; /*!< Number of pages for the program operation */
NirT 1:e8fac4061a5b 123 } QSPI_Info;
NirT 1:e8fac4061a5b 124
NirT 1:e8fac4061a5b 125 /**
NirT 1:e8fac4061a5b 126 * @}
NirT 1:e8fac4061a5b 127 */
NirT 1:e8fac4061a5b 128
NirT 1:e8fac4061a5b 129
NirT 1:e8fac4061a5b 130 /* Exported functions --------------------------------------------------------*/
NirT 1:e8fac4061a5b 131 /** @addtogroup STM32746G_DISCOVERY_QSPI_Exported_Functions
NirT 1:e8fac4061a5b 132 * @{
NirT 1:e8fac4061a5b 133 */
NirT 1:e8fac4061a5b 134 uint8_t BSP_QSPI_Init (void);
NirT 1:e8fac4061a5b 135 uint8_t BSP_QSPI_DeInit (void);
NirT 1:e8fac4061a5b 136 uint8_t BSP_QSPI_Read (uint8_t* pData, uint32_t ReadAddr, uint32_t Size);
NirT 1:e8fac4061a5b 137 uint8_t BSP_QSPI_Write (uint8_t* pData, uint32_t WriteAddr, uint32_t Size);
NirT 1:e8fac4061a5b 138 uint8_t BSP_QSPI_Erase_Block(uint32_t BlockAddress);
NirT 1:e8fac4061a5b 139 uint8_t BSP_QSPI_Erase_Chip (void);
NirT 1:e8fac4061a5b 140 uint8_t BSP_QSPI_GetStatus (void);
NirT 1:e8fac4061a5b 141 uint8_t BSP_QSPI_GetInfo (QSPI_Info* pInfo);
NirT 1:e8fac4061a5b 142 uint8_t BSP_QSPI_MemoryMappedMode(void);
NirT 1:e8fac4061a5b 143
NirT 1:e8fac4061a5b 144 /* These functions can be modified in case the current settings
NirT 1:e8fac4061a5b 145 need to be changed for specific application needs */
NirT 1:e8fac4061a5b 146 void BSP_QSPI_MspInit(QSPI_HandleTypeDef *hqspi, void *Params);
NirT 1:e8fac4061a5b 147 void BSP_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi, void *Params);
NirT 1:e8fac4061a5b 148
NirT 1:e8fac4061a5b 149 /**
NirT 1:e8fac4061a5b 150 * @}
NirT 1:e8fac4061a5b 151 */
NirT 1:e8fac4061a5b 152
NirT 1:e8fac4061a5b 153 /**
NirT 1:e8fac4061a5b 154 * @}
NirT 1:e8fac4061a5b 155 */
NirT 1:e8fac4061a5b 156
NirT 1:e8fac4061a5b 157 #ifdef __cplusplus
NirT 1:e8fac4061a5b 158 }
NirT 1:e8fac4061a5b 159 #endif
NirT 1:e8fac4061a5b 160
NirT 1:e8fac4061a5b 161 #endif /* __STM32746G_DISCOVERY_QSPI_H */
NirT 1:e8fac4061a5b 162 /**
NirT 1:e8fac4061a5b 163 * @}
NirT 1:e8fac4061a5b 164 */
NirT 1:e8fac4061a5b 165
NirT 1:e8fac4061a5b 166 /**
NirT 1:e8fac4061a5b 167 * @}
NirT 1:e8fac4061a5b 168 */
NirT 1:e8fac4061a5b 169
NirT 1:e8fac4061a5b 170 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
NirT 1:e8fac4061a5b 171