Ted Grosch / Mbed 2 deprecated Nucleo_TOF_I2C_DISCO

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OPT3101device_RegisterMap.cpp@0:62b846b3988a, 2020-10-25 (annotated)

Committer:
tgrosch
Date:
Sun Oct 25 00:58:24 2020 +0000
Revision:
0:62b846b3988a
First successful compile.

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tgrosch 0:62b846b3988a 1 /*!
tgrosch 0:62b846b3988a 2 * \file OPT3101device_RegisterMap.cpp
tgrosch 0:62b846b3988a 3 * \author Karthik Rajagopal <krthik@ti.com>
tgrosch 0:62b846b3988a 4 * \version 0.9.1
tgrosch 0:62b846b3988a 5 *
tgrosch 0:62b846b3988a 6 * \section COPYRIGHT
tgrosch 0:62b846b3988a 7 * TEXAS INSTRUMENTS TEXT FILE LICENSE
tgrosch 0:62b846b3988a 8 * Copyright (c) 2018 Texas Instruments Incorporated
tgrosch 0:62b846b3988a 9 * All rights reserved not granted herein.
tgrosch 0:62b846b3988a 10 * Limited License.
tgrosch 0:62b846b3988a 11 * Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive license under copyrights and patents it now or hereafter owns or controls to make, have made, use, import, offer to sell and sell ("Utilize") this software subject to the terms herein. With respect to the foregoing patent license, such license is granted solely to the extent that any such patent is necessary to Utilize the software alone. The patent license shall not apply to any combinations which include this software, other than combinations with devices manufactured by or for TI ("TI Devices"). No hardware patent is licensed hereunder.
tgrosch 0:62b846b3988a 12 * Redistributions must preserve existing copyright notices and reproduce this license (including the above copyright notice and the disclaimer and (if applicable) source code license limitations below) in the documentation and/or other materials provided with the distribution
tgrosch 0:62b846b3988a 13 * Redistribution and use in binary form, without modification, are permitted provided that the following conditions are met:
tgrosch 0:62b846b3988a 14 * * No reverse engineering, decompilation, or disassembly of this software is permitted with respect to any software provided in binary form.
tgrosch 0:62b846b3988a 15 * * any redistribution and use are licensed by TI for use only with TI Devices.
tgrosch 0:62b846b3988a 16 * * Nothing shall obligate TI to provide you with source code for the software licensed and provided to you in object code.
tgrosch 0:62b846b3988a 17 * If software source code is provided to you, modification and redistribution of the source code are permitted provided that the following conditions are met:
tgrosch 0:62b846b3988a 18 * * any redistribution and use of the source code, including any resulting derivative works, are licensed by TI for use only with TI Devices.
tgrosch 0:62b846b3988a 19 * * any redistribution and use of any object code compiled from the source code and any resulting derivative works, are licensed by TI for use only with TI Devices.
tgrosch 0:62b846b3988a 20 * Neither the name of Texas Instruments Incorporated nor the names of its suppliers may be used to endorse or promote products derived from this software without specific prior written permission.
tgrosch 0:62b846b3988a 21 * DISCLAIMER.
tgrosch 0:62b846b3988a 22 * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
tgrosch 0:62b846b3988a 23 *
tgrosch 0:62b846b3988a 24 * \section DESCRIPTION
tgrosch 0:62b846b3988a 25 * The file contains OPT3101::registers class constructor and assignment
tgrosch 0:62b846b3988a 26 */
tgrosch 0:62b846b3988a 27
tgrosch 0:62b846b3988a 28 #include "OPT3101RegisterDefinition.h"
tgrosch 0:62b846b3988a 29
tgrosch 0:62b846b3988a 30 OPT3101::registers::registers() :
tgrosch 0:62b846b3988a 31 dig_gpo_sel0(1), ///< dig_gpo_sel0;Register Addresses: 11[3:0];
tgrosch 0:62b846b3988a 32 dig_gpo_sel1(1), ///< dig_gpo_sel1;Register Addresses: 11[7:4];
tgrosch 0:62b846b3988a 33 dig_gpo_sel2(1), ///< dig_gpo_sel2;Register Addresses: 11[13:10];
tgrosch 0:62b846b3988a 34 dis_ovl_gating(1), ///< dis_ovl_gating;Register Addresses: 17[15:15];
tgrosch 0:62b846b3988a 35 phase_out(1), ///< phase_out;Register Addresses: 8[15:0];
tgrosch 0:62b846b3988a 36 phase_overflow(1), ///< phase_overflow;Register Addresses: 8[16:16];
tgrosch 0:62b846b3988a 37 hdr_mode(1), ///< hdr_mode;Register Addresses: 8[17:17];
tgrosch 0:62b846b3988a 38 tx_channel(1), ///< tx_channel;Register Addresses: 8[19:18];
tgrosch 0:62b846b3988a 39 frame_status(1), ///< frame_status;Register Addresses: 8[20:20];
tgrosch 0:62b846b3988a 40 mod_freq(1), ///< mod_freq;Register Addresses: 8[21:21];
tgrosch 0:62b846b3988a 41 frame_count0(1), ///< frame_count0;Register Addresses: 8[23:23];
tgrosch 0:62b846b3988a 42 amp_out(1), ///< amp_out;Register Addresses: 9[15:0];
tgrosch 0:62b846b3988a 43 frame_count1(1), ///< frame_count1;Register Addresses: 9[17:16];
tgrosch 0:62b846b3988a 44 sig_ovl_flag(1), ///< sig_ovl_flag;Register Addresses: 9[18:18];
tgrosch 0:62b846b3988a 45 dealias_bin(1), ///< dealias_bin;Register Addresses: 9[23:20];
tgrosch 0:62b846b3988a 46 frame_count2(1), ///< frame_count2;Register Addresses: 10[1:0];
tgrosch 0:62b846b3988a 47 amb_data(1), ///< amb_data;Register Addresses: 10[11:2];
tgrosch 0:62b846b3988a 48 tmain(1), ///< tmain;Register Addresses: 10[23:12];
tgrosch 0:62b846b3988a 49 amplitude_min_thr(2), ///< amplitude_min_thr;Register Addresses: 16[23:16], 17[23:16];
tgrosch 0:62b846b3988a 50 amb_ovl_flag(1), ///< amb_ovl_flag;Register Addresses: 8[22:22];
tgrosch 0:62b846b3988a 51 phase_overflow_f2(1), ///< phase_overflow_f2;Register Addresses: 9[19:19];
tgrosch 0:62b846b3988a 52 ref_count_limit(1), ///< ref_count_limit;Register Addresses: 15[14:0];this sets the limit of ref-clock count when meth1 is used. By programming this we no longer require frequencies which are multiples of powers of 2.;;The default is calculated for 32.768 Khz.
tgrosch 0:62b846b3988a 53 start_freq_calib(1), ///< start_freq_calib;Register Addresses: 15[16:16];starts the freq_calib
tgrosch 0:62b846b3988a 54 sys_clk_divider(1), ///< sys_clk_divider;Register Addresses: 15[20:17];The divider can be set according to the ratio b/w ref_clk and tg_clk. The default is 2 which means default ref_clk is assumed at 10 Mhz. ie 40Mhz/4
tgrosch 0:62b846b3988a 55 freq_count_read_reg(1), ///< freq_count_read_reg;Register Addresses: 16[14:0];read register which holds the value of freq_loop.
tgrosch 0:62b846b3988a 56 freq_count_reg(1), ///< freq_count_reg;Register Addresses: 17[14:0];The register which is used for frequency correction when enable_auto_freq_count = '0'
tgrosch 0:62b846b3988a 57 en_auto_freq_count(1), ///< en_auto_freq_count;Register Addresses: 15[21:21];When this is '1' internally computed values is used. Else register value is used.
tgrosch 0:62b846b3988a 58 en_floop(1), ///< en_floop;Register Addresses: 15[22:22];Enables the freq_loop block. If this is '0', the clock to the freq_loop is gated.
tgrosch 0:62b846b3988a 59 en_freq_corr(1), ///< en_freq_corr;Register Addresses: 15[23:23];This bit applies frequency correction on the phase data either from register or auto_freq.
tgrosch 0:62b846b3988a 60 en_cont_fcalib(1), ///< en_cont_fcalib;Register Addresses: 16[15:15];
tgrosch 0:62b846b3988a 61 monoshot_bit(1), ///< monoshot_bit;Register Addresses: 0[23:23];In monoshot mode the register to trigger a measurement.
tgrosch 0:62b846b3988a 62 monoshot_mode(1), ///< monoshot_mode;Register Addresses: 39[1:0];LSB: Enters monoshot mode.;;MSB: If this is set monoshot mode shutdown the oscclk. This has to be used together with monoshot_mode.
tgrosch 0:62b846b3988a 63 powerup_delay(1), ///< powerup_delay;Register Addresses: 38[23:10];The synchronous counter delay after the ripple counter expires before ungating the clock. About 256*25ns*2^6 ~ 400 us.
tgrosch 0:62b846b3988a 64 monoshot_numframe(1), ///< monoshot_numframe;Register Addresses: 39[7:2];The number of frames of TG to be run after a trigger before shutting down the TG. The default is kept as 6 allowing a led cycle.
tgrosch 0:62b846b3988a 65 monoshot_fz_clkcnt(1), ///< monoshot_fz_clkcnt;Register Addresses: 39[23:8];The pix_cnt at which a monoshot operation freezes. By default just freezes 100 cycles before a frame boundary.
tgrosch 0:62b846b3988a 66 en_tx_switch(1), ///< en_tx_switch;Register Addresses: 42[0:0];Enable switching of led drivers.
tgrosch 0:62b846b3988a 67 sel_tx_ch(1), ///< sel_tx_ch;Register Addresses: 42[2:1];choses the fix_reg value when switching is disabled.
tgrosch 0:62b846b3988a 68 tx_seq_reg(1), ///< tx_seq_reg;Register Addresses: 42[14:3];Stores the sequence of led switching in this register.;2-1-0-2-1-0. The sequence will come as 0-1-2-0-1-2
tgrosch 0:62b846b3988a 69 en_adaptive_hdr(1), ///< en_adaptive_hdr;Register Addresses: 42[15:15];enable the adaptive hdr. The num_avg_frame in this case should be programmed one more than the normal case.
tgrosch 0:62b846b3988a 70 sel_hdr_mode(1), ///< sel_hdr_mode;Register Addresses: 42[16:16];choses which current to use when enable_adaptive_hdr = '0'
tgrosch 0:62b846b3988a 71 hdr_thr_low(1), ///< hdr_thr_low;Register Addresses: 44[15:0];The low threshold of the hysterisis loop. Equivalent to ~64 confidence.
tgrosch 0:62b846b3988a 72 hdr_thr_high(1), ///< hdr_thr_high;Register Addresses: 43[15:0];the high threshold of the hyserisis loop. Default equivalent to confidence of 256 in 16 bit level.
tgrosch 0:62b846b3988a 73 illum_scale_l_tx0(1), ///< illum_scale_l_tx0;Register Addresses: 43[18:16];
tgrosch 0:62b846b3988a 74 illum_dac_l_tx0(1), ///< illum_dac_l_tx0;Register Addresses: 41[4:0];
tgrosch 0:62b846b3988a 75 illum_scale_h_tx0(1), ///< illum_scale_h_tx0;Register Addresses: 43[21:19];
tgrosch 0:62b846b3988a 76 illum_dac_h_tx0(1), ///< illum_dac_h_tx0;Register Addresses: 41[9:5];
tgrosch 0:62b846b3988a 77 illum_scale_l_tx1(1), ///< illum_scale_l_tx1;Register Addresses: 44[18:16];
tgrosch 0:62b846b3988a 78 illum_dac_l_tx1(1), ///< illum_dac_l_tx1;Register Addresses: 41[14:10];
tgrosch 0:62b846b3988a 79 illum_scale_h_tx1(1), ///< illum_scale_h_tx1;Register Addresses: 44[21:19];
tgrosch 0:62b846b3988a 80 illum_dac_h_tx1(1), ///< illum_dac_h_tx1;Register Addresses: 41[19:15];
tgrosch 0:62b846b3988a 81 illum_scale_l_tx2(1), ///< illum_scale_l_tx2;Register Addresses: 185[20:18];
tgrosch 0:62b846b3988a 82 illum_dac_l_tx2(2), ///< illum_dac_l_tx2;Register Addresses: 41[23:20], 42[23:23];
tgrosch 0:62b846b3988a 83 illum_scale_h_tx2(1), ///< illum_scale_h_tx2;Register Addresses: 185[23:21];
tgrosch 0:62b846b3988a 84 illum_dac_h_tx2(1), ///< illum_dac_h_tx2;Register Addresses: 42[22:18];
tgrosch 0:62b846b3988a 85 amb_adc_in_tx0(1), ///< amb_adc_in_tx0;Register Addresses: 185[13:12];
tgrosch 0:62b846b3988a 86 amb_adc_in_tx1(1), ///< amb_adc_in_tx1;Register Addresses: 185[15:14];
tgrosch 0:62b846b3988a 87 amb_adc_in_tx2(1), ///< amb_adc_in_tx2;Register Addresses: 185[17:16];
tgrosch 0:62b846b3988a 88 give_dealias_data(1), ///< give_dealias_data;Register Addresses: 184[20:20];
tgrosch 0:62b846b3988a 89 en_dealias_meas(1), ///< en_dealias_meas;Register Addresses: 64[0:0];enables dealias calculation.;Normally with enable_dealiased_measurement set and enable_multi_freq_phase is unset a combined distance and kb is given out. In the normal phase register, phase of the high frequency itself is given.;
tgrosch 0:62b846b3988a 90 ncr_config(1), ///< ncr_config;Register Addresses: 64[21:21];option to chose ncr configuration, that is 6/7 (0) or 6/5 (1). Chooses higher frequency by default.
tgrosch 0:62b846b3988a 91 alpha0_dealias_scale(1), ///< alpha0_dealias_scale;Register Addresses: 64[14:9];indicates the vector multiplication in intrinsic-xtalk component for the dealias frequency. Default is '1'.
tgrosch 0:62b846b3988a 92 beta0_dealias_scale(1), ///< beta0_dealias_scale;Register Addresses: 64[20:15];
tgrosch 0:62b846b3988a 93 alpha1_dealias_scale(1), ///< alpha1_dealias_scale;Register Addresses: 65[5:0];indicates the vector multiplication in optical-xtalk component for the dealias frequency. Default is '1'.
tgrosch 0:62b846b3988a 94 beta1_dealias_scale(1), ///< beta1_dealias_scale;Register Addresses: 65[11:6];
tgrosch 0:62b846b3988a 95 en_multi_freq_phase(1), ///< en_multi_freq_phase;Register Addresses: 64[22:22];With this bit set along with enable_dealiased_measurement, the usual phase register will have both the frequency information. The frequency of the phase will be indicated in one of the status bit.
tgrosch 0:62b846b3988a 96 temp_avg_main(1), ///< temp_avg_main;Register Addresses: 3[23:22];
tgrosch 0:62b846b3988a 97 dis_ovl_for_hdr_meth1(1), ///< dis_ovl_for_hdr_meth1;Register Addresses: 184[21:21];
tgrosch 0:62b846b3988a 98 en_ovl_for_hdr_meth2(1), ///< en_ovl_for_hdr_meth2;Register Addresses: 184[22:22];
tgrosch 0:62b846b3988a 99 en_tx1_on_tx0(1), ///< en_tx1_on_tx0;Register Addresses: 185[10:10];
tgrosch 0:62b846b3988a 100 en_tx2_on_tx0(1), ///< en_tx2_on_tx0;Register Addresses: 185[11:11];
tgrosch 0:62b846b3988a 101 clip_mode_fc(1), ///< clip_mode_fc;Register Addresses: 80[0:0];chooses either rounding off or clipping or wrap around when applying freq-correction. Default is kept as rounding.
tgrosch 0:62b846b3988a 102 clip_mode_nl(1), ///< clip_mode_nl;Register Addresses: 80[1:1];chooses either rounding off or clipping or wrap around when applying harmonic correction. Default is kept as rounding.
tgrosch 0:62b846b3988a 103 clip_mode_temp(1), ///< clip_mode_temp;Register Addresses: 80[2:2];chooses either rounding off or clipping or wrap around when applying temp correction. Default is kept as rounding.
tgrosch 0:62b846b3988a 104 clip_mode_offset(1), ///< clip_mode_offset;Register Addresses: 80[3:3];chooses either rounding off or clipping or wrap around when applying offset. Default is kept as rounding.
tgrosch 0:62b846b3988a 105 disable_syncing(1), ///< disable_syncing;Register Addresses: 80[21:21];Normally calc clock and afe_clk are synchronized to avoid reset to reset variation in spur levels. This option is to disable the syncing of dividers (of calc_clk). The default is now changed to '1' because we don't use divided clock for calc-clk from PG3P0 by default. If syncing is used frequency loop will have issues.
tgrosch 0:62b846b3988a 106 force_en_slave(1), ///< force_en_slave;Register Addresses: 0[22:22];Enable i2c slave for any address forcefully. That is whether auto_load completed or not.
tgrosch 0:62b846b3988a 107 force_en_bypass(1), ///< force_en_bypass;Register Addresses: 0[21:21];This bit allows the slave to write directly to the efuse. This is gated with stop condition at the port level to avoid transition signals at scl/sda.
tgrosch 0:62b846b3988a 108 override_clkgen_reg(1), ///< override_clkgen_reg;Register Addresses: 80[22:22];Setting this register '1' allows user to independenly control tm_clkgen(2:1) which controls dealias settings.
tgrosch 0:62b846b3988a 109 software_reset(1), ///< software_reset;Register Addresses: 0[0:0];
tgrosch 0:62b846b3988a 110 dis_tg_aconf(1), ///< dis_tg_aconf;Register Addresses: 128[23:23];Some of the tg registers are automatically configured such as pdn*_dyn_tg signal, capture_tg_channel etc. if these signals need to be configured by user this bit may be used as an override.
tgrosch 0:62b846b3988a 111 capture_clk_cnt(1), ///< capture_clk_cnt;Register Addresses: 160[15:0];This is where early_fvd/svd starts. early_fvd only comes in the frame which is equal num_avg. This is the subframe in which computation results comes up. Programm this to 10600 if planning to use lower frequency.
tgrosch 0:62b846b3988a 112 tg_en(1), ///< tg_en;Register Addresses: 128[0:0];gates the tg_clk with this bit.
tgrosch 0:62b846b3988a 113 num_sub_frames(1), ///< num_sub_frames;Register Addresses: 159[11:0];The numbef of subframes in a frame. This number should be greater than or equal to num_avg.
tgrosch 0:62b846b3988a 114 num_avg_sub_frames(1), ///< num_avg_sub_frames;Register Addresses: 159[23:12];The number of averages for the iq. Used in TG to generate early_fvd and some other TG signals.
tgrosch 0:62b846b3988a 115 sub_vd_clk_cnt(1), ///< sub_vd_clk_cnt;Register Addresses: 128[16:1];the number of pixels in a subframe. In PG3P0 the default is changed to support 4ksps. The number is also made a multiple of 32+16.
tgrosch 0:62b846b3988a 116 tg_illumen_start(1), ///< tg_illumen_start;Register Addresses: 143[15:0];spare2_tg. This is used for illum_en. Enabled throughout a subframe.
tgrosch 0:62b846b3988a 117 tg_illumen_end(1), ///< tg_illumen_end;Register Addresses: 144[15:0];Ending after the 8192+ 250 samples apx.
tgrosch 0:62b846b3988a 118 tg_illumen_mask_start(1), ///< tg_illumen_mask_start;Register Addresses: 156[11:0];spare2_mask. By default the mask is programmed till num_avg_iq only.
tgrosch 0:62b846b3988a 119 tg_illumen_mask_end(1), ///< tg_illumen_mask_end;Register Addresses: 156[23:12];
tgrosch 0:62b846b3988a 120 tg_afe_rst_start(1), ///< tg_afe_rst_start;Register Addresses: 131[15:0];demod_reset. Mask is programmed such that it comes every subframe.
tgrosch 0:62b846b3988a 121 tg_afe_rst_end(1), ///< tg_afe_rst_end;Register Addresses: 132[15:0];
tgrosch 0:62b846b3988a 122 tg_seq_int_start(1), ///< tg_seq_int_start;Register Addresses: 133[15:0];interrupt. Only happens in first subframe due to the mask programming
tgrosch 0:62b846b3988a 123 tg_seq_int_end(1), ///< tg_seq_int_end;Register Addresses: 134[15:0];
tgrosch 0:62b846b3988a 124 tg_capture_start(1), ///< tg_capture_start;Register Addresses: 135[15:0];capture_tg_channel. Internal TG signal. This signal need to be changed when you go to slower dealias mode. Program this to 11300 and 11800
tgrosch 0:62b846b3988a 125 tg_capture_end(1), ///< tg_capture_end;Register Addresses: 136[15:0];
tgrosch 0:62b846b3988a 126 tg_ovl_window_start(1), ///< tg_ovl_window_start;Register Addresses: 137[15:0];ovl_sample. During this time period only ovl is sampled. This exists for only for subframes till the num_avg.
tgrosch 0:62b846b3988a 127 tg_ovl_window_end(1), ///< tg_ovl_window_end;Register Addresses: 138[15:0];
tgrosch 0:62b846b3988a 128 tg_calc_start(1), ///< tg_calc_start;Register Addresses: 145[15:0];pdn_dyn_tg. This signal exists roughly from early_fvd start till end of the computation. The mask is programmed such that this only comes in the num_avg sub-frame. Programmed such that it will work even if the frequency changes in both direction.
tgrosch 0:62b846b3988a 129 tg_calc_end(1), ///< tg_calc_end;Register Addresses: 146[15:0];
tgrosch 0:62b846b3988a 130 tg_dynpdn_start(1), ///< tg_dynpdn_start;Register Addresses: 147[15:0];pdn_dyn1_tg. Used to power down less power intensive digital blocks and analog if tm_frame_vd_sub_cnt greater than num_avg_iq.
tgrosch 0:62b846b3988a 131 tg_dynpdn_end(1), ///< tg_dynpdn_end;Register Addresses: 148[15:0];
tgrosch 0:62b846b3988a 132 tg_seq_int_mask_start(1), ///< tg_seq_int_mask_start;Register Addresses: 151[11:0];interrupt. Comes only in first (num:0) subframe.
tgrosch 0:62b846b3988a 133 tg_seq_int_mask_end(1), ///< tg_seq_int_mask_end;Register Addresses: 151[23:12];
tgrosch 0:62b846b3988a 134 tg_capture_mask_start(1), ///< tg_capture_mask_start;Register Addresses: 152[11:0];capture_tg_channel. By default comes only in the num_avg subchannel. This mask is configurable by user only if dis_tg_aconf = '1'.
tgrosch 0:62b846b3988a 135 tg_capture_mask_end(1), ///< tg_capture_mask_end;Register Addresses: 152[23:12];
tgrosch 0:62b846b3988a 136 tg_ovl_window_mask_start(1), ///< tg_ovl_window_mask_start;Register Addresses: 153[11:0];ovl_sample. This exits till num_avg subframe.
tgrosch 0:62b846b3988a 137 tg_ovl_window_mask_end(1), ///< tg_ovl_window_mask_end;Register Addresses: 153[23:12];
tgrosch 0:62b846b3988a 138 tg_calc_mask_start(1), ///< tg_calc_mask_start;Register Addresses: 157[11:0];Mask for pdn_dyn_tg. Only enabled during num_avg subframe.
tgrosch 0:62b846b3988a 139 tg_calc_mask_end(1), ///< tg_calc_mask_end;Register Addresses: 157[23:12];
tgrosch 0:62b846b3988a 140 tg_dynpdn_mask_start(1), ///< tg_dynpdn_mask_start;Register Addresses: 158[11:0];Mask for pdn_dyn1_tg. Used to power down less power intensive digital blocks and analog if tm_frame_vd_sub_cnt greater than num_avg_iq. Enabled till num_avg subframe.
tgrosch 0:62b846b3988a 141 tg_dynpdn_mask_end(1), ///< tg_dynpdn_mask_end;Register Addresses: 158[23:12];
tgrosch 0:62b846b3988a 142 en_sequencer(1), ///< en_sequencer;Register Addresses: 20[16:16];clock gates the logic for sequencer normally. This bit is used to enable sequencer.
tgrosch 0:62b846b3988a 143 en_processor_values(1), ///< en_processor_values;Register Addresses: 20[17:17];Uses processor values instead of register values.
tgrosch 0:62b846b3988a 144 status_in_reg(1), ///< status_in_reg;Register Addresses: 20[18:18];the register is used to control the program flow in CPU
tgrosch 0:62b846b3988a 145 mux_sel_compin(1), ///< mux_sel_compin;Register Addresses: 19[2:0];choses the value used for comp_a register in cpu.;Following are the choices.;phase_out_fsm;dealiased_kb_fsm;dealiased_distance;confidence
tgrosch 0:62b846b3988a 146 compare_reg1(1), ///< compare_reg1;Register Addresses: 19[18:3];
tgrosch 0:62b846b3988a 147 compare_reg2(1), ///< compare_reg2;Register Addresses: 20[15:0];
tgrosch 0:62b846b3988a 148 dis_interrupt(1), ///< dis_interrupt;Register Addresses: 20[19:19];Disables the interrupt which triggers processor. Does not clock gate processor though.
tgrosch 0:62b846b3988a 149 command0(1), ///< command0;Register Addresses: 21[11:0];NOP for 99 cycles
tgrosch 0:62b846b3988a 150 command1(1), ///< command1;Register Addresses: 21[23:12];enable intrinsic-xtalk
tgrosch 0:62b846b3988a 151 command2(1), ///< command2;Register Addresses: 22[11:0];disable intrinsic xtalk
tgrosch 0:62b846b3988a 152 command3(1), ///< command3;Register Addresses: 22[23:12];Direct go to the first line
tgrosch 0:62b846b3988a 153 command4(1), ///< command4;Register Addresses: 23[11:0];
tgrosch 0:62b846b3988a 154 command5(1), ///< command5;Register Addresses: 23[23:12];
tgrosch 0:62b846b3988a 155 command6(1), ///< command6;Register Addresses: 24[11:0];
tgrosch 0:62b846b3988a 156 command7(1), ///< command7;Register Addresses: 24[23:12];
tgrosch 0:62b846b3988a 157 command8(1), ///< command8;Register Addresses: 25[11:0];
tgrosch 0:62b846b3988a 158 command9(1), ///< command9;Register Addresses: 25[23:12];
tgrosch 0:62b846b3988a 159 command10(1), ///< command10;Register Addresses: 26[11:0];
tgrosch 0:62b846b3988a 160 command11(1), ///< command11;Register Addresses: 26[23:12];
tgrosch 0:62b846b3988a 161 command12(1), ///< command12;Register Addresses: 27[11:0];
tgrosch 0:62b846b3988a 162 command13(1), ///< command13;Register Addresses: 27[23:12];
tgrosch 0:62b846b3988a 163 command14(1), ///< command14;Register Addresses: 28[11:0];
tgrosch 0:62b846b3988a 164 command15(1), ///< command15;Register Addresses: 28[23:12];
tgrosch 0:62b846b3988a 165 command16(1), ///< command16;Register Addresses: 29[11:0];
tgrosch 0:62b846b3988a 166 command17(1), ///< command17;Register Addresses: 29[23:12];
tgrosch 0:62b846b3988a 167 command18(1), ///< command18;Register Addresses: 30[11:0];
tgrosch 0:62b846b3988a 168 command19(1), ///< command19;Register Addresses: 30[23:12];
tgrosch 0:62b846b3988a 169 force_scale_val(1), ///< force_scale_val;Register Addresses: 46[2:0];Uses this scale value if disable_auto_scale is programmed. This scale value is also used during any xtalk calibration even if disable_auto_scale is not applied. Default is '0', which means 24bit demod is taken as it is giving maximum accuracy.
tgrosch 0:62b846b3988a 170 dis_auto_scale(1), ///< dis_auto_scale;Register Addresses: 46[3:3];
tgrosch 0:62b846b3988a 171 disable_conf_rescale(1), ///< disable_conf_rescale;Register Addresses: 46[13:13];This a mostly a debug register.. When this is set auto_scaled confidence doesn't rescale back. Even when force_scale_val is there, it doesn't rescale. This bit may be set along with force_scale_val to see the effect of confidence scaling.
tgrosch 0:62b846b3988a 172 int_xtalk_calib(1), ///< int_xtalk_calib;Register Addresses: 46[4:4];Puts the device into intrinsic calibration mode.
tgrosch 0:62b846b3988a 173 xtalk_filt_time_const(1), ///< xtalk_filt_time_const;Register Addresses: 46[23:20];Time constant during crosstalk filtering. Higher the time constant slower the filtering is.
tgrosch 0:62b846b3988a 174 use_xtalk_filt_int(1), ///< use_xtalk_filt_int;Register Addresses: 46[5:5];Whehter to use filter or direct sampling for intrinsic crosstalk.
tgrosch 0:62b846b3988a 175 use_xtalk_reg_int(1), ///< use_xtalk_reg_int;Register Addresses: 46[6:6];Whether to use register or filter/sample for intrinsic.
tgrosch 0:62b846b3988a 176 iq_read_data_sel(1), ///< iq_read_data_sel;Register Addresses: 46[11:9];mux used to chose which of the xtalk register is being read out.;;010 -- raw_i/q;000 -- intrinsic_xtalk;001 -- optical_xtalk
tgrosch 0:62b846b3988a 177 iphase_xtalk(1), ///< iphase_xtalk;Register Addresses: 59[23:0];
tgrosch 0:62b846b3988a 178 qphase_xtalk(1), ///< qphase_xtalk;Register Addresses: 60[23:0];
tgrosch 0:62b846b3988a 179 int_xtalk_reg_scale(1), ///< int_xtalk_reg_scale;Register Addresses: 46[16:14];allows scaling of the meaning of ixtalk register. 0- 2^0, 2^1, 2^2, 2^3 etc.
tgrosch 0:62b846b3988a 180 iphase_xtalk_int_reg(1), ///< iphase_xtalk_int_reg;Register Addresses: 61[15:0];inphase component for intrinsic xtalk
tgrosch 0:62b846b3988a 181 qphase_xtalk_int_reg(1), ///< qphase_xtalk_int_reg;Register Addresses: 62[15:0];quadrature component for intrinsic xtalk
tgrosch 0:62b846b3988a 182 illum_xtalk_calib(1), ///< illum_xtalk_calib;Register Addresses: 46[12:12];puts the device into optical calibration mode.
tgrosch 0:62b846b3988a 183 illum_xtalk_reg_scale(1), ///< illum_xtalk_reg_scale;Register Addresses: 46[19:17];allows scaling of the meaning of oxtalk register. 0- 2^0, 2^2, 2^4, 2^8.
tgrosch 0:62b846b3988a 184 use_xtalk_filt_illum(1), ///< use_xtalk_filt_illum;Register Addresses: 46[7:7];
tgrosch 0:62b846b3988a 185 use_xtalk_reg_illum(1), ///< use_xtalk_reg_illum;Register Addresses: 46[8:8];For optical default is to use the register values.
tgrosch 0:62b846b3988a 186 iphase_xtalk_reg_hdr0_tx0(1), ///< iphase_xtalk_reg_hdr0_tx0;Register Addresses: 47[15:0];inphase component of the xtalk for hdr0/led0
tgrosch 0:62b846b3988a 187 qphase_xtalk_reg_hdr0_tx0(1), ///< qphase_xtalk_reg_hdr0_tx0;Register Addresses: 48[15:0];quadrature component of the xtalk for hdr0/led0
tgrosch 0:62b846b3988a 188 iphase_xtalk_reg_hdr1_tx0(1), ///< iphase_xtalk_reg_hdr1_tx0;Register Addresses: 49[15:0];
tgrosch 0:62b846b3988a 189 qphase_xtalk_reg_hdr1_tx0(1), ///< qphase_xtalk_reg_hdr1_tx0;Register Addresses: 50[15:0];
tgrosch 0:62b846b3988a 190 iphase_xtalk_reg_hdr0_tx1(1), ///< iphase_xtalk_reg_hdr0_tx1;Register Addresses: 51[15:0];
tgrosch 0:62b846b3988a 191 qphase_xtalk_reg_hdr0_tx1(1), ///< qphase_xtalk_reg_hdr0_tx1;Register Addresses: 52[15:0];
tgrosch 0:62b846b3988a 192 iphase_xtalk_reg_hdr1_tx1(1), ///< iphase_xtalk_reg_hdr1_tx1;Register Addresses: 53[15:0];
tgrosch 0:62b846b3988a 193 qphase_xtalk_reg_hdr1_tx1(1), ///< qphase_xtalk_reg_hdr1_tx1;Register Addresses: 54[15:0];
tgrosch 0:62b846b3988a 194 iphase_xtalk_reg_hdr0_tx2(1), ///< iphase_xtalk_reg_hdr0_tx2;Register Addresses: 55[15:0];
tgrosch 0:62b846b3988a 195 qphase_xtalk_reg_hdr0_tx2(1), ///< qphase_xtalk_reg_hdr0_tx2;Register Addresses: 56[15:0];
tgrosch 0:62b846b3988a 196 iphase_xtalk_reg_hdr1_tx2(1), ///< iphase_xtalk_reg_hdr1_tx2;Register Addresses: 57[15:0];
tgrosch 0:62b846b3988a 197 qphase_xtalk_reg_hdr1_tx2(1), ///< qphase_xtalk_reg_hdr1_tx2;Register Addresses: 58[15:0];
tgrosch 0:62b846b3988a 198 en_temp_xtalk_corr(1), ///< en_temp_xtalk_corr;Register Addresses: 58[16:16];
tgrosch 0:62b846b3988a 199 scale_temp_coeff_xtalk(1), ///< scale_temp_coeff_xtalk;Register Addresses: 58[19:17];Allows programmability on the temp_coefficients range and precision.
tgrosch 0:62b846b3988a 200 temp_coeff_xtalk_iphase_hdr0_tx0(1), ///< temp_coeff_xtalk_iphase_hdr0_tx0;Register Addresses: 56[23:16];
tgrosch 0:62b846b3988a 201 temp_coeff_xtalk_qphase_hdr0_tx0(1), ///< temp_coeff_xtalk_qphase_hdr0_tx0;Register Addresses: 57[23:16];
tgrosch 0:62b846b3988a 202 temp_coeff_xtalk_iphase_hdr1_tx0(1), ///< temp_coeff_xtalk_iphase_hdr1_tx0;Register Addresses: 94[15:8];
tgrosch 0:62b846b3988a 203 temp_coeff_xtalk_qphase_hdr1_tx0(1), ///< temp_coeff_xtalk_qphase_hdr1_tx0;Register Addresses: 96[7:0];
tgrosch 0:62b846b3988a 204 temp_coeff_xtalk_iphase_hdr0_tx1(1), ///< temp_coeff_xtalk_iphase_hdr0_tx1;Register Addresses: 94[23:16];
tgrosch 0:62b846b3988a 205 temp_coeff_xtalk_qphase_hdr0_tx1(1), ///< temp_coeff_xtalk_qphase_hdr0_tx1;Register Addresses: 96[15:8];
tgrosch 0:62b846b3988a 206 temp_coeff_xtalk_iphase_hdr1_tx1(1), ///< temp_coeff_xtalk_iphase_hdr1_tx1;Register Addresses: 95[7:0];
tgrosch 0:62b846b3988a 207 temp_coeff_xtalk_qphase_hdr1_tx1(1), ///< temp_coeff_xtalk_qphase_hdr1_tx1;Register Addresses: 96[23:16];
tgrosch 0:62b846b3988a 208 temp_coeff_xtalk_iphase_hdr0_tx2(1), ///< temp_coeff_xtalk_iphase_hdr0_tx2;Register Addresses: 95[15:8];
tgrosch 0:62b846b3988a 209 temp_coeff_xtalk_qphase_hdr0_tx2(1), ///< temp_coeff_xtalk_qphase_hdr0_tx2;Register Addresses: 97[7:0];
tgrosch 0:62b846b3988a 210 temp_coeff_xtalk_iphase_hdr1_tx2(1), ///< temp_coeff_xtalk_iphase_hdr1_tx2;Register Addresses: 95[23:16];
tgrosch 0:62b846b3988a 211 temp_coeff_xtalk_qphase_hdr1_tx2(1), ///< temp_coeff_xtalk_qphase_hdr1_tx2;Register Addresses: 97[15:8];
tgrosch 0:62b846b3988a 212 temp_coeff_illum_xtalk_iphase_hdr0_tx0(1), ///< temp_coeff_illum_xtalk_iphase_hdr0_tx0;Register Addresses: 54[23:16];
tgrosch 0:62b846b3988a 213 temp_coeff_illum_xtalk_qphase_hdr0_tx0(1), ///< temp_coeff_illum_xtalk_qphase_hdr0_tx0;Register Addresses: 55[23:16];
tgrosch 0:62b846b3988a 214 temp_coeff_illum_xtalk_iphase_hdr1_tx0(1), ///< temp_coeff_illum_xtalk_iphase_hdr1_tx0;Register Addresses: 91[7:0];
tgrosch 0:62b846b3988a 215 temp_coeff_illum_xtalk_iphase_hdr0_tx1(1), ///< temp_coeff_illum_xtalk_iphase_hdr0_tx1;Register Addresses: 91[15:8];
tgrosch 0:62b846b3988a 216 temp_coeff_illum_xtalk_iphase_hdr1_tx1(1), ///< temp_coeff_illum_xtalk_iphase_hdr1_tx1;Register Addresses: 91[23:16];
tgrosch 0:62b846b3988a 217 temp_coeff_illum_xtalk_iphase_hdr0_tx2(1), ///< temp_coeff_illum_xtalk_iphase_hdr0_tx2;Register Addresses: 92[7:0];
tgrosch 0:62b846b3988a 218 temp_coeff_illum_xtalk_iphase_hdr1_tx2(1), ///< temp_coeff_illum_xtalk_iphase_hdr1_tx2;Register Addresses: 92[15:8];
tgrosch 0:62b846b3988a 219 temp_coeff_illum_xtalk_qphase_hdr1_tx0(1), ///< temp_coeff_illum_xtalk_qphase_hdr1_tx0;Register Addresses: 92[23:16];
tgrosch 0:62b846b3988a 220 temp_coeff_illum_xtalk_qphase_hdr0_tx1(1), ///< temp_coeff_illum_xtalk_qphase_hdr0_tx1;Register Addresses: 93[7:0];
tgrosch 0:62b846b3988a 221 temp_coeff_illum_xtalk_qphase_hdr1_tx1(1), ///< temp_coeff_illum_xtalk_qphase_hdr1_tx1;Register Addresses: 93[15:8];
tgrosch 0:62b846b3988a 222 temp_coeff_illum_xtalk_qphase_hdr0_tx2(1), ///< temp_coeff_illum_xtalk_qphase_hdr0_tx2;Register Addresses: 93[23:16];
tgrosch 0:62b846b3988a 223 temp_coeff_illum_xtalk_qphase_hdr1_tx2(1), ///< temp_coeff_illum_xtalk_qphase_hdr1_tx2;Register Addresses: 94[7:0];
tgrosch 0:62b846b3988a 224 amb_xtalk_qphase_coeff(1), ///< amb_xtalk_qphase_coeff;Register Addresses: 12[15:8];reflects the variation of quad component.
tgrosch 0:62b846b3988a 225 amb_xtalk_iphase_coeff(1), ///< amb_xtalk_iphase_coeff;Register Addresses: 12[7:0];reflect the variation of optical crosstalk inphase component.
tgrosch 0:62b846b3988a 226 scale_amb_coeff_xtalk(1), ///< scale_amb_coeff_xtalk;Register Addresses: 58[22:20];Ambient xtalk mode. Provides range/precision for ambient correction.
tgrosch 0:62b846b3988a 227 en_phase_corr(1), ///< en_phase_corr;Register Addresses: 67[0:0];enables phase correction from the values programmed.
tgrosch 0:62b846b3988a 228 phase_offset_hdr0_tx0(1), ///< phase_offset_hdr0_tx0;Register Addresses: 66[15:0];phase_offset for freq1
tgrosch 0:62b846b3988a 229 phase_offset_hdr1_tx0(1), ///< phase_offset_hdr1_tx0;Register Addresses: 81[15:0];
tgrosch 0:62b846b3988a 230 phase_offset_hdr0_tx1(1), ///< phase_offset_hdr0_tx1;Register Addresses: 82[15:0];
tgrosch 0:62b846b3988a 231 phase_offset_hdr1_tx1(1), ///< phase_offset_hdr1_tx1;Register Addresses: 83[15:0];
tgrosch 0:62b846b3988a 232 phase_offset_hdr0_tx2(1), ///< phase_offset_hdr0_tx2;Register Addresses: 84[15:0];
tgrosch 0:62b846b3988a 233 phase_offset_hdr1_tx2(1), ///< phase_offset_hdr1_tx2;Register Addresses: 85[15:0];
tgrosch 0:62b846b3988a 234 reverse_phase_before_offset(1), ///< reverse_phase_before_offset;Register Addresses: 67[9:9];
tgrosch 0:62b846b3988a 235 phase2_offset_hdr0_tx0(1), ///< phase2_offset_hdr0_tx0;Register Addresses: 68[15:0];phase offset for freq2
tgrosch 0:62b846b3988a 236 phase2_offset_hdr1_tx0(1), ///< phase2_offset_hdr1_tx0;Register Addresses: 86[15:0];
tgrosch 0:62b846b3988a 237 phase2_offset_hdr0_tx1(1), ///< phase2_offset_hdr0_tx1;Register Addresses: 87[15:0];
tgrosch 0:62b846b3988a 238 phase2_offset_hdr1_tx1(1), ///< phase2_offset_hdr1_tx1;Register Addresses: 88[15:0];
tgrosch 0:62b846b3988a 239 phase2_offset_hdr0_tx2(1), ///< phase2_offset_hdr0_tx2;Register Addresses: 89[15:0];
tgrosch 0:62b846b3988a 240 phase2_offset_hdr1_tx2(1), ///< phase2_offset_hdr1_tx2;Register Addresses: 90[15:0];
tgrosch 0:62b846b3988a 241 en_temp_corr(1), ///< en_temp_corr;Register Addresses: 67[1:1];enables temperature correction for phase
tgrosch 0:62b846b3988a 242 scale_phase_temp_coeff(1), ///< scale_phase_temp_coeff;Register Addresses: 67[8:6];changes the meaning of coefficients related to phase correction.
tgrosch 0:62b846b3988a 243 tmain_calib_hdr0_tx0(1), ///< tmain_calib_hdr0_tx0;Register Addresses: 71[11:0];calibrated temperature for main temp sensor.Default is 2048 because internally it is treated as offset binary
tgrosch 0:62b846b3988a 244 temp_coeff_main_hdr0_tx0(1), ///< temp_coeff_main_hdr0_tx0;Register Addresses: 69[11:0];temperature coefficient for phase correction for main temp. By default means phase change for 64 degrees of temperature.
tgrosch 0:62b846b3988a 245 tmain_calib_hdr1_tx0(1), ///< tmain_calib_hdr1_tx0;Register Addresses: 72[11:0];
tgrosch 0:62b846b3988a 246 temp_coeff_main_hdr1_tx0(1), ///< temp_coeff_main_hdr1_tx0;Register Addresses: 45[11:0];
tgrosch 0:62b846b3988a 247 tmain_calib_hdr0_tx1(1), ///< tmain_calib_hdr0_tx1;Register Addresses: 73[11:0];
tgrosch 0:62b846b3988a 248 temp_coeff_main_hdr0_tx1(1), ///< temp_coeff_main_hdr0_tx1;Register Addresses: 45[23:12];
tgrosch 0:62b846b3988a 249 tmain_calib_hdr1_tx1(1), ///< tmain_calib_hdr1_tx1;Register Addresses: 65[23:12];
tgrosch 0:62b846b3988a 250 temp_coeff_main_hdr1_tx1(2), ///< temp_coeff_main_hdr1_tx1;Register Addresses: 47[23:16], 48[23:20];
tgrosch 0:62b846b3988a 251 tmain_calib_hdr0_tx2(1), ///< tmain_calib_hdr0_tx2;Register Addresses: 63[11:0];
tgrosch 0:62b846b3988a 252 temp_coeff_main_hdr0_tx2(2), ///< temp_coeff_main_hdr0_tx2;Register Addresses: 49[23:16], 50[23:20];
tgrosch 0:62b846b3988a 253 tmain_calib_hdr1_tx2(1), ///< tmain_calib_hdr1_tx2;Register Addresses: 69[23:12];
tgrosch 0:62b846b3988a 254 temp_coeff_main_hdr1_tx2(2), ///< temp_coeff_main_hdr1_tx2;Register Addresses: 51[23:16], 52[23:20];
tgrosch 0:62b846b3988a 255 tillum_calib_hdr0_tx0(1), ///< tillum_calib_hdr0_tx0;Register Addresses: 71[23:12];calibrated temp for tillum. Default is 2048 because internally it is treated as offset binary
tgrosch 0:62b846b3988a 256 temp_coeff_illum_hdr0_tx0(1), ///< temp_coeff_illum_hdr0_tx0;Register Addresses: 70[11:0];temperature coefficient for phase correction for illum temp. By default means phase change for 64 degrees of temperature.
tgrosch 0:62b846b3988a 257 tillum_calib_hdr1_tx0(1), ///< tillum_calib_hdr1_tx0;Register Addresses: 72[23:12];
tgrosch 0:62b846b3988a 258 temp_coeff_illum_hdr1_tx0(2), ///< temp_coeff_illum_hdr1_tx0;Register Addresses: 81[23:16], 82[23:20];
tgrosch 0:62b846b3988a 259 tillum_calib_hdr0_tx1(1), ///< tillum_calib_hdr0_tx1;Register Addresses: 73[23:12];
tgrosch 0:62b846b3988a 260 temp_coeff_illum_hdr0_tx1(2), ///< temp_coeff_illum_hdr0_tx1;Register Addresses: 83[23:16], 84[23:20];
tgrosch 0:62b846b3988a 261 tillum_calib_hdr1_tx1(1), ///< tillum_calib_hdr1_tx1;Register Addresses: 67[23:12];
tgrosch 0:62b846b3988a 262 temp_coeff_illum_hdr1_tx1(2), ///< temp_coeff_illum_hdr1_tx1;Register Addresses: 85[23:16], 86[23:20];
tgrosch 0:62b846b3988a 263 tillum_calib_hdr0_tx2(1), ///< tillum_calib_hdr0_tx2;Register Addresses: 63[23:12];
tgrosch 0:62b846b3988a 264 temp_coeff_illum_hdr0_tx2(2), ///< temp_coeff_illum_hdr0_tx2;Register Addresses: 87[23:16], 88[23:20];
tgrosch 0:62b846b3988a 265 tillum_calib_hdr1_tx2(1), ///< tillum_calib_hdr1_tx2;Register Addresses: 70[23:12];
tgrosch 0:62b846b3988a 266 temp_coeff_illum_hdr1_tx2(2), ///< temp_coeff_illum_hdr1_tx2;Register Addresses: 89[23:16], 90[23:20];
tgrosch 0:62b846b3988a 267 amb_sat_thr(1), ///< amb_sat_thr;Register Addresses: 13[16:7];the threshold which is used to detect the ambient overload. Default is kept at highest.;Threshold set for 1v on the ambient dac resistor. 512x3/8xIR.
tgrosch 0:62b846b3988a 268 amb_calib(1), ///< amb_calib;Register Addresses: 11[23:14];the ambient at which device is calibrated for optical xtalk/phase offset etc.
tgrosch 0:62b846b3988a 269 amb_phase_corr_pwl_coeff0(1), ///< amb_phase_corr_pwl_coeff0;Register Addresses: 12[23:16];Captures the drift in the phase wrto ambient. Can be a negative number to reflect inverse relationship. The number is divided by 2^5 to get the actual value.
tgrosch 0:62b846b3988a 270 amb_phase_corr_pwl_x0(1), ///< amb_phase_corr_pwl_x0;Register Addresses: 184[9:0];
tgrosch 0:62b846b3988a 271 amb_phase_corr_pwl_x1(1), ///< amb_phase_corr_pwl_x1;Register Addresses: 184[19:10];
tgrosch 0:62b846b3988a 272 amb_phase_corr_pwl_x2(1), ///< amb_phase_corr_pwl_x2;Register Addresses: 185[9:0];
tgrosch 0:62b846b3988a 273 amb_phase_corr_pwl_coeff1(1), ///< amb_phase_corr_pwl_coeff1;Register Addresses: 180[7:0];The first coefficient is assumed to be the original one
tgrosch 0:62b846b3988a 274 amb_phase_corr_pwl_coeff2(1), ///< amb_phase_corr_pwl_coeff2;Register Addresses: 180[15:8];
tgrosch 0:62b846b3988a 275 amb_phase_corr_pwl_coeff3(1), ///< amb_phase_corr_pwl_coeff3;Register Addresses: 180[23:16];
tgrosch 0:62b846b3988a 276 scale_amb_phase_corr_coeff(1), ///< scale_amb_phase_corr_coeff;Register Addresses: 181[2:0];Scales the gain/vs accuracy.
tgrosch 0:62b846b3988a 277 temp_coeff_illum_square_hdr0(1), ///< temp_coeff_illum_square_hdr0;Register Addresses: 182[7:0];
tgrosch 0:62b846b3988a 278 temp_coeff_illum_square_hdr1(1), ///< temp_coeff_illum_square_hdr1;Register Addresses: 182[15:8];
tgrosch 0:62b846b3988a 279 temp_coeff_main_square_hdr0(1), ///< temp_coeff_main_square_hdr0;Register Addresses: 183[7:0];
tgrosch 0:62b846b3988a 280 temp_coeff_main_square_hdr1(1), ///< temp_coeff_main_square_hdr1;Register Addresses: 183[15:8];
tgrosch 0:62b846b3988a 281 scale_phase_temp_corr_square(1), ///< scale_phase_temp_corr_square;Register Addresses: 181[5:3];scales square correction range/accuracy.
tgrosch 0:62b846b3988a 282 en_nl_corr(1), ///< en_nl_corr;Register Addresses: 74[0:0];enables harmonic/nonlinear correction for phase.
tgrosch 0:62b846b3988a 283 a1_coeff_hdr0_tx0(1), ///< a1_coeff_hdr0_tx0;Register Addresses: 75[15:0];
tgrosch 0:62b846b3988a 284 a2_coeff_hdr0_tx0(1), ///< a2_coeff_hdr0_tx0;Register Addresses: 76[15:0];
tgrosch 0:62b846b3988a 285 a3_coeff_hdr0_tx0(1), ///< a3_coeff_hdr0_tx0;Register Addresses: 77[15:0];
tgrosch 0:62b846b3988a 286 a4_coeff_hdr0_tx0(1), ///< a4_coeff_hdr0_tx0;Register Addresses: 78[15:0];
tgrosch 0:62b846b3988a 287 scale_nl_corr_coeff(1), ///< scale_nl_corr_coeff;Register Addresses: 74[19:18];changes the meaning of the nonlinear coefficients.;
tgrosch 0:62b846b3988a 288 a0_coeff_hdr0_tx0(1), ///< a0_coeff_hdr0_tx0;Register Addresses: 74[17:2];
tgrosch 0:62b846b3988a 289 a0_coeff_hdr1_tx0(1), ///< a0_coeff_hdr1_tx0;Register Addresses: 162[15:0];
tgrosch 0:62b846b3988a 290 a0_coeff_hdr0_tx1(1), ///< a0_coeff_hdr0_tx1;Register Addresses: 163[15:0];
tgrosch 0:62b846b3988a 291 a0_coeff_hdr1_tx1(1), ///< a0_coeff_hdr1_tx1;Register Addresses: 164[15:0];
tgrosch 0:62b846b3988a 292 a0_coeff_hdr0_tx2(1), ///< a0_coeff_hdr0_tx2;Register Addresses: 165[15:0];
tgrosch 0:62b846b3988a 293 a0_coeff_hdr1_tx2(1), ///< a0_coeff_hdr1_tx2;Register Addresses: 166[15:0];
tgrosch 0:62b846b3988a 294 a1_coeff_hdr1_tx0(1), ///< a1_coeff_hdr1_tx0;Register Addresses: 167[15:0];
tgrosch 0:62b846b3988a 295 a1_coeff_hdr0_tx1(1), ///< a1_coeff_hdr0_tx1;Register Addresses: 168[15:0];
tgrosch 0:62b846b3988a 296 a1_coeff_hdr1_tx1(1), ///< a1_coeff_hdr1_tx1;Register Addresses: 169[15:0];
tgrosch 0:62b846b3988a 297 a1_coeff_hdr0_tx2(1), ///< a1_coeff_hdr0_tx2;Register Addresses: 170[15:0];
tgrosch 0:62b846b3988a 298 a1_coeff_hdr1_tx2(1), ///< a1_coeff_hdr1_tx2;Register Addresses: 171[15:0];
tgrosch 0:62b846b3988a 299 a2_coeff_hdr1_tx0(1), ///< a2_coeff_hdr1_tx0;Register Addresses: 172[15:0];
tgrosch 0:62b846b3988a 300 a2_coeff_hdr0_tx1(1), ///< a2_coeff_hdr0_tx1;Register Addresses: 173[15:0];
tgrosch 0:62b846b3988a 301 a2_coeff_hdr1_tx1(1), ///< a2_coeff_hdr1_tx1;Register Addresses: 174[15:0];
tgrosch 0:62b846b3988a 302 a2_coeff_hdr0_tx2(1), ///< a2_coeff_hdr0_tx2;Register Addresses: 175[15:0];
tgrosch 0:62b846b3988a 303 a2_coeff_hdr1_tx2(1), ///< a2_coeff_hdr1_tx2;Register Addresses: 176[15:0];
tgrosch 0:62b846b3988a 304 a3_coeff_hdr1_tx0(1), ///< a3_coeff_hdr1_tx0;Register Addresses: 177[15:0];
tgrosch 0:62b846b3988a 305 a3_coeff_hdr0_tx1(2), ///< a3_coeff_hdr0_tx1;Register Addresses: 162[23:16], 163[23:16];
tgrosch 0:62b846b3988a 306 a3_coeff_hdr1_tx1(2), ///< a3_coeff_hdr1_tx1;Register Addresses: 164[23:16], 165[23:16];
tgrosch 0:62b846b3988a 307 a3_coeff_hdr0_tx2(2), ///< a3_coeff_hdr0_tx2;Register Addresses: 166[23:16], 167[23:16];
tgrosch 0:62b846b3988a 308 a3_coeff_hdr1_tx2(2), ///< a3_coeff_hdr1_tx2;Register Addresses: 168[23:16], 169[23:16];
tgrosch 0:62b846b3988a 309 a4_coeff_hdr1_tx0(2), ///< a4_coeff_hdr1_tx0;Register Addresses: 170[23:16], 171[23:16];
tgrosch 0:62b846b3988a 310 a4_coeff_hdr0_tx1(2), ///< a4_coeff_hdr0_tx1;Register Addresses: 172[23:16], 173[23:16];
tgrosch 0:62b846b3988a 311 a4_coeff_hdr1_tx1(2), ///< a4_coeff_hdr1_tx1;Register Addresses: 174[23:16], 175[23:16];
tgrosch 0:62b846b3988a 312 a4_coeff_hdr0_tx2(2), ///< a4_coeff_hdr0_tx2;Register Addresses: 176[23:16], 177[23:16];
tgrosch 0:62b846b3988a 313 a4_coeff_hdr1_tx2(1), ///< a4_coeff_hdr1_tx2;Register Addresses: 178[15:0];
tgrosch 0:62b846b3988a 314 tillum(1), ///< tillum;Register Addresses: 4[19:8];The value of illum-temperature register.
tgrosch 0:62b846b3988a 315 tsens_slave0(1), ///< tsens_slave0;Register Addresses: 2[6:0];slave address of the led0 tsensor
tgrosch 0:62b846b3988a 316 tsens_slave1(1), ///< tsens_slave1;Register Addresses: 2[13:7];slave address of the led1 tsensor
tgrosch 0:62b846b3988a 317 tsens_slave2(1), ///< tsens_slave2;Register Addresses: 2[20:14];slave address of the led2 tsensor
tgrosch 0:62b846b3988a 318 config_tillum_msb(1), ///< config_tillum_msb;Register Addresses: 7[23:20];
tgrosch 0:62b846b3988a 319 en_tillum_12b(1), ///< en_tillum_12b;Register Addresses: 13[23:23];While interfacing with the TMP02 type tempsensor, this bit needs to be set to swap bytes to allow different read format.
tgrosch 0:62b846b3988a 320 tillum_unsigned(1), ///< tillum_unsigned;Register Addresses: 4[23:23];This bit is set '1' when temperature given by tmain/tillum sensor is in unsigned format.
tgrosch 0:62b846b3988a 321 temp_avg_illum(1), ///< temp_avg_illum;Register Addresses: 2[23:22];Based on this, temperature is averaged to remove quantization errors on temperature.
tgrosch 0:62b846b3988a 322 en_tsens_read_fvd(1), ///< en_tsens_read_fvd;Register Addresses: 3[18:18];If this bit is set tmain temperature is read every frame. Other wise it is read based on a register trigger.
tgrosch 0:62b846b3988a 323 en_tillum_read(1), ///< en_tillum_read;Register Addresses: 2[21:21];Enable i2c read of appropriate illum led. If this bit is not set illumination driver temperature is not read.
tgrosch 0:62b846b3988a 324 eeprom_read_trig(1), ///< eeprom_read_trig;Register Addresses: 1[0:0];Used to read efuse values into the chain using register trigger
tgrosch 0:62b846b3988a 325 swap_read_data(1), ///< swap_read_data;Register Addresses: 1[1:1];swaps/reverse the data read by i2c-host.
tgrosch 0:62b846b3988a 326 eeprom_start_reg_addr(1), ///< eeprom_start_reg_addr;Register Addresses: 1[16:9];The first byte written while reading from the efuse. This will typically be 0. At startup there is no way to program this.
tgrosch 0:62b846b3988a 327 frame_vd_trig(1), ///< frame_vd_trig;Register Addresses: 1[17:17];when this bit is '1' i2c host is triggered every frame vd. Else it is triggered based on the i2c_trig_reg.
tgrosch 0:62b846b3988a 328 i2c_trig_reg(1), ///< i2c_trig_reg;Register Addresses: 1[18:18];The trigger register for i2c transaction.
tgrosch 0:62b846b3988a 329 i2c_en(1), ///< i2c_en;Register Addresses: 1[19:19];Enables the i2c host operation. Does not control the init load.
tgrosch 0:62b846b3988a 330 i2c_rw(1), ///< i2c_rw;Register Addresses: 1[21:20];Choses the r/w for i2c host operation.;By default it reads temperature sensor.
tgrosch 0:62b846b3988a 331 i2c_read_data(1), ///< i2c_read_data;Register Addresses: 3[7:0];The hosts read data.
tgrosch 0:62b846b3988a 332 i2c_write_data1(1), ///< i2c_write_data1;Register Addresses: 3[16:9];The address where the read would start. Normally in temperature sensor read this is not required to be programmed.
tgrosch 0:62b846b3988a 333 i2c_num_tran(1), ///< i2c_num_tran;Register Addresses: 3[17:17];The number of transactions. Either 1 or 2.
tgrosch 0:62b846b3988a 334 en_eeprom_read(1), ///< en_eeprom_read;Register Addresses: 1[23:23];Disables the gating of auto_load clock after init_load_done. Should be used if register triggering has to work.
tgrosch 0:62b846b3988a 335 init_load_done(1), ///< init_load_done;Register Addresses: 3[8:8];Can be used to check whether initial auto_load is successful or not.
tgrosch 0:62b846b3988a 336 addr_slave_eeprom(1), ///< addr_slave_eeprom;Register Addresses: 1[8:2];
tgrosch 0:62b846b3988a 337 i2c_num_bytes_tran1(1), ///< i2c_num_bytes_tran1;Register Addresses: 7[17:16];Number of bytes used in the tran2 of i2c transaction.
tgrosch 0:62b846b3988a 338 i2c_num_bytes_tran2(1), ///< i2c_num_bytes_tran2;Register Addresses: 5[23:22];Number of bytes used in the tran2 of i2c transaction.
tgrosch 0:62b846b3988a 339 i2c_write_data2(1), ///< i2c_write_data2;Register Addresses: 7[7:0];
tgrosch 0:62b846b3988a 340 i2c_sel_read_bytes(1), ///< i2c_sel_read_bytes;Register Addresses: 7[19:18];choses which byte of i2c_read register to be read.
tgrosch 0:62b846b3988a 341 i2c_cont_rw(1), ///< i2c_cont_rw;Register Addresses: 0[6:6];
tgrosch 0:62b846b3988a 342 dis_ovldet(1), ///< dis_ovldet;Register Addresses: 101[23:23];to disable overload detection
tgrosch 0:62b846b3988a 343 prog_ovldet_refp(1), ///< prog_ovldet_refp;Register Addresses: 100[20:18];To program OVL_DET REFP
tgrosch 0:62b846b3988a 344 prog_ovldet_refm(1), ///< prog_ovldet_refm;Register Addresses: 100[23:21];To program OVL_DET REFM
tgrosch 0:62b846b3988a 345 iamb_max_sel(1), ///< iamb_max_sel;Register Addresses: 114[7:4];selects the value of DAC resistor
tgrosch 0:62b846b3988a 346 tm_vrefp_diode(1), ///< tm_vrefp_diode;Register Addresses: 109[2:0];To program the bias voltage INP
tgrosch 0:62b846b3988a 347 tm_vrefm_diode(1), ///< tm_vrefm_diode;Register Addresses: 109[5:3];To program the bias voltage INM
tgrosch 0:62b846b3988a 348 gpo1_mux_sel(1), ///< gpo1_mux_sel;Register Addresses: 120[8:6];
tgrosch 0:62b846b3988a 349 gpio1_obuf_en(1), ///< gpio1_obuf_en;Register Addresses: 120[12:12];
tgrosch 0:62b846b3988a 350 gpio1_ibuf_en(1), ///< gpio1_ibuf_en;Register Addresses: 120[13:13];
tgrosch 0:62b846b3988a 351 gpo2_mux_sel(1), ///< gpo2_mux_sel;Register Addresses: 120[11:9];
tgrosch 0:62b846b3988a 352 gpio2_obuf_en(1), ///< gpio2_obuf_en;Register Addresses: 120[15:15];
tgrosch 0:62b846b3988a 353 gpio2_ibuf_en(1), ///< gpio2_ibuf_en;Register Addresses: 120[16:16];
tgrosch 0:62b846b3988a 354 gpo3_mux_sel(1), ///< gpo3_mux_sel;Register Addresses: 120[2:0];
tgrosch 0:62b846b3988a 355 sel_gp3_on_sdam(1), ///< sel_gp3_on_sdam;Register Addresses: 120[22:22];
tgrosch 0:62b846b3988a 356 dealias_en(1), ///< dealias_en;Register Addresses: 113[1:1];To enable Dealias mode to get different Modulation freq close to 40MHz, ;34.3 MHz & 48 MHz.
tgrosch 0:62b846b3988a 357 dealias_freq(1), ///< dealias_freq;Register Addresses: 113[2:2];Changes o/p freq in dealias mode;- only when dealais mode is enabled (TM_CLKGENless than2greater than is set to '1').
tgrosch 0:62b846b3988a 358 shift_illum_phase(1), ///< shift_illum_phase;Register Addresses: 113[6:3];Shift bits to get different LED_CLK phases in calib mode.;;80M mode:16phases, 22.5 deg separation(360/16)-6.25n separation;;40M mode:16phases, 45 deg separation(360/8)-12.5n separation;;Basically 40M mode MSB bit is unused.
tgrosch 0:62b846b3988a 359 shut_clocks(1), ///< shut_clocks;Register Addresses: 113[8:8];to shut down all 20M, 10M clock switching
tgrosch 0:62b846b3988a 360 invert_tg_clk(1), ///< invert_tg_clk;Register Addresses: 113[9:9];to invert tg_clk for timing requirements
tgrosch 0:62b846b3988a 361 invert_afe_clk(1), ///< invert_afe_clk;Register Addresses: 113[11:11];
tgrosch 0:62b846b3988a 362 dis_illum_clk_tx(1), ///< dis_illum_clk_tx;Register Addresses: 113[12:12];Disable LED clk going to transmitter
tgrosch 0:62b846b3988a 363 en_illum_clk_gpio(1), ///< en_illum_clk_gpio;Register Addresses: 113[16:16];Disable LED CLK going to GPIO
tgrosch 0:62b846b3988a 364 illum_clk_gpio_mode(1), ///< illum_clk_gpio_mode;Register Addresses: 113[15:15];When this bit is '1', illum_en gating led_clk going to GPIO is masked.;
tgrosch 0:62b846b3988a 365 unmask_illumen_intxtalk(1), ///< unmask_illumen_intxtalk;Register Addresses: 113[17:17];Mask internal crosstalk signal gating illum_en.
tgrosch 0:62b846b3988a 366 temp_offset(1), ///< temp_offset;Register Addresses: 110[16:8];temperature offset
tgrosch 0:62b846b3988a 367 en_temp_conv(1), ///< en_temp_conv;Register Addresses: 110[19:19];To enable temperature conversion
tgrosch 0:62b846b3988a 368 calib_curr1_DAC_I(1), ///< calib_curr1_DAC_I; Register Address 116[3:0]
tgrosch 0:62b846b3988a 369 calib_curr1_DAC_Q(1), ///< calib_curr1_DAC_Q; Register Address 116[7:4]
tgrosch 0:62b846b3988a 370 calib_curr1_en_I(1), ///< calib_curr1_en_I; Register Address 116[8:8]
tgrosch 0:62b846b3988a 371 calib_curr1_en_Q(1), ///< calib_curr1_en_Q; Register Address 116[9:9]
tgrosch 0:62b846b3988a 372 calib_curr1_inv_CLK_I(1), ///< calib_curr1_inv_CLK_I; Register Address 116[10:10]
tgrosch 0:62b846b3988a 373 calib_curr1_inv_CLK_Q(1), ///< calib_curr1_inv_CLK_Q; Register Address 116[11:11]
tgrosch 0:62b846b3988a 374 calib_curr1_sel_CLK_I(1), ///< calib_curr1_sel_CLK_I; Register Address 116[12:12]
tgrosch 0:62b846b3988a 375 calib_curr1_gain_sel(1), ///< calib_curr1_gain_sel; Register Address 116[14:13]
tgrosch 0:62b846b3988a 376 calib_curr1_spare(1), ///< calib_curr1_spare; Register Address 116[15:15]
tgrosch 0:62b846b3988a 377 dis_glb_pd_refsys(1), ///< dis_glb_pd_refsys;Register Addresses: 118[0:0];
tgrosch 0:62b846b3988a 378 dis_glb_pd_temp_sens(1), ///< dis_glb_pd_temp_sens;Register Addresses: 118[1:1];
tgrosch 0:62b846b3988a 379 dis_glb_pd_illum_drv(1), ///< dis_glb_pd_illum_drv;Register Addresses: 118[2:2];
tgrosch 0:62b846b3988a 380 dis_glb_pd_afe(1), ///< dis_glb_pd_afe;Register Addresses: 118[3:3];
tgrosch 0:62b846b3988a 381 dis_glb_pd_afe_dac(1), ///< dis_glb_pd_afe_dac;Register Addresses: 118[4:4];
tgrosch 0:62b846b3988a 382 dis_glb_pd_amb_dac(1), ///< dis_glb_pd_amb_dac;Register Addresses: 118[5:5];
tgrosch 0:62b846b3988a 383 dis_glb_pd_amb_adc(1), ///< dis_glb_pd_amb_adc;Register Addresses: 118[6:6];
tgrosch 0:62b846b3988a 384 dis_glb_pd_test_curr(1), ///< dis_glb_pd_test_curr;Register Addresses: 118[7:7];
tgrosch 0:62b846b3988a 385 dis_glb_pd_osc(1), ///< dis_glb_pd_osc;Register Addresses: 118[8:8];
tgrosch 0:62b846b3988a 386 dis_glb_pd_i2chost(1), ///< dis_glb_pd_i2chost;Register Addresses: 118[9:9];
tgrosch 0:62b846b3988a 387 pdn_global(1), ///< pdn_global;Register Addresses: 118[11:11];
tgrosch 0:62b846b3988a 388 en_dyn_pd_refsys(1), ///< en_dyn_pd_refsys;Register Addresses: 119[0:0];
tgrosch 0:62b846b3988a 389 en_dyn_pd_temp_sens(1), ///< en_dyn_pd_temp_sens;Register Addresses: 119[1:1];
tgrosch 0:62b846b3988a 390 en_dyn_pd_illum_drv(1), ///< en_dyn_pd_illum_drv;Register Addresses: 119[2:2];
tgrosch 0:62b846b3988a 391 en_dyn_pd_afe(1), ///< en_dyn_pd_afe;Register Addresses: 119[3:3];
tgrosch 0:62b846b3988a 392 en_dyn_pd_afe_dac(1), ///< en_dyn_pd_afe_dac;Register Addresses: 119[4:4];
tgrosch 0:62b846b3988a 393 en_dyn_pd_amb_dac(1), ///< en_dyn_pd_amb_dac;Register Addresses: 119[5:5];
tgrosch 0:62b846b3988a 394 en_dyn_pd_amb_adc(1), ///< en_dyn_pd_amb_adc;Register Addresses: 119[6:6];
tgrosch 0:62b846b3988a 395 en_dyn_pd_test_curr(1), ///< en_dyn_pd_test_curr;Register Addresses: 119[7:7];
tgrosch 0:62b846b3988a 396 en_dyn_pd_osc(1), ///< en_dyn_pd_osc;Register Addresses: 119[8:8];
tgrosch 0:62b846b3988a 397 en_dyn_pd_i2chost_osc(1), ///< en_dyn_pd_i2chost_osc;Register Addresses: 119[9:9];
tgrosch 0:62b846b3988a 398 TX0_PIN_CONFIG(1), ///< TX0_PIN_CONFIG;Register Addresses: 122[5:4];
tgrosch 0:62b846b3988a 399 TX1_PIN_CONFIG(1), ///< TX1_PIN_CONFIG;Register Addresses: 122[1:0];
tgrosch 0:62b846b3988a 400 TX2_PIN_CONFIG(1), ///< TX2_PIN_CONFIG;Register Addresses: 122[3:2];
tgrosch 0:62b846b3988a 401 EN_TX_CLKB(1), ///< EN_TX_CLKB;Register Addresses: 121[0:0];
tgrosch 0:62b846b3988a 402 EN_TX_CLKZ(1), ///< EN_TX_CLKZ;Register Addresses: 121[2:2];
tgrosch 0:62b846b3988a 403 sel_illum_tx0_on_tx1(1), ///< sel_illum_tx0_on_tx1;Register Addresses: 121[3:3];Force ILLUM_EN_0 (TX0) onto ILLUM_EN_1 (TX1). This mode is required to enable static LED drive mode.
tgrosch 0:62b846b3988a 404 ILLUM_DC_CURR_DAC(1), ///< ILLUM_DC_CURR_DAC;Register Addresses: 121[11:8];0.5mA*register setting
tgrosch 0:62b846b3988a 405 PDN_ILLUM_DC_CURR(1), ///< PDN_ILLUM_DC_CURR;Register Addresses: 121[12:12];
tgrosch 0:62b846b3988a 406 FEEDBACK_CONT_MODE(1), ///< FEEDBACK_CONT_MODE;Register Addresses: 121[13:13];
tgrosch 0:62b846b3988a 407 PDN_ILLUM_DRV(1), ///< PDN_ILLUM_DRV;Register Addresses: 121[19:19];
tgrosch 0:62b846b3988a 408 EN_TX_DC_CURR_ALL(1), ///< EN_TX_DC_CURR_ALL;Register Addresses: 121[4:4];
tgrosch 0:62b846b3988a 409 EN_CTALK_FB_CLK(1), ///< EN_CTALK_FB_CLK; Register Address 122[11:11]
tgrosch 0:62b846b3988a 410 EN_CALIB_CLK(1) ///< EN_CALIB_CLK; Register Address 122[1:1]
tgrosch 0:62b846b3988a 411 {
tgrosch 0:62b846b3988a 412 //Initialization for register dig_gpo_sel0
tgrosch 0:62b846b3988a 413 this->dig_gpo_sel0.address[0] = 0x0b; ///< Address=11
tgrosch 0:62b846b3988a 414 this->dig_gpo_sel0.msb[0] = 3;
tgrosch 0:62b846b3988a 415 this->dig_gpo_sel0.lsb[0] = 0;
tgrosch 0:62b846b3988a 416
tgrosch 0:62b846b3988a 417 //Initialization for register dig_gpo_sel1
tgrosch 0:62b846b3988a 418 this->dig_gpo_sel1.address[0] = 0x0b; ///< Address=11
tgrosch 0:62b846b3988a 419 this->dig_gpo_sel1.msb[0] = 7;
tgrosch 0:62b846b3988a 420 this->dig_gpo_sel1.lsb[0] = 4;
tgrosch 0:62b846b3988a 421
tgrosch 0:62b846b3988a 422 //Initialization for register dig_gpo_sel2
tgrosch 0:62b846b3988a 423 this->dig_gpo_sel2.address[0] = 0x0b; ///< Address=11
tgrosch 0:62b846b3988a 424 this->dig_gpo_sel2.msb[0] = 13;
tgrosch 0:62b846b3988a 425 this->dig_gpo_sel2.lsb[0] = 10;
tgrosch 0:62b846b3988a 426
tgrosch 0:62b846b3988a 427 //Initialization for register dis_ovl_gating
tgrosch 0:62b846b3988a 428 this->dis_ovl_gating.address[0] = 0x11; ///< Address=17
tgrosch 0:62b846b3988a 429 this->dis_ovl_gating.msb[0] = 15;
tgrosch 0:62b846b3988a 430 this->dis_ovl_gating.lsb[0] = 15;
tgrosch 0:62b846b3988a 431
tgrosch 0:62b846b3988a 432 //Initialization for register phase_out
tgrosch 0:62b846b3988a 433 this->phase_out.address[0] = 0x08; ///< Address=8
tgrosch 0:62b846b3988a 434 this->phase_out.msb[0] = 15;
tgrosch 0:62b846b3988a 435 this->phase_out.lsb[0] = 0;
tgrosch 0:62b846b3988a 436
tgrosch 0:62b846b3988a 437 //Initialization for register phase_overflow
tgrosch 0:62b846b3988a 438 this->phase_overflow.address[0] = 0x08; ///< Address=8
tgrosch 0:62b846b3988a 439 this->phase_overflow.msb[0] = 16;
tgrosch 0:62b846b3988a 440 this->phase_overflow.lsb[0] = 16;
tgrosch 0:62b846b3988a 441
tgrosch 0:62b846b3988a 442 //Initialization for register hdr_mode
tgrosch 0:62b846b3988a 443 this->hdr_mode.address[0] = 0x08; ///< Address=8
tgrosch 0:62b846b3988a 444 this->hdr_mode.msb[0] = 17;
tgrosch 0:62b846b3988a 445 this->hdr_mode.lsb[0] = 17;
tgrosch 0:62b846b3988a 446
tgrosch 0:62b846b3988a 447 //Initialization for register tx_channel
tgrosch 0:62b846b3988a 448 this->tx_channel.address[0] = 0x08; ///< Address=8
tgrosch 0:62b846b3988a 449 this->tx_channel.msb[0] = 19;
tgrosch 0:62b846b3988a 450 this->tx_channel.lsb[0] = 18;
tgrosch 0:62b846b3988a 451
tgrosch 0:62b846b3988a 452 //Initialization for register frame_status
tgrosch 0:62b846b3988a 453 this->frame_status.address[0] = 0x08; ///< Address=8
tgrosch 0:62b846b3988a 454 this->frame_status.msb[0] = 20;
tgrosch 0:62b846b3988a 455 this->frame_status.lsb[0] = 20;
tgrosch 0:62b846b3988a 456
tgrosch 0:62b846b3988a 457 //Initialization for register mod_freq
tgrosch 0:62b846b3988a 458 this->mod_freq.address[0] = 0x08; ///< Address=8
tgrosch 0:62b846b3988a 459 this->mod_freq.msb[0] = 21;
tgrosch 0:62b846b3988a 460 this->mod_freq.lsb[0] = 21;
tgrosch 0:62b846b3988a 461
tgrosch 0:62b846b3988a 462 //Initialization for register frame_count0
tgrosch 0:62b846b3988a 463 this->frame_count0.address[0] = 0x08; ///< Address=8
tgrosch 0:62b846b3988a 464 this->frame_count0.msb[0] = 23;
tgrosch 0:62b846b3988a 465 this->frame_count0.lsb[0] = 23;
tgrosch 0:62b846b3988a 466
tgrosch 0:62b846b3988a 467 //Initialization for register amp_out
tgrosch 0:62b846b3988a 468 this->amp_out.address[0] = 0x09; ///< Address=9
tgrosch 0:62b846b3988a 469 this->amp_out.msb[0] = 15;
tgrosch 0:62b846b3988a 470 this->amp_out.lsb[0] = 0;
tgrosch 0:62b846b3988a 471
tgrosch 0:62b846b3988a 472 //Initialization for register frame_count1
tgrosch 0:62b846b3988a 473 this->frame_count1.address[0] = 0x09; ///< Address=9
tgrosch 0:62b846b3988a 474 this->frame_count1.msb[0] = 17;
tgrosch 0:62b846b3988a 475 this->frame_count1.lsb[0] = 16;
tgrosch 0:62b846b3988a 476
tgrosch 0:62b846b3988a 477 //Initialization for register sig_ovl_flag
tgrosch 0:62b846b3988a 478 this->sig_ovl_flag.address[0] = 0x09; ///< Address=9
tgrosch 0:62b846b3988a 479 this->sig_ovl_flag.msb[0] = 18;
tgrosch 0:62b846b3988a 480 this->sig_ovl_flag.lsb[0] = 18;
tgrosch 0:62b846b3988a 481
tgrosch 0:62b846b3988a 482 //Initialization for register dealias_bin
tgrosch 0:62b846b3988a 483 this->dealias_bin.address[0] = 0x09; ///< Address=9
tgrosch 0:62b846b3988a 484 this->dealias_bin.msb[0] = 23;
tgrosch 0:62b846b3988a 485 this->dealias_bin.lsb[0] = 20;
tgrosch 0:62b846b3988a 486
tgrosch 0:62b846b3988a 487 //Initialization for register frame_count2
tgrosch 0:62b846b3988a 488 this->frame_count2.address[0] = 0x0a; ///< Address=10
tgrosch 0:62b846b3988a 489 this->frame_count2.msb[0] = 1;
tgrosch 0:62b846b3988a 490 this->frame_count2.lsb[0] = 0;
tgrosch 0:62b846b3988a 491
tgrosch 0:62b846b3988a 492 //Initialization for register amb_data
tgrosch 0:62b846b3988a 493 this->amb_data.address[0] = 0x0a; ///< Address=10
tgrosch 0:62b846b3988a 494 this->amb_data.msb[0] = 11;
tgrosch 0:62b846b3988a 495 this->amb_data.lsb[0] = 2;
tgrosch 0:62b846b3988a 496
tgrosch 0:62b846b3988a 497 //Initialization for register tmain
tgrosch 0:62b846b3988a 498 this->tmain.address[0] = 0x0a; ///< Address=10
tgrosch 0:62b846b3988a 499 this->tmain.msb[0] = 23;
tgrosch 0:62b846b3988a 500 this->tmain.lsb[0] = 12;
tgrosch 0:62b846b3988a 501
tgrosch 0:62b846b3988a 502 //Initialization for register amplitude_min_thr
tgrosch 0:62b846b3988a 503 this->amplitude_min_thr.address[1] = 0x10; ///< Address=16
tgrosch 0:62b846b3988a 504 this->amplitude_min_thr.msb[1] = 23;
tgrosch 0:62b846b3988a 505 this->amplitude_min_thr.lsb[1] = 16;
tgrosch 0:62b846b3988a 506 this->amplitude_min_thr.address[0] = 0x11; ///< Address=17
tgrosch 0:62b846b3988a 507 this->amplitude_min_thr.msb[0] = 23;
tgrosch 0:62b846b3988a 508 this->amplitude_min_thr.lsb[0] = 16;
tgrosch 0:62b846b3988a 509
tgrosch 0:62b846b3988a 510 //Initialization for register amb_ovl_flag
tgrosch 0:62b846b3988a 511 this->amb_ovl_flag.address[0] = 0x08; ///< Address=8
tgrosch 0:62b846b3988a 512 this->amb_ovl_flag.msb[0] = 22;
tgrosch 0:62b846b3988a 513 this->amb_ovl_flag.lsb[0] = 22;
tgrosch 0:62b846b3988a 514
tgrosch 0:62b846b3988a 515 //Initialization for register phase_overflow_f2
tgrosch 0:62b846b3988a 516 this->phase_overflow_f2.address[0] = 0x09; ///< Address=9
tgrosch 0:62b846b3988a 517 this->phase_overflow_f2.msb[0] = 19;
tgrosch 0:62b846b3988a 518 this->phase_overflow_f2.lsb[0] = 19;
tgrosch 0:62b846b3988a 519
tgrosch 0:62b846b3988a 520 //Initialization for register ref_count_limit
tgrosch 0:62b846b3988a 521 this->ref_count_limit.address[0] = 0x0f; ///< Address=15
tgrosch 0:62b846b3988a 522 this->ref_count_limit.msb[0] = 14;
tgrosch 0:62b846b3988a 523 this->ref_count_limit.lsb[0] = 0;
tgrosch 0:62b846b3988a 524
tgrosch 0:62b846b3988a 525 //Initialization for register start_freq_calib
tgrosch 0:62b846b3988a 526 this->start_freq_calib.address[0] = 0x0f; ///< Address=15
tgrosch 0:62b846b3988a 527 this->start_freq_calib.msb[0] = 16;
tgrosch 0:62b846b3988a 528 this->start_freq_calib.lsb[0] = 16;
tgrosch 0:62b846b3988a 529
tgrosch 0:62b846b3988a 530 //Initialization for register sys_clk_divider
tgrosch 0:62b846b3988a 531 this->sys_clk_divider.address[0] = 0x0f; ///< Address=15
tgrosch 0:62b846b3988a 532 this->sys_clk_divider.msb[0] = 20;
tgrosch 0:62b846b3988a 533 this->sys_clk_divider.lsb[0] = 17;
tgrosch 0:62b846b3988a 534
tgrosch 0:62b846b3988a 535 //Initialization for register freq_count_read_reg
tgrosch 0:62b846b3988a 536 this->freq_count_read_reg.address[0] = 0x10; ///< Address=16
tgrosch 0:62b846b3988a 537 this->freq_count_read_reg.msb[0] = 14;
tgrosch 0:62b846b3988a 538 this->freq_count_read_reg.lsb[0] = 0;
tgrosch 0:62b846b3988a 539
tgrosch 0:62b846b3988a 540 //Initialization for register freq_count_reg
tgrosch 0:62b846b3988a 541 this->freq_count_reg.address[0] = 0x11; ///< Address=17
tgrosch 0:62b846b3988a 542 this->freq_count_reg.msb[0] = 14;
tgrosch 0:62b846b3988a 543 this->freq_count_reg.lsb[0] = 0;
tgrosch 0:62b846b3988a 544
tgrosch 0:62b846b3988a 545 //Initialization for register en_auto_freq_count
tgrosch 0:62b846b3988a 546 this->en_auto_freq_count.address[0] = 0x0f; ///< Address=15
tgrosch 0:62b846b3988a 547 this->en_auto_freq_count.msb[0] = 21;
tgrosch 0:62b846b3988a 548 this->en_auto_freq_count.lsb[0] = 21;
tgrosch 0:62b846b3988a 549
tgrosch 0:62b846b3988a 550 //Initialization for register en_floop
tgrosch 0:62b846b3988a 551 this->en_floop.address[0] = 0x0f; ///< Address=15
tgrosch 0:62b846b3988a 552 this->en_floop.msb[0] = 22;
tgrosch 0:62b846b3988a 553 this->en_floop.lsb[0] = 22;
tgrosch 0:62b846b3988a 554
tgrosch 0:62b846b3988a 555 //Initialization for register en_freq_corr
tgrosch 0:62b846b3988a 556 this->en_freq_corr.address[0] = 0x0f; ///< Address=15
tgrosch 0:62b846b3988a 557 this->en_freq_corr.msb[0] = 23;
tgrosch 0:62b846b3988a 558 this->en_freq_corr.lsb[0] = 23;
tgrosch 0:62b846b3988a 559
tgrosch 0:62b846b3988a 560 //Initialization for register en_cont_fcalib
tgrosch 0:62b846b3988a 561 this->en_cont_fcalib.address[0] = 0x10; ///< Address=16
tgrosch 0:62b846b3988a 562 this->en_cont_fcalib.msb[0] = 15;
tgrosch 0:62b846b3988a 563 this->en_cont_fcalib.lsb[0] = 15;
tgrosch 0:62b846b3988a 564
tgrosch 0:62b846b3988a 565 //Initialization for register monoshot_bit
tgrosch 0:62b846b3988a 566 this->monoshot_bit.address[0] = 0x00; ///< Address=0
tgrosch 0:62b846b3988a 567 this->monoshot_bit.msb[0] = 23;
tgrosch 0:62b846b3988a 568 this->monoshot_bit.lsb[0] = 23;
tgrosch 0:62b846b3988a 569
tgrosch 0:62b846b3988a 570 //Initialization for register monoshot_mode
tgrosch 0:62b846b3988a 571 this->monoshot_mode.address[0] = 0x27; ///< Address=39
tgrosch 0:62b846b3988a 572 this->monoshot_mode.msb[0] = 1;
tgrosch 0:62b846b3988a 573 this->monoshot_mode.lsb[0] = 0;
tgrosch 0:62b846b3988a 574
tgrosch 0:62b846b3988a 575 //Initialization for register powerup_delay
tgrosch 0:62b846b3988a 576 this->powerup_delay.address[0] = 0x26; ///< Address=38
tgrosch 0:62b846b3988a 577 this->powerup_delay.msb[0] = 23;
tgrosch 0:62b846b3988a 578 this->powerup_delay.lsb[0] = 10;
tgrosch 0:62b846b3988a 579
tgrosch 0:62b846b3988a 580 //Initialization for register monoshot_numframe
tgrosch 0:62b846b3988a 581 this->monoshot_numframe.address[0] = 0x27; ///< Address=39
tgrosch 0:62b846b3988a 582 this->monoshot_numframe.msb[0] = 7;
tgrosch 0:62b846b3988a 583 this->monoshot_numframe.lsb[0] = 2;
tgrosch 0:62b846b3988a 584
tgrosch 0:62b846b3988a 585 //Initialization for register monoshot_fz_clkcnt
tgrosch 0:62b846b3988a 586 this->monoshot_fz_clkcnt.address[0] = 0x27; ///< Address=39
tgrosch 0:62b846b3988a 587 this->monoshot_fz_clkcnt.msb[0] = 23;
tgrosch 0:62b846b3988a 588 this->monoshot_fz_clkcnt.lsb[0] = 8;
tgrosch 0:62b846b3988a 589
tgrosch 0:62b846b3988a 590 //Initialization for register en_tx_switch
tgrosch 0:62b846b3988a 591 this->en_tx_switch.address[0] = 0x2a; ///< Address=42
tgrosch 0:62b846b3988a 592 this->en_tx_switch.msb[0] = 0;
tgrosch 0:62b846b3988a 593 this->en_tx_switch.lsb[0] = 0;
tgrosch 0:62b846b3988a 594
tgrosch 0:62b846b3988a 595 //Initialization for register sel_tx_ch
tgrosch 0:62b846b3988a 596 this->sel_tx_ch.address[0] = 0x2a; ///< Address=42
tgrosch 0:62b846b3988a 597 this->sel_tx_ch.msb[0] = 2;
tgrosch 0:62b846b3988a 598 this->sel_tx_ch.lsb[0] = 1;
tgrosch 0:62b846b3988a 599
tgrosch 0:62b846b3988a 600 //Initialization for register tx_seq_reg
tgrosch 0:62b846b3988a 601 this->tx_seq_reg.address[0] = 0x2a; ///< Address=42
tgrosch 0:62b846b3988a 602 this->tx_seq_reg.msb[0] = 14;
tgrosch 0:62b846b3988a 603 this->tx_seq_reg.lsb[0] = 3;
tgrosch 0:62b846b3988a 604
tgrosch 0:62b846b3988a 605 //Initialization for register en_adaptive_hdr
tgrosch 0:62b846b3988a 606 this->en_adaptive_hdr.address[0] = 0x2a; ///< Address=42
tgrosch 0:62b846b3988a 607 this->en_adaptive_hdr.msb[0] = 15;
tgrosch 0:62b846b3988a 608 this->en_adaptive_hdr.lsb[0] = 15;
tgrosch 0:62b846b3988a 609
tgrosch 0:62b846b3988a 610 //Initialization for register sel_hdr_mode
tgrosch 0:62b846b3988a 611 this->sel_hdr_mode.address[0] = 0x2a; ///< Address=42
tgrosch 0:62b846b3988a 612 this->sel_hdr_mode.msb[0] = 16;
tgrosch 0:62b846b3988a 613 this->sel_hdr_mode.lsb[0] = 16;
tgrosch 0:62b846b3988a 614
tgrosch 0:62b846b3988a 615 //Initialization for register hdr_thr_low
tgrosch 0:62b846b3988a 616 this->hdr_thr_low.address[0] = 0x2c; ///< Address=44
tgrosch 0:62b846b3988a 617 this->hdr_thr_low.msb[0] = 15;
tgrosch 0:62b846b3988a 618 this->hdr_thr_low.lsb[0] = 0;
tgrosch 0:62b846b3988a 619
tgrosch 0:62b846b3988a 620 //Initialization for register hdr_thr_high
tgrosch 0:62b846b3988a 621 this->hdr_thr_high.address[0] = 0x2b; ///< Address=43
tgrosch 0:62b846b3988a 622 this->hdr_thr_high.msb[0] = 15;
tgrosch 0:62b846b3988a 623 this->hdr_thr_high.lsb[0] = 0;
tgrosch 0:62b846b3988a 624
tgrosch 0:62b846b3988a 625 //Initialization for register illum_scale_l_tx0
tgrosch 0:62b846b3988a 626 this->illum_scale_l_tx0.address[0] = 0x2b; ///< Address=43
tgrosch 0:62b846b3988a 627 this->illum_scale_l_tx0.msb[0] = 18;
tgrosch 0:62b846b3988a 628 this->illum_scale_l_tx0.lsb[0] = 16;
tgrosch 0:62b846b3988a 629
tgrosch 0:62b846b3988a 630 //Initialization for register illum_dac_l_tx0
tgrosch 0:62b846b3988a 631 this->illum_dac_l_tx0.address[0] = 0x29; ///< Address=41
tgrosch 0:62b846b3988a 632 this->illum_dac_l_tx0.msb[0] = 4;
tgrosch 0:62b846b3988a 633 this->illum_dac_l_tx0.lsb[0] = 0;
tgrosch 0:62b846b3988a 634
tgrosch 0:62b846b3988a 635 //Initialization for register illum_scale_h_tx0
tgrosch 0:62b846b3988a 636 this->illum_scale_h_tx0.address[0] = 0x2b; ///< Address=43
tgrosch 0:62b846b3988a 637 this->illum_scale_h_tx0.msb[0] = 21;
tgrosch 0:62b846b3988a 638 this->illum_scale_h_tx0.lsb[0] = 19;
tgrosch 0:62b846b3988a 639
tgrosch 0:62b846b3988a 640 //Initialization for register illum_dac_h_tx0
tgrosch 0:62b846b3988a 641 this->illum_dac_h_tx0.address[0] = 0x29; ///< Address=41
tgrosch 0:62b846b3988a 642 this->illum_dac_h_tx0.msb[0] = 9;
tgrosch 0:62b846b3988a 643 this->illum_dac_h_tx0.lsb[0] = 5;
tgrosch 0:62b846b3988a 644
tgrosch 0:62b846b3988a 645 //Initialization for register illum_scale_l_tx1
tgrosch 0:62b846b3988a 646 this->illum_scale_l_tx1.address[0] = 0x2c; ///< Address=44
tgrosch 0:62b846b3988a 647 this->illum_scale_l_tx1.msb[0] = 18;
tgrosch 0:62b846b3988a 648 this->illum_scale_l_tx1.lsb[0] = 16;
tgrosch 0:62b846b3988a 649
tgrosch 0:62b846b3988a 650 //Initialization for register illum_dac_l_tx1
tgrosch 0:62b846b3988a 651 this->illum_dac_l_tx1.address[0] = 0x29; ///< Address=41
tgrosch 0:62b846b3988a 652 this->illum_dac_l_tx1.msb[0] = 14;
tgrosch 0:62b846b3988a 653 this->illum_dac_l_tx1.lsb[0] = 10;
tgrosch 0:62b846b3988a 654
tgrosch 0:62b846b3988a 655 //Initialization for register illum_scale_h_tx1
tgrosch 0:62b846b3988a 656 this->illum_scale_h_tx1.address[0] = 0x2c; ///< Address=44
tgrosch 0:62b846b3988a 657 this->illum_scale_h_tx1.msb[0] = 21;
tgrosch 0:62b846b3988a 658 this->illum_scale_h_tx1.lsb[0] = 19;
tgrosch 0:62b846b3988a 659
tgrosch 0:62b846b3988a 660 //Initialization for register illum_dac_h_tx1
tgrosch 0:62b846b3988a 661 this->illum_dac_h_tx1.address[0] = 0x29; ///< Address=41
tgrosch 0:62b846b3988a 662 this->illum_dac_h_tx1.msb[0] = 19;
tgrosch 0:62b846b3988a 663 this->illum_dac_h_tx1.lsb[0] = 15;
tgrosch 0:62b846b3988a 664
tgrosch 0:62b846b3988a 665 //Initialization for register illum_scale_l_tx2
tgrosch 0:62b846b3988a 666 this->illum_scale_l_tx2.address[0] = 0xb9; ///< Address=185
tgrosch 0:62b846b3988a 667 this->illum_scale_l_tx2.msb[0] = 20;
tgrosch 0:62b846b3988a 668 this->illum_scale_l_tx2.lsb[0] = 18;
tgrosch 0:62b846b3988a 669
tgrosch 0:62b846b3988a 670 //Initialization for register illum_dac_l_tx2
tgrosch 0:62b846b3988a 671 this->illum_dac_l_tx2.address[1] = 0x29; ///< Address=41
tgrosch 0:62b846b3988a 672 this->illum_dac_l_tx2.msb[1] = 23;
tgrosch 0:62b846b3988a 673 this->illum_dac_l_tx2.lsb[1] = 20;
tgrosch 0:62b846b3988a 674 this->illum_dac_l_tx2.address[0] = 0x2a; ///< Address=42
tgrosch 0:62b846b3988a 675 this->illum_dac_l_tx2.msb[0] = 23;
tgrosch 0:62b846b3988a 676 this->illum_dac_l_tx2.lsb[0] = 23;
tgrosch 0:62b846b3988a 677
tgrosch 0:62b846b3988a 678 //Initialization for register illum_scale_h_tx2
tgrosch 0:62b846b3988a 679 this->illum_scale_h_tx2.address[0] = 0xb9; ///< Address=185
tgrosch 0:62b846b3988a 680 this->illum_scale_h_tx2.msb[0] = 23;
tgrosch 0:62b846b3988a 681 this->illum_scale_h_tx2.lsb[0] = 21;
tgrosch 0:62b846b3988a 682
tgrosch 0:62b846b3988a 683 //Initialization for register illum_dac_h_tx2
tgrosch 0:62b846b3988a 684 this->illum_dac_h_tx2.address[0] = 0x2a; ///< Address=42
tgrosch 0:62b846b3988a 685 this->illum_dac_h_tx2.msb[0] = 22;
tgrosch 0:62b846b3988a 686 this->illum_dac_h_tx2.lsb[0] = 18;
tgrosch 0:62b846b3988a 687
tgrosch 0:62b846b3988a 688 //Initialization for register amb_adc_in_tx0
tgrosch 0:62b846b3988a 689 this->amb_adc_in_tx0.address[0] = 0xb9; ///< Address=185
tgrosch 0:62b846b3988a 690 this->amb_adc_in_tx0.msb[0] = 13;
tgrosch 0:62b846b3988a 691 this->amb_adc_in_tx0.lsb[0] = 12;
tgrosch 0:62b846b3988a 692
tgrosch 0:62b846b3988a 693 //Initialization for register amb_adc_in_tx1
tgrosch 0:62b846b3988a 694 this->amb_adc_in_tx1.address[0] = 0xb9; ///< Address=185
tgrosch 0:62b846b3988a 695 this->amb_adc_in_tx1.msb[0] = 15;
tgrosch 0:62b846b3988a 696 this->amb_adc_in_tx1.lsb[0] = 14;
tgrosch 0:62b846b3988a 697
tgrosch 0:62b846b3988a 698 //Initialization for register amb_adc_in_tx2
tgrosch 0:62b846b3988a 699 this->amb_adc_in_tx2.address[0] = 0xb9; ///< Address=185
tgrosch 0:62b846b3988a 700 this->amb_adc_in_tx2.msb[0] = 17;
tgrosch 0:62b846b3988a 701 this->amb_adc_in_tx2.lsb[0] = 16;
tgrosch 0:62b846b3988a 702
tgrosch 0:62b846b3988a 703 //Initialization for register give_dealias_data
tgrosch 0:62b846b3988a 704 this->give_dealias_data.address[0] = 0xb8; ///< Address=184
tgrosch 0:62b846b3988a 705 this->give_dealias_data.msb[0] = 20;
tgrosch 0:62b846b3988a 706 this->give_dealias_data.lsb[0] = 20;
tgrosch 0:62b846b3988a 707
tgrosch 0:62b846b3988a 708 //Initialization for register en_dealias_meas
tgrosch 0:62b846b3988a 709 this->en_dealias_meas.address[0] = 0x40; ///< Address=64
tgrosch 0:62b846b3988a 710 this->en_dealias_meas.msb[0] = 0;
tgrosch 0:62b846b3988a 711 this->en_dealias_meas.lsb[0] = 0;
tgrosch 0:62b846b3988a 712
tgrosch 0:62b846b3988a 713 //Initialization for register ncr_config
tgrosch 0:62b846b3988a 714 this->ncr_config.address[0] = 0x40; ///< Address=64
tgrosch 0:62b846b3988a 715 this->ncr_config.msb[0] = 21;
tgrosch 0:62b846b3988a 716 this->ncr_config.lsb[0] = 21;
tgrosch 0:62b846b3988a 717
tgrosch 0:62b846b3988a 718 //Initialization for register alpha0_dealias_scale
tgrosch 0:62b846b3988a 719 this->alpha0_dealias_scale.address[0] = 0x40; ///< Address=64
tgrosch 0:62b846b3988a 720 this->alpha0_dealias_scale.msb[0] = 14;
tgrosch 0:62b846b3988a 721 this->alpha0_dealias_scale.lsb[0] = 9;
tgrosch 0:62b846b3988a 722
tgrosch 0:62b846b3988a 723 //Initialization for register beta0_dealias_scale
tgrosch 0:62b846b3988a 724 this->beta0_dealias_scale.address[0] = 0x40; ///< Address=64
tgrosch 0:62b846b3988a 725 this->beta0_dealias_scale.msb[0] = 20;
tgrosch 0:62b846b3988a 726 this->beta0_dealias_scale.lsb[0] = 15;
tgrosch 0:62b846b3988a 727
tgrosch 0:62b846b3988a 728 //Initialization for register alpha1_dealias_scale
tgrosch 0:62b846b3988a 729 this->alpha1_dealias_scale.address[0] = 0x41; ///< Address=65
tgrosch 0:62b846b3988a 730 this->alpha1_dealias_scale.msb[0] = 5;
tgrosch 0:62b846b3988a 731 this->alpha1_dealias_scale.lsb[0] = 0;
tgrosch 0:62b846b3988a 732
tgrosch 0:62b846b3988a 733 //Initialization for register beta1_dealias_scale
tgrosch 0:62b846b3988a 734 this->beta1_dealias_scale.address[0] = 0x41; ///< Address=65
tgrosch 0:62b846b3988a 735 this->beta1_dealias_scale.msb[0] = 11;
tgrosch 0:62b846b3988a 736 this->beta1_dealias_scale.lsb[0] = 6;
tgrosch 0:62b846b3988a 737
tgrosch 0:62b846b3988a 738 //Initialization for register en_multi_freq_phase
tgrosch 0:62b846b3988a 739 this->en_multi_freq_phase.address[0] = 0x40; ///< Address=64
tgrosch 0:62b846b3988a 740 this->en_multi_freq_phase.msb[0] = 22;
tgrosch 0:62b846b3988a 741 this->en_multi_freq_phase.lsb[0] = 22;
tgrosch 0:62b846b3988a 742
tgrosch 0:62b846b3988a 743 //Initialization for register temp_avg_main
tgrosch 0:62b846b3988a 744 this->temp_avg_main.address[0] = 0x03; ///< Address=3
tgrosch 0:62b846b3988a 745 this->temp_avg_main.msb[0] = 23;
tgrosch 0:62b846b3988a 746 this->temp_avg_main.lsb[0] = 22;
tgrosch 0:62b846b3988a 747
tgrosch 0:62b846b3988a 748 //Initialization for register dis_ovl_for_hdr_meth1
tgrosch 0:62b846b3988a 749 this->dis_ovl_for_hdr_meth1.address[0] = 0xb8; ///< Address=184
tgrosch 0:62b846b3988a 750 this->dis_ovl_for_hdr_meth1.msb[0] = 21;
tgrosch 0:62b846b3988a 751 this->dis_ovl_for_hdr_meth1.lsb[0] = 21;
tgrosch 0:62b846b3988a 752
tgrosch 0:62b846b3988a 753 //Initialization for register en_ovl_for_hdr_meth2
tgrosch 0:62b846b3988a 754 this->en_ovl_for_hdr_meth2.address[0] = 0xb8; ///< Address=184
tgrosch 0:62b846b3988a 755 this->en_ovl_for_hdr_meth2.msb[0] = 22;
tgrosch 0:62b846b3988a 756 this->en_ovl_for_hdr_meth2.lsb[0] = 22;
tgrosch 0:62b846b3988a 757
tgrosch 0:62b846b3988a 758 //Initialization for register en_tx1_on_tx0
tgrosch 0:62b846b3988a 759 this->en_tx1_on_tx0.address[0] = 0xb9; ///< Address=185
tgrosch 0:62b846b3988a 760 this->en_tx1_on_tx0.msb[0] = 10;
tgrosch 0:62b846b3988a 761 this->en_tx1_on_tx0.lsb[0] = 10;
tgrosch 0:62b846b3988a 762
tgrosch 0:62b846b3988a 763 //Initialization for register en_tx2_on_tx0
tgrosch 0:62b846b3988a 764 this->en_tx2_on_tx0.address[0] = 0xb9; ///< Address=185
tgrosch 0:62b846b3988a 765 this->en_tx2_on_tx0.msb[0] = 11;
tgrosch 0:62b846b3988a 766 this->en_tx2_on_tx0.lsb[0] = 11;
tgrosch 0:62b846b3988a 767
tgrosch 0:62b846b3988a 768 //Initialization for register clip_mode_fc
tgrosch 0:62b846b3988a 769 this->clip_mode_fc.address[0] = 0x50; ///< Address=80
tgrosch 0:62b846b3988a 770 this->clip_mode_fc.msb[0] = 0;
tgrosch 0:62b846b3988a 771 this->clip_mode_fc.lsb[0] = 0;
tgrosch 0:62b846b3988a 772
tgrosch 0:62b846b3988a 773 //Initialization for register clip_mode_nl
tgrosch 0:62b846b3988a 774 this->clip_mode_nl.address[0] = 0x50; ///< Address=80
tgrosch 0:62b846b3988a 775 this->clip_mode_nl.msb[0] = 1;
tgrosch 0:62b846b3988a 776 this->clip_mode_nl.lsb[0] = 1;
tgrosch 0:62b846b3988a 777
tgrosch 0:62b846b3988a 778 //Initialization for register clip_mode_temp
tgrosch 0:62b846b3988a 779 this->clip_mode_temp.address[0] = 0x50; ///< Address=80
tgrosch 0:62b846b3988a 780 this->clip_mode_temp.msb[0] = 2;
tgrosch 0:62b846b3988a 781 this->clip_mode_temp.lsb[0] = 2;
tgrosch 0:62b846b3988a 782
tgrosch 0:62b846b3988a 783 //Initialization for register clip_mode_offset
tgrosch 0:62b846b3988a 784 this->clip_mode_offset.address[0] = 0x50; ///< Address=80
tgrosch 0:62b846b3988a 785 this->clip_mode_offset.msb[0] = 3;
tgrosch 0:62b846b3988a 786 this->clip_mode_offset.lsb[0] = 3;
tgrosch 0:62b846b3988a 787
tgrosch 0:62b846b3988a 788 //Initialization for register disable_syncing
tgrosch 0:62b846b3988a 789 this->disable_syncing.address[0] = 0x50; ///< Address=80
tgrosch 0:62b846b3988a 790 this->disable_syncing.msb[0] = 21;
tgrosch 0:62b846b3988a 791 this->disable_syncing.lsb[0] = 21;
tgrosch 0:62b846b3988a 792
tgrosch 0:62b846b3988a 793 //Initialization for register force_en_slave
tgrosch 0:62b846b3988a 794 this->force_en_slave.address[0] = 0x00; ///< Address=0
tgrosch 0:62b846b3988a 795 this->force_en_slave.msb[0] = 22;
tgrosch 0:62b846b3988a 796 this->force_en_slave.lsb[0] = 22;
tgrosch 0:62b846b3988a 797
tgrosch 0:62b846b3988a 798 //Initialization for register force_en_bypass
tgrosch 0:62b846b3988a 799 this->force_en_bypass.address[0] = 0x00; ///< Address=0
tgrosch 0:62b846b3988a 800 this->force_en_bypass.msb[0] = 21;
tgrosch 0:62b846b3988a 801 this->force_en_bypass.lsb[0] = 21;
tgrosch 0:62b846b3988a 802
tgrosch 0:62b846b3988a 803 //Initialization for register override_clkgen_reg
tgrosch 0:62b846b3988a 804 this->override_clkgen_reg.address[0] = 0x50; ///< Address=80
tgrosch 0:62b846b3988a 805 this->override_clkgen_reg.msb[0] = 22;
tgrosch 0:62b846b3988a 806 this->override_clkgen_reg.lsb[0] = 22;
tgrosch 0:62b846b3988a 807
tgrosch 0:62b846b3988a 808 //Initialization for register software_reset
tgrosch 0:62b846b3988a 809 this->software_reset.address[0] = 0x00; ///< Address=0
tgrosch 0:62b846b3988a 810 this->software_reset.msb[0] = 0;
tgrosch 0:62b846b3988a 811 this->software_reset.lsb[0] = 0;
tgrosch 0:62b846b3988a 812
tgrosch 0:62b846b3988a 813 //Initialization for register dis_tg_aconf
tgrosch 0:62b846b3988a 814 this->dis_tg_aconf.address[0] = 0x80; ///< Address=128
tgrosch 0:62b846b3988a 815 this->dis_tg_aconf.msb[0] = 23;
tgrosch 0:62b846b3988a 816 this->dis_tg_aconf.lsb[0] = 23;
tgrosch 0:62b846b3988a 817
tgrosch 0:62b846b3988a 818 //Initialization for register capture_clk_cnt
tgrosch 0:62b846b3988a 819 this->capture_clk_cnt.address[0] = 0xa0; ///< Address=160
tgrosch 0:62b846b3988a 820 this->capture_clk_cnt.msb[0] = 15;
tgrosch 0:62b846b3988a 821 this->capture_clk_cnt.lsb[0] = 0;
tgrosch 0:62b846b3988a 822
tgrosch 0:62b846b3988a 823 //Initialization for register tg_en
tgrosch 0:62b846b3988a 824 this->tg_en.address[0] = 0x80; ///< Address=128
tgrosch 0:62b846b3988a 825 this->tg_en.msb[0] = 0;
tgrosch 0:62b846b3988a 826 this->tg_en.lsb[0] = 0;
tgrosch 0:62b846b3988a 827
tgrosch 0:62b846b3988a 828 //Initialization for register num_sub_frames
tgrosch 0:62b846b3988a 829 this->num_sub_frames.address[0] = 0x9f; ///< Address=159
tgrosch 0:62b846b3988a 830 this->num_sub_frames.msb[0] = 11;
tgrosch 0:62b846b3988a 831 this->num_sub_frames.lsb[0] = 0;
tgrosch 0:62b846b3988a 832
tgrosch 0:62b846b3988a 833 //Initialization for register num_avg_sub_frames
tgrosch 0:62b846b3988a 834 this->num_avg_sub_frames.address[0] = 0x9f; ///< Address=159
tgrosch 0:62b846b3988a 835 this->num_avg_sub_frames.msb[0] = 23;
tgrosch 0:62b846b3988a 836 this->num_avg_sub_frames.lsb[0] = 12;
tgrosch 0:62b846b3988a 837
tgrosch 0:62b846b3988a 838 //Initialization for register sub_vd_clk_cnt
tgrosch 0:62b846b3988a 839 this->sub_vd_clk_cnt.address[0] = 0x80; ///< Address=128
tgrosch 0:62b846b3988a 840 this->sub_vd_clk_cnt.msb[0] = 16;
tgrosch 0:62b846b3988a 841 this->sub_vd_clk_cnt.lsb[0] = 1;
tgrosch 0:62b846b3988a 842
tgrosch 0:62b846b3988a 843 //Initialization for register tg_illumen_start
tgrosch 0:62b846b3988a 844 this->tg_illumen_start.address[0] = 0x8f; ///< Address=143
tgrosch 0:62b846b3988a 845 this->tg_illumen_start.msb[0] = 15;
tgrosch 0:62b846b3988a 846 this->tg_illumen_start.lsb[0] = 0;
tgrosch 0:62b846b3988a 847
tgrosch 0:62b846b3988a 848 //Initialization for register tg_illumen_end
tgrosch 0:62b846b3988a 849 this->tg_illumen_end.address[0] = 0x90; ///< Address=144
tgrosch 0:62b846b3988a 850 this->tg_illumen_end.msb[0] = 15;
tgrosch 0:62b846b3988a 851 this->tg_illumen_end.lsb[0] = 0;
tgrosch 0:62b846b3988a 852
tgrosch 0:62b846b3988a 853 //Initialization for register tg_illumen_mask_start
tgrosch 0:62b846b3988a 854 this->tg_illumen_mask_start.address[0] = 0x9c; ///< Address=156
tgrosch 0:62b846b3988a 855 this->tg_illumen_mask_start.msb[0] = 11;
tgrosch 0:62b846b3988a 856 this->tg_illumen_mask_start.lsb[0] = 0;
tgrosch 0:62b846b3988a 857
tgrosch 0:62b846b3988a 858 //Initialization for register tg_illumen_mask_end
tgrosch 0:62b846b3988a 859 this->tg_illumen_mask_end.address[0] = 0x9c; ///< Address=156
tgrosch 0:62b846b3988a 860 this->tg_illumen_mask_end.msb[0] = 23;
tgrosch 0:62b846b3988a 861 this->tg_illumen_mask_end.lsb[0] = 12;
tgrosch 0:62b846b3988a 862
tgrosch 0:62b846b3988a 863 //Initialization for register tg_afe_rst_start
tgrosch 0:62b846b3988a 864 this->tg_afe_rst_start.address[0] = 0x83; ///< Address=131
tgrosch 0:62b846b3988a 865 this->tg_afe_rst_start.msb[0] = 15;
tgrosch 0:62b846b3988a 866 this->tg_afe_rst_start.lsb[0] = 0;
tgrosch 0:62b846b3988a 867
tgrosch 0:62b846b3988a 868 //Initialization for register tg_afe_rst_end
tgrosch 0:62b846b3988a 869 this->tg_afe_rst_end.address[0] = 0x84; ///< Address=132
tgrosch 0:62b846b3988a 870 this->tg_afe_rst_end.msb[0] = 15;
tgrosch 0:62b846b3988a 871 this->tg_afe_rst_end.lsb[0] = 0;
tgrosch 0:62b846b3988a 872
tgrosch 0:62b846b3988a 873 //Initialization for register tg_seq_int_start
tgrosch 0:62b846b3988a 874 this->tg_seq_int_start.address[0] = 0x85; ///< Address=133
tgrosch 0:62b846b3988a 875 this->tg_seq_int_start.msb[0] = 15;
tgrosch 0:62b846b3988a 876 this->tg_seq_int_start.lsb[0] = 0;
tgrosch 0:62b846b3988a 877
tgrosch 0:62b846b3988a 878 //Initialization for register tg_seq_int_end
tgrosch 0:62b846b3988a 879 this->tg_seq_int_end.address[0] = 0x86; ///< Address=134
tgrosch 0:62b846b3988a 880 this->tg_seq_int_end.msb[0] = 15;
tgrosch 0:62b846b3988a 881 this->tg_seq_int_end.lsb[0] = 0;
tgrosch 0:62b846b3988a 882
tgrosch 0:62b846b3988a 883 //Initialization for register tg_capture_start
tgrosch 0:62b846b3988a 884 this->tg_capture_start.address[0] = 0x87; ///< Address=135
tgrosch 0:62b846b3988a 885 this->tg_capture_start.msb[0] = 15;
tgrosch 0:62b846b3988a 886 this->tg_capture_start.lsb[0] = 0;
tgrosch 0:62b846b3988a 887
tgrosch 0:62b846b3988a 888 //Initialization for register tg_capture_end
tgrosch 0:62b846b3988a 889 this->tg_capture_end.address[0] = 0x88; ///< Address=136
tgrosch 0:62b846b3988a 890 this->tg_capture_end.msb[0] = 15;
tgrosch 0:62b846b3988a 891 this->tg_capture_end.lsb[0] = 0;
tgrosch 0:62b846b3988a 892
tgrosch 0:62b846b3988a 893 //Initialization for register tg_ovl_window_start
tgrosch 0:62b846b3988a 894 this->tg_ovl_window_start.address[0] = 0x89; ///< Address=137
tgrosch 0:62b846b3988a 895 this->tg_ovl_window_start.msb[0] = 15;
tgrosch 0:62b846b3988a 896 this->tg_ovl_window_start.lsb[0] = 0;
tgrosch 0:62b846b3988a 897
tgrosch 0:62b846b3988a 898 //Initialization for register tg_ovl_window_end
tgrosch 0:62b846b3988a 899 this->tg_ovl_window_end.address[0] = 0x8a; ///< Address=138
tgrosch 0:62b846b3988a 900 this->tg_ovl_window_end.msb[0] = 15;
tgrosch 0:62b846b3988a 901 this->tg_ovl_window_end.lsb[0] = 0;
tgrosch 0:62b846b3988a 902
tgrosch 0:62b846b3988a 903 //Initialization for register tg_calc_start
tgrosch 0:62b846b3988a 904 this->tg_calc_start.address[0] = 0x91; ///< Address=145
tgrosch 0:62b846b3988a 905 this->tg_calc_start.msb[0] = 15;
tgrosch 0:62b846b3988a 906 this->tg_calc_start.lsb[0] = 0;
tgrosch 0:62b846b3988a 907
tgrosch 0:62b846b3988a 908 //Initialization for register tg_calc_end
tgrosch 0:62b846b3988a 909 this->tg_calc_end.address[0] = 0x92; ///< Address=146
tgrosch 0:62b846b3988a 910 this->tg_calc_end.msb[0] = 15;
tgrosch 0:62b846b3988a 911 this->tg_calc_end.lsb[0] = 0;
tgrosch 0:62b846b3988a 912
tgrosch 0:62b846b3988a 913 //Initialization for register tg_dynpdn_start
tgrosch 0:62b846b3988a 914 this->tg_dynpdn_start.address[0] = 0x93; ///< Address=147
tgrosch 0:62b846b3988a 915 this->tg_dynpdn_start.msb[0] = 15;
tgrosch 0:62b846b3988a 916 this->tg_dynpdn_start.lsb[0] = 0;
tgrosch 0:62b846b3988a 917
tgrosch 0:62b846b3988a 918 //Initialization for register tg_dynpdn_end
tgrosch 0:62b846b3988a 919 this->tg_dynpdn_end.address[0] = 0x94; ///< Address=148
tgrosch 0:62b846b3988a 920 this->tg_dynpdn_end.msb[0] = 15;
tgrosch 0:62b846b3988a 921 this->tg_dynpdn_end.lsb[0] = 0;
tgrosch 0:62b846b3988a 922
tgrosch 0:62b846b3988a 923 //Initialization for register tg_seq_int_mask_start
tgrosch 0:62b846b3988a 924 this->tg_seq_int_mask_start.address[0] = 0x97; ///< Address=151
tgrosch 0:62b846b3988a 925 this->tg_seq_int_mask_start.msb[0] = 11;
tgrosch 0:62b846b3988a 926 this->tg_seq_int_mask_start.lsb[0] = 0;
tgrosch 0:62b846b3988a 927
tgrosch 0:62b846b3988a 928 //Initialization for register tg_seq_int_mask_end
tgrosch 0:62b846b3988a 929 this->tg_seq_int_mask_end.address[0] = 0x97; ///< Address=151
tgrosch 0:62b846b3988a 930 this->tg_seq_int_mask_end.msb[0] = 23;
tgrosch 0:62b846b3988a 931 this->tg_seq_int_mask_end.lsb[0] = 12;
tgrosch 0:62b846b3988a 932
tgrosch 0:62b846b3988a 933 //Initialization for register tg_capture_mask_start
tgrosch 0:62b846b3988a 934 this->tg_capture_mask_start.address[0] = 0x98; ///< Address=152
tgrosch 0:62b846b3988a 935 this->tg_capture_mask_start.msb[0] = 11;
tgrosch 0:62b846b3988a 936 this->tg_capture_mask_start.lsb[0] = 0;
tgrosch 0:62b846b3988a 937
tgrosch 0:62b846b3988a 938 //Initialization for register tg_capture_mask_end
tgrosch 0:62b846b3988a 939 this->tg_capture_mask_end.address[0] = 0x98; ///< Address=152
tgrosch 0:62b846b3988a 940 this->tg_capture_mask_end.msb[0] = 23;
tgrosch 0:62b846b3988a 941 this->tg_capture_mask_end.lsb[0] = 12;
tgrosch 0:62b846b3988a 942
tgrosch 0:62b846b3988a 943 //Initialization for register tg_ovl_window_mask_start
tgrosch 0:62b846b3988a 944 this->tg_ovl_window_mask_start.address[0] = 0x99; ///< Address=153
tgrosch 0:62b846b3988a 945 this->tg_ovl_window_mask_start.msb[0] = 11;
tgrosch 0:62b846b3988a 946 this->tg_ovl_window_mask_start.lsb[0] = 0;
tgrosch 0:62b846b3988a 947
tgrosch 0:62b846b3988a 948 //Initialization for register tg_ovl_window_mask_end
tgrosch 0:62b846b3988a 949 this->tg_ovl_window_mask_end.address[0] = 0x99; ///< Address=153
tgrosch 0:62b846b3988a 950 this->tg_ovl_window_mask_end.msb[0] = 23;
tgrosch 0:62b846b3988a 951 this->tg_ovl_window_mask_end.lsb[0] = 12;
tgrosch 0:62b846b3988a 952
tgrosch 0:62b846b3988a 953 //Initialization for register tg_calc_mask_start
tgrosch 0:62b846b3988a 954 this->tg_calc_mask_start.address[0] = 0x9d; ///< Address=157
tgrosch 0:62b846b3988a 955 this->tg_calc_mask_start.msb[0] = 11;
tgrosch 0:62b846b3988a 956 this->tg_calc_mask_start.lsb[0] = 0;
tgrosch 0:62b846b3988a 957
tgrosch 0:62b846b3988a 958 //Initialization for register tg_calc_mask_end
tgrosch 0:62b846b3988a 959 this->tg_calc_mask_end.address[0] = 0x9d; ///< Address=157
tgrosch 0:62b846b3988a 960 this->tg_calc_mask_end.msb[0] = 23;
tgrosch 0:62b846b3988a 961 this->tg_calc_mask_end.lsb[0] = 12;
tgrosch 0:62b846b3988a 962
tgrosch 0:62b846b3988a 963 //Initialization for register tg_dynpdn_mask_start
tgrosch 0:62b846b3988a 964 this->tg_dynpdn_mask_start.address[0] = 0x9e; ///< Address=158
tgrosch 0:62b846b3988a 965 this->tg_dynpdn_mask_start.msb[0] = 11;
tgrosch 0:62b846b3988a 966 this->tg_dynpdn_mask_start.lsb[0] = 0;
tgrosch 0:62b846b3988a 967
tgrosch 0:62b846b3988a 968 //Initialization for register tg_dynpdn_mask_end
tgrosch 0:62b846b3988a 969 this->tg_dynpdn_mask_end.address[0] = 0x9e; ///< Address=158
tgrosch 0:62b846b3988a 970 this->tg_dynpdn_mask_end.msb[0] = 23;
tgrosch 0:62b846b3988a 971 this->tg_dynpdn_mask_end.lsb[0] = 12;
tgrosch 0:62b846b3988a 972
tgrosch 0:62b846b3988a 973 //Initialization for register en_sequencer
tgrosch 0:62b846b3988a 974 this->en_sequencer.address[0] = 0x14; ///< Address=20
tgrosch 0:62b846b3988a 975 this->en_sequencer.msb[0] = 16;
tgrosch 0:62b846b3988a 976 this->en_sequencer.lsb[0] = 16;
tgrosch 0:62b846b3988a 977
tgrosch 0:62b846b3988a 978 //Initialization for register en_processor_values
tgrosch 0:62b846b3988a 979 this->en_processor_values.address[0] = 0x14; ///< Address=20
tgrosch 0:62b846b3988a 980 this->en_processor_values.msb[0] = 17;
tgrosch 0:62b846b3988a 981 this->en_processor_values.lsb[0] = 17;
tgrosch 0:62b846b3988a 982
tgrosch 0:62b846b3988a 983 //Initialization for register status_in_reg
tgrosch 0:62b846b3988a 984 this->status_in_reg.address[0] = 0x14; ///< Address=20
tgrosch 0:62b846b3988a 985 this->status_in_reg.msb[0] = 18;
tgrosch 0:62b846b3988a 986 this->status_in_reg.lsb[0] = 18;
tgrosch 0:62b846b3988a 987
tgrosch 0:62b846b3988a 988 //Initialization for register mux_sel_compin
tgrosch 0:62b846b3988a 989 this->mux_sel_compin.address[0] = 0x13; ///< Address=19
tgrosch 0:62b846b3988a 990 this->mux_sel_compin.msb[0] = 2;
tgrosch 0:62b846b3988a 991 this->mux_sel_compin.lsb[0] = 0;
tgrosch 0:62b846b3988a 992
tgrosch 0:62b846b3988a 993 //Initialization for register compare_reg1
tgrosch 0:62b846b3988a 994 this->compare_reg1.address[0] = 0x13; ///< Address=19
tgrosch 0:62b846b3988a 995 this->compare_reg1.msb[0] = 18;
tgrosch 0:62b846b3988a 996 this->compare_reg1.lsb[0] = 3;
tgrosch 0:62b846b3988a 997
tgrosch 0:62b846b3988a 998 //Initialization for register compare_reg2
tgrosch 0:62b846b3988a 999 this->compare_reg2.address[0] = 0x14; ///< Address=20
tgrosch 0:62b846b3988a 1000 this->compare_reg2.msb[0] = 15;
tgrosch 0:62b846b3988a 1001 this->compare_reg2.lsb[0] = 0;
tgrosch 0:62b846b3988a 1002
tgrosch 0:62b846b3988a 1003 //Initialization for register dis_interrupt
tgrosch 0:62b846b3988a 1004 this->dis_interrupt.address[0] = 0x14; ///< Address=20
tgrosch 0:62b846b3988a 1005 this->dis_interrupt.msb[0] = 19;
tgrosch 0:62b846b3988a 1006 this->dis_interrupt.lsb[0] = 19;
tgrosch 0:62b846b3988a 1007
tgrosch 0:62b846b3988a 1008 //Initialization for register command0
tgrosch 0:62b846b3988a 1009 this->command0.address[0] = 0x15; ///< Address=21
tgrosch 0:62b846b3988a 1010 this->command0.msb[0] = 11;
tgrosch 0:62b846b3988a 1011 this->command0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1012
tgrosch 0:62b846b3988a 1013 //Initialization for register command1
tgrosch 0:62b846b3988a 1014 this->command1.address[0] = 0x15; ///< Address=21
tgrosch 0:62b846b3988a 1015 this->command1.msb[0] = 23;
tgrosch 0:62b846b3988a 1016 this->command1.lsb[0] = 12;
tgrosch 0:62b846b3988a 1017
tgrosch 0:62b846b3988a 1018 //Initialization for register command2
tgrosch 0:62b846b3988a 1019 this->command2.address[0] = 0x16; ///< Address=22
tgrosch 0:62b846b3988a 1020 this->command2.msb[0] = 11;
tgrosch 0:62b846b3988a 1021 this->command2.lsb[0] = 0;
tgrosch 0:62b846b3988a 1022
tgrosch 0:62b846b3988a 1023 //Initialization for register command3
tgrosch 0:62b846b3988a 1024 this->command3.address[0] = 0x16; ///< Address=22
tgrosch 0:62b846b3988a 1025 this->command3.msb[0] = 23;
tgrosch 0:62b846b3988a 1026 this->command3.lsb[0] = 12;
tgrosch 0:62b846b3988a 1027
tgrosch 0:62b846b3988a 1028 //Initialization for register command4
tgrosch 0:62b846b3988a 1029 this->command4.address[0] = 0x17; ///< Address=23
tgrosch 0:62b846b3988a 1030 this->command4.msb[0] = 11;
tgrosch 0:62b846b3988a 1031 this->command4.lsb[0] = 0;
tgrosch 0:62b846b3988a 1032
tgrosch 0:62b846b3988a 1033 //Initialization for register command5
tgrosch 0:62b846b3988a 1034 this->command5.address[0] = 0x17; ///< Address=23
tgrosch 0:62b846b3988a 1035 this->command5.msb[0] = 23;
tgrosch 0:62b846b3988a 1036 this->command5.lsb[0] = 12;
tgrosch 0:62b846b3988a 1037
tgrosch 0:62b846b3988a 1038 //Initialization for register command6
tgrosch 0:62b846b3988a 1039 this->command6.address[0] = 0x18; ///< Address=24
tgrosch 0:62b846b3988a 1040 this->command6.msb[0] = 11;
tgrosch 0:62b846b3988a 1041 this->command6.lsb[0] = 0;
tgrosch 0:62b846b3988a 1042
tgrosch 0:62b846b3988a 1043 //Initialization for register command7
tgrosch 0:62b846b3988a 1044 this->command7.address[0] = 0x18; ///< Address=24
tgrosch 0:62b846b3988a 1045 this->command7.msb[0] = 23;
tgrosch 0:62b846b3988a 1046 this->command7.lsb[0] = 12;
tgrosch 0:62b846b3988a 1047
tgrosch 0:62b846b3988a 1048 //Initialization for register command8
tgrosch 0:62b846b3988a 1049 this->command8.address[0] = 0x19; ///< Address=25
tgrosch 0:62b846b3988a 1050 this->command8.msb[0] = 11;
tgrosch 0:62b846b3988a 1051 this->command8.lsb[0] = 0;
tgrosch 0:62b846b3988a 1052
tgrosch 0:62b846b3988a 1053 //Initialization for register command9
tgrosch 0:62b846b3988a 1054 this->command9.address[0] = 0x19; ///< Address=25
tgrosch 0:62b846b3988a 1055 this->command9.msb[0] = 23;
tgrosch 0:62b846b3988a 1056 this->command9.lsb[0] = 12;
tgrosch 0:62b846b3988a 1057
tgrosch 0:62b846b3988a 1058 //Initialization for register command10
tgrosch 0:62b846b3988a 1059 this->command10.address[0] = 0x1a; ///< Address=26
tgrosch 0:62b846b3988a 1060 this->command10.msb[0] = 11;
tgrosch 0:62b846b3988a 1061 this->command10.lsb[0] = 0;
tgrosch 0:62b846b3988a 1062
tgrosch 0:62b846b3988a 1063 //Initialization for register command11
tgrosch 0:62b846b3988a 1064 this->command11.address[0] = 0x1a; ///< Address=26
tgrosch 0:62b846b3988a 1065 this->command11.msb[0] = 23;
tgrosch 0:62b846b3988a 1066 this->command11.lsb[0] = 12;
tgrosch 0:62b846b3988a 1067
tgrosch 0:62b846b3988a 1068 //Initialization for register command12
tgrosch 0:62b846b3988a 1069 this->command12.address[0] = 0x1b; ///< Address=27
tgrosch 0:62b846b3988a 1070 this->command12.msb[0] = 11;
tgrosch 0:62b846b3988a 1071 this->command12.lsb[0] = 0;
tgrosch 0:62b846b3988a 1072
tgrosch 0:62b846b3988a 1073 //Initialization for register command13
tgrosch 0:62b846b3988a 1074 this->command13.address[0] = 0x1b; ///< Address=27
tgrosch 0:62b846b3988a 1075 this->command13.msb[0] = 23;
tgrosch 0:62b846b3988a 1076 this->command13.lsb[0] = 12;
tgrosch 0:62b846b3988a 1077
tgrosch 0:62b846b3988a 1078 //Initialization for register command14
tgrosch 0:62b846b3988a 1079 this->command14.address[0] = 0x1c; ///< Address=28
tgrosch 0:62b846b3988a 1080 this->command14.msb[0] = 11;
tgrosch 0:62b846b3988a 1081 this->command14.lsb[0] = 0;
tgrosch 0:62b846b3988a 1082
tgrosch 0:62b846b3988a 1083 //Initialization for register command15
tgrosch 0:62b846b3988a 1084 this->command15.address[0] = 0x1c; ///< Address=28
tgrosch 0:62b846b3988a 1085 this->command15.msb[0] = 23;
tgrosch 0:62b846b3988a 1086 this->command15.lsb[0] = 12;
tgrosch 0:62b846b3988a 1087
tgrosch 0:62b846b3988a 1088 //Initialization for register command16
tgrosch 0:62b846b3988a 1089 this->command16.address[0] = 0x1d; ///< Address=29
tgrosch 0:62b846b3988a 1090 this->command16.msb[0] = 11;
tgrosch 0:62b846b3988a 1091 this->command16.lsb[0] = 0;
tgrosch 0:62b846b3988a 1092
tgrosch 0:62b846b3988a 1093 //Initialization for register command17
tgrosch 0:62b846b3988a 1094 this->command17.address[0] = 0x1d; ///< Address=29
tgrosch 0:62b846b3988a 1095 this->command17.msb[0] = 23;
tgrosch 0:62b846b3988a 1096 this->command17.lsb[0] = 12;
tgrosch 0:62b846b3988a 1097
tgrosch 0:62b846b3988a 1098 //Initialization for register command18
tgrosch 0:62b846b3988a 1099 this->command18.address[0] = 0x1e; ///< Address=30
tgrosch 0:62b846b3988a 1100 this->command18.msb[0] = 11;
tgrosch 0:62b846b3988a 1101 this->command18.lsb[0] = 0;
tgrosch 0:62b846b3988a 1102
tgrosch 0:62b846b3988a 1103 //Initialization for register command19
tgrosch 0:62b846b3988a 1104 this->command19.address[0] = 0x1e; ///< Address=30
tgrosch 0:62b846b3988a 1105 this->command19.msb[0] = 23;
tgrosch 0:62b846b3988a 1106 this->command19.lsb[0] = 12;
tgrosch 0:62b846b3988a 1107
tgrosch 0:62b846b3988a 1108 //Initialization for register force_scale_val
tgrosch 0:62b846b3988a 1109 this->force_scale_val.address[0] = 0x2e; ///< Address=46
tgrosch 0:62b846b3988a 1110 this->force_scale_val.msb[0] = 2;
tgrosch 0:62b846b3988a 1111 this->force_scale_val.lsb[0] = 0;
tgrosch 0:62b846b3988a 1112
tgrosch 0:62b846b3988a 1113 //Initialization for register dis_auto_scale
tgrosch 0:62b846b3988a 1114 this->dis_auto_scale.address[0] = 0x2e; ///< Address=46
tgrosch 0:62b846b3988a 1115 this->dis_auto_scale.msb[0] = 3;
tgrosch 0:62b846b3988a 1116 this->dis_auto_scale.lsb[0] = 3;
tgrosch 0:62b846b3988a 1117
tgrosch 0:62b846b3988a 1118 //Initialization for register disable_conf_rescale
tgrosch 0:62b846b3988a 1119 this->disable_conf_rescale.address[0] = 0x2e; ///< Address=46
tgrosch 0:62b846b3988a 1120 this->disable_conf_rescale.msb[0] = 13;
tgrosch 0:62b846b3988a 1121 this->disable_conf_rescale.lsb[0] = 13;
tgrosch 0:62b846b3988a 1122
tgrosch 0:62b846b3988a 1123 //Initialization for register int_xtalk_calib
tgrosch 0:62b846b3988a 1124 this->int_xtalk_calib.address[0] = 0x2e; ///< Address=46
tgrosch 0:62b846b3988a 1125 this->int_xtalk_calib.msb[0] = 4;
tgrosch 0:62b846b3988a 1126 this->int_xtalk_calib.lsb[0] = 4;
tgrosch 0:62b846b3988a 1127
tgrosch 0:62b846b3988a 1128 //Initialization for register xtalk_filt_time_const
tgrosch 0:62b846b3988a 1129 this->xtalk_filt_time_const.address[0] = 0x2e; ///< Address=46
tgrosch 0:62b846b3988a 1130 this->xtalk_filt_time_const.msb[0] = 23;
tgrosch 0:62b846b3988a 1131 this->xtalk_filt_time_const.lsb[0] = 20;
tgrosch 0:62b846b3988a 1132
tgrosch 0:62b846b3988a 1133 //Initialization for register use_xtalk_filt_int
tgrosch 0:62b846b3988a 1134 this->use_xtalk_filt_int.address[0] = 0x2e; ///< Address=46
tgrosch 0:62b846b3988a 1135 this->use_xtalk_filt_int.msb[0] = 5;
tgrosch 0:62b846b3988a 1136 this->use_xtalk_filt_int.lsb[0] = 5;
tgrosch 0:62b846b3988a 1137
tgrosch 0:62b846b3988a 1138 //Initialization for register use_xtalk_reg_int
tgrosch 0:62b846b3988a 1139 this->use_xtalk_reg_int.address[0] = 0x2e; ///< Address=46
tgrosch 0:62b846b3988a 1140 this->use_xtalk_reg_int.msb[0] = 6;
tgrosch 0:62b846b3988a 1141 this->use_xtalk_reg_int.lsb[0] = 6;
tgrosch 0:62b846b3988a 1142
tgrosch 0:62b846b3988a 1143 //Initialization for register iq_read_data_sel
tgrosch 0:62b846b3988a 1144 this->iq_read_data_sel.address[0] = 0x2e; ///< Address=46
tgrosch 0:62b846b3988a 1145 this->iq_read_data_sel.msb[0] = 11;
tgrosch 0:62b846b3988a 1146 this->iq_read_data_sel.lsb[0] = 9;
tgrosch 0:62b846b3988a 1147
tgrosch 0:62b846b3988a 1148 //Initialization for register iphase_xtalk
tgrosch 0:62b846b3988a 1149 this->iphase_xtalk.address[0] = 0x3b; ///< Address=59
tgrosch 0:62b846b3988a 1150 this->iphase_xtalk.msb[0] = 23;
tgrosch 0:62b846b3988a 1151 this->iphase_xtalk.lsb[0] = 0;
tgrosch 0:62b846b3988a 1152
tgrosch 0:62b846b3988a 1153 //Initialization for register qphase_xtalk
tgrosch 0:62b846b3988a 1154 this->qphase_xtalk.address[0] = 0x3c; ///< Address=60
tgrosch 0:62b846b3988a 1155 this->qphase_xtalk.msb[0] = 23;
tgrosch 0:62b846b3988a 1156 this->qphase_xtalk.lsb[0] = 0;
tgrosch 0:62b846b3988a 1157
tgrosch 0:62b846b3988a 1158 //Initialization for register int_xtalk_reg_scale
tgrosch 0:62b846b3988a 1159 this->int_xtalk_reg_scale.address[0] = 0x2e; ///< Address=46
tgrosch 0:62b846b3988a 1160 this->int_xtalk_reg_scale.msb[0] = 16;
tgrosch 0:62b846b3988a 1161 this->int_xtalk_reg_scale.lsb[0] = 14;
tgrosch 0:62b846b3988a 1162
tgrosch 0:62b846b3988a 1163 //Initialization for register iphase_xtalk_int_reg
tgrosch 0:62b846b3988a 1164 this->iphase_xtalk_int_reg.address[0] = 0x3d; ///< Address=61
tgrosch 0:62b846b3988a 1165 this->iphase_xtalk_int_reg.msb[0] = 15;
tgrosch 0:62b846b3988a 1166 this->iphase_xtalk_int_reg.lsb[0] = 0;
tgrosch 0:62b846b3988a 1167
tgrosch 0:62b846b3988a 1168 //Initialization for register qphase_xtalk_int_reg
tgrosch 0:62b846b3988a 1169 this->qphase_xtalk_int_reg.address[0] = 0x3e; ///< Address=62
tgrosch 0:62b846b3988a 1170 this->qphase_xtalk_int_reg.msb[0] = 15;
tgrosch 0:62b846b3988a 1171 this->qphase_xtalk_int_reg.lsb[0] = 0;
tgrosch 0:62b846b3988a 1172
tgrosch 0:62b846b3988a 1173 //Initialization for register illum_xtalk_calib
tgrosch 0:62b846b3988a 1174 this->illum_xtalk_calib.address[0] = 0x2e; ///< Address=46
tgrosch 0:62b846b3988a 1175 this->illum_xtalk_calib.msb[0] = 12;
tgrosch 0:62b846b3988a 1176 this->illum_xtalk_calib.lsb[0] = 12;
tgrosch 0:62b846b3988a 1177
tgrosch 0:62b846b3988a 1178 //Initialization for register illum_xtalk_reg_scale
tgrosch 0:62b846b3988a 1179 this->illum_xtalk_reg_scale.address[0] = 0x2e; ///< Address=46
tgrosch 0:62b846b3988a 1180 this->illum_xtalk_reg_scale.msb[0] = 19;
tgrosch 0:62b846b3988a 1181 this->illum_xtalk_reg_scale.lsb[0] = 17;
tgrosch 0:62b846b3988a 1182
tgrosch 0:62b846b3988a 1183 //Initialization for register use_xtalk_filt_illum
tgrosch 0:62b846b3988a 1184 this->use_xtalk_filt_illum.address[0] = 0x2e; ///< Address=46
tgrosch 0:62b846b3988a 1185 this->use_xtalk_filt_illum.msb[0] = 7;
tgrosch 0:62b846b3988a 1186 this->use_xtalk_filt_illum.lsb[0] = 7;
tgrosch 0:62b846b3988a 1187
tgrosch 0:62b846b3988a 1188 //Initialization for register use_xtalk_reg_illum
tgrosch 0:62b846b3988a 1189 this->use_xtalk_reg_illum.address[0] = 0x2e; ///< Address=46
tgrosch 0:62b846b3988a 1190 this->use_xtalk_reg_illum.msb[0] = 8;
tgrosch 0:62b846b3988a 1191 this->use_xtalk_reg_illum.lsb[0] = 8;
tgrosch 0:62b846b3988a 1192
tgrosch 0:62b846b3988a 1193 //Initialization for register iphase_xtalk_reg_hdr0_tx0
tgrosch 0:62b846b3988a 1194 this->iphase_xtalk_reg_hdr0_tx0.address[0] = 0x2f; ///< Address=47
tgrosch 0:62b846b3988a 1195 this->iphase_xtalk_reg_hdr0_tx0.msb[0] = 15;
tgrosch 0:62b846b3988a 1196 this->iphase_xtalk_reg_hdr0_tx0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1197
tgrosch 0:62b846b3988a 1198 //Initialization for register qphase_xtalk_reg_hdr0_tx0
tgrosch 0:62b846b3988a 1199 this->qphase_xtalk_reg_hdr0_tx0.address[0] = 0x30; ///< Address=48
tgrosch 0:62b846b3988a 1200 this->qphase_xtalk_reg_hdr0_tx0.msb[0] = 15;
tgrosch 0:62b846b3988a 1201 this->qphase_xtalk_reg_hdr0_tx0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1202
tgrosch 0:62b846b3988a 1203 //Initialization for register iphase_xtalk_reg_hdr1_tx0
tgrosch 0:62b846b3988a 1204 this->iphase_xtalk_reg_hdr1_tx0.address[0] = 0x31; ///< Address=49
tgrosch 0:62b846b3988a 1205 this->iphase_xtalk_reg_hdr1_tx0.msb[0] = 15;
tgrosch 0:62b846b3988a 1206 this->iphase_xtalk_reg_hdr1_tx0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1207
tgrosch 0:62b846b3988a 1208 //Initialization for register qphase_xtalk_reg_hdr1_tx0
tgrosch 0:62b846b3988a 1209 this->qphase_xtalk_reg_hdr1_tx0.address[0] = 0x32; ///< Address=50
tgrosch 0:62b846b3988a 1210 this->qphase_xtalk_reg_hdr1_tx0.msb[0] = 15;
tgrosch 0:62b846b3988a 1211 this->qphase_xtalk_reg_hdr1_tx0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1212
tgrosch 0:62b846b3988a 1213 //Initialization for register iphase_xtalk_reg_hdr0_tx1
tgrosch 0:62b846b3988a 1214 this->iphase_xtalk_reg_hdr0_tx1.address[0] = 0x33; ///< Address=51
tgrosch 0:62b846b3988a 1215 this->iphase_xtalk_reg_hdr0_tx1.msb[0] = 15;
tgrosch 0:62b846b3988a 1216 this->iphase_xtalk_reg_hdr0_tx1.lsb[0] = 0;
tgrosch 0:62b846b3988a 1217
tgrosch 0:62b846b3988a 1218 //Initialization for register qphase_xtalk_reg_hdr0_tx1
tgrosch 0:62b846b3988a 1219 this->qphase_xtalk_reg_hdr0_tx1.address[0] = 0x34; ///< Address=52
tgrosch 0:62b846b3988a 1220 this->qphase_xtalk_reg_hdr0_tx1.msb[0] = 15;
tgrosch 0:62b846b3988a 1221 this->qphase_xtalk_reg_hdr0_tx1.lsb[0] = 0;
tgrosch 0:62b846b3988a 1222
tgrosch 0:62b846b3988a 1223 //Initialization for register iphase_xtalk_reg_hdr1_tx1
tgrosch 0:62b846b3988a 1224 this->iphase_xtalk_reg_hdr1_tx1.address[0] = 0x35; ///< Address=53
tgrosch 0:62b846b3988a 1225 this->iphase_xtalk_reg_hdr1_tx1.msb[0] = 15;
tgrosch 0:62b846b3988a 1226 this->iphase_xtalk_reg_hdr1_tx1.lsb[0] = 0;
tgrosch 0:62b846b3988a 1227
tgrosch 0:62b846b3988a 1228 //Initialization for register qphase_xtalk_reg_hdr1_tx1
tgrosch 0:62b846b3988a 1229 this->qphase_xtalk_reg_hdr1_tx1.address[0] = 0x36; ///< Address=54
tgrosch 0:62b846b3988a 1230 this->qphase_xtalk_reg_hdr1_tx1.msb[0] = 15;
tgrosch 0:62b846b3988a 1231 this->qphase_xtalk_reg_hdr1_tx1.lsb[0] = 0;
tgrosch 0:62b846b3988a 1232
tgrosch 0:62b846b3988a 1233 //Initialization for register iphase_xtalk_reg_hdr0_tx2
tgrosch 0:62b846b3988a 1234 this->iphase_xtalk_reg_hdr0_tx2.address[0] = 0x37; ///< Address=55
tgrosch 0:62b846b3988a 1235 this->iphase_xtalk_reg_hdr0_tx2.msb[0] = 15;
tgrosch 0:62b846b3988a 1236 this->iphase_xtalk_reg_hdr0_tx2.lsb[0] = 0;
tgrosch 0:62b846b3988a 1237
tgrosch 0:62b846b3988a 1238 //Initialization for register qphase_xtalk_reg_hdr0_tx2
tgrosch 0:62b846b3988a 1239 this->qphase_xtalk_reg_hdr0_tx2.address[0] = 0x38; ///< Address=56
tgrosch 0:62b846b3988a 1240 this->qphase_xtalk_reg_hdr0_tx2.msb[0] = 15;
tgrosch 0:62b846b3988a 1241 this->qphase_xtalk_reg_hdr0_tx2.lsb[0] = 0;
tgrosch 0:62b846b3988a 1242
tgrosch 0:62b846b3988a 1243 //Initialization for register iphase_xtalk_reg_hdr1_tx2
tgrosch 0:62b846b3988a 1244 this->iphase_xtalk_reg_hdr1_tx2.address[0] = 0x39; ///< Address=57
tgrosch 0:62b846b3988a 1245 this->iphase_xtalk_reg_hdr1_tx2.msb[0] = 15;
tgrosch 0:62b846b3988a 1246 this->iphase_xtalk_reg_hdr1_tx2.lsb[0] = 0;
tgrosch 0:62b846b3988a 1247
tgrosch 0:62b846b3988a 1248 //Initialization for register qphase_xtalk_reg_hdr1_tx2
tgrosch 0:62b846b3988a 1249 this->qphase_xtalk_reg_hdr1_tx2.address[0] = 0x3a; ///< Address=58
tgrosch 0:62b846b3988a 1250 this->qphase_xtalk_reg_hdr1_tx2.msb[0] = 15;
tgrosch 0:62b846b3988a 1251 this->qphase_xtalk_reg_hdr1_tx2.lsb[0] = 0;
tgrosch 0:62b846b3988a 1252
tgrosch 0:62b846b3988a 1253 //Initialization for register en_temp_xtalk_corr
tgrosch 0:62b846b3988a 1254 this->en_temp_xtalk_corr.address[0] = 0x3a; ///< Address=58
tgrosch 0:62b846b3988a 1255 this->en_temp_xtalk_corr.msb[0] = 16;
tgrosch 0:62b846b3988a 1256 this->en_temp_xtalk_corr.lsb[0] = 16;
tgrosch 0:62b846b3988a 1257
tgrosch 0:62b846b3988a 1258 //Initialization for register scale_temp_coeff_xtalk
tgrosch 0:62b846b3988a 1259 this->scale_temp_coeff_xtalk.address[0] = 0x3a; ///< Address=58
tgrosch 0:62b846b3988a 1260 this->scale_temp_coeff_xtalk.msb[0] = 19;
tgrosch 0:62b846b3988a 1261 this->scale_temp_coeff_xtalk.lsb[0] = 17;
tgrosch 0:62b846b3988a 1262
tgrosch 0:62b846b3988a 1263 //Initialization for register temp_coeff_xtalk_iphase_hdr0_tx0
tgrosch 0:62b846b3988a 1264 this->temp_coeff_xtalk_iphase_hdr0_tx0.address[0] = 0x38; ///< Address=56
tgrosch 0:62b846b3988a 1265 this->temp_coeff_xtalk_iphase_hdr0_tx0.msb[0] = 23;
tgrosch 0:62b846b3988a 1266 this->temp_coeff_xtalk_iphase_hdr0_tx0.lsb[0] = 16;
tgrosch 0:62b846b3988a 1267
tgrosch 0:62b846b3988a 1268 //Initialization for register temp_coeff_xtalk_qphase_hdr0_tx0
tgrosch 0:62b846b3988a 1269 this->temp_coeff_xtalk_qphase_hdr0_tx0.address[0] = 0x39; ///< Address=57
tgrosch 0:62b846b3988a 1270 this->temp_coeff_xtalk_qphase_hdr0_tx0.msb[0] = 23;
tgrosch 0:62b846b3988a 1271 this->temp_coeff_xtalk_qphase_hdr0_tx0.lsb[0] = 16;
tgrosch 0:62b846b3988a 1272
tgrosch 0:62b846b3988a 1273 //Initialization for register temp_coeff_xtalk_iphase_hdr1_tx0
tgrosch 0:62b846b3988a 1274 this->temp_coeff_xtalk_iphase_hdr1_tx0.address[0] = 0x5e; ///< Address=94
tgrosch 0:62b846b3988a 1275 this->temp_coeff_xtalk_iphase_hdr1_tx0.msb[0] = 15;
tgrosch 0:62b846b3988a 1276 this->temp_coeff_xtalk_iphase_hdr1_tx0.lsb[0] = 8;
tgrosch 0:62b846b3988a 1277
tgrosch 0:62b846b3988a 1278 //Initialization for register temp_coeff_xtalk_qphase_hdr1_tx0
tgrosch 0:62b846b3988a 1279 this->temp_coeff_xtalk_qphase_hdr1_tx0.address[0] = 0x60; ///< Address=96
tgrosch 0:62b846b3988a 1280 this->temp_coeff_xtalk_qphase_hdr1_tx0.msb[0] = 7;
tgrosch 0:62b846b3988a 1281 this->temp_coeff_xtalk_qphase_hdr1_tx0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1282
tgrosch 0:62b846b3988a 1283 //Initialization for register temp_coeff_xtalk_iphase_hdr0_tx1
tgrosch 0:62b846b3988a 1284 this->temp_coeff_xtalk_iphase_hdr0_tx1.address[0] = 0x5e; ///< Address=94
tgrosch 0:62b846b3988a 1285 this->temp_coeff_xtalk_iphase_hdr0_tx1.msb[0] = 23;
tgrosch 0:62b846b3988a 1286 this->temp_coeff_xtalk_iphase_hdr0_tx1.lsb[0] = 16;
tgrosch 0:62b846b3988a 1287
tgrosch 0:62b846b3988a 1288 //Initialization for register temp_coeff_xtalk_qphase_hdr0_tx1
tgrosch 0:62b846b3988a 1289 this->temp_coeff_xtalk_qphase_hdr0_tx1.address[0] = 0x60; ///< Address=96
tgrosch 0:62b846b3988a 1290 this->temp_coeff_xtalk_qphase_hdr0_tx1.msb[0] = 15;
tgrosch 0:62b846b3988a 1291 this->temp_coeff_xtalk_qphase_hdr0_tx1.lsb[0] = 8;
tgrosch 0:62b846b3988a 1292
tgrosch 0:62b846b3988a 1293 //Initialization for register temp_coeff_xtalk_iphase_hdr1_tx1
tgrosch 0:62b846b3988a 1294 this->temp_coeff_xtalk_iphase_hdr1_tx1.address[0] = 0x5f; ///< Address=95
tgrosch 0:62b846b3988a 1295 this->temp_coeff_xtalk_iphase_hdr1_tx1.msb[0] = 7;
tgrosch 0:62b846b3988a 1296 this->temp_coeff_xtalk_iphase_hdr1_tx1.lsb[0] = 0;
tgrosch 0:62b846b3988a 1297
tgrosch 0:62b846b3988a 1298 //Initialization for register temp_coeff_xtalk_qphase_hdr1_tx1
tgrosch 0:62b846b3988a 1299 this->temp_coeff_xtalk_qphase_hdr1_tx1.address[0] = 0x60; ///< Address=96
tgrosch 0:62b846b3988a 1300 this->temp_coeff_xtalk_qphase_hdr1_tx1.msb[0] = 23;
tgrosch 0:62b846b3988a 1301 this->temp_coeff_xtalk_qphase_hdr1_tx1.lsb[0] = 16;
tgrosch 0:62b846b3988a 1302
tgrosch 0:62b846b3988a 1303 //Initialization for register temp_coeff_xtalk_iphase_hdr0_tx2
tgrosch 0:62b846b3988a 1304 this->temp_coeff_xtalk_iphase_hdr0_tx2.address[0] = 0x5f; ///< Address=95
tgrosch 0:62b846b3988a 1305 this->temp_coeff_xtalk_iphase_hdr0_tx2.msb[0] = 15;
tgrosch 0:62b846b3988a 1306 this->temp_coeff_xtalk_iphase_hdr0_tx2.lsb[0] = 8;
tgrosch 0:62b846b3988a 1307
tgrosch 0:62b846b3988a 1308 //Initialization for register temp_coeff_xtalk_qphase_hdr0_tx2
tgrosch 0:62b846b3988a 1309 this->temp_coeff_xtalk_qphase_hdr0_tx2.address[0] = 0x61; ///< Address=97
tgrosch 0:62b846b3988a 1310 this->temp_coeff_xtalk_qphase_hdr0_tx2.msb[0] = 7;
tgrosch 0:62b846b3988a 1311 this->temp_coeff_xtalk_qphase_hdr0_tx2.lsb[0] = 0;
tgrosch 0:62b846b3988a 1312
tgrosch 0:62b846b3988a 1313 //Initialization for register temp_coeff_xtalk_iphase_hdr1_tx2
tgrosch 0:62b846b3988a 1314 this->temp_coeff_xtalk_iphase_hdr1_tx2.address[0] = 0x5f; ///< Address=95
tgrosch 0:62b846b3988a 1315 this->temp_coeff_xtalk_iphase_hdr1_tx2.msb[0] = 23;
tgrosch 0:62b846b3988a 1316 this->temp_coeff_xtalk_iphase_hdr1_tx2.lsb[0] = 16;
tgrosch 0:62b846b3988a 1317
tgrosch 0:62b846b3988a 1318 //Initialization for register temp_coeff_xtalk_qphase_hdr1_tx2
tgrosch 0:62b846b3988a 1319 this->temp_coeff_xtalk_qphase_hdr1_tx2.address[0] = 0x61; ///< Address=97
tgrosch 0:62b846b3988a 1320 this->temp_coeff_xtalk_qphase_hdr1_tx2.msb[0] = 15;
tgrosch 0:62b846b3988a 1321 this->temp_coeff_xtalk_qphase_hdr1_tx2.lsb[0] = 8;
tgrosch 0:62b846b3988a 1322
tgrosch 0:62b846b3988a 1323 //Initialization for register temp_coeff_illum_xtalk_iphase_hdr0_tx0
tgrosch 0:62b846b3988a 1324 this->temp_coeff_illum_xtalk_iphase_hdr0_tx0.address[0] = 0x36; ///< Address=54
tgrosch 0:62b846b3988a 1325 this->temp_coeff_illum_xtalk_iphase_hdr0_tx0.msb[0] = 23;
tgrosch 0:62b846b3988a 1326 this->temp_coeff_illum_xtalk_iphase_hdr0_tx0.lsb[0] = 16;
tgrosch 0:62b846b3988a 1327
tgrosch 0:62b846b3988a 1328 //Initialization for register temp_coeff_illum_xtalk_qphase_hdr0_tx0
tgrosch 0:62b846b3988a 1329 this->temp_coeff_illum_xtalk_qphase_hdr0_tx0.address[0] = 0x37; ///< Address=55
tgrosch 0:62b846b3988a 1330 this->temp_coeff_illum_xtalk_qphase_hdr0_tx0.msb[0] = 23;
tgrosch 0:62b846b3988a 1331 this->temp_coeff_illum_xtalk_qphase_hdr0_tx0.lsb[0] = 16;
tgrosch 0:62b846b3988a 1332
tgrosch 0:62b846b3988a 1333 //Initialization for register temp_coeff_illum_xtalk_iphase_hdr1_tx0
tgrosch 0:62b846b3988a 1334 this->temp_coeff_illum_xtalk_iphase_hdr1_tx0.address[0] = 0x5b; ///< Address=91
tgrosch 0:62b846b3988a 1335 this->temp_coeff_illum_xtalk_iphase_hdr1_tx0.msb[0] = 7;
tgrosch 0:62b846b3988a 1336 this->temp_coeff_illum_xtalk_iphase_hdr1_tx0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1337
tgrosch 0:62b846b3988a 1338 //Initialization for register temp_coeff_illum_xtalk_iphase_hdr0_tx1
tgrosch 0:62b846b3988a 1339 this->temp_coeff_illum_xtalk_iphase_hdr0_tx1.address[0] = 0x5b; ///< Address=91
tgrosch 0:62b846b3988a 1340 this->temp_coeff_illum_xtalk_iphase_hdr0_tx1.msb[0] = 15;
tgrosch 0:62b846b3988a 1341 this->temp_coeff_illum_xtalk_iphase_hdr0_tx1.lsb[0] = 8;
tgrosch 0:62b846b3988a 1342
tgrosch 0:62b846b3988a 1343 //Initialization for register temp_coeff_illum_xtalk_iphase_hdr1_tx1
tgrosch 0:62b846b3988a 1344 this->temp_coeff_illum_xtalk_iphase_hdr1_tx1.address[0] = 0x5b; ///< Address=91
tgrosch 0:62b846b3988a 1345 this->temp_coeff_illum_xtalk_iphase_hdr1_tx1.msb[0] = 23;
tgrosch 0:62b846b3988a 1346 this->temp_coeff_illum_xtalk_iphase_hdr1_tx1.lsb[0] = 16;
tgrosch 0:62b846b3988a 1347
tgrosch 0:62b846b3988a 1348 //Initialization for register temp_coeff_illum_xtalk_iphase_hdr0_tx2
tgrosch 0:62b846b3988a 1349 this->temp_coeff_illum_xtalk_iphase_hdr0_tx2.address[0] = 0x5c; ///< Address=92
tgrosch 0:62b846b3988a 1350 this->temp_coeff_illum_xtalk_iphase_hdr0_tx2.msb[0] = 7;
tgrosch 0:62b846b3988a 1351 this->temp_coeff_illum_xtalk_iphase_hdr0_tx2.lsb[0] = 0;
tgrosch 0:62b846b3988a 1352
tgrosch 0:62b846b3988a 1353 //Initialization for register temp_coeff_illum_xtalk_iphase_hdr1_tx2
tgrosch 0:62b846b3988a 1354 this->temp_coeff_illum_xtalk_iphase_hdr1_tx2.address[0] = 0x5c; ///< Address=92
tgrosch 0:62b846b3988a 1355 this->temp_coeff_illum_xtalk_iphase_hdr1_tx2.msb[0] = 15;
tgrosch 0:62b846b3988a 1356 this->temp_coeff_illum_xtalk_iphase_hdr1_tx2.lsb[0] = 8;
tgrosch 0:62b846b3988a 1357
tgrosch 0:62b846b3988a 1358 //Initialization for register temp_coeff_illum_xtalk_qphase_hdr1_tx0
tgrosch 0:62b846b3988a 1359 this->temp_coeff_illum_xtalk_qphase_hdr1_tx0.address[0] = 0x5c; ///< Address=92
tgrosch 0:62b846b3988a 1360 this->temp_coeff_illum_xtalk_qphase_hdr1_tx0.msb[0] = 23;
tgrosch 0:62b846b3988a 1361 this->temp_coeff_illum_xtalk_qphase_hdr1_tx0.lsb[0] = 16;
tgrosch 0:62b846b3988a 1362
tgrosch 0:62b846b3988a 1363 //Initialization for register temp_coeff_illum_xtalk_qphase_hdr0_tx1
tgrosch 0:62b846b3988a 1364 this->temp_coeff_illum_xtalk_qphase_hdr0_tx1.address[0] = 0x5d; ///< Address=93
tgrosch 0:62b846b3988a 1365 this->temp_coeff_illum_xtalk_qphase_hdr0_tx1.msb[0] = 7;
tgrosch 0:62b846b3988a 1366 this->temp_coeff_illum_xtalk_qphase_hdr0_tx1.lsb[0] = 0;
tgrosch 0:62b846b3988a 1367
tgrosch 0:62b846b3988a 1368 //Initialization for register temp_coeff_illum_xtalk_qphase_hdr1_tx1
tgrosch 0:62b846b3988a 1369 this->temp_coeff_illum_xtalk_qphase_hdr1_tx1.address[0] = 0x5d; ///< Address=93
tgrosch 0:62b846b3988a 1370 this->temp_coeff_illum_xtalk_qphase_hdr1_tx1.msb[0] = 15;
tgrosch 0:62b846b3988a 1371 this->temp_coeff_illum_xtalk_qphase_hdr1_tx1.lsb[0] = 8;
tgrosch 0:62b846b3988a 1372
tgrosch 0:62b846b3988a 1373 //Initialization for register temp_coeff_illum_xtalk_qphase_hdr0_tx2
tgrosch 0:62b846b3988a 1374 this->temp_coeff_illum_xtalk_qphase_hdr0_tx2.address[0] = 0x5d; ///< Address=93
tgrosch 0:62b846b3988a 1375 this->temp_coeff_illum_xtalk_qphase_hdr0_tx2.msb[0] = 23;
tgrosch 0:62b846b3988a 1376 this->temp_coeff_illum_xtalk_qphase_hdr0_tx2.lsb[0] = 16;
tgrosch 0:62b846b3988a 1377
tgrosch 0:62b846b3988a 1378 //Initialization for register temp_coeff_illum_xtalk_qphase_hdr1_tx2
tgrosch 0:62b846b3988a 1379 this->temp_coeff_illum_xtalk_qphase_hdr1_tx2.address[0] = 0x5e; ///< Address=94
tgrosch 0:62b846b3988a 1380 this->temp_coeff_illum_xtalk_qphase_hdr1_tx2.msb[0] = 7;
tgrosch 0:62b846b3988a 1381 this->temp_coeff_illum_xtalk_qphase_hdr1_tx2.lsb[0] = 0;
tgrosch 0:62b846b3988a 1382
tgrosch 0:62b846b3988a 1383 //Initialization for register amb_xtalk_qphase_coeff
tgrosch 0:62b846b3988a 1384 this->amb_xtalk_qphase_coeff.address[0] = 0x0c; ///< Address=12
tgrosch 0:62b846b3988a 1385 this->amb_xtalk_qphase_coeff.msb[0] = 15;
tgrosch 0:62b846b3988a 1386 this->amb_xtalk_qphase_coeff.lsb[0] = 8;
tgrosch 0:62b846b3988a 1387
tgrosch 0:62b846b3988a 1388 //Initialization for register amb_xtalk_iphase_coeff
tgrosch 0:62b846b3988a 1389 this->amb_xtalk_iphase_coeff.address[0] = 0x0c; ///< Address=12
tgrosch 0:62b846b3988a 1390 this->amb_xtalk_iphase_coeff.msb[0] = 7;
tgrosch 0:62b846b3988a 1391 this->amb_xtalk_iphase_coeff.lsb[0] = 0;
tgrosch 0:62b846b3988a 1392
tgrosch 0:62b846b3988a 1393 //Initialization for register scale_amb_coeff_xtalk
tgrosch 0:62b846b3988a 1394 this->scale_amb_coeff_xtalk.address[0] = 0x3a; ///< Address=58
tgrosch 0:62b846b3988a 1395 this->scale_amb_coeff_xtalk.msb[0] = 22;
tgrosch 0:62b846b3988a 1396 this->scale_amb_coeff_xtalk.lsb[0] = 20;
tgrosch 0:62b846b3988a 1397
tgrosch 0:62b846b3988a 1398 //Initialization for register en_phase_corr
tgrosch 0:62b846b3988a 1399 this->en_phase_corr.address[0] = 0x43; ///< Address=67
tgrosch 0:62b846b3988a 1400 this->en_phase_corr.msb[0] = 0;
tgrosch 0:62b846b3988a 1401 this->en_phase_corr.lsb[0] = 0;
tgrosch 0:62b846b3988a 1402
tgrosch 0:62b846b3988a 1403 //Initialization for register phase_offset_hdr0_tx0
tgrosch 0:62b846b3988a 1404 this->phase_offset_hdr0_tx0.address[0] = 0x42; ///< Address=66
tgrosch 0:62b846b3988a 1405 this->phase_offset_hdr0_tx0.msb[0] = 15;
tgrosch 0:62b846b3988a 1406 this->phase_offset_hdr0_tx0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1407
tgrosch 0:62b846b3988a 1408 //Initialization for register phase_offset_hdr1_tx0
tgrosch 0:62b846b3988a 1409 this->phase_offset_hdr1_tx0.address[0] = 0x51; ///< Address=81
tgrosch 0:62b846b3988a 1410 this->phase_offset_hdr1_tx0.msb[0] = 15;
tgrosch 0:62b846b3988a 1411 this->phase_offset_hdr1_tx0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1412
tgrosch 0:62b846b3988a 1413 //Initialization for register phase_offset_hdr0_tx1
tgrosch 0:62b846b3988a 1414 this->phase_offset_hdr0_tx1.address[0] = 0x52; ///< Address=82
tgrosch 0:62b846b3988a 1415 this->phase_offset_hdr0_tx1.msb[0] = 15;
tgrosch 0:62b846b3988a 1416 this->phase_offset_hdr0_tx1.lsb[0] = 0;
tgrosch 0:62b846b3988a 1417
tgrosch 0:62b846b3988a 1418 //Initialization for register phase_offset_hdr1_tx1
tgrosch 0:62b846b3988a 1419 this->phase_offset_hdr1_tx1.address[0] = 0x53; ///< Address=83
tgrosch 0:62b846b3988a 1420 this->phase_offset_hdr1_tx1.msb[0] = 15;
tgrosch 0:62b846b3988a 1421 this->phase_offset_hdr1_tx1.lsb[0] = 0;
tgrosch 0:62b846b3988a 1422
tgrosch 0:62b846b3988a 1423 //Initialization for register phase_offset_hdr0_tx2
tgrosch 0:62b846b3988a 1424 this->phase_offset_hdr0_tx2.address[0] = 0x54; ///< Address=84
tgrosch 0:62b846b3988a 1425 this->phase_offset_hdr0_tx2.msb[0] = 15;
tgrosch 0:62b846b3988a 1426 this->phase_offset_hdr0_tx2.lsb[0] = 0;
tgrosch 0:62b846b3988a 1427
tgrosch 0:62b846b3988a 1428 //Initialization for register phase_offset_hdr1_tx2
tgrosch 0:62b846b3988a 1429 this->phase_offset_hdr1_tx2.address[0] = 0x55; ///< Address=85
tgrosch 0:62b846b3988a 1430 this->phase_offset_hdr1_tx2.msb[0] = 15;
tgrosch 0:62b846b3988a 1431 this->phase_offset_hdr1_tx2.lsb[0] = 0;
tgrosch 0:62b846b3988a 1432
tgrosch 0:62b846b3988a 1433 //Initialization for register reverse_phase_before_offset
tgrosch 0:62b846b3988a 1434 this->reverse_phase_before_offset.address[0] = 0x43; ///< Address=67
tgrosch 0:62b846b3988a 1435 this->reverse_phase_before_offset.msb[0] = 9;
tgrosch 0:62b846b3988a 1436 this->reverse_phase_before_offset.lsb[0] = 9;
tgrosch 0:62b846b3988a 1437
tgrosch 0:62b846b3988a 1438 //Initialization for register phase2_offset_hdr0_tx0
tgrosch 0:62b846b3988a 1439 this->phase2_offset_hdr0_tx0.address[0] = 0x44; ///< Address=68
tgrosch 0:62b846b3988a 1440 this->phase2_offset_hdr0_tx0.msb[0] = 15;
tgrosch 0:62b846b3988a 1441 this->phase2_offset_hdr0_tx0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1442
tgrosch 0:62b846b3988a 1443 //Initialization for register phase2_offset_hdr1_tx0
tgrosch 0:62b846b3988a 1444 this->phase2_offset_hdr1_tx0.address[0] = 0x56; ///< Address=86
tgrosch 0:62b846b3988a 1445 this->phase2_offset_hdr1_tx0.msb[0] = 15;
tgrosch 0:62b846b3988a 1446 this->phase2_offset_hdr1_tx0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1447
tgrosch 0:62b846b3988a 1448 //Initialization for register phase2_offset_hdr0_tx1
tgrosch 0:62b846b3988a 1449 this->phase2_offset_hdr0_tx1.address[0] = 0x57; ///< Address=87
tgrosch 0:62b846b3988a 1450 this->phase2_offset_hdr0_tx1.msb[0] = 15;
tgrosch 0:62b846b3988a 1451 this->phase2_offset_hdr0_tx1.lsb[0] = 0;
tgrosch 0:62b846b3988a 1452
tgrosch 0:62b846b3988a 1453 //Initialization for register phase2_offset_hdr1_tx1
tgrosch 0:62b846b3988a 1454 this->phase2_offset_hdr1_tx1.address[0] = 0x58; ///< Address=88
tgrosch 0:62b846b3988a 1455 this->phase2_offset_hdr1_tx1.msb[0] = 15;
tgrosch 0:62b846b3988a 1456 this->phase2_offset_hdr1_tx1.lsb[0] = 0;
tgrosch 0:62b846b3988a 1457
tgrosch 0:62b846b3988a 1458 //Initialization for register phase2_offset_hdr0_tx2
tgrosch 0:62b846b3988a 1459 this->phase2_offset_hdr0_tx2.address[0] = 0x59; ///< Address=89
tgrosch 0:62b846b3988a 1460 this->phase2_offset_hdr0_tx2.msb[0] = 15;
tgrosch 0:62b846b3988a 1461 this->phase2_offset_hdr0_tx2.lsb[0] = 0;
tgrosch 0:62b846b3988a 1462
tgrosch 0:62b846b3988a 1463 //Initialization for register phase2_offset_hdr1_tx2
tgrosch 0:62b846b3988a 1464 this->phase2_offset_hdr1_tx2.address[0] = 0x5a; ///< Address=90
tgrosch 0:62b846b3988a 1465 this->phase2_offset_hdr1_tx2.msb[0] = 15;
tgrosch 0:62b846b3988a 1466 this->phase2_offset_hdr1_tx2.lsb[0] = 0;
tgrosch 0:62b846b3988a 1467
tgrosch 0:62b846b3988a 1468 //Initialization for register en_temp_corr
tgrosch 0:62b846b3988a 1469 this->en_temp_corr.address[0] = 0x43; ///< Address=67
tgrosch 0:62b846b3988a 1470 this->en_temp_corr.msb[0] = 1;
tgrosch 0:62b846b3988a 1471 this->en_temp_corr.lsb[0] = 1;
tgrosch 0:62b846b3988a 1472
tgrosch 0:62b846b3988a 1473 //Initialization for register scale_phase_temp_coeff
tgrosch 0:62b846b3988a 1474 this->scale_phase_temp_coeff.address[0] = 0x43; ///< Address=67
tgrosch 0:62b846b3988a 1475 this->scale_phase_temp_coeff.msb[0] = 8;
tgrosch 0:62b846b3988a 1476 this->scale_phase_temp_coeff.lsb[0] = 6;
tgrosch 0:62b846b3988a 1477
tgrosch 0:62b846b3988a 1478 //Initialization for register tmain_calib_hdr0_tx0
tgrosch 0:62b846b3988a 1479 this->tmain_calib_hdr0_tx0.address[0] = 0x47; ///< Address=71
tgrosch 0:62b846b3988a 1480 this->tmain_calib_hdr0_tx0.msb[0] = 11;
tgrosch 0:62b846b3988a 1481 this->tmain_calib_hdr0_tx0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1482
tgrosch 0:62b846b3988a 1483 //Initialization for register temp_coeff_main_hdr0_tx0
tgrosch 0:62b846b3988a 1484 this->temp_coeff_main_hdr0_tx0.address[0] = 0x45; ///< Address=69
tgrosch 0:62b846b3988a 1485 this->temp_coeff_main_hdr0_tx0.msb[0] = 11;
tgrosch 0:62b846b3988a 1486 this->temp_coeff_main_hdr0_tx0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1487
tgrosch 0:62b846b3988a 1488 //Initialization for register tmain_calib_hdr1_tx0
tgrosch 0:62b846b3988a 1489 this->tmain_calib_hdr1_tx0.address[0] = 0x48; ///< Address=72
tgrosch 0:62b846b3988a 1490 this->tmain_calib_hdr1_tx0.msb[0] = 11;
tgrosch 0:62b846b3988a 1491 this->tmain_calib_hdr1_tx0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1492
tgrosch 0:62b846b3988a 1493 //Initialization for register temp_coeff_main_hdr1_tx0
tgrosch 0:62b846b3988a 1494 this->temp_coeff_main_hdr1_tx0.address[0] = 0x2d; ///< Address=45
tgrosch 0:62b846b3988a 1495 this->temp_coeff_main_hdr1_tx0.msb[0] = 11;
tgrosch 0:62b846b3988a 1496 this->temp_coeff_main_hdr1_tx0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1497
tgrosch 0:62b846b3988a 1498 //Initialization for register tmain_calib_hdr0_tx1
tgrosch 0:62b846b3988a 1499 this->tmain_calib_hdr0_tx1.address[0] = 0x49; ///< Address=73
tgrosch 0:62b846b3988a 1500 this->tmain_calib_hdr0_tx1.msb[0] = 11;
tgrosch 0:62b846b3988a 1501 this->tmain_calib_hdr0_tx1.lsb[0] = 0;
tgrosch 0:62b846b3988a 1502
tgrosch 0:62b846b3988a 1503 //Initialization for register temp_coeff_main_hdr0_tx1
tgrosch 0:62b846b3988a 1504 this->temp_coeff_main_hdr0_tx1.address[0] = 0x2d; ///< Address=45
tgrosch 0:62b846b3988a 1505 this->temp_coeff_main_hdr0_tx1.msb[0] = 23;
tgrosch 0:62b846b3988a 1506 this->temp_coeff_main_hdr0_tx1.lsb[0] = 12;
tgrosch 0:62b846b3988a 1507
tgrosch 0:62b846b3988a 1508 //Initialization for register tmain_calib_hdr1_tx1
tgrosch 0:62b846b3988a 1509 this->tmain_calib_hdr1_tx1.address[0] = 0x41; ///< Address=65
tgrosch 0:62b846b3988a 1510 this->tmain_calib_hdr1_tx1.msb[0] = 23;
tgrosch 0:62b846b3988a 1511 this->tmain_calib_hdr1_tx1.lsb[0] = 12;
tgrosch 0:62b846b3988a 1512
tgrosch 0:62b846b3988a 1513 //Initialization for register temp_coeff_main_hdr1_tx1
tgrosch 0:62b846b3988a 1514 this->temp_coeff_main_hdr1_tx1.address[1] = 0x2f; ///< Address=47
tgrosch 0:62b846b3988a 1515 this->temp_coeff_main_hdr1_tx1.msb[1] = 23;
tgrosch 0:62b846b3988a 1516 this->temp_coeff_main_hdr1_tx1.lsb[1] = 16;
tgrosch 0:62b846b3988a 1517 this->temp_coeff_main_hdr1_tx1.address[0] = 0x30; ///< Address=48
tgrosch 0:62b846b3988a 1518 this->temp_coeff_main_hdr1_tx1.msb[0] = 23;
tgrosch 0:62b846b3988a 1519 this->temp_coeff_main_hdr1_tx1.lsb[0] = 20;
tgrosch 0:62b846b3988a 1520
tgrosch 0:62b846b3988a 1521 //Initialization for register tmain_calib_hdr0_tx2
tgrosch 0:62b846b3988a 1522 this->tmain_calib_hdr0_tx2.address[0] = 0x3f; ///< Address=63
tgrosch 0:62b846b3988a 1523 this->tmain_calib_hdr0_tx2.msb[0] = 11;
tgrosch 0:62b846b3988a 1524 this->tmain_calib_hdr0_tx2.lsb[0] = 0;
tgrosch 0:62b846b3988a 1525
tgrosch 0:62b846b3988a 1526 //Initialization for register temp_coeff_main_hdr0_tx2
tgrosch 0:62b846b3988a 1527 this->temp_coeff_main_hdr0_tx2.address[1] = 0x31; ///< Address=49
tgrosch 0:62b846b3988a 1528 this->temp_coeff_main_hdr0_tx2.msb[1] = 23;
tgrosch 0:62b846b3988a 1529 this->temp_coeff_main_hdr0_tx2.lsb[1] = 16;
tgrosch 0:62b846b3988a 1530 this->temp_coeff_main_hdr0_tx2.address[0] = 0x32; ///< Address=50
tgrosch 0:62b846b3988a 1531 this->temp_coeff_main_hdr0_tx2.msb[0] = 23;
tgrosch 0:62b846b3988a 1532 this->temp_coeff_main_hdr0_tx2.lsb[0] = 20;
tgrosch 0:62b846b3988a 1533
tgrosch 0:62b846b3988a 1534 //Initialization for register tmain_calib_hdr1_tx2
tgrosch 0:62b846b3988a 1535 this->tmain_calib_hdr1_tx2.address[0] = 0x45; ///< Address=69
tgrosch 0:62b846b3988a 1536 this->tmain_calib_hdr1_tx2.msb[0] = 23;
tgrosch 0:62b846b3988a 1537 this->tmain_calib_hdr1_tx2.lsb[0] = 12;
tgrosch 0:62b846b3988a 1538
tgrosch 0:62b846b3988a 1539 //Initialization for register temp_coeff_main_hdr1_tx2
tgrosch 0:62b846b3988a 1540 this->temp_coeff_main_hdr1_tx2.address[1] = 0x33; ///< Address=51
tgrosch 0:62b846b3988a 1541 this->temp_coeff_main_hdr1_tx2.msb[1] = 23;
tgrosch 0:62b846b3988a 1542 this->temp_coeff_main_hdr1_tx2.lsb[1] = 16;
tgrosch 0:62b846b3988a 1543 this->temp_coeff_main_hdr1_tx2.address[0] = 0x34; ///< Address=52
tgrosch 0:62b846b3988a 1544 this->temp_coeff_main_hdr1_tx2.msb[0] = 23;
tgrosch 0:62b846b3988a 1545 this->temp_coeff_main_hdr1_tx2.lsb[0] = 20;
tgrosch 0:62b846b3988a 1546
tgrosch 0:62b846b3988a 1547 //Initialization for register tillum_calib_hdr0_tx0
tgrosch 0:62b846b3988a 1548 this->tillum_calib_hdr0_tx0.address[0] = 0x47; ///< Address=71
tgrosch 0:62b846b3988a 1549 this->tillum_calib_hdr0_tx0.msb[0] = 23;
tgrosch 0:62b846b3988a 1550 this->tillum_calib_hdr0_tx0.lsb[0] = 12;
tgrosch 0:62b846b3988a 1551
tgrosch 0:62b846b3988a 1552 //Initialization for register temp_coeff_illum_hdr0_tx0
tgrosch 0:62b846b3988a 1553 this->temp_coeff_illum_hdr0_tx0.address[0] = 0x46; ///< Address=70
tgrosch 0:62b846b3988a 1554 this->temp_coeff_illum_hdr0_tx0.msb[0] = 11;
tgrosch 0:62b846b3988a 1555 this->temp_coeff_illum_hdr0_tx0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1556
tgrosch 0:62b846b3988a 1557 //Initialization for register tillum_calib_hdr1_tx0
tgrosch 0:62b846b3988a 1558 this->tillum_calib_hdr1_tx0.address[0] = 0x48; ///< Address=72
tgrosch 0:62b846b3988a 1559 this->tillum_calib_hdr1_tx0.msb[0] = 23;
tgrosch 0:62b846b3988a 1560 this->tillum_calib_hdr1_tx0.lsb[0] = 12;
tgrosch 0:62b846b3988a 1561
tgrosch 0:62b846b3988a 1562 //Initialization for register temp_coeff_illum_hdr1_tx0
tgrosch 0:62b846b3988a 1563 this->temp_coeff_illum_hdr1_tx0.address[1] = 0x51; ///< Address=81
tgrosch 0:62b846b3988a 1564 this->temp_coeff_illum_hdr1_tx0.msb[1] = 23;
tgrosch 0:62b846b3988a 1565 this->temp_coeff_illum_hdr1_tx0.lsb[1] = 16;
tgrosch 0:62b846b3988a 1566 this->temp_coeff_illum_hdr1_tx0.address[0] = 0x52; ///< Address=82
tgrosch 0:62b846b3988a 1567 this->temp_coeff_illum_hdr1_tx0.msb[0] = 23;
tgrosch 0:62b846b3988a 1568 this->temp_coeff_illum_hdr1_tx0.lsb[0] = 20;
tgrosch 0:62b846b3988a 1569
tgrosch 0:62b846b3988a 1570 //Initialization for register tillum_calib_hdr0_tx1
tgrosch 0:62b846b3988a 1571 this->tillum_calib_hdr0_tx1.address[0] = 0x49; ///< Address=73
tgrosch 0:62b846b3988a 1572 this->tillum_calib_hdr0_tx1.msb[0] = 23;
tgrosch 0:62b846b3988a 1573 this->tillum_calib_hdr0_tx1.lsb[0] = 12;
tgrosch 0:62b846b3988a 1574
tgrosch 0:62b846b3988a 1575 //Initialization for register temp_coeff_illum_hdr0_tx1
tgrosch 0:62b846b3988a 1576 this->temp_coeff_illum_hdr0_tx1.address[1] = 0x53; ///< Address=83
tgrosch 0:62b846b3988a 1577 this->temp_coeff_illum_hdr0_tx1.msb[1] = 23;
tgrosch 0:62b846b3988a 1578 this->temp_coeff_illum_hdr0_tx1.lsb[1] = 16;
tgrosch 0:62b846b3988a 1579 this->temp_coeff_illum_hdr0_tx1.address[0] = 0x54; ///< Address=84
tgrosch 0:62b846b3988a 1580 this->temp_coeff_illum_hdr0_tx1.msb[0] = 23;
tgrosch 0:62b846b3988a 1581 this->temp_coeff_illum_hdr0_tx1.lsb[0] = 20;
tgrosch 0:62b846b3988a 1582
tgrosch 0:62b846b3988a 1583 //Initialization for register tillum_calib_hdr1_tx1
tgrosch 0:62b846b3988a 1584 this->tillum_calib_hdr1_tx1.address[0] = 0x43; ///< Address=67
tgrosch 0:62b846b3988a 1585 this->tillum_calib_hdr1_tx1.msb[0] = 23;
tgrosch 0:62b846b3988a 1586 this->tillum_calib_hdr1_tx1.lsb[0] = 12;
tgrosch 0:62b846b3988a 1587
tgrosch 0:62b846b3988a 1588 //Initialization for register temp_coeff_illum_hdr1_tx1
tgrosch 0:62b846b3988a 1589 this->temp_coeff_illum_hdr1_tx1.address[1] = 0x55; ///< Address=85
tgrosch 0:62b846b3988a 1590 this->temp_coeff_illum_hdr1_tx1.msb[1] = 23;
tgrosch 0:62b846b3988a 1591 this->temp_coeff_illum_hdr1_tx1.lsb[1] = 16;
tgrosch 0:62b846b3988a 1592 this->temp_coeff_illum_hdr1_tx1.address[0] = 0x56; ///< Address=86
tgrosch 0:62b846b3988a 1593 this->temp_coeff_illum_hdr1_tx1.msb[0] = 23;
tgrosch 0:62b846b3988a 1594 this->temp_coeff_illum_hdr1_tx1.lsb[0] = 20;
tgrosch 0:62b846b3988a 1595
tgrosch 0:62b846b3988a 1596 //Initialization for register tillum_calib_hdr0_tx2
tgrosch 0:62b846b3988a 1597 this->tillum_calib_hdr0_tx2.address[0] = 0x3f; ///< Address=63
tgrosch 0:62b846b3988a 1598 this->tillum_calib_hdr0_tx2.msb[0] = 23;
tgrosch 0:62b846b3988a 1599 this->tillum_calib_hdr0_tx2.lsb[0] = 12;
tgrosch 0:62b846b3988a 1600
tgrosch 0:62b846b3988a 1601 //Initialization for register temp_coeff_illum_hdr0_tx2
tgrosch 0:62b846b3988a 1602 this->temp_coeff_illum_hdr0_tx2.address[1] = 0x57; ///< Address=87
tgrosch 0:62b846b3988a 1603 this->temp_coeff_illum_hdr0_tx2.msb[1] = 23;
tgrosch 0:62b846b3988a 1604 this->temp_coeff_illum_hdr0_tx2.lsb[1] = 16;
tgrosch 0:62b846b3988a 1605 this->temp_coeff_illum_hdr0_tx2.address[0] = 0x58; ///< Address=88
tgrosch 0:62b846b3988a 1606 this->temp_coeff_illum_hdr0_tx2.msb[0] = 23;
tgrosch 0:62b846b3988a 1607 this->temp_coeff_illum_hdr0_tx2.lsb[0] = 20;
tgrosch 0:62b846b3988a 1608
tgrosch 0:62b846b3988a 1609 //Initialization for register tillum_calib_hdr1_tx2
tgrosch 0:62b846b3988a 1610 this->tillum_calib_hdr1_tx2.address[0] = 0x46; ///< Address=70
tgrosch 0:62b846b3988a 1611 this->tillum_calib_hdr1_tx2.msb[0] = 23;
tgrosch 0:62b846b3988a 1612 this->tillum_calib_hdr1_tx2.lsb[0] = 12;
tgrosch 0:62b846b3988a 1613
tgrosch 0:62b846b3988a 1614 //Initialization for register temp_coeff_illum_hdr1_tx2
tgrosch 0:62b846b3988a 1615 this->temp_coeff_illum_hdr1_tx2.address[1] = 0x59; ///< Address=89
tgrosch 0:62b846b3988a 1616 this->temp_coeff_illum_hdr1_tx2.msb[1] = 23;
tgrosch 0:62b846b3988a 1617 this->temp_coeff_illum_hdr1_tx2.lsb[1] = 16;
tgrosch 0:62b846b3988a 1618 this->temp_coeff_illum_hdr1_tx2.address[0] = 0x5a; ///< Address=90
tgrosch 0:62b846b3988a 1619 this->temp_coeff_illum_hdr1_tx2.msb[0] = 23;
tgrosch 0:62b846b3988a 1620 this->temp_coeff_illum_hdr1_tx2.lsb[0] = 20;
tgrosch 0:62b846b3988a 1621
tgrosch 0:62b846b3988a 1622 //Initialization for register amb_sat_thr
tgrosch 0:62b846b3988a 1623 this->amb_sat_thr.address[0] = 0x0d; ///< Address=13
tgrosch 0:62b846b3988a 1624 this->amb_sat_thr.msb[0] = 16;
tgrosch 0:62b846b3988a 1625 this->amb_sat_thr.lsb[0] = 7;
tgrosch 0:62b846b3988a 1626
tgrosch 0:62b846b3988a 1627 //Initialization for register amb_calib
tgrosch 0:62b846b3988a 1628 this->amb_calib.address[0] = 0x0b; ///< Address=11
tgrosch 0:62b846b3988a 1629 this->amb_calib.msb[0] = 23;
tgrosch 0:62b846b3988a 1630 this->amb_calib.lsb[0] = 14;
tgrosch 0:62b846b3988a 1631
tgrosch 0:62b846b3988a 1632 //Initialization for register amb_phase_corr_pwl_coeff0
tgrosch 0:62b846b3988a 1633 this->amb_phase_corr_pwl_coeff0.address[0] = 0x0c; ///< Address=12
tgrosch 0:62b846b3988a 1634 this->amb_phase_corr_pwl_coeff0.msb[0] = 23;
tgrosch 0:62b846b3988a 1635 this->amb_phase_corr_pwl_coeff0.lsb[0] = 16;
tgrosch 0:62b846b3988a 1636
tgrosch 0:62b846b3988a 1637 //Initialization for register amb_phase_corr_pwl_x0
tgrosch 0:62b846b3988a 1638 this->amb_phase_corr_pwl_x0.address[0] = 0xb8; ///< Address=184
tgrosch 0:62b846b3988a 1639 this->amb_phase_corr_pwl_x0.msb[0] = 9;
tgrosch 0:62b846b3988a 1640 this->amb_phase_corr_pwl_x0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1641
tgrosch 0:62b846b3988a 1642 //Initialization for register amb_phase_corr_pwl_x1
tgrosch 0:62b846b3988a 1643 this->amb_phase_corr_pwl_x1.address[0] = 0xb8; ///< Address=184
tgrosch 0:62b846b3988a 1644 this->amb_phase_corr_pwl_x1.msb[0] = 19;
tgrosch 0:62b846b3988a 1645 this->amb_phase_corr_pwl_x1.lsb[0] = 10;
tgrosch 0:62b846b3988a 1646
tgrosch 0:62b846b3988a 1647 //Initialization for register amb_phase_corr_pwl_x2
tgrosch 0:62b846b3988a 1648 this->amb_phase_corr_pwl_x2.address[0] = 0xb9; ///< Address=185
tgrosch 0:62b846b3988a 1649 this->amb_phase_corr_pwl_x2.msb[0] = 9;
tgrosch 0:62b846b3988a 1650 this->amb_phase_corr_pwl_x2.lsb[0] = 0;
tgrosch 0:62b846b3988a 1651
tgrosch 0:62b846b3988a 1652 //Initialization for register amb_phase_corr_pwl_coeff1
tgrosch 0:62b846b3988a 1653 this->amb_phase_corr_pwl_coeff1.address[0] = 0xb4; ///< Address=180
tgrosch 0:62b846b3988a 1654 this->amb_phase_corr_pwl_coeff1.msb[0] = 7;
tgrosch 0:62b846b3988a 1655 this->amb_phase_corr_pwl_coeff1.lsb[0] = 0;
tgrosch 0:62b846b3988a 1656
tgrosch 0:62b846b3988a 1657 //Initialization for register amb_phase_corr_pwl_coeff2
tgrosch 0:62b846b3988a 1658 this->amb_phase_corr_pwl_coeff2.address[0] = 0xb4; ///< Address=180
tgrosch 0:62b846b3988a 1659 this->amb_phase_corr_pwl_coeff2.msb[0] = 15;
tgrosch 0:62b846b3988a 1660 this->amb_phase_corr_pwl_coeff2.lsb[0] = 8;
tgrosch 0:62b846b3988a 1661
tgrosch 0:62b846b3988a 1662 //Initialization for register amb_phase_corr_pwl_coeff3
tgrosch 0:62b846b3988a 1663 this->amb_phase_corr_pwl_coeff3.address[0] = 0xb4; ///< Address=180
tgrosch 0:62b846b3988a 1664 this->amb_phase_corr_pwl_coeff3.msb[0] = 23;
tgrosch 0:62b846b3988a 1665 this->amb_phase_corr_pwl_coeff3.lsb[0] = 16;
tgrosch 0:62b846b3988a 1666
tgrosch 0:62b846b3988a 1667 //Initialization for register scale_amb_phase_corr_coeff
tgrosch 0:62b846b3988a 1668 this->scale_amb_phase_corr_coeff.address[0] = 0xb5; ///< Address=181
tgrosch 0:62b846b3988a 1669 this->scale_amb_phase_corr_coeff.msb[0] = 2;
tgrosch 0:62b846b3988a 1670 this->scale_amb_phase_corr_coeff.lsb[0] = 0;
tgrosch 0:62b846b3988a 1671
tgrosch 0:62b846b3988a 1672 //Initialization for register temp_coeff_illum_square_hdr0
tgrosch 0:62b846b3988a 1673 this->temp_coeff_illum_square_hdr0.address[0] = 0xb6; ///< Address=182
tgrosch 0:62b846b3988a 1674 this->temp_coeff_illum_square_hdr0.msb[0] = 7;
tgrosch 0:62b846b3988a 1675 this->temp_coeff_illum_square_hdr0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1676
tgrosch 0:62b846b3988a 1677 //Initialization for register temp_coeff_illum_square_hdr1
tgrosch 0:62b846b3988a 1678 this->temp_coeff_illum_square_hdr1.address[0] = 0xb6; ///< Address=182
tgrosch 0:62b846b3988a 1679 this->temp_coeff_illum_square_hdr1.msb[0] = 15;
tgrosch 0:62b846b3988a 1680 this->temp_coeff_illum_square_hdr1.lsb[0] = 8;
tgrosch 0:62b846b3988a 1681
tgrosch 0:62b846b3988a 1682 //Initialization for register temp_coeff_main_square_hdr0
tgrosch 0:62b846b3988a 1683 this->temp_coeff_main_square_hdr0.address[0] = 0xb7; ///< Address=183
tgrosch 0:62b846b3988a 1684 this->temp_coeff_main_square_hdr0.msb[0] = 7;
tgrosch 0:62b846b3988a 1685 this->temp_coeff_main_square_hdr0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1686
tgrosch 0:62b846b3988a 1687 //Initialization for register temp_coeff_main_square_hdr1
tgrosch 0:62b846b3988a 1688 this->temp_coeff_main_square_hdr1.address[0] = 0xb7; ///< Address=183
tgrosch 0:62b846b3988a 1689 this->temp_coeff_main_square_hdr1.msb[0] = 15;
tgrosch 0:62b846b3988a 1690 this->temp_coeff_main_square_hdr1.lsb[0] = 8;
tgrosch 0:62b846b3988a 1691
tgrosch 0:62b846b3988a 1692 //Initialization for register scale_phase_temp_corr_square
tgrosch 0:62b846b3988a 1693 this->scale_phase_temp_corr_square.address[0] = 0xb5; ///< Address=181
tgrosch 0:62b846b3988a 1694 this->scale_phase_temp_corr_square.msb[0] = 5;
tgrosch 0:62b846b3988a 1695 this->scale_phase_temp_corr_square.lsb[0] = 3;
tgrosch 0:62b846b3988a 1696
tgrosch 0:62b846b3988a 1697 //Initialization for register en_nl_corr
tgrosch 0:62b846b3988a 1698 this->en_nl_corr.address[0] = 0x4a; ///< Address=74
tgrosch 0:62b846b3988a 1699 this->en_nl_corr.msb[0] = 0;
tgrosch 0:62b846b3988a 1700 this->en_nl_corr.lsb[0] = 0;
tgrosch 0:62b846b3988a 1701
tgrosch 0:62b846b3988a 1702 //Initialization for register a1_coeff_hdr0_tx0
tgrosch 0:62b846b3988a 1703 this->a1_coeff_hdr0_tx0.address[0] = 0x4b; ///< Address=75
tgrosch 0:62b846b3988a 1704 this->a1_coeff_hdr0_tx0.msb[0] = 15;
tgrosch 0:62b846b3988a 1705 this->a1_coeff_hdr0_tx0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1706
tgrosch 0:62b846b3988a 1707 //Initialization for register a2_coeff_hdr0_tx0
tgrosch 0:62b846b3988a 1708 this->a2_coeff_hdr0_tx0.address[0] = 0x4c; ///< Address=76
tgrosch 0:62b846b3988a 1709 this->a2_coeff_hdr0_tx0.msb[0] = 15;
tgrosch 0:62b846b3988a 1710 this->a2_coeff_hdr0_tx0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1711
tgrosch 0:62b846b3988a 1712 //Initialization for register a3_coeff_hdr0_tx0
tgrosch 0:62b846b3988a 1713 this->a3_coeff_hdr0_tx0.address[0] = 0x4d; ///< Address=77
tgrosch 0:62b846b3988a 1714 this->a3_coeff_hdr0_tx0.msb[0] = 15;
tgrosch 0:62b846b3988a 1715 this->a3_coeff_hdr0_tx0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1716
tgrosch 0:62b846b3988a 1717 //Initialization for register a4_coeff_hdr0_tx0
tgrosch 0:62b846b3988a 1718 this->a4_coeff_hdr0_tx0.address[0] = 0x4e; ///< Address=78
tgrosch 0:62b846b3988a 1719 this->a4_coeff_hdr0_tx0.msb[0] = 15;
tgrosch 0:62b846b3988a 1720 this->a4_coeff_hdr0_tx0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1721
tgrosch 0:62b846b3988a 1722 //Initialization for register scale_nl_corr_coeff
tgrosch 0:62b846b3988a 1723 this->scale_nl_corr_coeff.address[0] = 0x4a; ///< Address=74
tgrosch 0:62b846b3988a 1724 this->scale_nl_corr_coeff.msb[0] = 19;
tgrosch 0:62b846b3988a 1725 this->scale_nl_corr_coeff.lsb[0] = 18;
tgrosch 0:62b846b3988a 1726
tgrosch 0:62b846b3988a 1727 //Initialization for register a0_coeff_hdr0_tx0
tgrosch 0:62b846b3988a 1728 this->a0_coeff_hdr0_tx0.address[0] = 0x4a; ///< Address=74
tgrosch 0:62b846b3988a 1729 this->a0_coeff_hdr0_tx0.msb[0] = 17;
tgrosch 0:62b846b3988a 1730 this->a0_coeff_hdr0_tx0.lsb[0] = 2;
tgrosch 0:62b846b3988a 1731
tgrosch 0:62b846b3988a 1732 //Initialization for register a0_coeff_hdr1_tx0
tgrosch 0:62b846b3988a 1733 this->a0_coeff_hdr1_tx0.address[0] = 0xa2; ///< Address=162
tgrosch 0:62b846b3988a 1734 this->a0_coeff_hdr1_tx0.msb[0] = 15;
tgrosch 0:62b846b3988a 1735 this->a0_coeff_hdr1_tx0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1736
tgrosch 0:62b846b3988a 1737 //Initialization for register a0_coeff_hdr0_tx1
tgrosch 0:62b846b3988a 1738 this->a0_coeff_hdr0_tx1.address[0] = 0xa3; ///< Address=163
tgrosch 0:62b846b3988a 1739 this->a0_coeff_hdr0_tx1.msb[0] = 15;
tgrosch 0:62b846b3988a 1740 this->a0_coeff_hdr0_tx1.lsb[0] = 0;
tgrosch 0:62b846b3988a 1741
tgrosch 0:62b846b3988a 1742 //Initialization for register a0_coeff_hdr1_tx1
tgrosch 0:62b846b3988a 1743 this->a0_coeff_hdr1_tx1.address[0] = 0xa4; ///< Address=164
tgrosch 0:62b846b3988a 1744 this->a0_coeff_hdr1_tx1.msb[0] = 15;
tgrosch 0:62b846b3988a 1745 this->a0_coeff_hdr1_tx1.lsb[0] = 0;
tgrosch 0:62b846b3988a 1746
tgrosch 0:62b846b3988a 1747 //Initialization for register a0_coeff_hdr0_tx2
tgrosch 0:62b846b3988a 1748 this->a0_coeff_hdr0_tx2.address[0] = 0xa5; ///< Address=165
tgrosch 0:62b846b3988a 1749 this->a0_coeff_hdr0_tx2.msb[0] = 15;
tgrosch 0:62b846b3988a 1750 this->a0_coeff_hdr0_tx2.lsb[0] = 0;
tgrosch 0:62b846b3988a 1751
tgrosch 0:62b846b3988a 1752 //Initialization for register a0_coeff_hdr1_tx2
tgrosch 0:62b846b3988a 1753 this->a0_coeff_hdr1_tx2.address[0] = 0xa6; ///< Address=166
tgrosch 0:62b846b3988a 1754 this->a0_coeff_hdr1_tx2.msb[0] = 15;
tgrosch 0:62b846b3988a 1755 this->a0_coeff_hdr1_tx2.lsb[0] = 0;
tgrosch 0:62b846b3988a 1756
tgrosch 0:62b846b3988a 1757 //Initialization for register a1_coeff_hdr1_tx0
tgrosch 0:62b846b3988a 1758 this->a1_coeff_hdr1_tx0.address[0] = 0xa7; ///< Address=167
tgrosch 0:62b846b3988a 1759 this->a1_coeff_hdr1_tx0.msb[0] = 15;
tgrosch 0:62b846b3988a 1760 this->a1_coeff_hdr1_tx0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1761
tgrosch 0:62b846b3988a 1762 //Initialization for register a1_coeff_hdr0_tx1
tgrosch 0:62b846b3988a 1763 this->a1_coeff_hdr0_tx1.address[0] = 0xa8; ///< Address=168
tgrosch 0:62b846b3988a 1764 this->a1_coeff_hdr0_tx1.msb[0] = 15;
tgrosch 0:62b846b3988a 1765 this->a1_coeff_hdr0_tx1.lsb[0] = 0;
tgrosch 0:62b846b3988a 1766
tgrosch 0:62b846b3988a 1767 //Initialization for register a1_coeff_hdr1_tx1
tgrosch 0:62b846b3988a 1768 this->a1_coeff_hdr1_tx1.address[0] = 0xa9; ///< Address=169
tgrosch 0:62b846b3988a 1769 this->a1_coeff_hdr1_tx1.msb[0] = 15;
tgrosch 0:62b846b3988a 1770 this->a1_coeff_hdr1_tx1.lsb[0] = 0;
tgrosch 0:62b846b3988a 1771
tgrosch 0:62b846b3988a 1772 //Initialization for register a1_coeff_hdr0_tx2
tgrosch 0:62b846b3988a 1773 this->a1_coeff_hdr0_tx2.address[0] = 0xaa; ///< Address=170
tgrosch 0:62b846b3988a 1774 this->a1_coeff_hdr0_tx2.msb[0] = 15;
tgrosch 0:62b846b3988a 1775 this->a1_coeff_hdr0_tx2.lsb[0] = 0;
tgrosch 0:62b846b3988a 1776
tgrosch 0:62b846b3988a 1777 //Initialization for register a1_coeff_hdr1_tx2
tgrosch 0:62b846b3988a 1778 this->a1_coeff_hdr1_tx2.address[0] = 0xab; ///< Address=171
tgrosch 0:62b846b3988a 1779 this->a1_coeff_hdr1_tx2.msb[0] = 15;
tgrosch 0:62b846b3988a 1780 this->a1_coeff_hdr1_tx2.lsb[0] = 0;
tgrosch 0:62b846b3988a 1781
tgrosch 0:62b846b3988a 1782 //Initialization for register a2_coeff_hdr1_tx0
tgrosch 0:62b846b3988a 1783 this->a2_coeff_hdr1_tx0.address[0] = 0xac; ///< Address=172
tgrosch 0:62b846b3988a 1784 this->a2_coeff_hdr1_tx0.msb[0] = 15;
tgrosch 0:62b846b3988a 1785 this->a2_coeff_hdr1_tx0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1786
tgrosch 0:62b846b3988a 1787 //Initialization for register a2_coeff_hdr0_tx1
tgrosch 0:62b846b3988a 1788 this->a2_coeff_hdr0_tx1.address[0] = 0xad; ///< Address=173
tgrosch 0:62b846b3988a 1789 this->a2_coeff_hdr0_tx1.msb[0] = 15;
tgrosch 0:62b846b3988a 1790 this->a2_coeff_hdr0_tx1.lsb[0] = 0;
tgrosch 0:62b846b3988a 1791
tgrosch 0:62b846b3988a 1792 //Initialization for register a2_coeff_hdr1_tx1
tgrosch 0:62b846b3988a 1793 this->a2_coeff_hdr1_tx1.address[0] = 0xae; ///< Address=174
tgrosch 0:62b846b3988a 1794 this->a2_coeff_hdr1_tx1.msb[0] = 15;
tgrosch 0:62b846b3988a 1795 this->a2_coeff_hdr1_tx1.lsb[0] = 0;
tgrosch 0:62b846b3988a 1796
tgrosch 0:62b846b3988a 1797 //Initialization for register a2_coeff_hdr0_tx2
tgrosch 0:62b846b3988a 1798 this->a2_coeff_hdr0_tx2.address[0] = 0xaf; ///< Address=175
tgrosch 0:62b846b3988a 1799 this->a2_coeff_hdr0_tx2.msb[0] = 15;
tgrosch 0:62b846b3988a 1800 this->a2_coeff_hdr0_tx2.lsb[0] = 0;
tgrosch 0:62b846b3988a 1801
tgrosch 0:62b846b3988a 1802 //Initialization for register a2_coeff_hdr1_tx2
tgrosch 0:62b846b3988a 1803 this->a2_coeff_hdr1_tx2.address[0] = 0xb0; ///< Address=176
tgrosch 0:62b846b3988a 1804 this->a2_coeff_hdr1_tx2.msb[0] = 15;
tgrosch 0:62b846b3988a 1805 this->a2_coeff_hdr1_tx2.lsb[0] = 0;
tgrosch 0:62b846b3988a 1806
tgrosch 0:62b846b3988a 1807 //Initialization for register a3_coeff_hdr1_tx0
tgrosch 0:62b846b3988a 1808 this->a3_coeff_hdr1_tx0.address[0] = 0xb1; ///< Address=177
tgrosch 0:62b846b3988a 1809 this->a3_coeff_hdr1_tx0.msb[0] = 15;
tgrosch 0:62b846b3988a 1810 this->a3_coeff_hdr1_tx0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1811
tgrosch 0:62b846b3988a 1812 //Initialization for register a3_coeff_hdr0_tx1
tgrosch 0:62b846b3988a 1813 this->a3_coeff_hdr0_tx1.address[1] = 0xa2; ///< Address=162
tgrosch 0:62b846b3988a 1814 this->a3_coeff_hdr0_tx1.msb[1] = 23;
tgrosch 0:62b846b3988a 1815 this->a3_coeff_hdr0_tx1.lsb[1] = 16;
tgrosch 0:62b846b3988a 1816 this->a3_coeff_hdr0_tx1.address[0] = 0xa3; ///< Address=163
tgrosch 0:62b846b3988a 1817 this->a3_coeff_hdr0_tx1.msb[0] = 23;
tgrosch 0:62b846b3988a 1818 this->a3_coeff_hdr0_tx1.lsb[0] = 16;
tgrosch 0:62b846b3988a 1819
tgrosch 0:62b846b3988a 1820 //Initialization for register a3_coeff_hdr1_tx1
tgrosch 0:62b846b3988a 1821 this->a3_coeff_hdr1_tx1.address[1] = 0xa4; ///< Address=164
tgrosch 0:62b846b3988a 1822 this->a3_coeff_hdr1_tx1.msb[1] = 23;
tgrosch 0:62b846b3988a 1823 this->a3_coeff_hdr1_tx1.lsb[1] = 16;
tgrosch 0:62b846b3988a 1824 this->a3_coeff_hdr1_tx1.address[0] = 0xa5; ///< Address=165
tgrosch 0:62b846b3988a 1825 this->a3_coeff_hdr1_tx1.msb[0] = 23;
tgrosch 0:62b846b3988a 1826 this->a3_coeff_hdr1_tx1.lsb[0] = 16;
tgrosch 0:62b846b3988a 1827
tgrosch 0:62b846b3988a 1828 //Initialization for register a3_coeff_hdr0_tx2
tgrosch 0:62b846b3988a 1829 this->a3_coeff_hdr0_tx2.address[1] = 0xa6; ///< Address=166
tgrosch 0:62b846b3988a 1830 this->a3_coeff_hdr0_tx2.msb[1] = 23;
tgrosch 0:62b846b3988a 1831 this->a3_coeff_hdr0_tx2.lsb[1] = 16;
tgrosch 0:62b846b3988a 1832 this->a3_coeff_hdr0_tx2.address[0] = 0xa7; ///< Address=167
tgrosch 0:62b846b3988a 1833 this->a3_coeff_hdr0_tx2.msb[0] = 23;
tgrosch 0:62b846b3988a 1834 this->a3_coeff_hdr0_tx2.lsb[0] = 16;
tgrosch 0:62b846b3988a 1835
tgrosch 0:62b846b3988a 1836 //Initialization for register a3_coeff_hdr1_tx2
tgrosch 0:62b846b3988a 1837 this->a3_coeff_hdr1_tx2.address[1] = 0xa8; ///< Address=168
tgrosch 0:62b846b3988a 1838 this->a3_coeff_hdr1_tx2.msb[1] = 23;
tgrosch 0:62b846b3988a 1839 this->a3_coeff_hdr1_tx2.lsb[1] = 16;
tgrosch 0:62b846b3988a 1840 this->a3_coeff_hdr1_tx2.address[0] = 0xa9; ///< Address=169
tgrosch 0:62b846b3988a 1841 this->a3_coeff_hdr1_tx2.msb[0] = 23;
tgrosch 0:62b846b3988a 1842 this->a3_coeff_hdr1_tx2.lsb[0] = 16;
tgrosch 0:62b846b3988a 1843
tgrosch 0:62b846b3988a 1844 //Initialization for register a4_coeff_hdr1_tx0
tgrosch 0:62b846b3988a 1845 this->a4_coeff_hdr1_tx0.address[1] = 0xaa; ///< Address=170
tgrosch 0:62b846b3988a 1846 this->a4_coeff_hdr1_tx0.msb[1] = 23;
tgrosch 0:62b846b3988a 1847 this->a4_coeff_hdr1_tx0.lsb[1] = 16;
tgrosch 0:62b846b3988a 1848 this->a4_coeff_hdr1_tx0.address[0] = 0xab; ///< Address=171
tgrosch 0:62b846b3988a 1849 this->a4_coeff_hdr1_tx0.msb[0] = 23;
tgrosch 0:62b846b3988a 1850 this->a4_coeff_hdr1_tx0.lsb[0] = 16;
tgrosch 0:62b846b3988a 1851
tgrosch 0:62b846b3988a 1852 //Initialization for register a4_coeff_hdr0_tx1
tgrosch 0:62b846b3988a 1853 this->a4_coeff_hdr0_tx1.address[1] = 0xac; ///< Address=172
tgrosch 0:62b846b3988a 1854 this->a4_coeff_hdr0_tx1.msb[1] = 23;
tgrosch 0:62b846b3988a 1855 this->a4_coeff_hdr0_tx1.lsb[1] = 16;
tgrosch 0:62b846b3988a 1856 this->a4_coeff_hdr0_tx1.address[0] = 0xad; ///< Address=173
tgrosch 0:62b846b3988a 1857 this->a4_coeff_hdr0_tx1.msb[0] = 23;
tgrosch 0:62b846b3988a 1858 this->a4_coeff_hdr0_tx1.lsb[0] = 16;
tgrosch 0:62b846b3988a 1859
tgrosch 0:62b846b3988a 1860 //Initialization for register a4_coeff_hdr1_tx1
tgrosch 0:62b846b3988a 1861 this->a4_coeff_hdr1_tx1.address[1] = 0xae; ///< Address=174
tgrosch 0:62b846b3988a 1862 this->a4_coeff_hdr1_tx1.msb[1] = 23;
tgrosch 0:62b846b3988a 1863 this->a4_coeff_hdr1_tx1.lsb[1] = 16;
tgrosch 0:62b846b3988a 1864 this->a4_coeff_hdr1_tx1.address[0] = 0xaf; ///< Address=175
tgrosch 0:62b846b3988a 1865 this->a4_coeff_hdr1_tx1.msb[0] = 23;
tgrosch 0:62b846b3988a 1866 this->a4_coeff_hdr1_tx1.lsb[0] = 16;
tgrosch 0:62b846b3988a 1867
tgrosch 0:62b846b3988a 1868 //Initialization for register a4_coeff_hdr0_tx2
tgrosch 0:62b846b3988a 1869 this->a4_coeff_hdr0_tx2.address[1] = 0xb0; ///< Address=176
tgrosch 0:62b846b3988a 1870 this->a4_coeff_hdr0_tx2.msb[1] = 23;
tgrosch 0:62b846b3988a 1871 this->a4_coeff_hdr0_tx2.lsb[1] = 16;
tgrosch 0:62b846b3988a 1872 this->a4_coeff_hdr0_tx2.address[0] = 0xb1; ///< Address=177
tgrosch 0:62b846b3988a 1873 this->a4_coeff_hdr0_tx2.msb[0] = 23;
tgrosch 0:62b846b3988a 1874 this->a4_coeff_hdr0_tx2.lsb[0] = 16;
tgrosch 0:62b846b3988a 1875
tgrosch 0:62b846b3988a 1876 //Initialization for register a4_coeff_hdr1_tx2
tgrosch 0:62b846b3988a 1877 this->a4_coeff_hdr1_tx2.address[0] = 0xb2; ///< Address=178
tgrosch 0:62b846b3988a 1878 this->a4_coeff_hdr1_tx2.msb[0] = 15;
tgrosch 0:62b846b3988a 1879 this->a4_coeff_hdr1_tx2.lsb[0] = 0;
tgrosch 0:62b846b3988a 1880
tgrosch 0:62b846b3988a 1881 //Initialization for register tillum
tgrosch 0:62b846b3988a 1882 this->tillum.address[0] = 0x04; ///< Address=4
tgrosch 0:62b846b3988a 1883 this->tillum.msb[0] = 19;
tgrosch 0:62b846b3988a 1884 this->tillum.lsb[0] = 8;
tgrosch 0:62b846b3988a 1885
tgrosch 0:62b846b3988a 1886 //Initialization for register tsens_slave0
tgrosch 0:62b846b3988a 1887 this->tsens_slave0.address[0] = 0x02; ///< Address=2
tgrosch 0:62b846b3988a 1888 this->tsens_slave0.msb[0] = 6;
tgrosch 0:62b846b3988a 1889 this->tsens_slave0.lsb[0] = 0;
tgrosch 0:62b846b3988a 1890
tgrosch 0:62b846b3988a 1891 //Initialization for register tsens_slave1
tgrosch 0:62b846b3988a 1892 this->tsens_slave1.address[0] = 0x02; ///< Address=2
tgrosch 0:62b846b3988a 1893 this->tsens_slave1.msb[0] = 13;
tgrosch 0:62b846b3988a 1894 this->tsens_slave1.lsb[0] = 7;
tgrosch 0:62b846b3988a 1895
tgrosch 0:62b846b3988a 1896 //Initialization for register tsens_slave2
tgrosch 0:62b846b3988a 1897 this->tsens_slave2.address[0] = 0x02; ///< Address=2
tgrosch 0:62b846b3988a 1898 this->tsens_slave2.msb[0] = 20;
tgrosch 0:62b846b3988a 1899 this->tsens_slave2.lsb[0] = 14;
tgrosch 0:62b846b3988a 1900
tgrosch 0:62b846b3988a 1901 //Initialization for register config_tillum_msb
tgrosch 0:62b846b3988a 1902 this->config_tillum_msb.address[0] = 0x07; ///< Address=7
tgrosch 0:62b846b3988a 1903 this->config_tillum_msb.msb[0] = 23;
tgrosch 0:62b846b3988a 1904 this->config_tillum_msb.lsb[0] = 20;
tgrosch 0:62b846b3988a 1905
tgrosch 0:62b846b3988a 1906 //Initialization for register en_tillum_12b
tgrosch 0:62b846b3988a 1907 this->en_tillum_12b.address[0] = 0x0d; ///< Address=13
tgrosch 0:62b846b3988a 1908 this->en_tillum_12b.msb[0] = 23;
tgrosch 0:62b846b3988a 1909 this->en_tillum_12b.lsb[0] = 23;
tgrosch 0:62b846b3988a 1910
tgrosch 0:62b846b3988a 1911 //Initialization for register tillum_unsigned
tgrosch 0:62b846b3988a 1912 this->tillum_unsigned.address[0] = 0x04; ///< Address=4
tgrosch 0:62b846b3988a 1913 this->tillum_unsigned.msb[0] = 23;
tgrosch 0:62b846b3988a 1914 this->tillum_unsigned.lsb[0] = 23;
tgrosch 0:62b846b3988a 1915
tgrosch 0:62b846b3988a 1916 //Initialization for register temp_avg_illum
tgrosch 0:62b846b3988a 1917 this->temp_avg_illum.address[0] = 0x02; ///< Address=2
tgrosch 0:62b846b3988a 1918 this->temp_avg_illum.msb[0] = 23;
tgrosch 0:62b846b3988a 1919 this->temp_avg_illum.lsb[0] = 22;
tgrosch 0:62b846b3988a 1920
tgrosch 0:62b846b3988a 1921 //Initialization for register en_tsens_read_fvd
tgrosch 0:62b846b3988a 1922 this->en_tsens_read_fvd.address[0] = 0x03; ///< Address=3
tgrosch 0:62b846b3988a 1923 this->en_tsens_read_fvd.msb[0] = 18;
tgrosch 0:62b846b3988a 1924 this->en_tsens_read_fvd.lsb[0] = 18;
tgrosch 0:62b846b3988a 1925
tgrosch 0:62b846b3988a 1926 //Initialization for register en_tillum_read
tgrosch 0:62b846b3988a 1927 this->en_tillum_read.address[0] = 0x02; ///< Address=2
tgrosch 0:62b846b3988a 1928 this->en_tillum_read.msb[0] = 21;
tgrosch 0:62b846b3988a 1929 this->en_tillum_read.lsb[0] = 21;
tgrosch 0:62b846b3988a 1930
tgrosch 0:62b846b3988a 1931 //Initialization for register eeprom_read_trig
tgrosch 0:62b846b3988a 1932 this->eeprom_read_trig.address[0] = 0x01; ///< Address=1
tgrosch 0:62b846b3988a 1933 this->eeprom_read_trig.msb[0] = 0;
tgrosch 0:62b846b3988a 1934 this->eeprom_read_trig.lsb[0] = 0;
tgrosch 0:62b846b3988a 1935
tgrosch 0:62b846b3988a 1936 //Initialization for register swap_read_data
tgrosch 0:62b846b3988a 1937 this->swap_read_data.address[0] = 0x01; ///< Address=1
tgrosch 0:62b846b3988a 1938 this->swap_read_data.msb[0] = 1;
tgrosch 0:62b846b3988a 1939 this->swap_read_data.lsb[0] = 1;
tgrosch 0:62b846b3988a 1940
tgrosch 0:62b846b3988a 1941 //Initialization for register eeprom_start_reg_addr
tgrosch 0:62b846b3988a 1942 this->eeprom_start_reg_addr.address[0] = 0x01; ///< Address=1
tgrosch 0:62b846b3988a 1943 this->eeprom_start_reg_addr.msb[0] = 16;
tgrosch 0:62b846b3988a 1944 this->eeprom_start_reg_addr.lsb[0] = 9;
tgrosch 0:62b846b3988a 1945
tgrosch 0:62b846b3988a 1946 //Initialization for register frame_vd_trig
tgrosch 0:62b846b3988a 1947 this->frame_vd_trig.address[0] = 0x01; ///< Address=1
tgrosch 0:62b846b3988a 1948 this->frame_vd_trig.msb[0] = 17;
tgrosch 0:62b846b3988a 1949 this->frame_vd_trig.lsb[0] = 17;
tgrosch 0:62b846b3988a 1950
tgrosch 0:62b846b3988a 1951 //Initialization for register i2c_trig_reg
tgrosch 0:62b846b3988a 1952 this->i2c_trig_reg.address[0] = 0x01; ///< Address=1
tgrosch 0:62b846b3988a 1953 this->i2c_trig_reg.msb[0] = 18;
tgrosch 0:62b846b3988a 1954 this->i2c_trig_reg.lsb[0] = 18;
tgrosch 0:62b846b3988a 1955
tgrosch 0:62b846b3988a 1956 //Initialization for register i2c_en
tgrosch 0:62b846b3988a 1957 this->i2c_en.address[0] = 0x01; ///< Address=1
tgrosch 0:62b846b3988a 1958 this->i2c_en.msb[0] = 19;
tgrosch 0:62b846b3988a 1959 this->i2c_en.lsb[0] = 19;
tgrosch 0:62b846b3988a 1960
tgrosch 0:62b846b3988a 1961 //Initialization for register i2c_rw
tgrosch 0:62b846b3988a 1962 this->i2c_rw.address[0] = 0x01; ///< Address=1
tgrosch 0:62b846b3988a 1963 this->i2c_rw.msb[0] = 21;
tgrosch 0:62b846b3988a 1964 this->i2c_rw.lsb[0] = 20;
tgrosch 0:62b846b3988a 1965
tgrosch 0:62b846b3988a 1966 //Initialization for register i2c_read_data
tgrosch 0:62b846b3988a 1967 this->i2c_read_data.address[0] = 0x03; ///< Address=3
tgrosch 0:62b846b3988a 1968 this->i2c_read_data.msb[0] = 7;
tgrosch 0:62b846b3988a 1969 this->i2c_read_data.lsb[0] = 0;
tgrosch 0:62b846b3988a 1970
tgrosch 0:62b846b3988a 1971 //Initialization for register i2c_write_data1
tgrosch 0:62b846b3988a 1972 this->i2c_write_data1.address[0] = 0x03; ///< Address=3
tgrosch 0:62b846b3988a 1973 this->i2c_write_data1.msb[0] = 16;
tgrosch 0:62b846b3988a 1974 this->i2c_write_data1.lsb[0] = 9;
tgrosch 0:62b846b3988a 1975
tgrosch 0:62b846b3988a 1976 //Initialization for register i2c_num_tran
tgrosch 0:62b846b3988a 1977 this->i2c_num_tran.address[0] = 0x03; ///< Address=3
tgrosch 0:62b846b3988a 1978 this->i2c_num_tran.msb[0] = 17;
tgrosch 0:62b846b3988a 1979 this->i2c_num_tran.lsb[0] = 17;
tgrosch 0:62b846b3988a 1980
tgrosch 0:62b846b3988a 1981 //Initialization for register en_eeprom_read
tgrosch 0:62b846b3988a 1982 this->en_eeprom_read.address[0] = 0x01; ///< Address=1
tgrosch 0:62b846b3988a 1983 this->en_eeprom_read.msb[0] = 23;
tgrosch 0:62b846b3988a 1984 this->en_eeprom_read.lsb[0] = 23;
tgrosch 0:62b846b3988a 1985
tgrosch 0:62b846b3988a 1986 //Initialization for register init_load_done
tgrosch 0:62b846b3988a 1987 this->init_load_done.address[0] = 0x03; ///< Address=3
tgrosch 0:62b846b3988a 1988 this->init_load_done.msb[0] = 8;
tgrosch 0:62b846b3988a 1989 this->init_load_done.lsb[0] = 8;
tgrosch 0:62b846b3988a 1990
tgrosch 0:62b846b3988a 1991 //Initialization for register addr_slave_eeprom
tgrosch 0:62b846b3988a 1992 this->addr_slave_eeprom.address[0] = 0x01; ///< Address=1
tgrosch 0:62b846b3988a 1993 this->addr_slave_eeprom.msb[0] = 8;
tgrosch 0:62b846b3988a 1994 this->addr_slave_eeprom.lsb[0] = 2;
tgrosch 0:62b846b3988a 1995
tgrosch 0:62b846b3988a 1996 //Initialization for register i2c_num_bytes_tran1
tgrosch 0:62b846b3988a 1997 this->i2c_num_bytes_tran1.address[0] = 0x07; ///< Address=7
tgrosch 0:62b846b3988a 1998 this->i2c_num_bytes_tran1.msb[0] = 17;
tgrosch 0:62b846b3988a 1999 this->i2c_num_bytes_tran1.lsb[0] = 16;
tgrosch 0:62b846b3988a 2000
tgrosch 0:62b846b3988a 2001 //Initialization for register i2c_num_bytes_tran2
tgrosch 0:62b846b3988a 2002 this->i2c_num_bytes_tran2.address[0] = 0x05; ///< Address=5
tgrosch 0:62b846b3988a 2003 this->i2c_num_bytes_tran2.msb[0] = 23;
tgrosch 0:62b846b3988a 2004 this->i2c_num_bytes_tran2.lsb[0] = 22;
tgrosch 0:62b846b3988a 2005
tgrosch 0:62b846b3988a 2006 //Initialization for register i2c_write_data2
tgrosch 0:62b846b3988a 2007 this->i2c_write_data2.address[0] = 0x07; ///< Address=7
tgrosch 0:62b846b3988a 2008 this->i2c_write_data2.msb[0] = 7;
tgrosch 0:62b846b3988a 2009 this->i2c_write_data2.lsb[0] = 0;
tgrosch 0:62b846b3988a 2010
tgrosch 0:62b846b3988a 2011 //Initialization for register i2c_sel_read_bytes
tgrosch 0:62b846b3988a 2012 this->i2c_sel_read_bytes.address[0] = 0x07; ///< Address=7
tgrosch 0:62b846b3988a 2013 this->i2c_sel_read_bytes.msb[0] = 19;
tgrosch 0:62b846b3988a 2014 this->i2c_sel_read_bytes.lsb[0] = 18;
tgrosch 0:62b846b3988a 2015
tgrosch 0:62b846b3988a 2016 //Initialization for register i2c_cont_rw
tgrosch 0:62b846b3988a 2017 this->i2c_cont_rw.address[0] = 0x00; ///< Address=0
tgrosch 0:62b846b3988a 2018 this->i2c_cont_rw.msb[0] = 6;
tgrosch 0:62b846b3988a 2019 this->i2c_cont_rw.lsb[0] = 6;
tgrosch 0:62b846b3988a 2020
tgrosch 0:62b846b3988a 2021 //Initialization for register dis_ovldet
tgrosch 0:62b846b3988a 2022 this->dis_ovldet.address[0] = 0x65; ///< Address=101
tgrosch 0:62b846b3988a 2023 this->dis_ovldet.msb[0] = 23;
tgrosch 0:62b846b3988a 2024 this->dis_ovldet.lsb[0] = 23;
tgrosch 0:62b846b3988a 2025
tgrosch 0:62b846b3988a 2026 //Initialization for register prog_ovldet_refp
tgrosch 0:62b846b3988a 2027 this->prog_ovldet_refp.address[0] = 0x64; ///< Address=100
tgrosch 0:62b846b3988a 2028 this->prog_ovldet_refp.msb[0] = 20;
tgrosch 0:62b846b3988a 2029 this->prog_ovldet_refp.lsb[0] = 18;
tgrosch 0:62b846b3988a 2030
tgrosch 0:62b846b3988a 2031 //Initialization for register prog_ovldet_refm
tgrosch 0:62b846b3988a 2032 this->prog_ovldet_refm.address[0] = 0x64; ///< Address=100
tgrosch 0:62b846b3988a 2033 this->prog_ovldet_refm.msb[0] = 23;
tgrosch 0:62b846b3988a 2034 this->prog_ovldet_refm.lsb[0] = 21;
tgrosch 0:62b846b3988a 2035
tgrosch 0:62b846b3988a 2036 //Initialization for register iamb_max_sel
tgrosch 0:62b846b3988a 2037 this->iamb_max_sel.address[0] = 0x72; ///< Address=114
tgrosch 0:62b846b3988a 2038 this->iamb_max_sel.msb[0] = 7;
tgrosch 0:62b846b3988a 2039 this->iamb_max_sel.lsb[0] = 4;
tgrosch 0:62b846b3988a 2040
tgrosch 0:62b846b3988a 2041 //Initialization for register tm_vrefp_diode
tgrosch 0:62b846b3988a 2042 this->tm_vrefp_diode.address[0] = 0x6d; ///< Address=109
tgrosch 0:62b846b3988a 2043 this->tm_vrefp_diode.msb[0] = 2;
tgrosch 0:62b846b3988a 2044 this->tm_vrefp_diode.lsb[0] = 0;
tgrosch 0:62b846b3988a 2045
tgrosch 0:62b846b3988a 2046 //Initialization for register tm_vrefm_diode
tgrosch 0:62b846b3988a 2047 this->tm_vrefm_diode.address[0] = 0x6d; ///< Address=109
tgrosch 0:62b846b3988a 2048 this->tm_vrefm_diode.msb[0] = 5;
tgrosch 0:62b846b3988a 2049 this->tm_vrefm_diode.lsb[0] = 3;
tgrosch 0:62b846b3988a 2050
tgrosch 0:62b846b3988a 2051 //Initialization for register gpo1_mux_sel
tgrosch 0:62b846b3988a 2052 this->gpo1_mux_sel.address[0] = 0x78; ///< Address=120
tgrosch 0:62b846b3988a 2053 this->gpo1_mux_sel.msb[0] = 8;
tgrosch 0:62b846b3988a 2054 this->gpo1_mux_sel.lsb[0] = 6;
tgrosch 0:62b846b3988a 2055
tgrosch 0:62b846b3988a 2056 //Initialization for register gpio1_obuf_en
tgrosch 0:62b846b3988a 2057 this->gpio1_obuf_en.address[0] = 0x78; ///< Address=120
tgrosch 0:62b846b3988a 2058 this->gpio1_obuf_en.msb[0] = 12;
tgrosch 0:62b846b3988a 2059 this->gpio1_obuf_en.lsb[0] = 12;
tgrosch 0:62b846b3988a 2060
tgrosch 0:62b846b3988a 2061 //Initialization for register gpio1_ibuf_en
tgrosch 0:62b846b3988a 2062 this->gpio1_ibuf_en.address[0] = 0x78; ///< Address=120
tgrosch 0:62b846b3988a 2063 this->gpio1_ibuf_en.msb[0] = 13;
tgrosch 0:62b846b3988a 2064 this->gpio1_ibuf_en.lsb[0] = 13;
tgrosch 0:62b846b3988a 2065
tgrosch 0:62b846b3988a 2066 //Initialization for register gpo2_mux_sel
tgrosch 0:62b846b3988a 2067 this->gpo2_mux_sel.address[0] = 0x78; ///< Address=120
tgrosch 0:62b846b3988a 2068 this->gpo2_mux_sel.msb[0] = 11;
tgrosch 0:62b846b3988a 2069 this->gpo2_mux_sel.lsb[0] = 9;
tgrosch 0:62b846b3988a 2070
tgrosch 0:62b846b3988a 2071 //Initialization for register gpio2_obuf_en
tgrosch 0:62b846b3988a 2072 this->gpio2_obuf_en.address[0] = 0x78; ///< Address=120
tgrosch 0:62b846b3988a 2073 this->gpio2_obuf_en.msb[0] = 15;
tgrosch 0:62b846b3988a 2074 this->gpio2_obuf_en.lsb[0] = 15;
tgrosch 0:62b846b3988a 2075
tgrosch 0:62b846b3988a 2076 //Initialization for register gpio2_ibuf_en
tgrosch 0:62b846b3988a 2077 this->gpio2_ibuf_en.address[0] = 0x78; ///< Address=120
tgrosch 0:62b846b3988a 2078 this->gpio2_ibuf_en.msb[0] = 16;
tgrosch 0:62b846b3988a 2079 this->gpio2_ibuf_en.lsb[0] = 16;
tgrosch 0:62b846b3988a 2080
tgrosch 0:62b846b3988a 2081 //Initialization for register gpo3_mux_sel
tgrosch 0:62b846b3988a 2082 this->gpo3_mux_sel.address[0] = 0x78; ///< Address=120
tgrosch 0:62b846b3988a 2083 this->gpo3_mux_sel.msb[0] = 2;
tgrosch 0:62b846b3988a 2084 this->gpo3_mux_sel.lsb[0] = 0;
tgrosch 0:62b846b3988a 2085
tgrosch 0:62b846b3988a 2086 //Initialization for register sel_gp3_on_sdam
tgrosch 0:62b846b3988a 2087 this->sel_gp3_on_sdam.address[0] = 0x78; ///< Address=120
tgrosch 0:62b846b3988a 2088 this->sel_gp3_on_sdam.msb[0] = 22;
tgrosch 0:62b846b3988a 2089 this->sel_gp3_on_sdam.lsb[0] = 22;
tgrosch 0:62b846b3988a 2090
tgrosch 0:62b846b3988a 2091 //Initialization for register dealias_en
tgrosch 0:62b846b3988a 2092 this->dealias_en.address[0] = 0x71; ///< Address=113
tgrosch 0:62b846b3988a 2093 this->dealias_en.msb[0] = 1;
tgrosch 0:62b846b3988a 2094 this->dealias_en.lsb[0] = 1;
tgrosch 0:62b846b3988a 2095
tgrosch 0:62b846b3988a 2096 //Initialization for register dealias_freq
tgrosch 0:62b846b3988a 2097 this->dealias_freq.address[0] = 0x71; ///< Address=113
tgrosch 0:62b846b3988a 2098 this->dealias_freq.msb[0] = 2;
tgrosch 0:62b846b3988a 2099 this->dealias_freq.lsb[0] = 2;
tgrosch 0:62b846b3988a 2100
tgrosch 0:62b846b3988a 2101 //Initialization for register shift_illum_phase
tgrosch 0:62b846b3988a 2102 this->shift_illum_phase.address[0] = 0x71; ///< Address=113
tgrosch 0:62b846b3988a 2103 this->shift_illum_phase.msb[0] = 6;
tgrosch 0:62b846b3988a 2104 this->shift_illum_phase.lsb[0] = 3;
tgrosch 0:62b846b3988a 2105
tgrosch 0:62b846b3988a 2106 //Initialization for register shut_clocks
tgrosch 0:62b846b3988a 2107 this->shut_clocks.address[0] = 0x71; ///< Address=113
tgrosch 0:62b846b3988a 2108 this->shut_clocks.msb[0] = 8;
tgrosch 0:62b846b3988a 2109 this->shut_clocks.lsb[0] = 8;
tgrosch 0:62b846b3988a 2110
tgrosch 0:62b846b3988a 2111 //Initialization for register invert_tg_clk
tgrosch 0:62b846b3988a 2112 this->invert_tg_clk.address[0] = 0x71; ///< Address=113
tgrosch 0:62b846b3988a 2113 this->invert_tg_clk.msb[0] = 9;
tgrosch 0:62b846b3988a 2114 this->invert_tg_clk.lsb[0] = 9;
tgrosch 0:62b846b3988a 2115
tgrosch 0:62b846b3988a 2116 //Initialization for register invert_afe_clk
tgrosch 0:62b846b3988a 2117 this->invert_afe_clk.address[0] = 0x71; ///< Address=113
tgrosch 0:62b846b3988a 2118 this->invert_afe_clk.msb[0] = 11;
tgrosch 0:62b846b3988a 2119 this->invert_afe_clk.lsb[0] = 11;
tgrosch 0:62b846b3988a 2120
tgrosch 0:62b846b3988a 2121 //Initialization for register dis_illum_clk_tx
tgrosch 0:62b846b3988a 2122 this->dis_illum_clk_tx.address[0] = 0x71; ///< Address=113
tgrosch 0:62b846b3988a 2123 this->dis_illum_clk_tx.msb[0] = 12;
tgrosch 0:62b846b3988a 2124 this->dis_illum_clk_tx.lsb[0] = 12;
tgrosch 0:62b846b3988a 2125
tgrosch 0:62b846b3988a 2126 //Initialization for register en_illum_clk_gpio
tgrosch 0:62b846b3988a 2127 this->en_illum_clk_gpio.address[0] = 0x71; ///< Address=113
tgrosch 0:62b846b3988a 2128 this->en_illum_clk_gpio.msb[0] = 16;
tgrosch 0:62b846b3988a 2129 this->en_illum_clk_gpio.lsb[0] = 16;
tgrosch 0:62b846b3988a 2130
tgrosch 0:62b846b3988a 2131 //Initialization for register illum_clk_gpio_mode
tgrosch 0:62b846b3988a 2132 this->illum_clk_gpio_mode.address[0] = 0x71; ///< Address=113
tgrosch 0:62b846b3988a 2133 this->illum_clk_gpio_mode.msb[0] = 15;
tgrosch 0:62b846b3988a 2134 this->illum_clk_gpio_mode.lsb[0] = 15;
tgrosch 0:62b846b3988a 2135
tgrosch 0:62b846b3988a 2136 //Initialization for register unmask_illumen_intxtalk
tgrosch 0:62b846b3988a 2137 this->unmask_illumen_intxtalk.address[0] = 0x71; ///< Address=113
tgrosch 0:62b846b3988a 2138 this->unmask_illumen_intxtalk.msb[0] = 17;
tgrosch 0:62b846b3988a 2139 this->unmask_illumen_intxtalk.lsb[0] = 17;
tgrosch 0:62b846b3988a 2140
tgrosch 0:62b846b3988a 2141 //Initialization for register temp_offset
tgrosch 0:62b846b3988a 2142 this->temp_offset.address[0] = 0x6e; ///< Address=110
tgrosch 0:62b846b3988a 2143 this->temp_offset.msb[0] = 16;
tgrosch 0:62b846b3988a 2144 this->temp_offset.lsb[0] = 8;
tgrosch 0:62b846b3988a 2145
tgrosch 0:62b846b3988a 2146 //Initialization for register en_temp_conv
tgrosch 0:62b846b3988a 2147 this->en_temp_conv.address[0] = 0x6e; ///< Address=110
tgrosch 0:62b846b3988a 2148 this->en_temp_conv.msb[0] = 19;
tgrosch 0:62b846b3988a 2149 this->en_temp_conv.lsb[0] = 19;
tgrosch 0:62b846b3988a 2150
tgrosch 0:62b846b3988a 2151 //Initialization for register calib_curr1_DAC_I
tgrosch 0:62b846b3988a 2152 this->calib_curr1_DAC_I.address[0] = 0x74; ///< Address=116
tgrosch 0:62b846b3988a 2153 this->calib_curr1_DAC_I.msb[0] = 3;
tgrosch 0:62b846b3988a 2154 this->calib_curr1_DAC_I.lsb[0] = 0;
tgrosch 0:62b846b3988a 2155
tgrosch 0:62b846b3988a 2156 //Initialization for register calib_curr1_DAC_Q
tgrosch 0:62b846b3988a 2157 this->calib_curr1_DAC_Q.address[0] = 0x74; ///< Address=116
tgrosch 0:62b846b3988a 2158 this->calib_curr1_DAC_Q.msb[0] = 7;
tgrosch 0:62b846b3988a 2159 this->calib_curr1_DAC_Q.lsb[0] = 4;
tgrosch 0:62b846b3988a 2160
tgrosch 0:62b846b3988a 2161 //Initialization for register calib_curr1_en_I
tgrosch 0:62b846b3988a 2162 this->calib_curr1_en_I.address[0] = 0x74; ///< Address=116
tgrosch 0:62b846b3988a 2163 this->calib_curr1_en_I.msb[0] = 8;
tgrosch 0:62b846b3988a 2164 this->calib_curr1_en_I.lsb[0] = 8;
tgrosch 0:62b846b3988a 2165
tgrosch 0:62b846b3988a 2166 //Initialization for register calib_curr1_en_Q
tgrosch 0:62b846b3988a 2167 this->calib_curr1_en_Q.address[0] = 0x74; ///< Address=116
tgrosch 0:62b846b3988a 2168 this->calib_curr1_en_Q.msb[0] = 9;
tgrosch 0:62b846b3988a 2169 this->calib_curr1_en_Q.lsb[0] = 9;
tgrosch 0:62b846b3988a 2170
tgrosch 0:62b846b3988a 2171 //Initialization for register calib_curr1_inv_CLK_I
tgrosch 0:62b846b3988a 2172 this->calib_curr1_inv_CLK_I.address[0] = 0x74; ///< Address=116
tgrosch 0:62b846b3988a 2173 this->calib_curr1_inv_CLK_I.msb[0] = 10;
tgrosch 0:62b846b3988a 2174 this->calib_curr1_inv_CLK_I.lsb[0] = 10;
tgrosch 0:62b846b3988a 2175
tgrosch 0:62b846b3988a 2176 //Initialization for register calib_curr1_inv_CLK_Q
tgrosch 0:62b846b3988a 2177 this->calib_curr1_inv_CLK_Q.address[0] = 0x74; ///< Address=116
tgrosch 0:62b846b3988a 2178 this->calib_curr1_inv_CLK_Q.msb[0] = 11;
tgrosch 0:62b846b3988a 2179 this->calib_curr1_inv_CLK_Q.lsb[0] = 11;
tgrosch 0:62b846b3988a 2180
tgrosch 0:62b846b3988a 2181 //Initialization for register calib_curr1_sel_CLK_I
tgrosch 0:62b846b3988a 2182 this->calib_curr1_sel_CLK_I.address[0] = 0x74; ///< Address=116
tgrosch 0:62b846b3988a 2183 this->calib_curr1_sel_CLK_I.msb[0] = 12;
tgrosch 0:62b846b3988a 2184 this->calib_curr1_sel_CLK_I.lsb[0] = 12;
tgrosch 0:62b846b3988a 2185
tgrosch 0:62b846b3988a 2186 //Initialization for register calib_curr1_gain_sel
tgrosch 0:62b846b3988a 2187 this->calib_curr1_gain_sel.address[0] = 0x74; ///< Address=116
tgrosch 0:62b846b3988a 2188 this->calib_curr1_gain_sel.msb[0] = 14;
tgrosch 0:62b846b3988a 2189 this->calib_curr1_gain_sel.lsb[0] = 13;
tgrosch 0:62b846b3988a 2190
tgrosch 0:62b846b3988a 2191 //Initialization for register calib_curr1_spare
tgrosch 0:62b846b3988a 2192 this->calib_curr1_spare.address[0] = 0x74; ///< Address=116
tgrosch 0:62b846b3988a 2193 this->calib_curr1_spare.msb[0] = 15;
tgrosch 0:62b846b3988a 2194 this->calib_curr1_spare.lsb[0] = 15;
tgrosch 0:62b846b3988a 2195
tgrosch 0:62b846b3988a 2196 //Initialization for register dis_glb_pd_refsys
tgrosch 0:62b846b3988a 2197 this->dis_glb_pd_refsys.address[0] = 0x76; ///< Address=118
tgrosch 0:62b846b3988a 2198 this->dis_glb_pd_refsys.msb[0] = 0;
tgrosch 0:62b846b3988a 2199 this->dis_glb_pd_refsys.lsb[0] = 0;
tgrosch 0:62b846b3988a 2200
tgrosch 0:62b846b3988a 2201 //Initialization for register dis_glb_pd_temp_sens
tgrosch 0:62b846b3988a 2202 this->dis_glb_pd_temp_sens.address[0] = 0x76; ///< Address=118
tgrosch 0:62b846b3988a 2203 this->dis_glb_pd_temp_sens.msb[0] = 1;
tgrosch 0:62b846b3988a 2204 this->dis_glb_pd_temp_sens.lsb[0] = 1;
tgrosch 0:62b846b3988a 2205
tgrosch 0:62b846b3988a 2206 //Initialization for register dis_glb_pd_illum_drv
tgrosch 0:62b846b3988a 2207 this->dis_glb_pd_illum_drv.address[0] = 0x76; ///< Address=118
tgrosch 0:62b846b3988a 2208 this->dis_glb_pd_illum_drv.msb[0] = 2;
tgrosch 0:62b846b3988a 2209 this->dis_glb_pd_illum_drv.lsb[0] = 2;
tgrosch 0:62b846b3988a 2210
tgrosch 0:62b846b3988a 2211 //Initialization for register dis_glb_pd_afe
tgrosch 0:62b846b3988a 2212 this->dis_glb_pd_afe.address[0] = 0x76; ///< Address=118
tgrosch 0:62b846b3988a 2213 this->dis_glb_pd_afe.msb[0] = 3;
tgrosch 0:62b846b3988a 2214 this->dis_glb_pd_afe.lsb[0] = 3;
tgrosch 0:62b846b3988a 2215
tgrosch 0:62b846b3988a 2216 //Initialization for register dis_glb_pd_afe_dac
tgrosch 0:62b846b3988a 2217 this->dis_glb_pd_afe_dac.address[0] = 0x76; ///< Address=118
tgrosch 0:62b846b3988a 2218 this->dis_glb_pd_afe_dac.msb[0] = 4;
tgrosch 0:62b846b3988a 2219 this->dis_glb_pd_afe_dac.lsb[0] = 4;
tgrosch 0:62b846b3988a 2220
tgrosch 0:62b846b3988a 2221 //Initialization for register dis_glb_pd_amb_dac
tgrosch 0:62b846b3988a 2222 this->dis_glb_pd_amb_dac.address[0] = 0x76; ///< Address=118
tgrosch 0:62b846b3988a 2223 this->dis_glb_pd_amb_dac.msb[0] = 5;
tgrosch 0:62b846b3988a 2224 this->dis_glb_pd_amb_dac.lsb[0] = 5;
tgrosch 0:62b846b3988a 2225
tgrosch 0:62b846b3988a 2226 //Initialization for register dis_glb_pd_amb_adc
tgrosch 0:62b846b3988a 2227 this->dis_glb_pd_amb_adc.address[0] = 0x76; ///< Address=118
tgrosch 0:62b846b3988a 2228 this->dis_glb_pd_amb_adc.msb[0] = 6;
tgrosch 0:62b846b3988a 2229 this->dis_glb_pd_amb_adc.lsb[0] = 6;
tgrosch 0:62b846b3988a 2230
tgrosch 0:62b846b3988a 2231 //Initialization for register dis_glb_pd_test_curr
tgrosch 0:62b846b3988a 2232 this->dis_glb_pd_test_curr.address[0] = 0x76; ///< Address=118
tgrosch 0:62b846b3988a 2233 this->dis_glb_pd_test_curr.msb[0] = 7;
tgrosch 0:62b846b3988a 2234 this->dis_glb_pd_test_curr.lsb[0] = 7;
tgrosch 0:62b846b3988a 2235
tgrosch 0:62b846b3988a 2236 //Initialization for register dis_glb_pd_osc
tgrosch 0:62b846b3988a 2237 this->dis_glb_pd_osc.address[0] = 0x76; ///< Address=118
tgrosch 0:62b846b3988a 2238 this->dis_glb_pd_osc.msb[0] = 8;
tgrosch 0:62b846b3988a 2239 this->dis_glb_pd_osc.lsb[0] = 8;
tgrosch 0:62b846b3988a 2240
tgrosch 0:62b846b3988a 2241 //Initialization for register dis_glb_pd_i2chost
tgrosch 0:62b846b3988a 2242 this->dis_glb_pd_i2chost.address[0] = 0x76; ///< Address=118
tgrosch 0:62b846b3988a 2243 this->dis_glb_pd_i2chost.msb[0] = 9;
tgrosch 0:62b846b3988a 2244 this->dis_glb_pd_i2chost.lsb[0] = 9;
tgrosch 0:62b846b3988a 2245
tgrosch 0:62b846b3988a 2246 //Initialization for register pdn_global
tgrosch 0:62b846b3988a 2247 this->pdn_global.address[0] = 0x76; ///< Address=118
tgrosch 0:62b846b3988a 2248 this->pdn_global.msb[0] = 11;
tgrosch 0:62b846b3988a 2249 this->pdn_global.lsb[0] = 11;
tgrosch 0:62b846b3988a 2250
tgrosch 0:62b846b3988a 2251 //Initialization for register en_dyn_pd_refsys
tgrosch 0:62b846b3988a 2252 this->en_dyn_pd_refsys.address[0] = 0x77; ///< Address=119
tgrosch 0:62b846b3988a 2253 this->en_dyn_pd_refsys.msb[0] = 0;
tgrosch 0:62b846b3988a 2254 this->en_dyn_pd_refsys.lsb[0] = 0;
tgrosch 0:62b846b3988a 2255
tgrosch 0:62b846b3988a 2256 //Initialization for register en_dyn_pd_temp_sens
tgrosch 0:62b846b3988a 2257 this->en_dyn_pd_temp_sens.address[0] = 0x77; ///< Address=119
tgrosch 0:62b846b3988a 2258 this->en_dyn_pd_temp_sens.msb[0] = 1;
tgrosch 0:62b846b3988a 2259 this->en_dyn_pd_temp_sens.lsb[0] = 1;
tgrosch 0:62b846b3988a 2260
tgrosch 0:62b846b3988a 2261 //Initialization for register en_dyn_pd_illum_drv
tgrosch 0:62b846b3988a 2262 this->en_dyn_pd_illum_drv.address[0] = 0x77; ///< Address=119
tgrosch 0:62b846b3988a 2263 this->en_dyn_pd_illum_drv.msb[0] = 2;
tgrosch 0:62b846b3988a 2264 this->en_dyn_pd_illum_drv.lsb[0] = 2;
tgrosch 0:62b846b3988a 2265
tgrosch 0:62b846b3988a 2266 //Initialization for register en_dyn_pd_afe
tgrosch 0:62b846b3988a 2267 this->en_dyn_pd_afe.address[0] = 0x77; ///< Address=119
tgrosch 0:62b846b3988a 2268 this->en_dyn_pd_afe.msb[0] = 3;
tgrosch 0:62b846b3988a 2269 this->en_dyn_pd_afe.lsb[0] = 3;
tgrosch 0:62b846b3988a 2270
tgrosch 0:62b846b3988a 2271 //Initialization for register en_dyn_pd_afe_dac
tgrosch 0:62b846b3988a 2272 this->en_dyn_pd_afe_dac.address[0] = 0x77; ///< Address=119
tgrosch 0:62b846b3988a 2273 this->en_dyn_pd_afe_dac.msb[0] = 4;
tgrosch 0:62b846b3988a 2274 this->en_dyn_pd_afe_dac.lsb[0] = 4;
tgrosch 0:62b846b3988a 2275
tgrosch 0:62b846b3988a 2276 //Initialization for register en_dyn_pd_amb_dac
tgrosch 0:62b846b3988a 2277 this->en_dyn_pd_amb_dac.address[0] = 0x77; ///< Address=119
tgrosch 0:62b846b3988a 2278 this->en_dyn_pd_amb_dac.msb[0] = 5;
tgrosch 0:62b846b3988a 2279 this->en_dyn_pd_amb_dac.lsb[0] = 5;
tgrosch 0:62b846b3988a 2280
tgrosch 0:62b846b3988a 2281 //Initialization for register en_dyn_pd_amb_adc
tgrosch 0:62b846b3988a 2282 this->en_dyn_pd_amb_adc.address[0] = 0x77; ///< Address=119
tgrosch 0:62b846b3988a 2283 this->en_dyn_pd_amb_adc.msb[0] = 6;
tgrosch 0:62b846b3988a 2284 this->en_dyn_pd_amb_adc.lsb[0] = 6;
tgrosch 0:62b846b3988a 2285
tgrosch 0:62b846b3988a 2286 //Initialization for register en_dyn_pd_test_curr
tgrosch 0:62b846b3988a 2287 this->en_dyn_pd_test_curr.address[0] = 0x77; ///< Address=119
tgrosch 0:62b846b3988a 2288 this->en_dyn_pd_test_curr.msb[0] = 7;
tgrosch 0:62b846b3988a 2289 this->en_dyn_pd_test_curr.lsb[0] = 7;
tgrosch 0:62b846b3988a 2290
tgrosch 0:62b846b3988a 2291 //Initialization for register en_dyn_pd_osc
tgrosch 0:62b846b3988a 2292 this->en_dyn_pd_osc.address[0] = 0x77; ///< Address=119
tgrosch 0:62b846b3988a 2293 this->en_dyn_pd_osc.msb[0] = 8;
tgrosch 0:62b846b3988a 2294 this->en_dyn_pd_osc.lsb[0] = 8;
tgrosch 0:62b846b3988a 2295
tgrosch 0:62b846b3988a 2296 //Initialization for register en_dyn_pd_i2chost_osc
tgrosch 0:62b846b3988a 2297 this->en_dyn_pd_i2chost_osc.address[0] = 0x77; ///< Address=119
tgrosch 0:62b846b3988a 2298 this->en_dyn_pd_i2chost_osc.msb[0] = 9;
tgrosch 0:62b846b3988a 2299 this->en_dyn_pd_i2chost_osc.lsb[0] = 9;
tgrosch 0:62b846b3988a 2300
tgrosch 0:62b846b3988a 2301 //Initialization for register TX0_PIN_CONFIG
tgrosch 0:62b846b3988a 2302 this->TX0_PIN_CONFIG.address[0] = 0x7a; ///< Address=122
tgrosch 0:62b846b3988a 2303 this->TX0_PIN_CONFIG.msb[0] = 5;
tgrosch 0:62b846b3988a 2304 this->TX0_PIN_CONFIG.lsb[0] = 4;
tgrosch 0:62b846b3988a 2305
tgrosch 0:62b846b3988a 2306 //Initialization for register TX1_PIN_CONFIG
tgrosch 0:62b846b3988a 2307 this->TX1_PIN_CONFIG.address[0] = 0x7a; ///< Address=122
tgrosch 0:62b846b3988a 2308 this->TX1_PIN_CONFIG.msb[0] = 1;
tgrosch 0:62b846b3988a 2309 this->TX1_PIN_CONFIG.lsb[0] = 0;
tgrosch 0:62b846b3988a 2310
tgrosch 0:62b846b3988a 2311 //Initialization for register TX2_PIN_CONFIG
tgrosch 0:62b846b3988a 2312 this->TX2_PIN_CONFIG.address[0] = 0x7a; ///< Address=122
tgrosch 0:62b846b3988a 2313 this->TX2_PIN_CONFIG.msb[0] = 3;
tgrosch 0:62b846b3988a 2314 this->TX2_PIN_CONFIG.lsb[0] = 2;
tgrosch 0:62b846b3988a 2315
tgrosch 0:62b846b3988a 2316 //Initialization for register EN_TX_CLKB
tgrosch 0:62b846b3988a 2317 this->EN_TX_CLKB.address[0] = 0x79; ///< Address=121
tgrosch 0:62b846b3988a 2318 this->EN_TX_CLKB.msb[0] = 0;
tgrosch 0:62b846b3988a 2319 this->EN_TX_CLKB.lsb[0] = 0;
tgrosch 0:62b846b3988a 2320
tgrosch 0:62b846b3988a 2321 //Initialization for register EN_TX_CLKZ
tgrosch 0:62b846b3988a 2322 this->EN_TX_CLKZ.address[0] = 0x79; ///< Address=121
tgrosch 0:62b846b3988a 2323 this->EN_TX_CLKZ.msb[0] = 2;
tgrosch 0:62b846b3988a 2324 this->EN_TX_CLKZ.lsb[0] = 2;
tgrosch 0:62b846b3988a 2325
tgrosch 0:62b846b3988a 2326 //Initialization for register sel_illum_tx0_on_tx1
tgrosch 0:62b846b3988a 2327 this->sel_illum_tx0_on_tx1.address[0] = 0x79; ///< Address=121
tgrosch 0:62b846b3988a 2328 this->sel_illum_tx0_on_tx1.msb[0] = 3;
tgrosch 0:62b846b3988a 2329 this->sel_illum_tx0_on_tx1.lsb[0] = 3;
tgrosch 0:62b846b3988a 2330
tgrosch 0:62b846b3988a 2331 //Initialization for register ILLUM_DC_CURR_DAC
tgrosch 0:62b846b3988a 2332 this->ILLUM_DC_CURR_DAC.address[0] = 0x79; ///< Address=121
tgrosch 0:62b846b3988a 2333 this->ILLUM_DC_CURR_DAC.msb[0] = 11;
tgrosch 0:62b846b3988a 2334 this->ILLUM_DC_CURR_DAC.lsb[0] = 8;
tgrosch 0:62b846b3988a 2335
tgrosch 0:62b846b3988a 2336 //Initialization for register PDN_ILLUM_DC_CURR
tgrosch 0:62b846b3988a 2337 this->PDN_ILLUM_DC_CURR.address[0] = 0x79; ///< Address=121
tgrosch 0:62b846b3988a 2338 this->PDN_ILLUM_DC_CURR.msb[0] = 12;
tgrosch 0:62b846b3988a 2339 this->PDN_ILLUM_DC_CURR.lsb[0] = 12;
tgrosch 0:62b846b3988a 2340
tgrosch 0:62b846b3988a 2341 //Initialization for register FEEDBACK_CONT_MODE
tgrosch 0:62b846b3988a 2342 this->FEEDBACK_CONT_MODE.address[0] = 0x79; ///< Address=121
tgrosch 0:62b846b3988a 2343 this->FEEDBACK_CONT_MODE.msb[0] = 13;
tgrosch 0:62b846b3988a 2344 this->FEEDBACK_CONT_MODE.lsb[0] = 13;
tgrosch 0:62b846b3988a 2345
tgrosch 0:62b846b3988a 2346 //Initialization for register PDN_ILLUM_DRV
tgrosch 0:62b846b3988a 2347 this->PDN_ILLUM_DRV.address[0] = 0x79; ///< Address=121
tgrosch 0:62b846b3988a 2348 this->PDN_ILLUM_DRV.msb[0] = 19;
tgrosch 0:62b846b3988a 2349 this->PDN_ILLUM_DRV.lsb[0] = 19;
tgrosch 0:62b846b3988a 2350
tgrosch 0:62b846b3988a 2351 //Initialization for register EN_TX_DC_CURR_ALL
tgrosch 0:62b846b3988a 2352 this->EN_TX_DC_CURR_ALL.address[0] = 0x79; ///< Address=121
tgrosch 0:62b846b3988a 2353 this->EN_TX_DC_CURR_ALL.msb[0] = 4;
tgrosch 0:62b846b3988a 2354 this->EN_TX_DC_CURR_ALL.lsb[0] = 4;
tgrosch 0:62b846b3988a 2355
tgrosch 0:62b846b3988a 2356 //Initialization for register EN_CTALK_FB_CLK
tgrosch 0:62b846b3988a 2357 this->EN_CTALK_FB_CLK.address[0] = 0x7A; ///< Address=122
tgrosch 0:62b846b3988a 2358 this->EN_CTALK_FB_CLK.msb[0] = 11;
tgrosch 0:62b846b3988a 2359 this->EN_CTALK_FB_CLK.lsb[0] = 11;
tgrosch 0:62b846b3988a 2360
tgrosch 0:62b846b3988a 2361 //Initialization for register EN_CALIB_CLK
tgrosch 0:62b846b3988a 2362 this->EN_CALIB_CLK.address[0] = 0x79; ///< Address=??
tgrosch 0:62b846b3988a 2363 this->EN_CALIB_CLK.msb[0] = 1;
tgrosch 0:62b846b3988a 2364 this->EN_CALIB_CLK.lsb[0] = 1;
tgrosch 0:62b846b3988a 2365
tgrosch 0:62b846b3988a 2366 }
tgrosch 0:62b846b3988a 2367
tgrosch 0:62b846b3988a 2368