Jason Engelman / mcp2515

Dependents:   Kamal_CAN ReadFromSerial446 USNA-UMBC-KF-02_v3-noise USNA-UMBC-KF-01

mcp2515_bittime.h@8:872137b3a8a8, 2010-10-18 (annotated)

Committer:
tecnosys
Date:
Mon Oct 18 13:40:02 2010 +0000
Revision:
8:872137b3a8a8
Parent:
1:dbc44582f2f8 
0.1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tecnosys 0:d8f50b1e384f 1 /******************************************************************************
tecnosys 0:d8f50b1e384f 2 *
tecnosys 0:d8f50b1e384f 3 * Controller Area Network (CAN) Demo-Application
tecnosys 0:d8f50b1e384f 4 * Atmel AVR with Microchip MCP2515
tecnosys 0:d8f50b1e384f 5 *
tecnosys 0:d8f50b1e384f 6 * Copyright (C) 2005 Martin THOMAS, Kaiserslautern, Germany
tecnosys 0:d8f50b1e384f 7 * <eversmith@heizung-thomas.de>
tecnosys 0:d8f50b1e384f 8 * http://www.siwawi.arubi.uni-kl.de/avr_projects
tecnosys 0:d8f50b1e384f 9 *
tecnosys 0:d8f50b1e384f 10 *****************************************************************************
tecnosys 0:d8f50b1e384f 11 *
tecnosys 0:d8f50b1e384f 12 * File : mcp2515_bittime.h
tecnosys 0:d8f50b1e384f 13 * Version : 0.9
tecnosys 0:d8f50b1e384f 14 *
tecnosys 0:d8f50b1e384f 15 * Summary : MCP2515 CAN-timing values. Calculated with
tecnosys 0:d8f50b1e384f 16 * a spreadsheet-based "Preprocessor" with information
tecnosys 0:d8f50b1e384f 17 * from the MCP2515 and AT90CAN128 datasheets.
tecnosys 0:d8f50b1e384f 18 *
tecnosys 0:d8f50b1e384f 19 *****************************************************************************/
tecnosys 0:d8f50b1e384f 20
tecnosys 0:d8f50b1e384f 21 #include "mcp2515_defs.h"
tecnosys 0:d8f50b1e384f 22
tecnosys 0:d8f50b1e384f 23 /*-----------------------*/
tecnosys 0:d8f50b1e384f 24 /* global settings */
tecnosys 0:d8f50b1e384f 25 /*-----------------------*/
tecnosys 0:d8f50b1e384f 26
tecnosys 0:d8f50b1e384f 27 /* CFG3 */
tecnosys 0:d8f50b1e384f 28
tecnosys 0:d8f50b1e384f 29 // Start of Frame SOF (CLKOUT)
tecnosys 0:d8f50b1e384f 30 // either SOF_ENABLE or SOF_DISABLE
tecnosys 0:d8f50b1e384f 31 #define MCP_GENERAL_SOF (SOF_DISABLE)
tecnosys 0:d8f50b1e384f 32
tecnosys 0:d8f50b1e384f 33 // Wake up Filter (WAKFIL)
tecnosys 0:d8f50b1e384f 34 // either WAKFIL_ENABLE or WAKFIL_DISABLE
tecnosys 0:d8f50b1e384f 35 #define MCP_GENERAL_WAKFIL (WAKFIL_DISABLE)
tecnosys 0:d8f50b1e384f 36
tecnosys 0:d8f50b1e384f 37
tecnosys 0:d8f50b1e384f 38 /*-----------------------*/
tecnosys 0:d8f50b1e384f 39 /* 125 kBPS @ 4MHZ F_OSC */
tecnosys 0:d8f50b1e384f 40 /*-----------------------*/
tecnosys 0:d8f50b1e384f 41
tecnosys 0:d8f50b1e384f 42 /* CNF1 */
tecnosys 0:d8f50b1e384f 43
tecnosys 0:d8f50b1e384f 44 // SJW as defined in mcp_defs.h
tecnosys 0:d8f50b1e384f 45 // here: SJW = 1*TQ
tecnosys 0:d8f50b1e384f 46 #define MCP_4MHz_125kBPS_SJW (SJW1)
tecnosys 0:d8f50b1e384f 47
tecnosys 0:d8f50b1e384f 48 // Prescaler = (BRP+1)*2
tecnosys 0:d8f50b1e384f 49 // here Prescaler = 4 -> BRP=1
tecnosys 0:d8f50b1e384f 50 #define MCP_4MHz_125kBPS_BRP (1)
tecnosys 0:d8f50b1e384f 51
tecnosys 0:d8f50b1e384f 52
tecnosys 0:d8f50b1e384f 53 /* CNF2 */
tecnosys 0:d8f50b1e384f 54
tecnosys 0:d8f50b1e384f 55 // BLT-Mode defined in CNF3 (0 or BTLMODE from mcp_defs.h)
tecnosys 0:d8f50b1e384f 56 #define MCP_4MHz_125kBPS_BLTMODE (BTLMODE)
tecnosys 0:d8f50b1e384f 57
tecnosys 0:d8f50b1e384f 58 // 3 samples (SAMPLE_3X) or 1 sample (SAMPLE_1X)
tecnosys 0:d8f50b1e384f 59 #define MCP_4MHz_125kBPS_SAM (SAMPLE_1X)
tecnosys 0:d8f50b1e384f 60
tecnosys 0:d8f50b1e384f 61 // (Phase Segment 1) PHSEG1 = PS1 - 1
tecnosys 0:d8f50b1e384f 62 // here: PS1 calculated as 2
tecnosys 0:d8f50b1e384f 63 #define MCP_4MHz_125kBPS_PHSEG1 ((2-1)<<3)
tecnosys 0:d8f50b1e384f 64
tecnosys 0:d8f50b1e384f 65 // (Propagation Delay) PRSEG = PRSEQTQ-1
tecnosys 0:d8f50b1e384f 66 // here PRSEQTQ = 2
tecnosys 0:d8f50b1e384f 67 #define MCP_4MHz_125kBPS_PRSEG (2-1)
tecnosys 0:d8f50b1e384f 68
tecnosys 0:d8f50b1e384f 69 /* CNF3 */
tecnosys 0:d8f50b1e384f 70
tecnosys 0:d8f50b1e384f 71 // (Phase Segment 2) PHSEG2 = PS2 - 1
tecnosys 0:d8f50b1e384f 72 // here: PS2 calculated as 3
tecnosys 0:d8f50b1e384f 73 #define MCP_4MHz_125kBPS_PHSEG (3-1)
tecnosys 0:d8f50b1e384f 74
tecnosys 0:d8f50b1e384f 75
tecnosys 0:d8f50b1e384f 76 #define MCP_4MHz_125kBPS_CFG1 (MCP_4MHz_125kBPS_SJW | MCP_4MHz_125kBPS_BRP)
tecnosys 1:dbc44582f2f8 77 #define MCP_4MHz_125kBPS_CFG2 (MCP_4MHz_125kBPS_BLTMODE | MCP_4MHz_125kBPS_SAM | MCP_4MHz_125kBPS_PHSEG1 | MCP_4MHz_125kBPS_PRSEG)
tecnosys 1:dbc44582f2f8 78 #define MCP_4MHz_125kBPS_CFG3 (MCP_GENERAL_SOF | MCP_GENERAL_WAKFIL | MCP_4MHz_125kBPS_PHSEG)
tecnosys 0:d8f50b1e384f 79
tecnosys 0:d8f50b1e384f 80
tecnosys 0:d8f50b1e384f 81 /*-----------------------*/
tecnosys 0:d8f50b1e384f 82 /* 20 kBPS @ 4MHZ F_OSC */
tecnosys 0:d8f50b1e384f 83 /*-----------------------*/
tecnosys 0:d8f50b1e384f 84
tecnosys 0:d8f50b1e384f 85 /* CNF1 */
tecnosys 0:d8f50b1e384f 86
tecnosys 0:d8f50b1e384f 87 // SJW as defined in mcp_defs.h
tecnosys 0:d8f50b1e384f 88 // here: SJW = 1*TQ
tecnosys 0:d8f50b1e384f 89 #define MCP_4MHz_20kBPS_SJW (SJW1)
tecnosys 0:d8f50b1e384f 90
tecnosys 0:d8f50b1e384f 91 // Prescaler = (BRP+1)*2
tecnosys 0:d8f50b1e384f 92 // here Prescaler = 10 -> BRP=4 (20TQ)
tecnosys 0:d8f50b1e384f 93 #define MCP_4MHz_20kBPS_BRP (4)
tecnosys 0:d8f50b1e384f 94
tecnosys 0:d8f50b1e384f 95
tecnosys 0:d8f50b1e384f 96 /* CNF2 */
tecnosys 0:d8f50b1e384f 97
tecnosys 0:d8f50b1e384f 98 // BLT-Mode defined in CNF3 (0 or BTLMODE from mcp_defs.h)
tecnosys 0:d8f50b1e384f 99 #define MCP_4MHz_20kBPS_BLTMODE (BTLMODE)
tecnosys 0:d8f50b1e384f 100
tecnosys 0:d8f50b1e384f 101 // 3 samples (SAMPLE_1X) or 1 sample (SAMPLE_1X)
tecnosys 0:d8f50b1e384f 102 #define MCP_4MHz_20kBPS_SAM (SAMPLE_1X)
tecnosys 0:d8f50b1e384f 103
tecnosys 0:d8f50b1e384f 104 // (Phase Segment 1) PHSEG1 = PS1 - 1
tecnosys 0:d8f50b1e384f 105 // here: PS1 calculated as 8
tecnosys 0:d8f50b1e384f 106 #define MCP_4MHz_20kBPS_PHSEG1 ((8-1)<<3)
tecnosys 0:d8f50b1e384f 107
tecnosys 0:d8f50b1e384f 108 // (Propagation Delay) PRSEG = PRSEQTQ-1
tecnosys 0:d8f50b1e384f 109 // here PRSEQTQ = 3
tecnosys 0:d8f50b1e384f 110 #define MCP_4MHz_20kBPS_PRSEG (3-1)
tecnosys 0:d8f50b1e384f 111
tecnosys 0:d8f50b1e384f 112 /* CNF3 */
tecnosys 0:d8f50b1e384f 113
tecnosys 0:d8f50b1e384f 114 // (Phase Segment 2) PHSEG2 = PS2 - 1
tecnosys 0:d8f50b1e384f 115 // here: PS2 calculated as 8
tecnosys 0:d8f50b1e384f 116 #define MCP_4MHz_20kBPS_PHSEG (8-1)
tecnosys 0:d8f50b1e384f 117
tecnosys 0:d8f50b1e384f 118
tecnosys 0:d8f50b1e384f 119 #define MCP_4MHz_20kBPS_CFG1 (MCP_4MHz_20kBPS_SJW | MCP_4MHz_20kBPS_BRP)
tecnosys 1:dbc44582f2f8 120 #define MCP_4MHz_20kBPS_CFG2 (MCP_4MHz_20kBPS_BLTMODE | MCP_4MHz_20kBPS_SAM | MCP_4MHz_20kBPS_PHSEG1 | MCP_4MHz_20kBPS_PRSEG)
tecnosys 1:dbc44582f2f8 121 #define MCP_4MHz_20kBPS_CFG3 (MCP_GENERAL_SOF | MCP_GENERAL_WAKFIL | MCP_4MHz_20kBPS_PHSEG)