USBCDC - Port of Keils USBCDC example, compiles ok. Gets s…

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Jason Engelman / Mbed 2 deprecated USBCDC

Port of Keils USBCDC example, compiles ok. Gets stuck at init

serial.c@0:0b777ff85deb, 2010-07-05 (annotated)

Committer:: tecnosys
Date:: Mon Jul 05 10:16:57 2010 +0000
Revision:: 0:0b777ff85deb

Who changed what in which revision?

User	Revision	Line number	New contents of line
tecnosys	0:0b777ff85deb	1	/*----------------------------------------------------------------------------
tecnosys	0:0b777ff85deb	2	* Name: serial.c
tecnosys	0:0b777ff85deb	3	* Purpose: serial port handling for LPC17xx
tecnosys	0:0b777ff85deb	4	* Version: V1.20
tecnosys	0:0b777ff85deb	5	*----------------------------------------------------------------------------
tecnosys	0:0b777ff85deb	6	* This software is supplied "AS IS" without any warranties, express,
tecnosys	0:0b777ff85deb	7	* implied or statutory, including but not limited to the implied
tecnosys	0:0b777ff85deb	8	* warranties of fitness for purpose, satisfactory quality and
tecnosys	0:0b777ff85deb	9	* noninfringement. Keil extends you a royalty-free right to reproduce
tecnosys	0:0b777ff85deb	10	* and distribute executable files created using this software for use
tecnosys	0:0b777ff85deb	11	* on NXP Semiconductors LPC microcontroller devices only. Nothing else
tecnosys	0:0b777ff85deb	12	* gives you the right to use this software.
tecnosys	0:0b777ff85deb	13	*
tecnosys	0:0b777ff85deb	14	* Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
tecnosys	0:0b777ff85deb	15	---------------------------------------------------------------------------/
tecnosys	0:0b777ff85deb	16	#include "LPC17xx.h" // LPC17xx definitions
tecnosys	0:0b777ff85deb	17	//#include "LPC23xx.h"
tecnosys	0:0b777ff85deb	18	#include "type.h"
tecnosys	0:0b777ff85deb	19	#include "serial.h"
tecnosys	0:0b777ff85deb	20
tecnosys	0:0b777ff85deb	21	#include "compatible.h"
tecnosys	0:0b777ff85deb	22
tecnosys	0:0b777ff85deb	23	/*----------------------------------------------------------------------------
tecnosys	0:0b777ff85deb	24	Defines for ring buffers
tecnosys	0:0b777ff85deb	25	---------------------------------------------------------------------------/
tecnosys	0:0b777ff85deb	26	#define SER_BUF_SIZE (128) // serial buffer in bytes (power 2)
tecnosys	0:0b777ff85deb	27	#define SER_BUF_MASK (SER_BUF_SIZE-1ul) // buffer size mask
tecnosys	0:0b777ff85deb	28
tecnosys	0:0b777ff85deb	29	/* Buffer read / write macros */
tecnosys	0:0b777ff85deb	30	#define SER_BUF_RESET(serBuf) (serBuf.rdIdx = serBuf.wrIdx = 0)
tecnosys	0:0b777ff85deb	31	#define SER_BUF_WR(serBuf, dataIn) (serBuf.data[SER_BUF_MASK & serBuf.wrIdx++] = (dataIn))
tecnosys	0:0b777ff85deb	32	#define SER_BUF_RD(serBuf) (serBuf.data[SER_BUF_MASK & serBuf.rdIdx++])
tecnosys	0:0b777ff85deb	33	#define SER_BUF_EMPTY(serBuf) (serBuf.rdIdx == serBuf.wrIdx)
tecnosys	0:0b777ff85deb	34	#define SER_BUF_FULL(serBuf) (serBuf.rdIdx == serBuf.wrIdx+1)
tecnosys	0:0b777ff85deb	35	#define SER_BUF_COUNT(serBuf) (SER_BUF_MASK & (serBuf.wrIdx - serBuf.rdIdx))
tecnosys	0:0b777ff85deb	36
tecnosys	0:0b777ff85deb	37	// buffer type
tecnosys	0:0b777ff85deb	38	typedef struct __SER_BUF_T {
tecnosys	0:0b777ff85deb	39	unsigned char data[SER_BUF_SIZE];
tecnosys	0:0b777ff85deb	40	unsigned int wrIdx;
tecnosys	0:0b777ff85deb	41	unsigned int rdIdx;
tecnosys	0:0b777ff85deb	42	} SER_BUF_T;
tecnosys	0:0b777ff85deb	43
tecnosys	0:0b777ff85deb	44	unsigned long ser_txRestart; // NZ if TX restart is required
tecnosys	0:0b777ff85deb	45	unsigned short ser_lineState; // ((msr << 8) \| (lsr))
tecnosys	0:0b777ff85deb	46	SER_BUF_T ser_out; // Serial data buffers
tecnosys	0:0b777ff85deb	47	SER_BUF_T ser_in;
tecnosys	0:0b777ff85deb	48
tecnosys	0:0b777ff85deb	49	/*----------------------------------------------------------------------------
tecnosys	0:0b777ff85deb	50	open the serial port
tecnosys	0:0b777ff85deb	51	---------------------------------------------------------------------------/
tecnosys	0:0b777ff85deb	52	void ser_OpenPort (char portNum) {
tecnosys	0:0b777ff85deb	53
tecnosys	0:0b777ff85deb	54	if ( portNum == 0 )
tecnosys	0:0b777ff85deb	55	{
tecnosys	0:0b777ff85deb	56	/* Port 0 */
tecnosys	0:0b777ff85deb	57	NVIC_DisableIRQ(UART0_IRQn);
tecnosys	0:0b777ff85deb	58	LPC_PINCON->PINSEL0 &= ~0x000000F0;
tecnosys	0:0b777ff85deb	59	LPC_PINCON->PINSEL0 \|= 0x00000050; /* RxD0 is P0.3 and TxD0 is P0.2 */
tecnosys	0:0b777ff85deb	60	}
tecnosys	0:0b777ff85deb	61	else
tecnosys	0:0b777ff85deb	62	{
tecnosys	0:0b777ff85deb	63	/* Port 1 */
tecnosys	0:0b777ff85deb	64	NVIC_DisableIRQ(UART1_IRQn);
tecnosys	0:0b777ff85deb	65	LPC_PINCON->PINSEL4 &= ~0x0000000F;
tecnosys	0:0b777ff85deb	66	LPC_PINCON->PINSEL4 \|= 0x0000000A; /* Enable RxD1 P2.1, TxD1 P2.0 */
tecnosys	0:0b777ff85deb	67	}
tecnosys	0:0b777ff85deb	68	return;
tecnosys	0:0b777ff85deb	69	}
tecnosys	0:0b777ff85deb	70
tecnosys	0:0b777ff85deb	71	/*----------------------------------------------------------------------------
tecnosys	0:0b777ff85deb	72	close the serial port
tecnosys	0:0b777ff85deb	73	---------------------------------------------------------------------------/
tecnosys	0:0b777ff85deb	74	void ser_ClosePort (char portNum ) {
tecnosys	0:0b777ff85deb	75	if ( portNum == 0 )
tecnosys	0:0b777ff85deb	76	{
tecnosys	0:0b777ff85deb	77	/* POrt 0 */
tecnosys	0:0b777ff85deb	78	LPC_PINCON->PINSEL0 &= ~0x000000F0;
tecnosys	0:0b777ff85deb	79	/* Disable the interrupt in the VIC and UART controllers */
tecnosys	0:0b777ff85deb	80	LPC_UART0->IER = 0;
tecnosys	0:0b777ff85deb	81	NVIC_DisableIRQ(UART0_IRQn);
tecnosys	0:0b777ff85deb	82	}
tecnosys	0:0b777ff85deb	83	else
tecnosys	0:0b777ff85deb	84	{
tecnosys	0:0b777ff85deb	85	/* Port 1 */
tecnosys	0:0b777ff85deb	86	LPC_PINCON->PINSEL4 &= ~0x0000000F;
tecnosys	0:0b777ff85deb	87	/* Disable the interrupt in the VIC and UART controllers */
tecnosys	0:0b777ff85deb	88	LPC_UART1->IER = 0;
tecnosys	0:0b777ff85deb	89	NVIC_DisableIRQ(UART1_IRQn);
tecnosys	0:0b777ff85deb	90	}
tecnosys	0:0b777ff85deb	91	return;
tecnosys	0:0b777ff85deb	92	}
tecnosys	0:0b777ff85deb	93
tecnosys	0:0b777ff85deb	94	/*----------------------------------------------------------------------------
tecnosys	0:0b777ff85deb	95	initialize the serial port
tecnosys	0:0b777ff85deb	96	---------------------------------------------------------------------------/
tecnosys	0:0b777ff85deb	97	void ser_InitPort0 (unsigned long baudrate, unsigned int databits,
tecnosys	0:0b777ff85deb	98	unsigned int parity, unsigned int stopbits) {
tecnosys	0:0b777ff85deb	99
tecnosys	0:0b777ff85deb	100	unsigned char lcr_p, lcr_s, lcr_d;
tecnosys	0:0b777ff85deb	101	unsigned int dll;
tecnosys	0:0b777ff85deb	102	unsigned int pclkdiv, pclk;
tecnosys	0:0b777ff85deb	103
tecnosys	0:0b777ff85deb	104	switch (databits) {
tecnosys	0:0b777ff85deb	105	case 5: // 5 Data bits
tecnosys	0:0b777ff85deb	106	lcr_d = 0x00;
tecnosys	0:0b777ff85deb	107	break;
tecnosys	0:0b777ff85deb	108	case 6: // 6 Data bits
tecnosys	0:0b777ff85deb	109	lcr_d = 0x01;
tecnosys	0:0b777ff85deb	110	break;
tecnosys	0:0b777ff85deb	111	case 7: // 7 Data bits
tecnosys	0:0b777ff85deb	112	lcr_d = 0x02;
tecnosys	0:0b777ff85deb	113	break;
tecnosys	0:0b777ff85deb	114	case 8: // 8 Data bits
tecnosys	0:0b777ff85deb	115	default:
tecnosys	0:0b777ff85deb	116	lcr_d = 0x03;
tecnosys	0:0b777ff85deb	117	break;
tecnosys	0:0b777ff85deb	118	}
tecnosys	0:0b777ff85deb	119
tecnosys	0:0b777ff85deb	120	switch (stopbits) {
tecnosys	0:0b777ff85deb	121	case 1: // 1,5 Stop bits
tecnosys	0:0b777ff85deb	122	case 2: // 2 Stop bits
tecnosys	0:0b777ff85deb	123	lcr_s = 0x04;
tecnosys	0:0b777ff85deb	124	break;
tecnosys	0:0b777ff85deb	125	case 0: // 1 Stop bit
tecnosys	0:0b777ff85deb	126	default:
tecnosys	0:0b777ff85deb	127	lcr_s = 0x00;
tecnosys	0:0b777ff85deb	128	break;
tecnosys	0:0b777ff85deb	129	}
tecnosys	0:0b777ff85deb	130
tecnosys	0:0b777ff85deb	131	switch (parity) {
tecnosys	0:0b777ff85deb	132	case 1: // Parity Odd
tecnosys	0:0b777ff85deb	133	lcr_p = 0x08;
tecnosys	0:0b777ff85deb	134	break;
tecnosys	0:0b777ff85deb	135	case 2: // Parity Even
tecnosys	0:0b777ff85deb	136	lcr_p = 0x18;
tecnosys	0:0b777ff85deb	137	break;
tecnosys	0:0b777ff85deb	138	case 3: // Parity Mark
tecnosys	0:0b777ff85deb	139	lcr_p = 0x28;
tecnosys	0:0b777ff85deb	140	break;
tecnosys	0:0b777ff85deb	141	case 4: // Parity Space
tecnosys	0:0b777ff85deb	142	lcr_p = 0x38;
tecnosys	0:0b777ff85deb	143	break;
tecnosys	0:0b777ff85deb	144	case 0: // Parity None
tecnosys	0:0b777ff85deb	145	default:
tecnosys	0:0b777ff85deb	146	lcr_p = 0x00;
tecnosys	0:0b777ff85deb	147	break;
tecnosys	0:0b777ff85deb	148	}
tecnosys	0:0b777ff85deb	149
tecnosys	0:0b777ff85deb	150	SER_BUF_RESET(ser_out); // reset out buffer
tecnosys	0:0b777ff85deb	151	SER_BUF_RESET(ser_in); // reset in buffer
tecnosys	0:0b777ff85deb	152
tecnosys	0:0b777ff85deb	153	/* Bit 6~7 is for UART0 */
tecnosys	0:0b777ff85deb	154	pclkdiv = (LPC_SC->PCLKSEL0 >> 6) & 0x03;
tecnosys	0:0b777ff85deb	155
tecnosys	0:0b777ff85deb	156	switch ( pclkdiv )
tecnosys	0:0b777ff85deb	157	{
tecnosys	0:0b777ff85deb	158	case 0x00:
tecnosys	0:0b777ff85deb	159	default:
tecnosys	0:0b777ff85deb	160	pclk = SystemFrequency/4;
tecnosys	0:0b777ff85deb	161	break;
tecnosys	0:0b777ff85deb	162	case 0x01:
tecnosys	0:0b777ff85deb	163	pclk = SystemFrequency;
tecnosys	0:0b777ff85deb	164	break;
tecnosys	0:0b777ff85deb	165	case 0x02:
tecnosys	0:0b777ff85deb	166	pclk = SystemFrequency/2;
tecnosys	0:0b777ff85deb	167	break;
tecnosys	0:0b777ff85deb	168	case 0x03:
tecnosys	0:0b777ff85deb	169	pclk = SystemFrequency/8;
tecnosys	0:0b777ff85deb	170	break;
tecnosys	0:0b777ff85deb	171	}
tecnosys	0:0b777ff85deb	172
tecnosys	0:0b777ff85deb	173	dll = (pclk/16)/baudrate ; /baud rate /
tecnosys	0:0b777ff85deb	174	LPC_UART0->FDR = 0; // Fractional divider not used
tecnosys	0:0b777ff85deb	175	LPC_UART0->LCR = 0x80 \| lcr_d \| lcr_p \| lcr_s; // Data bits, Parity, Stop bit
tecnosys	0:0b777ff85deb	176	LPC_UART0->DLL = dll; // Baud Rate depending on PCLK
tecnosys	0:0b777ff85deb	177	LPC_UART0->DLM = (dll >> 8); // High divisor latch
tecnosys	0:0b777ff85deb	178	LPC_UART0->LCR = 0x00 \| lcr_d \| lcr_p \| lcr_s; // DLAB = 0
tecnosys	0:0b777ff85deb	179	LPC_UART0->IER = 0x03; // Enable TX/RX interrupts
tecnosys	0:0b777ff85deb	180
tecnosys	0:0b777ff85deb	181	LPC_UART0->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
tecnosys	0:0b777ff85deb	182	ser_txRestart = 1; // TX fifo is empty
tecnosys	0:0b777ff85deb	183
tecnosys	0:0b777ff85deb	184	/* Enable the UART Interrupt */
tecnosys	0:0b777ff85deb	185	NVIC_EnableIRQ(UART0_IRQn);
tecnosys	0:0b777ff85deb	186	return;
tecnosys	0:0b777ff85deb	187	}
tecnosys	0:0b777ff85deb	188
tecnosys	0:0b777ff85deb	189	/*----------------------------------------------------------------------------
tecnosys	0:0b777ff85deb	190	initialize the serial port
tecnosys	0:0b777ff85deb	191	---------------------------------------------------------------------------/
tecnosys	0:0b777ff85deb	192	void ser_InitPort1 (unsigned long baudrate, unsigned int databits,
tecnosys	0:0b777ff85deb	193	unsigned int parity, unsigned int stopbits) {
tecnosys	0:0b777ff85deb	194
tecnosys	0:0b777ff85deb	195	unsigned char lcr_p, lcr_s, lcr_d;
tecnosys	0:0b777ff85deb	196	unsigned int dll;
tecnosys	0:0b777ff85deb	197	unsigned int pclkdiv, pclk;
tecnosys	0:0b777ff85deb	198
tecnosys	0:0b777ff85deb	199	switch (databits) {
tecnosys	0:0b777ff85deb	200	case 5: // 5 Data bits
tecnosys	0:0b777ff85deb	201	lcr_d = 0x00;
tecnosys	0:0b777ff85deb	202	break;
tecnosys	0:0b777ff85deb	203	case 6: // 6 Data bits
tecnosys	0:0b777ff85deb	204	lcr_d = 0x01;
tecnosys	0:0b777ff85deb	205	break;
tecnosys	0:0b777ff85deb	206	case 7: // 7 Data bits
tecnosys	0:0b777ff85deb	207	lcr_d = 0x02;
tecnosys	0:0b777ff85deb	208	break;
tecnosys	0:0b777ff85deb	209	case 8: // 8 Data bits
tecnosys	0:0b777ff85deb	210	default:
tecnosys	0:0b777ff85deb	211	lcr_d = 0x03;
tecnosys	0:0b777ff85deb	212	break;
tecnosys	0:0b777ff85deb	213	}
tecnosys	0:0b777ff85deb	214
tecnosys	0:0b777ff85deb	215	switch (stopbits) {
tecnosys	0:0b777ff85deb	216	case 1: // 1,5 Stop bits
tecnosys	0:0b777ff85deb	217	case 2: // 2 Stop bits
tecnosys	0:0b777ff85deb	218	lcr_s = 0x04;
tecnosys	0:0b777ff85deb	219	break;
tecnosys	0:0b777ff85deb	220	case 0: // 1 Stop bit
tecnosys	0:0b777ff85deb	221	default:
tecnosys	0:0b777ff85deb	222	lcr_s = 0x00;
tecnosys	0:0b777ff85deb	223	break;
tecnosys	0:0b777ff85deb	224	}
tecnosys	0:0b777ff85deb	225
tecnosys	0:0b777ff85deb	226	switch (parity) {
tecnosys	0:0b777ff85deb	227	case 1: // Parity Odd
tecnosys	0:0b777ff85deb	228	lcr_p = 0x08;
tecnosys	0:0b777ff85deb	229	break;
tecnosys	0:0b777ff85deb	230	case 2: // Parity Even
tecnosys	0:0b777ff85deb	231	lcr_p = 0x18;
tecnosys	0:0b777ff85deb	232	break;
tecnosys	0:0b777ff85deb	233	case 3: // Parity Mark
tecnosys	0:0b777ff85deb	234	lcr_p = 0x28;
tecnosys	0:0b777ff85deb	235	break;
tecnosys	0:0b777ff85deb	236	case 4: // Parity Space
tecnosys	0:0b777ff85deb	237	lcr_p = 0x38;
tecnosys	0:0b777ff85deb	238	break;
tecnosys	0:0b777ff85deb	239	case 0: // Parity None
tecnosys	0:0b777ff85deb	240	default:
tecnosys	0:0b777ff85deb	241	lcr_p = 0x00;
tecnosys	0:0b777ff85deb	242	break;
tecnosys	0:0b777ff85deb	243	}
tecnosys	0:0b777ff85deb	244
tecnosys	0:0b777ff85deb	245	SER_BUF_RESET(ser_out); // reset out buffer
tecnosys	0:0b777ff85deb	246	SER_BUF_RESET(ser_in); // reset in buffer
tecnosys	0:0b777ff85deb	247
tecnosys	0:0b777ff85deb	248	/* Bit 8,9 are for UART1 */
tecnosys	0:0b777ff85deb	249	pclkdiv = (LPC_SC->PCLKSEL0 >> 8) & 0x03;
tecnosys	0:0b777ff85deb	250
tecnosys	0:0b777ff85deb	251	switch ( pclkdiv )
tecnosys	0:0b777ff85deb	252	{
tecnosys	0:0b777ff85deb	253	case 0x00:
tecnosys	0:0b777ff85deb	254	default:
tecnosys	0:0b777ff85deb	255	pclk = SystemFrequency/4;
tecnosys	0:0b777ff85deb	256	break;
tecnosys	0:0b777ff85deb	257	case 0x01:
tecnosys	0:0b777ff85deb	258	pclk = SystemFrequency;
tecnosys	0:0b777ff85deb	259	break;
tecnosys	0:0b777ff85deb	260	case 0x02:
tecnosys	0:0b777ff85deb	261	pclk = SystemFrequency/2;
tecnosys	0:0b777ff85deb	262	break;
tecnosys	0:0b777ff85deb	263	case 0x03:
tecnosys	0:0b777ff85deb	264	pclk = SystemFrequency/8;
tecnosys	0:0b777ff85deb	265	break;
tecnosys	0:0b777ff85deb	266	}
tecnosys	0:0b777ff85deb	267
tecnosys	0:0b777ff85deb	268	dll = (pclk/16)/baudrate ; /baud rate /
tecnosys	0:0b777ff85deb	269	LPC_UART1->FDR = 0; // Fractional divider not used
tecnosys	0:0b777ff85deb	270	LPC_UART1->LCR = 0x80 \| lcr_d \| lcr_p \| lcr_s; // Data bits, Parity, Stop bit
tecnosys	0:0b777ff85deb	271	LPC_UART1->DLL = dll; // Baud Rate depending on PCLK
tecnosys	0:0b777ff85deb	272	LPC_UART1->DLM = (dll >> 8); // High divisor latch
tecnosys	0:0b777ff85deb	273	LPC_UART1->LCR = 0x00 \| lcr_d \| lcr_p \| lcr_s; // DLAB = 0
tecnosys	0:0b777ff85deb	274	LPC_UART1->IER = 0x03; // Enable TX/RX interrupts
tecnosys	0:0b777ff85deb	275
tecnosys	0:0b777ff85deb	276	LPC_UART1->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
tecnosys	0:0b777ff85deb	277	ser_txRestart = 1; // TX fifo is empty
tecnosys	0:0b777ff85deb	278
tecnosys	0:0b777ff85deb	279	/* Enable the UART Interrupt */
tecnosys	0:0b777ff85deb	280	NVIC_EnableIRQ(UART1_IRQn);
tecnosys	0:0b777ff85deb	281	return;
tecnosys	0:0b777ff85deb	282	}
tecnosys	0:0b777ff85deb	283
tecnosys	0:0b777ff85deb	284	/*----------------------------------------------------------------------------
tecnosys	0:0b777ff85deb	285	read data from serial port
tecnosys	0:0b777ff85deb	286	---------------------------------------------------------------------------/
tecnosys	0:0b777ff85deb	287	int ser_Read (char buffer, const int length) {
tecnosys	0:0b777ff85deb	288	int bytesToRead, bytesRead;
tecnosys	0:0b777ff85deb	289
tecnosys	0:0b777ff85deb	290	/* Read length bytes, block if bytes are not avaialable */
tecnosys	0:0b777ff85deb	291	bytesToRead = *length;
tecnosys	0:0b777ff85deb	292	bytesToRead = (bytesToRead < (length)) ? bytesToRead : (length);
tecnosys	0:0b777ff85deb	293	bytesRead = bytesToRead;
tecnosys	0:0b777ff85deb	294
tecnosys	0:0b777ff85deb	295	while (bytesToRead--) {
tecnosys	0:0b777ff85deb	296	while (SER_BUF_EMPTY(ser_in)); // Block until data is available if none
tecnosys	0:0b777ff85deb	297	*buffer++ = SER_BUF_RD(ser_in);
tecnosys	0:0b777ff85deb	298	}
tecnosys	0:0b777ff85deb	299	return (bytesRead);
tecnosys	0:0b777ff85deb	300	}
tecnosys	0:0b777ff85deb	301
tecnosys	0:0b777ff85deb	302	/*----------------------------------------------------------------------------
tecnosys	0:0b777ff85deb	303	write data to the serial port
tecnosys	0:0b777ff85deb	304	---------------------------------------------------------------------------/
tecnosys	0:0b777ff85deb	305	int ser_Write (char portNum, const char buffer, int length) {
tecnosys	0:0b777ff85deb	306	int bytesToWrite, bytesWritten;
tecnosys	0:0b777ff85deb	307
tecnosys	0:0b777ff85deb	308	// Write *length bytes
tecnosys	0:0b777ff85deb	309	bytesToWrite = *length;
tecnosys	0:0b777ff85deb	310	bytesWritten = bytesToWrite;
tecnosys	0:0b777ff85deb	311
tecnosys	0:0b777ff85deb	312	while (!SER_BUF_EMPTY(ser_out)); // Block until space is available if none
tecnosys	0:0b777ff85deb	313	while (bytesToWrite) {
tecnosys	0:0b777ff85deb	314	SER_BUF_WR(ser_out, *buffer++); // Read Rx FIFO to buffer
tecnosys	0:0b777ff85deb	315	bytesToWrite--;
tecnosys	0:0b777ff85deb	316	}
tecnosys	0:0b777ff85deb	317
tecnosys	0:0b777ff85deb	318	if (ser_txRestart) {
tecnosys	0:0b777ff85deb	319	ser_txRestart = 0;
tecnosys	0:0b777ff85deb	320	if ( portNum == 0 )
tecnosys	0:0b777ff85deb	321	{
tecnosys	0:0b777ff85deb	322	LPC_UART0->THR = SER_BUF_RD(ser_out); // Write to the Tx Register
tecnosys	0:0b777ff85deb	323	}
tecnosys	0:0b777ff85deb	324	else
tecnosys	0:0b777ff85deb	325	{
tecnosys	0:0b777ff85deb	326	LPC_UART1->THR = SER_BUF_RD(ser_out); // Write to the Tx Register
tecnosys	0:0b777ff85deb	327	}
tecnosys	0:0b777ff85deb	328	}
tecnosys	0:0b777ff85deb	329
tecnosys	0:0b777ff85deb	330	return (bytesWritten);
tecnosys	0:0b777ff85deb	331	}
tecnosys	0:0b777ff85deb	332
tecnosys	0:0b777ff85deb	333	/*----------------------------------------------------------------------------
tecnosys	0:0b777ff85deb	334	check if character(s) are available at the serial interface
tecnosys	0:0b777ff85deb	335	---------------------------------------------------------------------------/
tecnosys	0:0b777ff85deb	336	void ser_AvailChar (int *availChar) {
tecnosys	0:0b777ff85deb	337
tecnosys	0:0b777ff85deb	338	*availChar = SER_BUF_COUNT(ser_in);
tecnosys	0:0b777ff85deb	339
tecnosys	0:0b777ff85deb	340	}
tecnosys	0:0b777ff85deb	341
tecnosys	0:0b777ff85deb	342	/*----------------------------------------------------------------------------
tecnosys	0:0b777ff85deb	343	read the line state of the serial port
tecnosys	0:0b777ff85deb	344	---------------------------------------------------------------------------/
tecnosys	0:0b777ff85deb	345	void ser_LineState (unsigned short *lineState) {
tecnosys	0:0b777ff85deb	346
tecnosys	0:0b777ff85deb	347	*lineState = ser_lineState;
tecnosys	0:0b777ff85deb	348	ser_lineState = 0;
tecnosys	0:0b777ff85deb	349
tecnosys	0:0b777ff85deb	350	}
tecnosys	0:0b777ff85deb	351
tecnosys	0:0b777ff85deb	352	/*----------------------------------------------------------------------------
tecnosys	0:0b777ff85deb	353	serial port 0 interrupt
tecnosys	0:0b777ff85deb	354	---------------------------------------------------------------------------/
tecnosys	0:0b777ff85deb	355	void UART0_IRQHandler(void)
tecnosys	0:0b777ff85deb	356	{
tecnosys	0:0b777ff85deb	357	volatile unsigned long iir;
tecnosys	0:0b777ff85deb	358
tecnosys	0:0b777ff85deb	359	iir = LPC_UART0->IIR;
tecnosys	0:0b777ff85deb	360
tecnosys	0:0b777ff85deb	361	if ((iir & 0x4) \|\| (iir & 0xC)) { // RDA or CTI pending
tecnosys	0:0b777ff85deb	362	while (LPC_UART0->LSR & 0x01) { // Rx FIFO is not empty
tecnosys	0:0b777ff85deb	363	SER_BUF_WR(ser_in, LPC_UART0->RBR); // Read Rx FIFO to buffer
tecnosys	0:0b777ff85deb	364	}
tecnosys	0:0b777ff85deb	365	}
tecnosys	0:0b777ff85deb	366	if ((iir & 0x2)) { // TXMIS pending
tecnosys	0:0b777ff85deb	367	if (SER_BUF_COUNT(ser_out) != 0) {
tecnosys	0:0b777ff85deb	368	LPC_UART0->THR = SER_BUF_RD(ser_out); // Write to the Tx FIFO
tecnosys	0:0b777ff85deb	369	ser_txRestart = 0;
tecnosys	0:0b777ff85deb	370	}
tecnosys	0:0b777ff85deb	371	else {
tecnosys	0:0b777ff85deb	372	ser_txRestart = 1;
tecnosys	0:0b777ff85deb	373	}
tecnosys	0:0b777ff85deb	374	}
tecnosys	0:0b777ff85deb	375	ser_lineState = LPC_UART0->LSR & 0x1E; // update linestate
tecnosys	0:0b777ff85deb	376	return;
tecnosys	0:0b777ff85deb	377	}
tecnosys	0:0b777ff85deb	378
tecnosys	0:0b777ff85deb	379	/*----------------------------------------------------------------------------
tecnosys	0:0b777ff85deb	380	serial port 1 interrupt
tecnosys	0:0b777ff85deb	381	---------------------------------------------------------------------------/
tecnosys	0:0b777ff85deb	382	void UART1_IRQHandler(void)
tecnosys	0:0b777ff85deb	383	{
tecnosys	0:0b777ff85deb	384	volatile unsigned long iir;
tecnosys	0:0b777ff85deb	385
tecnosys	0:0b777ff85deb	386	iir = LPC_UART1->IIR;
tecnosys	0:0b777ff85deb	387
tecnosys	0:0b777ff85deb	388	if ((iir & 0x4) \|\| (iir & 0xC)) { // RDA or CTI pending
tecnosys	0:0b777ff85deb	389	while (LPC_UART1->LSR & 0x01) { // Rx FIFO is not empty
tecnosys	0:0b777ff85deb	390	SER_BUF_WR(ser_in, LPC_UART1->RBR); // Read Rx FIFO to buffer
tecnosys	0:0b777ff85deb	391	}
tecnosys	0:0b777ff85deb	392	}
tecnosys	0:0b777ff85deb	393	if ((iir & 0x2)) { // TXMIS pending
tecnosys	0:0b777ff85deb	394	if (SER_BUF_COUNT(ser_out) != 0) {
tecnosys	0:0b777ff85deb	395	LPC_UART1->THR = SER_BUF_RD(ser_out); // Write to the Tx FIFO
tecnosys	0:0b777ff85deb	396	ser_txRestart = 0;
tecnosys	0:0b777ff85deb	397	}
tecnosys	0:0b777ff85deb	398	else {
tecnosys	0:0b777ff85deb	399	ser_txRestart = 1;
tecnosys	0:0b777ff85deb	400	}
tecnosys	0:0b777ff85deb	401	}
tecnosys	0:0b777ff85deb	402	ser_lineState = ((LPC_UART1->MSR<<8)\|LPC_UART1->LSR) & 0xE01E; // update linestate
tecnosys	0:0b777ff85deb	403	return;
tecnosys	0:0b777ff85deb	404	}
tecnosys	0:0b777ff85deb	405
tecnosys	0:0b777ff85deb	406

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	05 Jul 2010
Imports:	131
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	4

serial.c@0:0b777ff85deb, 2010-07-05 (annotated)

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