TASS Belgium / lpc1768-picotcp-eth

A PicoTCP driver for the lpc1768 mbed board

Dependents:   lpc1768-picotcp-demo TCPSocket_HelloWorld_PicoTCP Pico_TCP_UDP_Test TCPSocket_HelloWorld_PicoTCP ... more

pico_dev_mbed_emac_private.h@15:53fd77850eee, 2014-01-16 (annotated)

Committer:
tass
Date:
Thu Jan 16 14:21:58 2014 +0000
Revision:
15:53fd77850eee
Parent:
2:a8d9cf10e65a 
fixed warning unused variable

Who changed what in which revision?

UserRevisionLine numberNew contents of line
tass 0:b6a2ecc0d29e 1 /******************************************************************************
tass 0:b6a2ecc0d29e 2 PicoTCP. Copyright (c) 2012-2013 TASS Belgium NV. Some rights reserved.
tass 0:b6a2ecc0d29e 3 See LICENSE and COPYING for usage. https://github.com/tass-belgium/picotcp
tass 0:b6a2ecc0d29e 4
tass 0:b6a2ecc0d29e 5 This library is free software; you can redistribute it and/or
tass 0:b6a2ecc0d29e 6 modify it under the terms of the GNU General Public License Version 2
tass 0:b6a2ecc0d29e 7 as published by the Free Software Foundation;
tass 0:b6a2ecc0d29e 8
tass 0:b6a2ecc0d29e 9 Some of the code contained in this file is based on mbed.org
tass 0:b6a2ecc0d29e 10 mbed/libraries/mbed/vendor/NXP/capi/ethernet_api.c module,
tass 0:b6a2ecc0d29e 11 licensed under the Apache License, Version 2.0
tass 0:b6a2ecc0d29e 12 and is Copyright (c) 2006-2013 ARM Limited
tass 0:b6a2ecc0d29e 13
tass 0:b6a2ecc0d29e 14 Authors: Maxime Vincent, Andrei Carp
tass 0:b6a2ecc0d29e 15
tass 0:b6a2ecc0d29e 16 ******************************************************************************/
tass 0:b6a2ecc0d29e 17
tass 0:b6a2ecc0d29e 18 #ifndef __PICO_DEV_MBED_EMAC_PRIVATE_H
tass 0:b6a2ecc0d29e 19 #define __PICO_DEV_MBED_EMAC_PRIVATE_H
tass 0:b6a2ecc0d29e 20
tass 0:b6a2ecc0d29e 21 /***********
tass 0:b6a2ecc0d29e 22 * DEFINES *
tass 0:b6a2ecc0d29e 23 ***********/
tass 0:b6a2ecc0d29e 24
daniele 2:a8d9cf10e65a 25 #define EMAC_INTERRUPT_PRIORITY 0 /* the lower the number, the higher the priority */
tass 0:b6a2ecc0d29e 26
tass 0:b6a2ecc0d29e 27 /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
tass 0:b6a2ecc0d29e 28 #define NUM_RX_FRAG 3 /* Num.of RX Fragments 4*1536= 6.0kB */
daniele 2:a8d9cf10e65a 29 #define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */
tass 0:b6a2ecc0d29e 30 #define ETH_MAX_MTU 1536 /* Max. Ethernet Frame Size */
tass 0:b6a2ecc0d29e 31
tass 0:b6a2ecc0d29e 32 /* EMAC variables located in AHB SRAM bank 1*/
tass 0:b6a2ecc0d29e 33 #define ETH_AHB_RAM_BASE 0x20080000
tass 0:b6a2ecc0d29e 34 #define RX_DESC_BASE 0x20080000
tass 0:b6a2ecc0d29e 35 #define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)
tass 0:b6a2ecc0d29e 36 #define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)
tass 0:b6a2ecc0d29e 37 #define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)
tass 0:b6a2ecc0d29e 38 #define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4)
tass 0:b6a2ecc0d29e 39 #define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_MAX_MTU)
tass 0:b6a2ecc0d29e 40
tass 0:b6a2ecc0d29e 41 /* RX and TX descriptor and status definitions. */
tass 0:b6a2ecc0d29e 42 #define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i))
tass 0:b6a2ecc0d29e 43 #define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))
tass 0:b6a2ecc0d29e 44 #define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i))
tass 0:b6a2ecc0d29e 45 #define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))
tass 0:b6a2ecc0d29e 46 #define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i))
tass 0:b6a2ecc0d29e 47 #define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))
tass 0:b6a2ecc0d29e 48 #define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i))
tass 0:b6a2ecc0d29e 49 #define RX_BUF(i) (RX_BUF_BASE + ETH_MAX_MTU*i)
tass 0:b6a2ecc0d29e 50 #define TX_BUF(i) (TX_BUF_BASE + ETH_MAX_MTU*i)
tass 0:b6a2ecc0d29e 51
tass 0:b6a2ecc0d29e 52 /* MAC Configuration Register 1 */
tass 0:b6a2ecc0d29e 53 #define MAC1_REC_EN 0x00000001 /* Receive Enable */
tass 0:b6a2ecc0d29e 54 #define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */
tass 0:b6a2ecc0d29e 55 #define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */
tass 0:b6a2ecc0d29e 56 #define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */
tass 0:b6a2ecc0d29e 57 #define MAC1_LOOPB 0x00000010 /* Loop Back Mode */
tass 0:b6a2ecc0d29e 58 #define MAC1_RES_TX 0x00000100 /* Reset TX Logic */
tass 0:b6a2ecc0d29e 59 #define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */
tass 0:b6a2ecc0d29e 60 #define MAC1_RES_RX 0x00000400 /* Reset RX Logic */
tass 0:b6a2ecc0d29e 61 #define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */
tass 0:b6a2ecc0d29e 62 #define MAC1_SIM_RES 0x00004000 /* Simulation Reset */
tass 0:b6a2ecc0d29e 63 #define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */
tass 0:b6a2ecc0d29e 64
tass 0:b6a2ecc0d29e 65 /* MAC Configuration Register 2 */
tass 0:b6a2ecc0d29e 66 #define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */
tass 0:b6a2ecc0d29e 67 #define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */
tass 0:b6a2ecc0d29e 68 #define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */
tass 0:b6a2ecc0d29e 69 #define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */
tass 0:b6a2ecc0d29e 70 #define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */
tass 0:b6a2ecc0d29e 71 #define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */
tass 0:b6a2ecc0d29e 72 #define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */
tass 0:b6a2ecc0d29e 73 #define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */
tass 0:b6a2ecc0d29e 74 #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
tass 0:b6a2ecc0d29e 75 #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
tass 0:b6a2ecc0d29e 76 #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
tass 0:b6a2ecc0d29e 77 #define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
tass 0:b6a2ecc0d29e 78 #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
tass 0:b6a2ecc0d29e 79
tass 0:b6a2ecc0d29e 80 /* Back-to-Back Inter-Packet-Gap Register */
tass 0:b6a2ecc0d29e 81 #define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */
tass 0:b6a2ecc0d29e 82 #define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */
tass 0:b6a2ecc0d29e 83
tass 0:b6a2ecc0d29e 84 /* Non Back-to-Back Inter-Packet-Gap Register */
tass 0:b6a2ecc0d29e 85 #define IPGR_DEF 0x00000012 /* Recommended value */
tass 0:b6a2ecc0d29e 86
tass 0:b6a2ecc0d29e 87 /* Collision Window/Retry Register */
tass 0:b6a2ecc0d29e 88 #define CLRT_DEF 0x0000370F /* Default value */
tass 0:b6a2ecc0d29e 89
tass 0:b6a2ecc0d29e 90 /* PHY Support Register */
tass 0:b6a2ecc0d29e 91 #define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */
tass 0:b6a2ecc0d29e 92 #define SUPP_RES_RMII 0x00000000 /* Reset Reduced MII Logic */
tass 0:b6a2ecc0d29e 93
tass 0:b6a2ecc0d29e 94 /* Test Register */
tass 0:b6a2ecc0d29e 95 #define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */
tass 0:b6a2ecc0d29e 96 #define TEST_TST_PAUSE 0x00000002 /* Test Pause */
tass 0:b6a2ecc0d29e 97 #define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */
tass 0:b6a2ecc0d29e 98
tass 0:b6a2ecc0d29e 99 /* MII Management Configuration Register */
tass 0:b6a2ecc0d29e 100 #define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */
tass 0:b6a2ecc0d29e 101 #define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */
tass 0:b6a2ecc0d29e 102 #define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */
tass 0:b6a2ecc0d29e 103 #define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */
tass 0:b6a2ecc0d29e 104
tass 0:b6a2ecc0d29e 105 /* MII Management Command Register */
tass 0:b6a2ecc0d29e 106 #define MCMD_READ 0x00000001 /* MII Read */
tass 0:b6a2ecc0d29e 107 #define MCMD_SCAN 0x00000002 /* MII Scan continuously */
tass 0:b6a2ecc0d29e 108
tass 0:b6a2ecc0d29e 109 #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
tass 0:b6a2ecc0d29e 110 #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
tass 0:b6a2ecc0d29e 111
tass 0:b6a2ecc0d29e 112 /* MII Management Address Register */
tass 0:b6a2ecc0d29e 113 #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
tass 0:b6a2ecc0d29e 114 #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
tass 0:b6a2ecc0d29e 115
tass 0:b6a2ecc0d29e 116 /* MII Management Indicators Register */
tass 0:b6a2ecc0d29e 117 #define MIND_BUSY 0x00000001 /* MII is Busy */
tass 0:b6a2ecc0d29e 118 #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
tass 0:b6a2ecc0d29e 119 #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
tass 0:b6a2ecc0d29e 120 #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
tass 0:b6a2ecc0d29e 121
tass 0:b6a2ecc0d29e 122 /* Command Register */
tass 0:b6a2ecc0d29e 123 #define CR_RX_EN 0x00000001 /* Enable Receive */
tass 0:b6a2ecc0d29e 124 #define CR_TX_EN 0x00000002 /* Enable Transmit */
tass 0:b6a2ecc0d29e 125 #define CR_REG_RES 0x00000008 /* Reset Host Registers */
tass 0:b6a2ecc0d29e 126 #define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */
tass 0:b6a2ecc0d29e 127 #define CR_RX_RES 0x00000020 /* Reset Receive Datapath */
tass 0:b6a2ecc0d29e 128 #define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */
tass 0:b6a2ecc0d29e 129 #define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */
tass 0:b6a2ecc0d29e 130 #define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */
tass 0:b6a2ecc0d29e 131 #define CR_RMII 0x00000200 /* Reduced MII Interface */
tass 0:b6a2ecc0d29e 132 #define CR_FULL_DUP 0x00000400 /* Full Duplex */
tass 0:b6a2ecc0d29e 133
tass 0:b6a2ecc0d29e 134 /* Status Register */
tass 0:b6a2ecc0d29e 135 #define SR_RX_EN 0x00000001 /* Enable Receive */
tass 0:b6a2ecc0d29e 136 #define SR_TX_EN 0x00000002 /* Enable Transmit */
tass 0:b6a2ecc0d29e 137
tass 0:b6a2ecc0d29e 138 /* Transmit Status Vector 0 Register */
tass 0:b6a2ecc0d29e 139 #define TSV0_CRC_ERR 0x00000001 /* CRC error */
tass 0:b6a2ecc0d29e 140 #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */
tass 0:b6a2ecc0d29e 141 #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */
tass 0:b6a2ecc0d29e 142 #define TSV0_DONE 0x00000008 /* Tramsmission Completed */
tass 0:b6a2ecc0d29e 143 #define TSV0_MCAST 0x00000010 /* Multicast Destination */
tass 0:b6a2ecc0d29e 144 #define TSV0_BCAST 0x00000020 /* Broadcast Destination */
tass 0:b6a2ecc0d29e 145 #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
tass 0:b6a2ecc0d29e 146 #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
tass 0:b6a2ecc0d29e 147 #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
tass 0:b6a2ecc0d29e 148 #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
tass 0:b6a2ecc0d29e 149 #define TSV0_GIANT 0x00000400 /* Giant Frame */
tass 0:b6a2ecc0d29e 150 #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
tass 0:b6a2ecc0d29e 151 #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
tass 0:b6a2ecc0d29e 152 #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */
tass 0:b6a2ecc0d29e 153 #define TSV0_PAUSE 0x20000000 /* Pause Frame */
tass 0:b6a2ecc0d29e 154 #define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */
tass 0:b6a2ecc0d29e 155 #define TSV0_VLAN 0x80000000 /* VLAN Frame */
tass 0:b6a2ecc0d29e 156
tass 0:b6a2ecc0d29e 157 /* Transmit Status Vector 1 Register */
tass 0:b6a2ecc0d29e 158 #define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */
tass 0:b6a2ecc0d29e 159 #define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */
tass 0:b6a2ecc0d29e 160
tass 0:b6a2ecc0d29e 161 /* Receive Status Vector Register */
tass 0:b6a2ecc0d29e 162 #define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */
tass 0:b6a2ecc0d29e 163 #define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */
tass 0:b6a2ecc0d29e 164 #define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */
tass 0:b6a2ecc0d29e 165 #define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */
tass 0:b6a2ecc0d29e 166 #define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */
tass 0:b6a2ecc0d29e 167 #define RSV_CRC_ERR 0x00100000 /* CRC Error */
tass 0:b6a2ecc0d29e 168 #define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */
tass 0:b6a2ecc0d29e 169 #define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */
tass 0:b6a2ecc0d29e 170 #define RSV_REC_OK 0x00800000 /* Frame Received OK */
tass 0:b6a2ecc0d29e 171 #define RSV_MCAST 0x01000000 /* Multicast Frame */
tass 0:b6a2ecc0d29e 172 #define RSV_BCAST 0x02000000 /* Broadcast Frame */
tass 0:b6a2ecc0d29e 173 #define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */
tass 0:b6a2ecc0d29e 174 #define RSV_CTRL_FRAME 0x08000000 /* Control Frame */
tass 0:b6a2ecc0d29e 175 #define RSV_PAUSE 0x10000000 /* Pause Frame */
tass 0:b6a2ecc0d29e 176 #define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */
tass 0:b6a2ecc0d29e 177 #define RSV_VLAN 0x40000000 /* VLAN Frame */
tass 0:b6a2ecc0d29e 178
tass 0:b6a2ecc0d29e 179 /* Flow Control Counter Register */
tass 0:b6a2ecc0d29e 180 #define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */
tass 0:b6a2ecc0d29e 181 #define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */
tass 0:b6a2ecc0d29e 182
tass 0:b6a2ecc0d29e 183 /* Flow Control Status Register */
tass 0:b6a2ecc0d29e 184 #define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */
tass 0:b6a2ecc0d29e 185
tass 0:b6a2ecc0d29e 186 /* Receive Filter Control Register */
tass 0:b6a2ecc0d29e 187 #define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */
tass 0:b6a2ecc0d29e 188 #define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */
tass 0:b6a2ecc0d29e 189 #define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */
tass 0:b6a2ecc0d29e 190 #define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */
tass 0:b6a2ecc0d29e 191 #define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/
tass 0:b6a2ecc0d29e 192 #define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */
tass 0:b6a2ecc0d29e 193 #define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */
tass 0:b6a2ecc0d29e 194 #define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */
tass 0:b6a2ecc0d29e 195
tass 0:b6a2ecc0d29e 196 /* Receive Filter WoL Status/Clear Registers */
tass 0:b6a2ecc0d29e 197 #define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */
tass 0:b6a2ecc0d29e 198 #define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */
tass 0:b6a2ecc0d29e 199 #define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */
tass 0:b6a2ecc0d29e 200 #define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */
tass 0:b6a2ecc0d29e 201 #define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */
tass 0:b6a2ecc0d29e 202 #define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */
tass 0:b6a2ecc0d29e 203 #define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */
tass 0:b6a2ecc0d29e 204 #define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */
tass 0:b6a2ecc0d29e 205
tass 0:b6a2ecc0d29e 206 /* Interrupt Status/Enable/Clear/Set Registers */
tass 0:b6a2ecc0d29e 207 #define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */
tass 0:b6a2ecc0d29e 208 #define INT_RX_ERR 0x00000002 /* Receive Error */
tass 0:b6a2ecc0d29e 209 #define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */
tass 0:b6a2ecc0d29e 210 #define INT_RX_DONE 0x00000008 /* Receive Done */
tass 0:b6a2ecc0d29e 211 #define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */
tass 0:b6a2ecc0d29e 212 #define INT_TX_ERR 0x00000020 /* Transmit Error */
tass 0:b6a2ecc0d29e 213 #define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */
tass 0:b6a2ecc0d29e 214 #define INT_TX_DONE 0x00000080 /* Transmit Done */
tass 0:b6a2ecc0d29e 215 #define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */
tass 0:b6a2ecc0d29e 216 #define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */
tass 0:b6a2ecc0d29e 217
tass 0:b6a2ecc0d29e 218 /* Power Down Register */
tass 0:b6a2ecc0d29e 219 #define PD_POWER_DOWN 0x80000000 /* Power Down MAC */
tass 0:b6a2ecc0d29e 220
tass 0:b6a2ecc0d29e 221 /* RX Descriptor Control Word */
tass 0:b6a2ecc0d29e 222 #define RCTRL_SIZE 0x000007FF /* Buffer size mask */
tass 0:b6a2ecc0d29e 223 #define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */
tass 0:b6a2ecc0d29e 224
tass 0:b6a2ecc0d29e 225 /* RX Status Hash CRC Word */
tass 0:b6a2ecc0d29e 226 #define RHASH_SA 0x000001FF /* Hash CRC for Source Address */
tass 0:b6a2ecc0d29e 227 #define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */
tass 0:b6a2ecc0d29e 228
tass 0:b6a2ecc0d29e 229 /* RX Status Information Word */
tass 0:b6a2ecc0d29e 230 #define RINFO_SIZE 0x000007FF /* Data size in bytes */
tass 0:b6a2ecc0d29e 231 #define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */
tass 0:b6a2ecc0d29e 232 #define RINFO_VLAN 0x00080000 /* VLAN Frame */
tass 0:b6a2ecc0d29e 233 #define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */
tass 0:b6a2ecc0d29e 234 #define RINFO_MCAST 0x00200000 /* Multicast Frame */
tass 0:b6a2ecc0d29e 235 #define RINFO_BCAST 0x00400000 /* Broadcast Frame */
tass 0:b6a2ecc0d29e 236 #define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */
tass 0:b6a2ecc0d29e 237 #define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */
tass 0:b6a2ecc0d29e 238 #define RINFO_LEN_ERR 0x02000000 /* Length Error */
tass 0:b6a2ecc0d29e 239 #define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */
tass 0:b6a2ecc0d29e 240 #define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */
tass 0:b6a2ecc0d29e 241 #define RINFO_OVERRUN 0x10000000 /* Receive overrun */
tass 0:b6a2ecc0d29e 242 #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
tass 0:b6a2ecc0d29e 243 #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
tass 0:b6a2ecc0d29e 244 #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
tass 0:b6a2ecc0d29e 245
tass 0:b6a2ecc0d29e 246 #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \
tass 0:b6a2ecc0d29e 247 RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
tass 0:b6a2ecc0d29e 248
tass 0:b6a2ecc0d29e 249 /* TX Descriptor Control Word */
tass 0:b6a2ecc0d29e 250 #define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */
tass 0:b6a2ecc0d29e 251 #define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */
tass 0:b6a2ecc0d29e 252 #define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */
tass 0:b6a2ecc0d29e 253 #define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */
tass 0:b6a2ecc0d29e 254 #define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */
tass 0:b6a2ecc0d29e 255 #define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */
tass 0:b6a2ecc0d29e 256 #define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */
tass 0:b6a2ecc0d29e 257
tass 0:b6a2ecc0d29e 258 /* TX Status Information Word */
tass 0:b6a2ecc0d29e 259 #define TINFO_COL_CNT 0x01E00000 /* Collision Count */
tass 0:b6a2ecc0d29e 260 #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
tass 0:b6a2ecc0d29e 261 #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
tass 0:b6a2ecc0d29e 262 #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
tass 0:b6a2ecc0d29e 263 #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
tass 0:b6a2ecc0d29e 264 #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
tass 0:b6a2ecc0d29e 265 #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
tass 0:b6a2ecc0d29e 266 #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
tass 0:b6a2ecc0d29e 267
tass 0:b6a2ecc0d29e 268 /* ENET Device Revision ID */
tass 0:b6a2ecc0d29e 269 #define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */
tass 0:b6a2ecc0d29e 270
tass 0:b6a2ecc0d29e 271 /* DP83848C PHY Registers */
tass 0:b6a2ecc0d29e 272 #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
tass 0:b6a2ecc0d29e 273 #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
tass 0:b6a2ecc0d29e 274 #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
tass 0:b6a2ecc0d29e 275 #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
tass 0:b6a2ecc0d29e 276 #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
tass 0:b6a2ecc0d29e 277 #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
tass 0:b6a2ecc0d29e 278 #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
tass 0:b6a2ecc0d29e 279 #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
tass 0:b6a2ecc0d29e 280
tass 0:b6a2ecc0d29e 281 /* PHY Extended Registers */
tass 0:b6a2ecc0d29e 282 #define PHY_REG_STS 0x10 /* Status Register */
tass 0:b6a2ecc0d29e 283 #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
tass 0:b6a2ecc0d29e 284 #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
tass 0:b6a2ecc0d29e 285 #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
tass 0:b6a2ecc0d29e 286 #define PHY_REG_RECR 0x15 /* Receive Error Counter */
tass 0:b6a2ecc0d29e 287 #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
tass 0:b6a2ecc0d29e 288 #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
tass 0:b6a2ecc0d29e 289 #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
tass 0:b6a2ecc0d29e 290 #define PHY_REG_PHYCR 0x19 /* PHY Control Register */
tass 0:b6a2ecc0d29e 291 #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
tass 0:b6a2ecc0d29e 292 #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
tass 0:b6a2ecc0d29e 293 #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
tass 0:b6a2ecc0d29e 294
tass 0:b6a2ecc0d29e 295 #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
tass 0:b6a2ecc0d29e 296 #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
tass 0:b6a2ecc0d29e 297 #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
tass 0:b6a2ecc0d29e 298 #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
tass 0:b6a2ecc0d29e 299 #define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
tass 0:b6a2ecc0d29e 300
tass 0:b6a2ecc0d29e 301 #define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */
tass 0:b6a2ecc0d29e 302 #define DP83848C_ID 0x20005C90 /* PHY Identifier */
tass 0:b6a2ecc0d29e 303
tass 0:b6a2ecc0d29e 304 /** \brief DP83848 PHY status definitions */
tass 0:b6a2ecc0d29e 305 #define DP8_REMOTEFAULT (1 << 6) /**< Remote fault */
tass 0:b6a2ecc0d29e 306 #define DP8_FULLDUPLEX (1 << 2) /**< 1=full duplex */
tass 0:b6a2ecc0d29e 307 #define DP8_SPEED10MBPS (1 << 1) /**< 1=10MBps speed */
tass 0:b6a2ecc0d29e 308 #define DP8_VALID_LINK (1 << 0) /**< 1=Link active */
tass 0:b6a2ecc0d29e 309
tass 0:b6a2ecc0d29e 310 #define DISABLE_ETH_RX_INTERRUPT LPC_EMAC->IntEnable = LPC_EMAC->IntEnable & ~(INT_RX_DONE)
tass 0:b6a2ecc0d29e 311 #define ENABLE_ETH_RX_INTERRUPT LPC_EMAC->IntEnable = LPC_EMAC->IntEnable | (INT_RX_DONE)
tass 0:b6a2ecc0d29e 312
tass 0:b6a2ecc0d29e 313 #endif