LSM303DLHC library with Free Fall Interrupt Initialisation.
Fork of LSM303DLHC by
LSM303DLHC.cpp@7:1dabdf7beada, 2018-08-23 (annotated)
- Committer:
- tash1000
- Date:
- Thu Aug 23 18:47:32 2018 +0000
- Revision:
- 7:1dabdf7beada
- Parent:
- 6:0b1dad2f6270
V 1.1
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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bclaus | 3:4d9465e7e10e | 1 | /** LSM303DLHC Interface Library |
bclaus | 3:4d9465e7e10e | 2 | * |
bclaus | 3:4d9465e7e10e | 3 | * base on code by Michael Shimniok http://bot-thoughts.com |
bclaus | 3:4d9465e7e10e | 4 | * |
bclaus | 3:4d9465e7e10e | 5 | * and on test program by @tosihisa and |
bclaus | 3:4d9465e7e10e | 6 | * |
bclaus | 3:4d9465e7e10e | 7 | * and on Pololu sample library for LSM303DLHC breakout by ryantm: |
bclaus | 3:4d9465e7e10e | 8 | * |
bclaus | 3:4d9465e7e10e | 9 | * Copyright (c) 2011 Pololu Corporation. For more information, see |
bclaus | 3:4d9465e7e10e | 10 | * |
bclaus | 3:4d9465e7e10e | 11 | * http://www.pololu.com/ |
bclaus | 3:4d9465e7e10e | 12 | * http://forum.pololu.com/ |
bclaus | 3:4d9465e7e10e | 13 | * |
tash1000 | 6:0b1dad2f6270 | 14 | * FREE FALL INTERRUPT CODE ADDED BY TASOS CHARISIS |
tash1000 | 6:0b1dad2f6270 | 15 | * |
bclaus | 3:4d9465e7e10e | 16 | * Permission is hereby granted, free of charge, to any person |
bclaus | 3:4d9465e7e10e | 17 | * obtaining a copy of this software and associated documentation |
bclaus | 3:4d9465e7e10e | 18 | * files (the "Software"), to deal in the Software without |
bclaus | 3:4d9465e7e10e | 19 | * restriction, including without limitation the rights to use, |
bclaus | 3:4d9465e7e10e | 20 | * copy, modify, merge, publish, distribute, sublicense, and/or sell |
bclaus | 3:4d9465e7e10e | 21 | * copies of the Software, and to permit persons to whom the |
bclaus | 3:4d9465e7e10e | 22 | * Software is furnished to do so, subject to the following |
bclaus | 3:4d9465e7e10e | 23 | * conditions: |
bclaus | 3:4d9465e7e10e | 24 | * |
bclaus | 3:4d9465e7e10e | 25 | * The above copyright notice and this permission notice shall be |
bclaus | 3:4d9465e7e10e | 26 | * included in all copies or substantial portions of the Software. |
bclaus | 3:4d9465e7e10e | 27 | * |
bclaus | 3:4d9465e7e10e | 28 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
bclaus | 3:4d9465e7e10e | 29 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
bclaus | 3:4d9465e7e10e | 30 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
bclaus | 3:4d9465e7e10e | 31 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
bclaus | 3:4d9465e7e10e | 32 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, |
bclaus | 3:4d9465e7e10e | 33 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
bclaus | 3:4d9465e7e10e | 34 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
bclaus | 3:4d9465e7e10e | 35 | * OTHER DEALINGS IN THE SOFTWARE. |
bclaus | 3:4d9465e7e10e | 36 | */ |
bclaus | 3:4d9465e7e10e | 37 | #include "mbed.h" |
bclaus | 3:4d9465e7e10e | 38 | #include "LSM303DLHC.h" |
bclaus | 3:4d9465e7e10e | 39 | |
bclaus | 3:4d9465e7e10e | 40 | |
bclaus | 3:4d9465e7e10e | 41 | const int addr_acc = 0x32; |
bclaus | 3:4d9465e7e10e | 42 | const int addr_mag = 0x3c; |
bclaus | 3:4d9465e7e10e | 43 | |
bclaus | 3:4d9465e7e10e | 44 | enum REG_ADDRS { |
bclaus | 3:4d9465e7e10e | 45 | /* --- Mag --- */ |
bclaus | 3:4d9465e7e10e | 46 | CRA_REG_M = 0x00, |
bclaus | 3:4d9465e7e10e | 47 | CRB_REG_M = 0x01, |
bclaus | 3:4d9465e7e10e | 48 | MR_REG_M = 0x02, |
bclaus | 3:4d9465e7e10e | 49 | OUT_X_M = 0x03, |
bclaus | 3:4d9465e7e10e | 50 | OUT_Y_M = 0x05, |
bclaus | 3:4d9465e7e10e | 51 | OUT_Z_M = 0x07, |
bclaus | 3:4d9465e7e10e | 52 | /* --- Acc --- */ |
bclaus | 3:4d9465e7e10e | 53 | CTRL_REG1_A = 0x20, |
tash1000 | 6:0b1dad2f6270 | 54 | CTRL_REG3_A = 0x22, |
bclaus | 3:4d9465e7e10e | 55 | CTRL_REG4_A = 0x23, |
tash1000 | 6:0b1dad2f6270 | 56 | CTRL_REG5_A = 0x24, |
tash1000 | 6:0b1dad2f6270 | 57 | REFERENCE_A = 0x26, |
tash1000 | 6:0b1dad2f6270 | 58 | INT1_CFG_A = 0x30, |
tash1000 | 6:0b1dad2f6270 | 59 | INT1_THS_A = 0x32, |
tash1000 | 6:0b1dad2f6270 | 60 | INT1_DURATION_A = 0x33, |
bclaus | 3:4d9465e7e10e | 61 | OUT_X_A = 0x28, |
bclaus | 3:4d9465e7e10e | 62 | OUT_Y_A = 0x2A, |
bclaus | 3:4d9465e7e10e | 63 | OUT_Z_A = 0x2C, |
bclaus | 3:4d9465e7e10e | 64 | }; |
bclaus | 3:4d9465e7e10e | 65 | |
bclaus | 3:4d9465e7e10e | 66 | bool LSM303DLHC::write_reg(int addr_i2c,int addr_reg, char v) |
bclaus | 3:4d9465e7e10e | 67 | { |
bclaus | 3:4d9465e7e10e | 68 | char data[2] = {addr_reg, v}; |
bclaus | 3:4d9465e7e10e | 69 | return LSM303DLHC::_LSM303.write(addr_i2c, data, 2) == 0; |
bclaus | 3:4d9465e7e10e | 70 | } |
bclaus | 3:4d9465e7e10e | 71 | |
bclaus | 3:4d9465e7e10e | 72 | bool LSM303DLHC::read_reg(int addr_i2c,int addr_reg, char *v) |
bclaus | 3:4d9465e7e10e | 73 | { |
bclaus | 3:4d9465e7e10e | 74 | char data = addr_reg; |
bclaus | 3:4d9465e7e10e | 75 | bool result = false; |
bclaus | 3:4d9465e7e10e | 76 | |
bclaus | 3:4d9465e7e10e | 77 | __disable_irq(); |
bclaus | 3:4d9465e7e10e | 78 | if ((_LSM303.write(addr_i2c, &data, 1) == 0) && (_LSM303.read(addr_i2c, &data, 1) == 0)){ |
bclaus | 3:4d9465e7e10e | 79 | *v = data; |
bclaus | 3:4d9465e7e10e | 80 | result = true; |
bclaus | 3:4d9465e7e10e | 81 | } |
bclaus | 3:4d9465e7e10e | 82 | __enable_irq(); |
bclaus | 3:4d9465e7e10e | 83 | return result; |
bclaus | 3:4d9465e7e10e | 84 | } |
bclaus | 3:4d9465e7e10e | 85 | |
bclaus | 3:4d9465e7e10e | 86 | |
bclaus | 3:4d9465e7e10e | 87 | LSM303DLHC::LSM303DLHC(PinName sda, PinName scl): |
bclaus | 3:4d9465e7e10e | 88 | _LSM303(sda, scl) |
bclaus | 3:4d9465e7e10e | 89 | { |
bclaus | 3:4d9465e7e10e | 90 | char reg_v; |
bclaus | 5:ee458711d467 | 91 | _LSM303.frequency(200000); |
bclaus | 3:4d9465e7e10e | 92 | |
bclaus | 3:4d9465e7e10e | 93 | reg_v = 0; |
bclaus | 3:4d9465e7e10e | 94 | |
tash1000 | 6:0b1dad2f6270 | 95 | reg_v |= 0x57; /* Normal mode 100 Hz X/Y/Z axis enable. */ |
bclaus | 3:4d9465e7e10e | 96 | write_reg(addr_acc,CTRL_REG1_A,reg_v); |
bclaus | 3:4d9465e7e10e | 97 | |
bclaus | 3:4d9465e7e10e | 98 | reg_v = 0; |
bclaus | 3:4d9465e7e10e | 99 | // reg_v |= 0x01 << 6; /* 1: data MSB @ lower address */ |
tash1000 | 7:1dabdf7beada | 100 | reg_v = 0x01 << 4; /* +/- 4g */ |
bclaus | 3:4d9465e7e10e | 101 | write_reg(addr_acc,CTRL_REG4_A,reg_v); |
bclaus | 3:4d9465e7e10e | 102 | |
bclaus | 3:4d9465e7e10e | 103 | /* -- mag --- */ |
bclaus | 3:4d9465e7e10e | 104 | reg_v = 0; |
tash1000 | 6:0b1dad2f6270 | 105 | reg_v |= 0x06 << 2; /* Minimum magnetic data output rate = 75Hz */ |
bclaus | 3:4d9465e7e10e | 106 | write_reg(addr_mag,CRA_REG_M,reg_v); |
bclaus | 3:4d9465e7e10e | 107 | |
bclaus | 3:4d9465e7e10e | 108 | reg_v = 0; |
bclaus | 3:4d9465e7e10e | 109 | reg_v |= 0x01 << 5; /* +-1.3Gauss */ |
bclaus | 3:4d9465e7e10e | 110 | //reg_v |= 0x07 << 5; /* +-8.1Gauss */ |
bclaus | 3:4d9465e7e10e | 111 | write_reg(addr_mag,CRB_REG_M,reg_v); |
bclaus | 3:4d9465e7e10e | 112 | |
bclaus | 3:4d9465e7e10e | 113 | reg_v = 0; /* Continuous-conversion mode */ |
bclaus | 3:4d9465e7e10e | 114 | write_reg(addr_mag,MR_REG_M,reg_v); |
tash1000 | 6:0b1dad2f6270 | 115 | |
tash1000 | 6:0b1dad2f6270 | 116 | /** ------------------------FREE FALL INTERRUPT SETTINGS------------------------------------------- |
tash1000 | 6:0b1dad2f6270 | 117 | --------------------CALIBRATION VALUES ARE g THRESHOLD AND DURATION---------------------------------- |
tash1000 | 6:0b1dad2f6270 | 118 | **/ |
tash1000 | 6:0b1dad2f6270 | 119 | |
tash1000 | 6:0b1dad2f6270 | 120 | //Setup Free Fall INT as INT1 |
tash1000 | 6:0b1dad2f6270 | 121 | reg_v = 0x40; /* AOI1 interrupt on INT1 */ |
tash1000 | 6:0b1dad2f6270 | 122 | write_reg(addr_acc,CTRL_REG3_A,reg_v); |
tash1000 | 6:0b1dad2f6270 | 123 | |
tash1000 | 7:1dabdf7beada | 124 | reg_v = 0x64; /* 100 Counts --> 0.2g at +- 4g scale (2mg/LSB*/ |
tash1000 | 6:0b1dad2f6270 | 125 | write_reg(addr_acc,INT1_THS_A,reg_v); |
tash1000 | 6:0b1dad2f6270 | 126 | |
tash1000 | 6:0b1dad2f6270 | 127 | reg_v = 0x5; /* 5 Counts --> 50ms duration at 100Hz sampling */ |
tash1000 | 6:0b1dad2f6270 | 128 | write_reg(addr_acc,INT1_DURATION_A,reg_v); |
tash1000 | 6:0b1dad2f6270 | 129 | |
tash1000 | 6:0b1dad2f6270 | 130 | reg_v = 0x95; /* Enable AOI and low events not high on all axes */ |
tash1000 | 6:0b1dad2f6270 | 131 | write_reg(addr_acc,INT1_CFG_A,reg_v); |
bclaus | 3:4d9465e7e10e | 132 | } |
bclaus | 3:4d9465e7e10e | 133 | |
bclaus | 3:4d9465e7e10e | 134 | |
bclaus | 3:4d9465e7e10e | 135 | bool LSM303DLHC::read(float *ax, float *ay, float *az, float *mx, float *my, float *mz) { |
bclaus | 3:4d9465e7e10e | 136 | char acc[6], mag[6]; |
bclaus | 3:4d9465e7e10e | 137 | |
bclaus | 3:4d9465e7e10e | 138 | if (recv(addr_acc, OUT_X_A, acc, 6) && recv(addr_mag, OUT_X_M, mag, 6)) { |
bclaus | 3:4d9465e7e10e | 139 | *ax = float(short(acc[1] << 8 | acc[0]))/8192; //32768/4=8192 |
bclaus | 3:4d9465e7e10e | 140 | *ay = float(short(acc[3] << 8 | acc[2]))/8192; |
bclaus | 3:4d9465e7e10e | 141 | *az = float(short(acc[5] << 8 | acc[4]))/8192; |
bclaus | 3:4d9465e7e10e | 142 | //full scale magnetic readings are from -2048 to 2047 |
bclaus | 3:4d9465e7e10e | 143 | //gain is x,y =1100; z = 980 LSB/gauss |
bclaus | 3:4d9465e7e10e | 144 | *mx = float(short(mag[0] << 8 | mag[1]))/1100; |
bclaus | 3:4d9465e7e10e | 145 | *mz = float(short(mag[2] << 8 | mag[3]))/980; |
bclaus | 3:4d9465e7e10e | 146 | *my = float(short(mag[4] << 8 | mag[5]))/1100; |
bclaus | 3:4d9465e7e10e | 147 | |
tash1000 | 6:0b1dad2f6270 | 148 | return 1; |
bclaus | 3:4d9465e7e10e | 149 | } |
bclaus | 3:4d9465e7e10e | 150 | |
tash1000 | 6:0b1dad2f6270 | 151 | return 0; |
bclaus | 3:4d9465e7e10e | 152 | } |
bclaus | 3:4d9465e7e10e | 153 | |
bclaus | 3:4d9465e7e10e | 154 | |
bclaus | 3:4d9465e7e10e | 155 | bool LSM303DLHC::recv(char sad, char sub, char *buf, int length) { |
bclaus | 3:4d9465e7e10e | 156 | if (length > 1) sub |= 0x80; |
bclaus | 3:4d9465e7e10e | 157 | |
bclaus | 3:4d9465e7e10e | 158 | return _LSM303.write(sad, &sub, 1, true) == 0 && _LSM303.read(sad, buf, length) == 0; |
bclaus | 3:4d9465e7e10e | 159 | } |