Greg Steiert / pegasus_dev

Development mbed library for MAX32630FTHR

Dependents:   blinky_max32630fthr

hal/spi_api.h@3:1198227e6421, 2016-12-16 (annotated)

Committer:
switches
Date:
Fri Dec 16 16:27:57 2016 +0000
Revision:
3:1198227e6421
Parent:
0:5c4d7b2438d3 
Changed ADC scale for MAX32625 platforms to 1.2V full scale to match MAX32630 platforms

Who changed what in which revision?

UserRevisionLine numberNew contents of line
switches 0:5c4d7b2438d3 1
switches 0:5c4d7b2438d3 2 /** \addtogroup hal */
switches 0:5c4d7b2438d3 3 /** @{*/
switches 0:5c4d7b2438d3 4 /* mbed Microcontroller Library
switches 0:5c4d7b2438d3 5 * Copyright (c) 2006-2013 ARM Limited
switches 0:5c4d7b2438d3 6 *
switches 0:5c4d7b2438d3 7 * Licensed under the Apache License, Version 2.0 (the "License");
switches 0:5c4d7b2438d3 8 * you may not use this file except in compliance with the License.
switches 0:5c4d7b2438d3 9 * You may obtain a copy of the License at
switches 0:5c4d7b2438d3 10 *
switches 0:5c4d7b2438d3 11 * http://www.apache.org/licenses/LICENSE-2.0
switches 0:5c4d7b2438d3 12 *
switches 0:5c4d7b2438d3 13 * Unless required by applicable law or agreed to in writing, software
switches 0:5c4d7b2438d3 14 * distributed under the License is distributed on an "AS IS" BASIS,
switches 0:5c4d7b2438d3 15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
switches 0:5c4d7b2438d3 16 * See the License for the specific language governing permissions and
switches 0:5c4d7b2438d3 17 * limitations under the License.
switches 0:5c4d7b2438d3 18 */
switches 0:5c4d7b2438d3 19 #ifndef MBED_SPI_API_H
switches 0:5c4d7b2438d3 20 #define MBED_SPI_API_H
switches 0:5c4d7b2438d3 21
switches 0:5c4d7b2438d3 22 #include "device.h"
switches 0:5c4d7b2438d3 23 #include "hal/dma_api.h"
switches 0:5c4d7b2438d3 24 #include "hal/buffer.h"
switches 0:5c4d7b2438d3 25
switches 0:5c4d7b2438d3 26 #if DEVICE_SPI
switches 0:5c4d7b2438d3 27
switches 0:5c4d7b2438d3 28 #define SPI_EVENT_ERROR (1 << 1)
switches 0:5c4d7b2438d3 29 #define SPI_EVENT_COMPLETE (1 << 2)
switches 0:5c4d7b2438d3 30 #define SPI_EVENT_RX_OVERFLOW (1 << 3)
switches 0:5c4d7b2438d3 31 #define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
switches 0:5c4d7b2438d3 32
switches 0:5c4d7b2438d3 33 #define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred
switches 0:5c4d7b2438d3 34
switches 0:5c4d7b2438d3 35 #define SPI_FILL_WORD (0xFFFF)
switches 0:5c4d7b2438d3 36
switches 0:5c4d7b2438d3 37 #if DEVICE_SPI_ASYNCH
switches 0:5c4d7b2438d3 38 /** Asynch SPI HAL structure
switches 0:5c4d7b2438d3 39 */
switches 0:5c4d7b2438d3 40 typedef struct {
switches 0:5c4d7b2438d3 41 struct spi_s spi; /**< Target specific SPI structure */
switches 0:5c4d7b2438d3 42 struct buffer_s tx_buff; /**< Tx buffer */
switches 0:5c4d7b2438d3 43 struct buffer_s rx_buff; /**< Rx buffer */
switches 0:5c4d7b2438d3 44 } spi_t;
switches 0:5c4d7b2438d3 45
switches 0:5c4d7b2438d3 46 #else
switches 0:5c4d7b2438d3 47 /** Non-asynch SPI HAL structure
switches 0:5c4d7b2438d3 48 */
switches 0:5c4d7b2438d3 49 typedef struct spi_s spi_t;
switches 0:5c4d7b2438d3 50
switches 0:5c4d7b2438d3 51 #endif
switches 0:5c4d7b2438d3 52
switches 0:5c4d7b2438d3 53 #ifdef __cplusplus
switches 0:5c4d7b2438d3 54 extern "C" {
switches 0:5c4d7b2438d3 55 #endif
switches 0:5c4d7b2438d3 56
switches 0:5c4d7b2438d3 57 /**
switches 0:5c4d7b2438d3 58 * \defgroup hal_GeneralSPI SPI Configuration Functions
switches 0:5c4d7b2438d3 59 * @{
switches 0:5c4d7b2438d3 60 */
switches 0:5c4d7b2438d3 61
switches 0:5c4d7b2438d3 62 /** Initialize the SPI peripheral
switches 0:5c4d7b2438d3 63 *
switches 0:5c4d7b2438d3 64 * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
switches 0:5c4d7b2438d3 65 * @param[out] obj The SPI object to initialize
switches 0:5c4d7b2438d3 66 * @param[in] mosi The pin to use for MOSI
switches 0:5c4d7b2438d3 67 * @param[in] miso The pin to use for MISO
switches 0:5c4d7b2438d3 68 * @param[in] sclk The pin to use for SCLK
switches 0:5c4d7b2438d3 69 * @param[in] ssel The pin to use for SSEL
switches 0:5c4d7b2438d3 70 */
switches 0:5c4d7b2438d3 71 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
switches 0:5c4d7b2438d3 72
switches 0:5c4d7b2438d3 73 /** Release a SPI object
switches 0:5c4d7b2438d3 74 *
switches 0:5c4d7b2438d3 75 * TODO: spi_free is currently unimplemented
switches 0:5c4d7b2438d3 76 * This will require reference counting at the C++ level to be safe
switches 0:5c4d7b2438d3 77 *
switches 0:5c4d7b2438d3 78 * Return the pins owned by the SPI object to their reset state
switches 0:5c4d7b2438d3 79 * Disable the SPI peripheral
switches 0:5c4d7b2438d3 80 * Disable the SPI clock
switches 0:5c4d7b2438d3 81 * @param[in] obj The SPI object to deinitialize
switches 0:5c4d7b2438d3 82 */
switches 0:5c4d7b2438d3 83 void spi_free(spi_t *obj);
switches 0:5c4d7b2438d3 84
switches 0:5c4d7b2438d3 85 /** Configure the SPI format
switches 0:5c4d7b2438d3 86 *
switches 0:5c4d7b2438d3 87 * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
switches 0:5c4d7b2438d3 88 * The default bit order is MSB.
switches 0:5c4d7b2438d3 89 * @param[in,out] obj The SPI object to configure
switches 0:5c4d7b2438d3 90 * @param[in] bits The number of bits per frame
switches 0:5c4d7b2438d3 91 * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
switches 0:5c4d7b2438d3 92 * @param[in] slave Zero for master mode or non-zero for slave mode
switches 0:5c4d7b2438d3 93 */
switches 0:5c4d7b2438d3 94 void spi_format(spi_t *obj, int bits, int mode, int slave);
switches 0:5c4d7b2438d3 95
switches 0:5c4d7b2438d3 96 /** Set the SPI baud rate
switches 0:5c4d7b2438d3 97 *
switches 0:5c4d7b2438d3 98 * Actual frequency may differ from the desired frequency due to available dividers and bus clock
switches 0:5c4d7b2438d3 99 * Configures the SPI peripheral's baud rate
switches 0:5c4d7b2438d3 100 * @param[in,out] obj The SPI object to configure
switches 0:5c4d7b2438d3 101 * @param[in] hz The baud rate in Hz
switches 0:5c4d7b2438d3 102 */
switches 0:5c4d7b2438d3 103 void spi_frequency(spi_t *obj, int hz);
switches 0:5c4d7b2438d3 104
switches 0:5c4d7b2438d3 105 /**@}*/
switches 0:5c4d7b2438d3 106 /**
switches 0:5c4d7b2438d3 107 * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
switches 0:5c4d7b2438d3 108 * @{
switches 0:5c4d7b2438d3 109 */
switches 0:5c4d7b2438d3 110
switches 0:5c4d7b2438d3 111 /** Write a byte out in master mode and receive a value
switches 0:5c4d7b2438d3 112 *
switches 0:5c4d7b2438d3 113 * @param[in] obj The SPI peripheral to use for sending
switches 0:5c4d7b2438d3 114 * @param[in] value The value to send
switches 0:5c4d7b2438d3 115 * @return Returns the value received during send
switches 0:5c4d7b2438d3 116 */
switches 0:5c4d7b2438d3 117 int spi_master_write(spi_t *obj, int value);
switches 0:5c4d7b2438d3 118
switches 0:5c4d7b2438d3 119 /** Check if a value is available to read
switches 0:5c4d7b2438d3 120 *
switches 0:5c4d7b2438d3 121 * @param[in] obj The SPI peripheral to check
switches 0:5c4d7b2438d3 122 * @return non-zero if a value is available
switches 0:5c4d7b2438d3 123 */
switches 0:5c4d7b2438d3 124 int spi_slave_receive(spi_t *obj);
switches 0:5c4d7b2438d3 125
switches 0:5c4d7b2438d3 126 /** Get a received value out of the SPI receive buffer in slave mode
switches 0:5c4d7b2438d3 127 *
switches 0:5c4d7b2438d3 128 * Blocks until a value is available
switches 0:5c4d7b2438d3 129 * @param[in] obj The SPI peripheral to read
switches 0:5c4d7b2438d3 130 * @return The value received
switches 0:5c4d7b2438d3 131 */
switches 0:5c4d7b2438d3 132 int spi_slave_read(spi_t *obj);
switches 0:5c4d7b2438d3 133
switches 0:5c4d7b2438d3 134 /** Write a value to the SPI peripheral in slave mode
switches 0:5c4d7b2438d3 135 *
switches 0:5c4d7b2438d3 136 * Blocks until the SPI peripheral can be written to
switches 0:5c4d7b2438d3 137 * @param[in] obj The SPI peripheral to write
switches 0:5c4d7b2438d3 138 * @param[in] value The value to write
switches 0:5c4d7b2438d3 139 */
switches 0:5c4d7b2438d3 140 void spi_slave_write(spi_t *obj, int value);
switches 0:5c4d7b2438d3 141
switches 0:5c4d7b2438d3 142 /** Checks if the specified SPI peripheral is in use
switches 0:5c4d7b2438d3 143 *
switches 0:5c4d7b2438d3 144 * @param[in] obj The SPI peripheral to check
switches 0:5c4d7b2438d3 145 * @return non-zero if the peripheral is currently transmitting
switches 0:5c4d7b2438d3 146 */
switches 0:5c4d7b2438d3 147 int spi_busy(spi_t *obj);
switches 0:5c4d7b2438d3 148
switches 0:5c4d7b2438d3 149 /** Get the module number
switches 0:5c4d7b2438d3 150 *
switches 0:5c4d7b2438d3 151 * @param[in] obj The SPI peripheral to check
switches 0:5c4d7b2438d3 152 * @return The module number
switches 0:5c4d7b2438d3 153 */
switches 0:5c4d7b2438d3 154 uint8_t spi_get_module(spi_t *obj);
switches 0:5c4d7b2438d3 155
switches 0:5c4d7b2438d3 156 /**@}*/
switches 0:5c4d7b2438d3 157
switches 0:5c4d7b2438d3 158 #if DEVICE_SPI_ASYNCH
switches 0:5c4d7b2438d3 159 /**
switches 0:5c4d7b2438d3 160 * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
switches 0:5c4d7b2438d3 161 * @{
switches 0:5c4d7b2438d3 162 */
switches 0:5c4d7b2438d3 163
switches 0:5c4d7b2438d3 164 /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
switches 0:5c4d7b2438d3 165 *
switches 0:5c4d7b2438d3 166 * @param[in] obj The SPI object that holds the transfer information
switches 0:5c4d7b2438d3 167 * @param[in] tx The transmit buffer
switches 0:5c4d7b2438d3 168 * @param[in] tx_length The number of bytes to transmit
switches 0:5c4d7b2438d3 169 * @param[in] rx The receive buffer
switches 0:5c4d7b2438d3 170 * @param[in] rx_length The number of bytes to receive
switches 0:5c4d7b2438d3 171 * @param[in] bit_width The bit width of buffer words
switches 0:5c4d7b2438d3 172 * @param[in] event The logical OR of events to be registered
switches 0:5c4d7b2438d3 173 * @param[in] handler SPI interrupt handler
switches 0:5c4d7b2438d3 174 * @param[in] hint A suggestion for how to use DMA with this transfer
switches 0:5c4d7b2438d3 175 */
switches 0:5c4d7b2438d3 176 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
switches 0:5c4d7b2438d3 177
switches 0:5c4d7b2438d3 178 /** The asynchronous IRQ handler
switches 0:5c4d7b2438d3 179 *
switches 0:5c4d7b2438d3 180 * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
switches 0:5c4d7b2438d3 181 * conditions, such as buffer overflows or transfer complete.
switches 0:5c4d7b2438d3 182 * @param[in] obj The SPI object that holds the transfer information
switches 0:5c4d7b2438d3 183 * @return Event flags if a transfer termination condition was met; otherwise 0.
switches 0:5c4d7b2438d3 184 */
switches 0:5c4d7b2438d3 185 uint32_t spi_irq_handler_asynch(spi_t *obj);
switches 0:5c4d7b2438d3 186
switches 0:5c4d7b2438d3 187 /** Attempts to determine if the SPI peripheral is already in use
switches 0:5c4d7b2438d3 188 *
switches 0:5c4d7b2438d3 189 * If a temporary DMA channel has been allocated, peripheral is in use.
switches 0:5c4d7b2438d3 190 * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
switches 0:5c4d7b2438d3 191 * channel were allocated.
switches 0:5c4d7b2438d3 192 * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
switches 0:5c4d7b2438d3 193 * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
switches 0:5c4d7b2438d3 194 * there are any bytes in the FIFOs.
switches 0:5c4d7b2438d3 195 * @param[in] obj The SPI object to check for activity
switches 0:5c4d7b2438d3 196 * @return Non-zero if the SPI port is active or zero if it is not.
switches 0:5c4d7b2438d3 197 */
switches 0:5c4d7b2438d3 198 uint8_t spi_active(spi_t *obj);
switches 0:5c4d7b2438d3 199
switches 0:5c4d7b2438d3 200 /** Abort an SPI transfer
switches 0:5c4d7b2438d3 201 *
switches 0:5c4d7b2438d3 202 * @param obj The SPI peripheral to stop
switches 0:5c4d7b2438d3 203 */
switches 0:5c4d7b2438d3 204 void spi_abort_asynch(spi_t *obj);
switches 0:5c4d7b2438d3 205
switches 0:5c4d7b2438d3 206
switches 0:5c4d7b2438d3 207 #endif
switches 0:5c4d7b2438d3 208
switches 0:5c4d7b2438d3 209 /**@}*/
switches 0:5c4d7b2438d3 210
switches 0:5c4d7b2438d3 211 #ifdef __cplusplus
switches 0:5c4d7b2438d3 212 }
switches 0:5c4d7b2438d3 213 #endif // __cplusplus
switches 0:5c4d7b2438d3 214
switches 0:5c4d7b2438d3 215 #endif // SPI_DEVICE
switches 0:5c4d7b2438d3 216
switches 0:5c4d7b2438d3 217 #endif // MBED_SPI_API_H
switches 0:5c4d7b2438d3 218
switches 0:5c4d7b2438d3 219 /** @}*/