Greg Steiert / pegasus_dev

Development mbed library for MAX32630FTHR

Dependents:   blinky_max32630fthr

tools/export/codered_lpc824_cproject.tmpl@3:1198227e6421, 2016-12-16 (annotated)

Committer:
switches
Date:
Fri Dec 16 16:27:57 2016 +0000
Revision:
3:1198227e6421
Parent:
0:5c4d7b2438d3 
Changed ADC scale for MAX32625 platforms to 1.2V full scale to match MAX32630 platforms

Who changed what in which revision?

UserRevisionLine numberNew contents of line
switches 0:5c4d7b2438d3 1 {% extends "codered_cproject_cortexm0_common.tmpl" %}
switches 0:5c4d7b2438d3 2
switches 0:5c4d7b2438d3 3 {% block startup_file %}startup_LPC824_CR.cpp{% endblock %}
switches 0:5c4d7b2438d3 4
switches 0:5c4d7b2438d3 5 {% block cpu_config %}<?xml version="1.0" encoding="UTF-8"?>
switches 0:5c4d7b2438d3 6 <TargetConfig>
switches 0:5c4d7b2438d3 7 <Properties property_0="" property_2="LPC800_32.cfx" property_3="NXP" property_4="LPC824" property_count="5" version="70200"/>
switches 0:5c4d7b2438d3 8 <infoList vendor="NXP"><info chip="LPC824" flash_driver="LPC800_32.cfx" match_id="0x0" name="LPC824" stub="crt_emu_cm3_gen"><chip><name>LPC824</name>
switches 0:5c4d7b2438d3 9 <family>LPC82x</family>
switches 0:5c4d7b2438d3 10 <vendor>NXP (formerly Philips)</vendor>
switches 0:5c4d7b2438d3 11 <reset board="None" core="Real" sys="Real"/>
switches 0:5c4d7b2438d3 12 <clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/>
switches 0:5c4d7b2438d3 13 <memory can_program="true" id="Flash" is_ro="true" type="Flash"/>
switches 0:5c4d7b2438d3 14 <memory id="RAM" type="RAM"/>
switches 0:5c4d7b2438d3 15 <memory id="Periph" is_volatile="true" type="Peripheral"/>
switches 0:5c4d7b2438d3 16 <memoryInstance derived_from="Flash" id="MFlash32" location="0x0" size="0x8000"/>
switches 0:5c4d7b2438d3 17 <memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/>
switches 0:5c4d7b2438d3 18 <peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/>
switches 0:5c4d7b2438d3 19 <peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/>
switches 0:5c4d7b2438d3 20 <peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40000000"/>
switches 0:5c4d7b2438d3 21 <peripheralInstance derived_from="MRT" determined="infoFile" id="MRT" location="0x40004000"/>
switches 0:5c4d7b2438d3 22 <peripheralInstance derived_from="WKT" determined="infoFile" id="WKT" location="0x40008000"/>
switches 0:5c4d7b2438d3 23 <peripheralInstance derived_from="SWM" determined="infoFile" id="SWM" location="0x4000c000"/>
switches 0:5c4d7b2438d3 24 <peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/>
switches 0:5c4d7b2438d3 25 <peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40020000"/>
switches 0:5c4d7b2438d3 26 <peripheralInstance derived_from="CMP" determined="infoFile" id="CMP" location="0x40024000"/>
switches 0:5c4d7b2438d3 27 <peripheralInstance derived_from="DMATRIGMUX" determined="infoFile" id="DMATRIGMUX" location="0x40028000"/>
switches 0:5c4d7b2438d3 28 <peripheralInstance derived_from="INPUTMUX" determined="infoFile" id="INPUTMUX" location="0x4002c000"/>
switches 0:5c4d7b2438d3 29 <peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x40040000"/>
switches 0:5c4d7b2438d3 30 <peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/>
switches 0:5c4d7b2438d3 31 <peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/>
switches 0:5c4d7b2438d3 32 <peripheralInstance derived_from="I2C0" determined="infoFile" id="I2C0" location="0x40050000"/>
switches 0:5c4d7b2438d3 33 <peripheralInstance derived_from="I2C1" determined="infoFile" id="I2C1" location="0x40054000"/>
switches 0:5c4d7b2438d3 34 <peripheralInstance derived_from="SPI0" determined="infoFile" id="SPI0" location="0x40058000"/>
switches 0:5c4d7b2438d3 35 <peripheralInstance derived_from="SPI1" determined="infoFile" id="SPI1" location="0x4005c000"/>
switches 0:5c4d7b2438d3 36 <peripheralInstance derived_from="USART0" determined="infoFile" id="USART0" location="0x40064000"/>
switches 0:5c4d7b2438d3 37 <peripheralInstance derived_from="USART1" determined="infoFile" id="USART1" location="0x40068000"/>
switches 0:5c4d7b2438d3 38 <peripheralInstance derived_from="USART2" determined="infoFile" id="USART2" location="0x4006c000"/>
switches 0:5c4d7b2438d3 39 <peripheralInstance derived_from="I2C2" determined="infoFile" id="I2C2" location="0x40070000"/>
switches 0:5c4d7b2438d3 40 <peripheralInstance derived_from="I2C3" determined="infoFile" id="I2C3" location="0x40074000"/>
switches 0:5c4d7b2438d3 41 <peripheralInstance derived_from="CRC" determined="infoFile" id="CRC" location="0x50000000"/>
switches 0:5c4d7b2438d3 42 <peripheralInstance derived_from="SCT" determined="infoFile" id="SCT" location="0x50004000"/>
switches 0:5c4d7b2438d3 43 <peripheralInstance derived_from="DMA" determined="infoFile" id="DMA" location="0x50008000"/>
switches 0:5c4d7b2438d3 44 <peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0xa0000000"/>
switches 0:5c4d7b2438d3 45 <peripheralInstance derived_from="PIN-INT" determined="infoFile" id="PIN-INT" location="0xa0004000"/>
switches 0:5c4d7b2438d3 46 </chip>
switches 0:5c4d7b2438d3 47 <processor><name gcc_name="cortex-m0">Cortex-M0</name>
switches 0:5c4d7b2438d3 48 <family>Cortex-M</family>
switches 0:5c4d7b2438d3 49 </processor>
switches 0:5c4d7b2438d3 50 <link href="LPC82x_peripheral.xme" show="embed" type="simple"/>
switches 0:5c4d7b2438d3 51 </info>
switches 0:5c4d7b2438d3 52 </infoList>
switches 0:5c4d7b2438d3 53 </TargetConfig>{% endblock %}