Greg Steiert / pegasus_dev

Development mbed library for MAX32630FTHR

Dependents:   blinky_max32630fthr

tools/export/codered_lpc1768_cproject.tmpl@3:1198227e6421, 2016-12-16 (annotated)

Committer:
switches
Date:
Fri Dec 16 16:27:57 2016 +0000
Revision:
3:1198227e6421
Parent:
0:5c4d7b2438d3 
Changed ADC scale for MAX32625 platforms to 1.2V full scale to match MAX32630 platforms

Who changed what in which revision?

UserRevisionLine numberNew contents of line
switches 0:5c4d7b2438d3 1 {% extends "codered_cproject_cortexm3_common.tmpl" %}
switches 0:5c4d7b2438d3 2
switches 0:5c4d7b2438d3 3 {% block startup_file %}cr_startup_lpc176x.c{% endblock %}
switches 0:5c4d7b2438d3 4
switches 0:5c4d7b2438d3 5 {% block cpu_config %}<?xml version="1.0" encoding="UTF-8"?>
switches 0:5c4d7b2438d3 6 <TargetConfig>
switches 0:5c4d7b2438d3 7 <Properties property_0="" property_1="" property_2="" property_3="NXP" property_4="LPC1768" property_count="5" version="1"/>
switches 0:5c4d7b2438d3 8 <infoList vendor="NXP">
switches 0:5c4d7b2438d3 9 <info chip="LPC1768" match_id="0x00013f37,0x26013F37,0x26113F37" name="LPC1768" package="lpc17_lqfp100.xml">
switches 0:5c4d7b2438d3 10 <chip>
switches 0:5c4d7b2438d3 11 <name>LPC1768</name>
switches 0:5c4d7b2438d3 12 <family>LPC17xx</family>
switches 0:5c4d7b2438d3 13 <vendor>NXP (formerly Philips)</vendor>
switches 0:5c4d7b2438d3 14 <reset board="None" core="Real" sys="Real"/>
switches 0:5c4d7b2438d3 15 <clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/>
switches 0:5c4d7b2438d3 16 <memory can_program="true" id="Flash" is_ro="true" type="Flash"/>
switches 0:5c4d7b2438d3 17 <memory id="RAM" type="RAM"/>
switches 0:5c4d7b2438d3 18 <memory id="Periph" is_volatile="true" type="Peripheral"/>
switches 0:5c4d7b2438d3 19 <memoryInstance derived_from="Flash" id="MFlash512" location="0x00000000" size="0x80000"/>
switches 0:5c4d7b2438d3 20 <memoryInstance derived_from="RAM" id="RamLoc32" location="0x10000000" size="0x8000"/>
switches 0:5c4d7b2438d3 21 <memoryInstance derived_from="RAM" id="RamAHB32" location="0x2007c000" size="0x8000"/>
switches 0:5c4d7b2438d3 22 <prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/>
switches 0:5c4d7b2438d3 23 <prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/>
switches 0:5c4d7b2438d3 24 <peripheralInstance derived_from="LPC17_NVIC" determined="infoFile" id="NVIC" location="0xE000E000"/>
switches 0:5c4d7b2438d3 25 <peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM0&0x1" id="TIMER0" location="0x40004000"/>
switches 0:5c4d7b2438d3 26 <peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM1&0x1" id="TIMER1" location="0x40008000"/>
switches 0:5c4d7b2438d3 27 <peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM2&0x1" id="TIMER2" location="0x40090000"/>
switches 0:5c4d7b2438d3 28 <peripheralInstance derived_from="TIMER" determined="infoFile" enable="SYSCTL.PCONP.PCTIM3&0x1" id="TIMER3" location="0x40094000"/>
switches 0:5c4d7b2438d3 29 <peripheralInstance derived_from="LPC17_RIT" determined="infoFile" enable="SYSCTL.PCONP.PCRIT&0x1" id="RIT" location="0x400B0000"/>
switches 0:5c4d7b2438d3 30 <peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO0" location="0x2009C000"/>
switches 0:5c4d7b2438d3 31 <peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO1" location="0x2009C020"/>
switches 0:5c4d7b2438d3 32 <peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO2" location="0x2009C040"/>
switches 0:5c4d7b2438d3 33 <peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO3" location="0x2009C060"/>
switches 0:5c4d7b2438d3 34 <peripheralInstance derived_from="FGPIO" determined="infoFile" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO4" location="0x2009C080"/>
switches 0:5c4d7b2438d3 35 <peripheralInstance derived_from="LPC17_I2S" determined="infoFile" enable="SYSCTL.PCONP&0x08000000" id="I2S" location="0x400A8000"/>
switches 0:5c4d7b2438d3 36 <peripheralInstance derived_from="LPC17_SYSCTL" determined="infoFile" id="SYSCTL" location="0x400FC000"/>
switches 0:5c4d7b2438d3 37 <peripheralInstance derived_from="LPC17_DAC" determined="infoFile" enable="PCB.PINSEL1.P0_26&0x2=2" id="DAC" location="0x4008C000"/>
switches 0:5c4d7b2438d3 38 <peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART0&0x1" id="UART0" location="0x4000C000"/>
switches 0:5c4d7b2438d3 39 <peripheralInstance derived_from="LPC17xx_UART_MODEM" determined="infoFile" enable="SYSCTL.PCONP.PCUART1&0x1" id="UART1" location="0x40010000"/>
switches 0:5c4d7b2438d3 40 <peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART2&0x1" id="UART2" location="0x40098000"/>
switches 0:5c4d7b2438d3 41 <peripheralInstance derived_from="LPC17xx_UART" determined="infoFile" enable="SYSCTL.PCONP.PCUART3&0x1" id="UART3" location="0x4009C000"/>
switches 0:5c4d7b2438d3 42 <peripheralInstance derived_from="SPI" determined="infoFile" enable="SYSCTL.PCONP.PCSPI&0x1" id="SPI" location="0x40020000"/>
switches 0:5c4d7b2438d3 43 <peripheralInstance derived_from="LPC17_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP0&0x1" id="SSP0" location="0x40088000"/>
switches 0:5c4d7b2438d3 44 <peripheralInstance derived_from="LPC17_SSP" determined="infoFile" enable="SYSCTL.PCONP.PCSSP1&0x1" id="SSP1" location="0x40030000"/>
switches 0:5c4d7b2438d3 45 <peripheralInstance derived_from="LPC17_ADC" determined="infoFile" enable="SYSCTL.PCONP.PCAD&0x1" id="ADC" location="0x40034000"/>
switches 0:5c4d7b2438d3 46 <peripheralInstance derived_from="LPC17_USBINTST" determined="infoFile" enable="USBCLKCTL.USBClkCtrl&0x12" id="USBINTSTAT" location="0x400fc1c0"/>
switches 0:5c4d7b2438d3 47 <peripheralInstance derived_from="LPC17_USB_CLK_CTL" determined="infoFile" id="USBCLKCTL" location="0x5000cff4"/>
switches 0:5c4d7b2438d3 48 <peripheralInstance derived_from="LPC17_USBDEV" determined="infoFile" enable="USBCLKCTL.USBClkSt&0x12=0x12" id="USBDEV" location="0x5000C200"/>
switches 0:5c4d7b2438d3 49 <peripheralInstance derived_from="LPC17_PWM" determined="infoFile" enable="SYSCTL.PCONP.PWM1&0x1" id="PWM" location="0x40018000"/>
switches 0:5c4d7b2438d3 50 <peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C0&0x1" id="I2C0" location="0x4001C000"/>
switches 0:5c4d7b2438d3 51 <peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C1&0x1" id="I2C1" location="0x4005C000"/>
switches 0:5c4d7b2438d3 52 <peripheralInstance derived_from="LPC17_I2C" determined="infoFile" enable="SYSCTL.PCONP.PCI2C2&0x1" id="I2C2" location="0x400A0000"/>
switches 0:5c4d7b2438d3 53 <peripheralInstance derived_from="LPC17_DMA" determined="infoFile" enable="SYSCTL.PCONP.PCGPDMA&0x1" id="DMA" location="0x50004000"/>
switches 0:5c4d7b2438d3 54 <peripheralInstance derived_from="LPC17_ENET" determined="infoFile" enable="SYSCTL.PCONP.PCENET&0x1" id="ENET" location="0x50000000"/>
switches 0:5c4d7b2438d3 55 <peripheralInstance derived_from="CM3_DCR" determined="infoFile" id="DCR" location="0xE000EDF0"/>
switches 0:5c4d7b2438d3 56 <peripheralInstance derived_from="LPC17_PCB" determined="infoFile" id="PCB" location="0x4002c000"/>
switches 0:5c4d7b2438d3 57 <peripheralInstance derived_from="LPC17_QEI" determined="infoFile" enable="SYSCTL.PCONP.PCQEI&0x1" id="QEI" location="0x400bc000"/>
switches 0:5c4d7b2438d3 58 <peripheralInstance derived_from="LPC17_USBHOST" determined="infoFile" enable="USBCLKCTL.USBClkSt&0x11=0x11" id="USBHOST" location="0x5000C000"/>
switches 0:5c4d7b2438d3 59 <peripheralInstance derived_from="LPC17_USBOTG" determined="infoFile" enable="USBCLKCTL.USBClkSt&0x1c=0x1c" id="USBOTG" location="0x5000C000"/>
switches 0:5c4d7b2438d3 60 <peripheralInstance derived_from="LPC17_RTC" determined="infoFile" enable="SYSCTL.PCONP.PCRTC&0x1" id="RTC" location="0x40024000"/>
switches 0:5c4d7b2438d3 61 <peripheralInstance derived_from="MPU" determined="infoFile" id="MPU" location="0xE000ED90"/>
switches 0:5c4d7b2438d3 62 <peripheralInstance derived_from="LPC1x_WDT" determined="infoFile" id="WDT" location="0x40000000"/>
switches 0:5c4d7b2438d3 63 <peripheralInstance derived_from="LPC17_FLASHCFG" determined="infoFile" id="FLASHACCEL" location="0x400FC000"/>
switches 0:5c4d7b2438d3 64 <peripheralInstance derived_from="GPIO_INT" determined="infoFile" id="GPIOINTMAP" location="0x40028080"/>
switches 0:5c4d7b2438d3 65 <peripheralInstance derived_from="LPC17_CANAFR" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&0x1|SYSCTL.PCONP.PCCAN2&0x1" id="CANAFR" location="0x4003C000"/>
switches 0:5c4d7b2438d3 66 <peripheralInstance derived_from="LPC17_CANCEN" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&0x1|SYSCTL.PCONP.PCCAN2&0x1" id="CANCEN" location="0x40040000"/>
switches 0:5c4d7b2438d3 67 <peripheralInstance derived_from="LPC17_CANWAKESLEEP" determined="infoFile" id="CANWAKESLEEP" location="0x400FC110"/>
switches 0:5c4d7b2438d3 68 <peripheralInstance derived_from="LPC17_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN1&0x1" id="CANCON1" location="0x40044000"/>
switches 0:5c4d7b2438d3 69 <peripheralInstance derived_from="LPC17_CANCON" determined="infoFile" enable="SYSCTL.PCONP.PCCAN2&0x1" id="CANCON2" location="0x40048000"/>
switches 0:5c4d7b2438d3 70 <peripheralInstance derived_from="LPC17_MCPWM" determined="infoFile" enable="SYSCTL.PCONP.PCMCPWM&0x1" id="MCPWM" location="0x400B8000"/>
switches 0:5c4d7b2438d3 71 </chip>
switches 0:5c4d7b2438d3 72 <processor>
switches 0:5c4d7b2438d3 73 <name gcc_name="cortex-m3">Cortex-M3</name>
switches 0:5c4d7b2438d3 74 <family>Cortex-M</family>
switches 0:5c4d7b2438d3 75 </processor>
switches 0:5c4d7b2438d3 76 <link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/>
switches 0:5c4d7b2438d3 77 </info>
switches 0:5c4d7b2438d3 78 </infoList>
switches 0:5c4d7b2438d3 79 </TargetConfig>{% endblock %}