Greg Steiert / pegasus_dev

Development mbed library for MAX32630FTHR

Dependents:   blinky_max32630fthr

targets/TARGET_Maxim/TARGET_MAX32600/sleep.c@3:1198227e6421, 2016-12-16 (annotated)

Committer:
switches
Date:
Fri Dec 16 16:27:57 2016 +0000
Revision:
3:1198227e6421
Parent:
0:5c4d7b2438d3 
Changed ADC scale for MAX32625 platforms to 1.2V full scale to match MAX32630 platforms

Who changed what in which revision?

UserRevisionLine numberNew contents of line
switches 0:5c4d7b2438d3 1 /*******************************************************************************
switches 0:5c4d7b2438d3 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
switches 0:5c4d7b2438d3 3 *
switches 0:5c4d7b2438d3 4 * Permission is hereby granted, free of charge, to any person obtaining a
switches 0:5c4d7b2438d3 5 * copy of this software and associated documentation files (the "Software"),
switches 0:5c4d7b2438d3 6 * to deal in the Software without restriction, including without limitation
switches 0:5c4d7b2438d3 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
switches 0:5c4d7b2438d3 8 * and/or sell copies of the Software, and to permit persons to whom the
switches 0:5c4d7b2438d3 9 * Software is furnished to do so, subject to the following conditions:
switches 0:5c4d7b2438d3 10 *
switches 0:5c4d7b2438d3 11 * The above copyright notice and this permission notice shall be included
switches 0:5c4d7b2438d3 12 * in all copies or substantial portions of the Software.
switches 0:5c4d7b2438d3 13 *
switches 0:5c4d7b2438d3 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
switches 0:5c4d7b2438d3 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
switches 0:5c4d7b2438d3 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
switches 0:5c4d7b2438d3 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
switches 0:5c4d7b2438d3 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
switches 0:5c4d7b2438d3 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
switches 0:5c4d7b2438d3 20 * OTHER DEALINGS IN THE SOFTWARE.
switches 0:5c4d7b2438d3 21 *
switches 0:5c4d7b2438d3 22 * Except as contained in this notice, the name of Maxim Integrated
switches 0:5c4d7b2438d3 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
switches 0:5c4d7b2438d3 24 * Products, Inc. Branding Policy.
switches 0:5c4d7b2438d3 25 *
switches 0:5c4d7b2438d3 26 * The mere transfer of this software does not imply any licenses
switches 0:5c4d7b2438d3 27 * of trade secrets, proprietary technology, copyrights, patents,
switches 0:5c4d7b2438d3 28 * trademarks, maskwork rights, or any other form of intellectual
switches 0:5c4d7b2438d3 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
switches 0:5c4d7b2438d3 30 * ownership rights.
switches 0:5c4d7b2438d3 31 *******************************************************************************
switches 0:5c4d7b2438d3 32 */
switches 0:5c4d7b2438d3 33
switches 0:5c4d7b2438d3 34 #include "sleep_api.h"
switches 0:5c4d7b2438d3 35 #include "cmsis.h"
switches 0:5c4d7b2438d3 36 #include "pwrman_regs.h"
switches 0:5c4d7b2438d3 37 #include "pwrseq_regs.h"
switches 0:5c4d7b2438d3 38 #include "ioman_regs.h"
switches 0:5c4d7b2438d3 39 #include "rtc_regs.h"
switches 0:5c4d7b2438d3 40
switches 0:5c4d7b2438d3 41 static mxc_uart_regs_t *stdio_uart = (mxc_uart_regs_t*)STDIO_UART;
switches 0:5c4d7b2438d3 42
switches 0:5c4d7b2438d3 43 // Normal wait mode
switches 0:5c4d7b2438d3 44 void sleep(void)
switches 0:5c4d7b2438d3 45 {
switches 0:5c4d7b2438d3 46 // Normal sleep mode for ARM core
switches 0:5c4d7b2438d3 47 SCB->SCR = 0;
switches 0:5c4d7b2438d3 48
switches 0:5c4d7b2438d3 49 __DSB();
switches 0:5c4d7b2438d3 50 __WFI();
switches 0:5c4d7b2438d3 51 }
switches 0:5c4d7b2438d3 52
switches 0:5c4d7b2438d3 53 // Work-around for issue of clearing power sequencer I/O flag
switches 0:5c4d7b2438d3 54 static void clearAllGPIOWUD(void)
switches 0:5c4d7b2438d3 55 {
switches 0:5c4d7b2438d3 56 uint32_t wud_req0 = MXC_IOMAN->wud_req0;
switches 0:5c4d7b2438d3 57 uint32_t wud_req1 = MXC_IOMAN->wud_req1;
switches 0:5c4d7b2438d3 58
switches 0:5c4d7b2438d3 59 // I/O must be a wakeup detect to clear
switches 0:5c4d7b2438d3 60 MXC_IOMAN->wud_req0 = 0xffffffff;
switches 0:5c4d7b2438d3 61 MXC_IOMAN->wud_req1 = 0xffffffff;
switches 0:5c4d7b2438d3 62
switches 0:5c4d7b2438d3 63 // Clear all WUDs
switches 0:5c4d7b2438d3 64 MXC_PWRMAN->wud_ctrl = (MXC_E_PWRMAN_PAD_MODE_CLEAR_SET << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS) | MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL;
switches 0:5c4d7b2438d3 65 MXC_PWRMAN->wud_pulse0 = 1;
switches 0:5c4d7b2438d3 66
switches 0:5c4d7b2438d3 67 // Restore WUD requests
switches 0:5c4d7b2438d3 68 MXC_IOMAN->wud_req0 = wud_req0;
switches 0:5c4d7b2438d3 69 MXC_IOMAN->wud_req1 = wud_req1;
switches 0:5c4d7b2438d3 70 }
switches 0:5c4d7b2438d3 71
switches 0:5c4d7b2438d3 72 // Low-power stop mode
switches 0:5c4d7b2438d3 73 void deepsleep(void)
switches 0:5c4d7b2438d3 74 {
switches 0:5c4d7b2438d3 75 __disable_irq();
switches 0:5c4d7b2438d3 76
switches 0:5c4d7b2438d3 77 // Wait for all STDIO characters to be sent. The UART clock will stop.
switches 0:5c4d7b2438d3 78 while (stdio_uart->status & MXC_F_UART_STATUS_TX_BUSY);
switches 0:5c4d7b2438d3 79
switches 0:5c4d7b2438d3 80 // Prepare for LP1
switches 0:5c4d7b2438d3 81 uint32_t reg0 = MXC_PWRSEQ->reg0;
switches 0:5c4d7b2438d3 82 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP; // disable VDD3 SVM during sleep mode
switches 0:5c4d7b2438d3 83 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP; // disable VREG18 SVM during sleep mode
switches 0:5c4d7b2438d3 84 if (reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN) { // if real-time clock enabled during run
switches 0:5c4d7b2438d3 85 reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP; // enable real-time clock during sleep mode
switches 0:5c4d7b2438d3 86 } else {
switches 0:5c4d7b2438d3 87 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP; // disable real-time clock during sleep mode
switches 0:5c4d7b2438d3 88 }
switches 0:5c4d7b2438d3 89 reg0 |= MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP; // enable CHZY regulator during sleep mode
switches 0:5c4d7b2438d3 90 reg0 |= MXC_F_PWRSEQ_REG0_PWR_LP1; // go into LP1
switches 0:5c4d7b2438d3 91 reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT; // clear first boot flag
switches 0:5c4d7b2438d3 92 MXC_PWRSEQ->reg0 = reg0;
switches 0:5c4d7b2438d3 93
switches 0:5c4d7b2438d3 94 MXC_PWRSEQ->reg3 = (MXC_PWRSEQ->reg3 & ~MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK) | (3 << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS);
switches 0:5c4d7b2438d3 95
switches 0:5c4d7b2438d3 96 // Deep sleep for ARM core
switches 0:5c4d7b2438d3 97 SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
switches 0:5c4d7b2438d3 98
switches 0:5c4d7b2438d3 99 // clear latches for wakeup detect
switches 0:5c4d7b2438d3 100 MXC_PWRSEQ->flags = MXC_PWRSEQ->flags;
switches 0:5c4d7b2438d3 101 if (MXC_PWRSEQ->flags & MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP) {
switches 0:5c4d7b2438d3 102 // attempt work-around for I/O flag clearing issue
switches 0:5c4d7b2438d3 103 clearAllGPIOWUD();
switches 0:5c4d7b2438d3 104 MXC_PWRSEQ->flags = MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP;
switches 0:5c4d7b2438d3 105 }
switches 0:5c4d7b2438d3 106
switches 0:5c4d7b2438d3 107 // Wait for pending RTC transaction
switches 0:5c4d7b2438d3 108 while (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
switches 0:5c4d7b2438d3 109
switches 0:5c4d7b2438d3 110 // Ensure that the event register is clear
switches 0:5c4d7b2438d3 111 __SEV(); // set event
switches 0:5c4d7b2438d3 112 __WFE(); // clear event
switches 0:5c4d7b2438d3 113
switches 0:5c4d7b2438d3 114 // Enter LP1
switches 0:5c4d7b2438d3 115 __WFE();
switches 0:5c4d7b2438d3 116 // Woke up from LP1
switches 0:5c4d7b2438d3 117
switches 0:5c4d7b2438d3 118 // The RTC timer does not update until the next tick
switches 0:5c4d7b2438d3 119 uint32_t temp = MXC_RTCTMR->timer;
switches 0:5c4d7b2438d3 120 while (MXC_RTCTMR->timer == temp);
switches 0:5c4d7b2438d3 121
switches 0:5c4d7b2438d3 122 __enable_irq();
switches 0:5c4d7b2438d3 123 }