Greg Steiert / pegasus_dev

Development mbed library for MAX32630FTHR

Dependents:   blinky_max32630fthr

targets/TARGET_Maxim/TARGET_MAX32600/PeripheralPins.c@3:1198227e6421, 2016-12-16 (annotated)

Committer:
switches
Date:
Fri Dec 16 16:27:57 2016 +0000
Revision:
3:1198227e6421
Parent:
0:5c4d7b2438d3 
Changed ADC scale for MAX32625 platforms to 1.2V full scale to match MAX32630 platforms

Who changed what in which revision?

UserRevisionLine numberNew contents of line
switches 0:5c4d7b2438d3 1 /*******************************************************************************
switches 0:5c4d7b2438d3 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
switches 0:5c4d7b2438d3 3 *
switches 0:5c4d7b2438d3 4 * Permission is hereby granted, free of charge, to any person obtaining a
switches 0:5c4d7b2438d3 5 * copy of this software and associated documentation files (the "Software"),
switches 0:5c4d7b2438d3 6 * to deal in the Software without restriction, including without limitation
switches 0:5c4d7b2438d3 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
switches 0:5c4d7b2438d3 8 * and/or sell copies of the Software, and to permit persons to whom the
switches 0:5c4d7b2438d3 9 * Software is furnished to do so, subject to the following conditions:
switches 0:5c4d7b2438d3 10 *
switches 0:5c4d7b2438d3 11 * The above copyright notice and this permission notice shall be included
switches 0:5c4d7b2438d3 12 * in all copies or substantial portions of the Software.
switches 0:5c4d7b2438d3 13 *
switches 0:5c4d7b2438d3 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
switches 0:5c4d7b2438d3 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
switches 0:5c4d7b2438d3 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
switches 0:5c4d7b2438d3 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
switches 0:5c4d7b2438d3 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
switches 0:5c4d7b2438d3 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
switches 0:5c4d7b2438d3 20 * OTHER DEALINGS IN THE SOFTWARE.
switches 0:5c4d7b2438d3 21 *
switches 0:5c4d7b2438d3 22 * Except as contained in this notice, the name of Maxim Integrated
switches 0:5c4d7b2438d3 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
switches 0:5c4d7b2438d3 24 * Products, Inc. Branding Policy.
switches 0:5c4d7b2438d3 25 *
switches 0:5c4d7b2438d3 26 * The mere transfer of this software does not imply any licenses
switches 0:5c4d7b2438d3 27 * of trade secrets, proprietary technology, copyrights, patents,
switches 0:5c4d7b2438d3 28 * trademarks, maskwork rights, or any other form of intellectual
switches 0:5c4d7b2438d3 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
switches 0:5c4d7b2438d3 30 * ownership rights.
switches 0:5c4d7b2438d3 31 *******************************************************************************
switches 0:5c4d7b2438d3 32 */
switches 0:5c4d7b2438d3 33
switches 0:5c4d7b2438d3 34 #include "device.h"
switches 0:5c4d7b2438d3 35 #include "PeripheralPins.h"
switches 0:5c4d7b2438d3 36 #include "ioman_regs.h"
switches 0:5c4d7b2438d3 37
switches 0:5c4d7b2438d3 38 /*
switches 0:5c4d7b2438d3 39 * To select a peripheral function on Maxim microcontrollers, multiple
switches 0:5c4d7b2438d3 40 * configurations must be made. The mbed PinMap structure only includes one
switches 0:5c4d7b2438d3 41 * data member to hold this information. To extend the configuration storage,
switches 0:5c4d7b2438d3 42 * the "function" data member is used as a pointer to a pin_function_t
switches 0:5c4d7b2438d3 43 * structure. This structure is defined in objects.h. The definitions below
switches 0:5c4d7b2438d3 44 * include the creation of the pin_function_t structures and the assignment of
switches 0:5c4d7b2438d3 45 * the pointers to the "function" data members.
switches 0:5c4d7b2438d3 46 */
switches 0:5c4d7b2438d3 47
switches 0:5c4d7b2438d3 48 #ifdef TOOLCHAIN_ARM_STD
switches 0:5c4d7b2438d3 49 #pragma diag_suppress 1296
switches 0:5c4d7b2438d3 50 #endif
switches 0:5c4d7b2438d3 51
switches 0:5c4d7b2438d3 52 /************I2C***************/
switches 0:5c4d7b2438d3 53 const PinMap PinMap_I2C_SDA[] = {
switches 0:5c4d7b2438d3 54 { P2_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
switches 0:5c4d7b2438d3 55 { P2_6, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
switches 0:5c4d7b2438d3 56 { P1_6, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
switches 0:5c4d7b2438d3 57 { P2_2, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
switches 0:5c4d7b2438d3 58 { P7_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
switches 0:5c4d7b2438d3 59 { P7_6, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
switches 0:5c4d7b2438d3 60 { P7_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
switches 0:5c4d7b2438d3 61 { P7_6, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
switches 0:5c4d7b2438d3 62 { P0_4, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
switches 0:5c4d7b2438d3 63 { P0_6, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
switches 0:5c4d7b2438d3 64 { NC, NC, 0 }
switches 0:5c4d7b2438d3 65 };
switches 0:5c4d7b2438d3 66
switches 0:5c4d7b2438d3 67 const PinMap PinMap_I2C_SCL[] = {
switches 0:5c4d7b2438d3 68 { P2_5, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
switches 0:5c4d7b2438d3 69 { P2_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
switches 0:5c4d7b2438d3 70 { P1_7, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
switches 0:5c4d7b2438d3 71 { P2_3, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
switches 0:5c4d7b2438d3 72 { P7_5, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
switches 0:5c4d7b2438d3 73 { P7_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
switches 0:5c4d7b2438d3 74 { P7_5, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
switches 0:5c4d7b2438d3 75 { P7_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
switches 0:5c4d7b2438d3 76 { P0_5, I2C_0, (int)&((pin_function_t){&MXC_IOMAN->i2cm0_req, &MXC_IOMAN->i2cm0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
switches 0:5c4d7b2438d3 77 { P0_7, I2C_1, (int)&((pin_function_t){&MXC_IOMAN->i2cm1_req, &MXC_IOMAN->i2cm1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_I2CM_CORE_IO), (MXC_F_IOMAN_I2CM_MAPPING | MXC_F_IOMAN_I2CM_CORE_IO)}) },
switches 0:5c4d7b2438d3 78 { NC, NC, 0 }
switches 0:5c4d7b2438d3 79 };
switches 0:5c4d7b2438d3 80
switches 0:5c4d7b2438d3 81 /************UART***************/
switches 0:5c4d7b2438d3 82 const PinMap PinMap_UART_TX[] = {
switches 0:5c4d7b2438d3 83 { P1_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
switches 0:5c4d7b2438d3 84 { P1_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
switches 0:5c4d7b2438d3 85 { P2_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
switches 0:5c4d7b2438d3 86 { P2_5, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
switches 0:5c4d7b2438d3 87 { P7_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
switches 0:5c4d7b2438d3 88 { P7_3, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
switches 0:5c4d7b2438d3 89 { P0_1, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
switches 0:5c4d7b2438d3 90 { P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
switches 0:5c4d7b2438d3 91 { NC, NC, 0 }
switches 0:5c4d7b2438d3 92 };
switches 0:5c4d7b2438d3 93
switches 0:5c4d7b2438d3 94 const PinMap PinMap_UART_RX[] = {
switches 0:5c4d7b2438d3 95 { P1_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
switches 0:5c4d7b2438d3 96 { P1_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
switches 0:5c4d7b2438d3 97 { P2_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
switches 0:5c4d7b2438d3 98 { P2_4, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
switches 0:5c4d7b2438d3 99 { P7_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
switches 0:5c4d7b2438d3 100 { P7_2, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
switches 0:5c4d7b2438d3 101 { P0_0, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
switches 0:5c4d7b2438d3 102 { P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CORE_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CORE_IO)}) },
switches 0:5c4d7b2438d3 103 { NC, NC, 0 }
switches 0:5c4d7b2438d3 104 };
switches 0:5c4d7b2438d3 105
switches 0:5c4d7b2438d3 106 const PinMap PinMap_UART_CTS[] = {
switches 0:5c4d7b2438d3 107 { P1_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
switches 0:5c4d7b2438d3 108 { P2_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
switches 0:5c4d7b2438d3 109 { P1_4, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
switches 0:5c4d7b2438d3 110 { P1_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
switches 0:5c4d7b2438d3 111 { P7_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
switches 0:5c4d7b2438d3 112 { P7_6, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
switches 0:5c4d7b2438d3 113 { P0_2, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_CTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_CTS_IO)}) },
switches 0:5c4d7b2438d3 114 { NC, NC, 0 }
switches 0:5c4d7b2438d3 115 };
switches 0:5c4d7b2438d3 116
switches 0:5c4d7b2438d3 117 const PinMap PinMap_UART_RTS[] = {
switches 0:5c4d7b2438d3 118 { P1_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
switches 0:5c4d7b2438d3 119 { P2_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
switches 0:5c4d7b2438d3 120 { P1_5, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
switches 0:5c4d7b2438d3 121 { P1_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
switches 0:5c4d7b2438d3 122 { P7_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
switches 0:5c4d7b2438d3 123 { P7_7, UART_1, (int)&((pin_function_t){&MXC_IOMAN->uart1_req, &MXC_IOMAN->uart1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
switches 0:5c4d7b2438d3 124 { P0_3, UART_0, (int)&((pin_function_t){&MXC_IOMAN->uart0_req, &MXC_IOMAN->uart0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_D | MXC_F_IOMAN_UART_RTS_IO), (MXC_F_IOMAN_UART_MAPPING | MXC_F_IOMAN_UART_RTS_IO)}) },
switches 0:5c4d7b2438d3 125 { NC, NC, 0 }
switches 0:5c4d7b2438d3 126 };
switches 0:5c4d7b2438d3 127
switches 0:5c4d7b2438d3 128 /************SPI***************/
switches 0:5c4d7b2438d3 129 const PinMap PinMap_SPI_SCLK[] = {
switches 0:5c4d7b2438d3 130 { P0_0, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
switches 0:5c4d7b2438d3 131 { P0_4, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
switches 0:5c4d7b2438d3 132 { P2_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
switches 0:5c4d7b2438d3 133 { P1_0, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
switches 0:5c4d7b2438d3 134 { P2_4, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
switches 0:5c4d7b2438d3 135 { P2_0, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
switches 0:5c4d7b2438d3 136 { P6_0, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
switches 0:5c4d7b2438d3 137 { P6_4, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
switches 0:5c4d7b2438d3 138 { NC, NC, 0}
switches 0:5c4d7b2438d3 139 };
switches 0:5c4d7b2438d3 140
switches 0:5c4d7b2438d3 141 const PinMap PinMap_SPI_MOSI[] = {
switches 0:5c4d7b2438d3 142 { P0_1, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
switches 0:5c4d7b2438d3 143 { P0_5, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
switches 0:5c4d7b2438d3 144 { P2_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
switches 0:5c4d7b2438d3 145 { P1_1, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
switches 0:5c4d7b2438d3 146 { P2_5, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
switches 0:5c4d7b2438d3 147 { P2_1, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
switches 0:5c4d7b2438d3 148 { P6_1, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
switches 0:5c4d7b2438d3 149 { P6_5, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
switches 0:5c4d7b2438d3 150 { NC, NC, 0}
switches 0:5c4d7b2438d3 151 };
switches 0:5c4d7b2438d3 152
switches 0:5c4d7b2438d3 153 const PinMap PinMap_SPI_MISO[] = {
switches 0:5c4d7b2438d3 154 { P0_2, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
switches 0:5c4d7b2438d3 155 { P0_6, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
switches 0:5c4d7b2438d3 156 { P2_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
switches 0:5c4d7b2438d3 157 { P1_2, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
switches 0:5c4d7b2438d3 158 { P2_6, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
switches 0:5c4d7b2438d3 159 { P2_2, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
switches 0:5c4d7b2438d3 160 { P6_2, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
switches 0:5c4d7b2438d3 161 { P6_6, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_CORE_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_CORE_IO)}) },
switches 0:5c4d7b2438d3 162 { NC, NC, 0}
switches 0:5c4d7b2438d3 163 };
switches 0:5c4d7b2438d3 164
switches 0:5c4d7b2438d3 165 const PinMap PinMap_SPI_SSEL[] = {
switches 0:5c4d7b2438d3 166 #if (defined(EM9301_CSN) && (EM9301_CSN == P0_3))
switches 0:5c4d7b2438d3 167 { P0_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO)}) },
switches 0:5c4d7b2438d3 168 #else
switches 0:5c4d7b2438d3 169 { P0_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
switches 0:5c4d7b2438d3 170 #endif
switches 0:5c4d7b2438d3 171 { P0_7, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
switches 0:5c4d7b2438d3 172 { P2_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
switches 0:5c4d7b2438d3 173 { P1_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
switches 0:5c4d7b2438d3 174 { P2_7, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
switches 0:5c4d7b2438d3 175 #if (defined(EM9301_CSN) && (EM9301_CSN == P2_3))
switches 0:5c4d7b2438d3 176 { P2_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_A | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO | MXC_F_IOMAN_SPI_SR0_IO)}) },
switches 0:5c4d7b2438d3 177 #else
switches 0:5c4d7b2438d3 178 { P2_3, SPI_2, (int)&((pin_function_t){&MXC_IOMAN->spi2_req, &MXC_IOMAN->spi2_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_B | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
switches 0:5c4d7b2438d3 179 #endif
switches 0:5c4d7b2438d3 180 { P6_3, SPI_0, (int)&((pin_function_t){&MXC_IOMAN->spi0_req, &MXC_IOMAN->spi0_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
switches 0:5c4d7b2438d3 181 { P6_7, SPI_1, (int)&((pin_function_t){&MXC_IOMAN->spi1_req, &MXC_IOMAN->spi1_ack, ((uint32_t)MXC_E_IOMAN_MAPPING_C | MXC_F_IOMAN_SPI_SS0_IO), (MXC_F_IOMAN_SPI_MAPPING | MXC_F_IOMAN_SPI_SS0_IO)}) },
switches 0:5c4d7b2438d3 182 { NC, NC, 0}
switches 0:5c4d7b2438d3 183 };
switches 0:5c4d7b2438d3 184
switches 0:5c4d7b2438d3 185 /************PWM***************/
switches 0:5c4d7b2438d3 186 const PinMap PinMap_PWM[] = {
switches 0:5c4d7b2438d3 187 {P0_0, PWM_0, 1}, {P0_0, PWM_0, 2}, {P0_0, PWM_4, 3},
switches 0:5c4d7b2438d3 188 {P0_1, PWM_1, 1}, {P0_1, PWM_4, 2}, {P0_1, PWM_0, 3},
switches 0:5c4d7b2438d3 189 {P0_2, PWM_2, 1}, {P0_2, PWM_1, 2}, {P0_2, PWM_5, 3},
switches 0:5c4d7b2438d3 190 {P0_3, PWM_3, 1}, {P0_3, PWM_5, 2}, {P0_3, PWM_1, 3},
switches 0:5c4d7b2438d3 191 {P0_4, PWM_4, 1}, {P0_4, PWM_2, 2}, {P0_4, PWM_6, 3},
switches 0:5c4d7b2438d3 192 {P0_5, PWM_5, 1}, {P0_5, PWM_6, 2}, {P0_5, PWM_2, 3},
switches 0:5c4d7b2438d3 193 {P0_6, PWM_6, 1}, {P0_6, PWM_3, 2}, {P0_6, PWM_7, 3},
switches 0:5c4d7b2438d3 194 {P0_7, PWM_7, 1}, {P0_7, PWM_7, 2}, {P0_7, PWM_3, 3},
switches 0:5c4d7b2438d3 195
switches 0:5c4d7b2438d3 196 {P1_0, PWM_0, 1}, {P1_0, PWM_0, 2}, {P1_0, PWM_4, 3},
switches 0:5c4d7b2438d3 197 {P1_1, PWM_1, 1}, {P1_1, PWM_4, 2}, {P1_1, PWM_0, 3},
switches 0:5c4d7b2438d3 198 {P1_2, PWM_2, 1}, {P1_2, PWM_1, 2}, {P1_2, PWM_5, 3},
switches 0:5c4d7b2438d3 199 {P1_3, PWM_3, 1}, {P1_3, PWM_5, 2}, {P1_3, PWM_1, 3},
switches 0:5c4d7b2438d3 200 {P1_4, PWM_4, 1}, {P1_4, PWM_2, 2}, {P1_4, PWM_6, 3},
switches 0:5c4d7b2438d3 201 {P1_5, PWM_5, 1}, {P1_5, PWM_6, 2}, {P1_5, PWM_2, 3},
switches 0:5c4d7b2438d3 202 {P1_6, PWM_6, 1}, {P1_6, PWM_3, 2}, {P1_6, PWM_7, 3},
switches 0:5c4d7b2438d3 203 {P1_7, PWM_7, 1}, {P1_7, PWM_7, 2}, {P1_7, PWM_3, 3},
switches 0:5c4d7b2438d3 204
switches 0:5c4d7b2438d3 205 {P2_0, PWM_0, 1}, {P2_0, PWM_0, 2}, {P2_0, PWM_4, 3},
switches 0:5c4d7b2438d3 206 {P2_1, PWM_1, 1}, {P2_1, PWM_4, 2}, {P2_1, PWM_0, 3},
switches 0:5c4d7b2438d3 207 {P2_2, PWM_2, 1}, {P2_2, PWM_1, 2}, {P2_2, PWM_5, 3},
switches 0:5c4d7b2438d3 208 {P2_3, PWM_3, 1}, {P2_3, PWM_5, 2}, {P2_3, PWM_1, 3},
switches 0:5c4d7b2438d3 209 {P2_4, PWM_4, 1}, {P2_4, PWM_2, 2}, {P2_4, PWM_6, 3},
switches 0:5c4d7b2438d3 210 {P2_5, PWM_5, 1}, {P2_5, PWM_6, 2}, {P2_5, PWM_2, 3},
switches 0:5c4d7b2438d3 211 {P2_6, PWM_6, 1}, {P2_6, PWM_3, 2}, {P2_6, PWM_7, 3},
switches 0:5c4d7b2438d3 212 {P2_7, PWM_7, 1}, {P2_7, PWM_7, 2}, {P2_7, PWM_3, 3},
switches 0:5c4d7b2438d3 213
switches 0:5c4d7b2438d3 214 {P6_0, PWM_0, 1}, {P6_0, PWM_0, 2}, {P6_0, PWM_4, 3},
switches 0:5c4d7b2438d3 215 {P6_1, PWM_1, 1}, {P6_1, PWM_4, 2}, {P6_1, PWM_0, 3},
switches 0:5c4d7b2438d3 216 {P6_2, PWM_2, 1}, {P6_2, PWM_1, 2}, {P6_2, PWM_5, 3},
switches 0:5c4d7b2438d3 217 {P6_3, PWM_3, 1}, {P6_3, PWM_5, 2}, {P6_3, PWM_1, 3},
switches 0:5c4d7b2438d3 218 {P6_4, PWM_4, 1}, {P6_4, PWM_2, 2}, {P6_4, PWM_6, 3},
switches 0:5c4d7b2438d3 219 {P6_5, PWM_5, 1}, {P6_5, PWM_6, 2}, {P6_5, PWM_2, 3},
switches 0:5c4d7b2438d3 220 {P6_6, PWM_6, 1}, {P6_6, PWM_3, 2}, {P6_6, PWM_7, 3},
switches 0:5c4d7b2438d3 221 {P6_7, PWM_7, 1}, {P6_7, PWM_7, 2}, {P6_7, PWM_3, 3},
switches 0:5c4d7b2438d3 222
switches 0:5c4d7b2438d3 223 {P7_0, PWM_0, 1}, {P7_0, PWM_0, 2}, {P7_0, PWM_4, 3},
switches 0:5c4d7b2438d3 224 {P7_1, PWM_1, 1}, {P7_1, PWM_4, 2}, {P7_1, PWM_0, 3},
switches 0:5c4d7b2438d3 225 {P7_2, PWM_2, 1}, {P7_2, PWM_1, 2}, {P7_2, PWM_5, 3},
switches 0:5c4d7b2438d3 226 {P7_3, PWM_3, 1}, {P7_3, PWM_5, 2}, {P7_3, PWM_1, 3},
switches 0:5c4d7b2438d3 227 {P7_4, PWM_4, 1}, {P7_4, PWM_2, 2}, {P7_4, PWM_6, 3},
switches 0:5c4d7b2438d3 228 {P7_5, PWM_5, 1}, {P7_5, PWM_6, 2}, {P7_5, PWM_2, 3},
switches 0:5c4d7b2438d3 229 {P7_6, PWM_6, 1}, {P7_6, PWM_3, 2}, {P7_6, PWM_7, 3},
switches 0:5c4d7b2438d3 230 {P7_7, PWM_7, 1}, {P7_7, PWM_7, 2}, {P7_7, PWM_3, 3},
switches 0:5c4d7b2438d3 231
switches 0:5c4d7b2438d3 232 {NC, NC, 0}
switches 0:5c4d7b2438d3 233 };
switches 0:5c4d7b2438d3 234
switches 0:5c4d7b2438d3 235 /************ADC***************/
switches 0:5c4d7b2438d3 236 const PinMap PinMap_ADC[] = {
switches 0:5c4d7b2438d3 237 {AIN_0P, ADC, 0},
switches 0:5c4d7b2438d3 238 {AIN_1P, ADC, 0},
switches 0:5c4d7b2438d3 239 {AIN_2P, ADC, 0},
switches 0:5c4d7b2438d3 240 {AIN_3P, ADC, 0},
switches 0:5c4d7b2438d3 241 {AIN_4P, ADC, 0},
switches 0:5c4d7b2438d3 242 {AIN_5P, ADC, 0},
switches 0:5c4d7b2438d3 243 {AIN_6P, ADC, 0},
switches 0:5c4d7b2438d3 244 {AIN_7P, ADC, 0},
switches 0:5c4d7b2438d3 245
switches 0:5c4d7b2438d3 246 {AIN_0N, ADC, 0},
switches 0:5c4d7b2438d3 247 {AIN_1N, ADC, 0},
switches 0:5c4d7b2438d3 248 {AIN_2N, ADC, 0},
switches 0:5c4d7b2438d3 249 {AIN_3N, ADC, 0},
switches 0:5c4d7b2438d3 250 {AIN_4N, ADC, 0},
switches 0:5c4d7b2438d3 251 {AIN_5N, ADC, 0},
switches 0:5c4d7b2438d3 252 {AIN_6N, ADC, 0},
switches 0:5c4d7b2438d3 253 {AIN_7N, ADC, 0},
switches 0:5c4d7b2438d3 254
switches 0:5c4d7b2438d3 255 {AIN_0D, ADC, 1},
switches 0:5c4d7b2438d3 256 {AIN_1D, ADC, 1},
switches 0:5c4d7b2438d3 257 {AIN_2D, ADC, 1},
switches 0:5c4d7b2438d3 258 {AIN_3D, ADC, 1},
switches 0:5c4d7b2438d3 259 {AIN_4D, ADC, 1},
switches 0:5c4d7b2438d3 260 {AIN_5D, ADC, 1},
switches 0:5c4d7b2438d3 261 {AIN_6D, ADC, 1},
switches 0:5c4d7b2438d3 262 {AIN_7D, ADC, 1},
switches 0:5c4d7b2438d3 263 {NC, NC, 0}
switches 0:5c4d7b2438d3 264 };
switches 0:5c4d7b2438d3 265
switches 0:5c4d7b2438d3 266 /************DAC***************/
switches 0:5c4d7b2438d3 267 const PinMap PinMap_DAC[] = {
switches 0:5c4d7b2438d3 268 {AOUT_AO, DAC0, 0},
switches 0:5c4d7b2438d3 269 {AOUT_BO, DAC1, 0},
switches 0:5c4d7b2438d3 270 {AOUT_CO, DAC2, 0},
switches 0:5c4d7b2438d3 271 {AOUT_DO, DAC3, 0},
switches 0:5c4d7b2438d3 272 {NC, NC, 0}
switches 0:5c4d7b2438d3 273 };