Greg Steiert / maxim_dev

Maxim mbed development library

Dependents:   sensomed

cmsis/core_cmSimd.h@0:0e018d759a2a, 2016-11-08 (annotated)

Committer:
switches
Date:
Tue Nov 08 18:27:11 2016 +0000
Revision:
0:0e018d759a2a
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
switches 0:0e018d759a2a 1 /**************************************************************************//**
switches 0:0e018d759a2a 2 * @file core_cmSimd.h
switches 0:0e018d759a2a 3 * @brief CMSIS Cortex-M SIMD Header File
switches 0:0e018d759a2a 4 * @version V4.10
switches 0:0e018d759a2a 5 * @date 18. March 2015
switches 0:0e018d759a2a 6 *
switches 0:0e018d759a2a 7 * @note
switches 0:0e018d759a2a 8 *
switches 0:0e018d759a2a 9 ******************************************************************************/
switches 0:0e018d759a2a 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
switches 0:0e018d759a2a 11
switches 0:0e018d759a2a 12 All rights reserved.
switches 0:0e018d759a2a 13 Redistribution and use in source and binary forms, with or without
switches 0:0e018d759a2a 14 modification, are permitted provided that the following conditions are met:
switches 0:0e018d759a2a 15 - Redistributions of source code must retain the above copyright
switches 0:0e018d759a2a 16 notice, this list of conditions and the following disclaimer.
switches 0:0e018d759a2a 17 - Redistributions in binary form must reproduce the above copyright
switches 0:0e018d759a2a 18 notice, this list of conditions and the following disclaimer in the
switches 0:0e018d759a2a 19 documentation and/or other materials provided with the distribution.
switches 0:0e018d759a2a 20 - Neither the name of ARM nor the names of its contributors may be used
switches 0:0e018d759a2a 21 to endorse or promote products derived from this software without
switches 0:0e018d759a2a 22 specific prior written permission.
switches 0:0e018d759a2a 23 *
switches 0:0e018d759a2a 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
switches 0:0e018d759a2a 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
switches 0:0e018d759a2a 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
switches 0:0e018d759a2a 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
switches 0:0e018d759a2a 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
switches 0:0e018d759a2a 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
switches 0:0e018d759a2a 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
switches 0:0e018d759a2a 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
switches 0:0e018d759a2a 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
switches 0:0e018d759a2a 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
switches 0:0e018d759a2a 34 POSSIBILITY OF SUCH DAMAGE.
switches 0:0e018d759a2a 35 ---------------------------------------------------------------------------*/
switches 0:0e018d759a2a 36
switches 0:0e018d759a2a 37
switches 0:0e018d759a2a 38 #if defined ( __ICCARM__ )
switches 0:0e018d759a2a 39 #pragma system_include /* treat file as system include file for MISRA check */
switches 0:0e018d759a2a 40 #endif
switches 0:0e018d759a2a 41
switches 0:0e018d759a2a 42 #ifndef __CORE_CMSIMD_H
switches 0:0e018d759a2a 43 #define __CORE_CMSIMD_H
switches 0:0e018d759a2a 44
switches 0:0e018d759a2a 45 #ifdef __cplusplus
switches 0:0e018d759a2a 46 extern "C" {
switches 0:0e018d759a2a 47 #endif
switches 0:0e018d759a2a 48
switches 0:0e018d759a2a 49
switches 0:0e018d759a2a 50 /*******************************************************************************
switches 0:0e018d759a2a 51 * Hardware Abstraction Layer
switches 0:0e018d759a2a 52 ******************************************************************************/
switches 0:0e018d759a2a 53
switches 0:0e018d759a2a 54
switches 0:0e018d759a2a 55 /* ################### Compiler specific Intrinsics ########################### */
switches 0:0e018d759a2a 56 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
switches 0:0e018d759a2a 57 Access to dedicated SIMD instructions
switches 0:0e018d759a2a 58 @{
switches 0:0e018d759a2a 59 */
switches 0:0e018d759a2a 60
switches 0:0e018d759a2a 61 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
switches 0:0e018d759a2a 62 /* ARM armcc specific functions */
switches 0:0e018d759a2a 63 #define __SADD8 __sadd8
switches 0:0e018d759a2a 64 #define __QADD8 __qadd8
switches 0:0e018d759a2a 65 #define __SHADD8 __shadd8
switches 0:0e018d759a2a 66 #define __UADD8 __uadd8
switches 0:0e018d759a2a 67 #define __UQADD8 __uqadd8
switches 0:0e018d759a2a 68 #define __UHADD8 __uhadd8
switches 0:0e018d759a2a 69 #define __SSUB8 __ssub8
switches 0:0e018d759a2a 70 #define __QSUB8 __qsub8
switches 0:0e018d759a2a 71 #define __SHSUB8 __shsub8
switches 0:0e018d759a2a 72 #define __USUB8 __usub8
switches 0:0e018d759a2a 73 #define __UQSUB8 __uqsub8
switches 0:0e018d759a2a 74 #define __UHSUB8 __uhsub8
switches 0:0e018d759a2a 75 #define __SADD16 __sadd16
switches 0:0e018d759a2a 76 #define __QADD16 __qadd16
switches 0:0e018d759a2a 77 #define __SHADD16 __shadd16
switches 0:0e018d759a2a 78 #define __UADD16 __uadd16
switches 0:0e018d759a2a 79 #define __UQADD16 __uqadd16
switches 0:0e018d759a2a 80 #define __UHADD16 __uhadd16
switches 0:0e018d759a2a 81 #define __SSUB16 __ssub16
switches 0:0e018d759a2a 82 #define __QSUB16 __qsub16
switches 0:0e018d759a2a 83 #define __SHSUB16 __shsub16
switches 0:0e018d759a2a 84 #define __USUB16 __usub16
switches 0:0e018d759a2a 85 #define __UQSUB16 __uqsub16
switches 0:0e018d759a2a 86 #define __UHSUB16 __uhsub16
switches 0:0e018d759a2a 87 #define __SASX __sasx
switches 0:0e018d759a2a 88 #define __QASX __qasx
switches 0:0e018d759a2a 89 #define __SHASX __shasx
switches 0:0e018d759a2a 90 #define __UASX __uasx
switches 0:0e018d759a2a 91 #define __UQASX __uqasx
switches 0:0e018d759a2a 92 #define __UHASX __uhasx
switches 0:0e018d759a2a 93 #define __SSAX __ssax
switches 0:0e018d759a2a 94 #define __QSAX __qsax
switches 0:0e018d759a2a 95 #define __SHSAX __shsax
switches 0:0e018d759a2a 96 #define __USAX __usax
switches 0:0e018d759a2a 97 #define __UQSAX __uqsax
switches 0:0e018d759a2a 98 #define __UHSAX __uhsax
switches 0:0e018d759a2a 99 #define __USAD8 __usad8
switches 0:0e018d759a2a 100 #define __USADA8 __usada8
switches 0:0e018d759a2a 101 #define __SSAT16 __ssat16
switches 0:0e018d759a2a 102 #define __USAT16 __usat16
switches 0:0e018d759a2a 103 #define __UXTB16 __uxtb16
switches 0:0e018d759a2a 104 #define __UXTAB16 __uxtab16
switches 0:0e018d759a2a 105 #define __SXTB16 __sxtb16
switches 0:0e018d759a2a 106 #define __SXTAB16 __sxtab16
switches 0:0e018d759a2a 107 #define __SMUAD __smuad
switches 0:0e018d759a2a 108 #define __SMUADX __smuadx
switches 0:0e018d759a2a 109 #define __SMLAD __smlad
switches 0:0e018d759a2a 110 #define __SMLADX __smladx
switches 0:0e018d759a2a 111 #define __SMLALD __smlald
switches 0:0e018d759a2a 112 #define __SMLALDX __smlaldx
switches 0:0e018d759a2a 113 #define __SMUSD __smusd
switches 0:0e018d759a2a 114 #define __SMUSDX __smusdx
switches 0:0e018d759a2a 115 #define __SMLSD __smlsd
switches 0:0e018d759a2a 116 #define __SMLSDX __smlsdx
switches 0:0e018d759a2a 117 #define __SMLSLD __smlsld
switches 0:0e018d759a2a 118 #define __SMLSLDX __smlsldx
switches 0:0e018d759a2a 119 #define __SEL __sel
switches 0:0e018d759a2a 120 #define __QADD __qadd
switches 0:0e018d759a2a 121 #define __QSUB __qsub
switches 0:0e018d759a2a 122
switches 0:0e018d759a2a 123 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
switches 0:0e018d759a2a 124 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
switches 0:0e018d759a2a 125
switches 0:0e018d759a2a 126 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
switches 0:0e018d759a2a 127 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
switches 0:0e018d759a2a 128
switches 0:0e018d759a2a 129 #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
switches 0:0e018d759a2a 130 ((int64_t)(ARG3) << 32) ) >> 32))
switches 0:0e018d759a2a 131
switches 0:0e018d759a2a 132
switches 0:0e018d759a2a 133 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
switches 0:0e018d759a2a 134 /* GNU gcc specific functions */
switches 0:0e018d759a2a 135 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 136 {
switches 0:0e018d759a2a 137 uint32_t result;
switches 0:0e018d759a2a 138
switches 0:0e018d759a2a 139 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 140 return(result);
switches 0:0e018d759a2a 141 }
switches 0:0e018d759a2a 142
switches 0:0e018d759a2a 143 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 144 {
switches 0:0e018d759a2a 145 uint32_t result;
switches 0:0e018d759a2a 146
switches 0:0e018d759a2a 147 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 148 return(result);
switches 0:0e018d759a2a 149 }
switches 0:0e018d759a2a 150
switches 0:0e018d759a2a 151 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 152 {
switches 0:0e018d759a2a 153 uint32_t result;
switches 0:0e018d759a2a 154
switches 0:0e018d759a2a 155 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 156 return(result);
switches 0:0e018d759a2a 157 }
switches 0:0e018d759a2a 158
switches 0:0e018d759a2a 159 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 160 {
switches 0:0e018d759a2a 161 uint32_t result;
switches 0:0e018d759a2a 162
switches 0:0e018d759a2a 163 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 164 return(result);
switches 0:0e018d759a2a 165 }
switches 0:0e018d759a2a 166
switches 0:0e018d759a2a 167 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 168 {
switches 0:0e018d759a2a 169 uint32_t result;
switches 0:0e018d759a2a 170
switches 0:0e018d759a2a 171 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 172 return(result);
switches 0:0e018d759a2a 173 }
switches 0:0e018d759a2a 174
switches 0:0e018d759a2a 175 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 176 {
switches 0:0e018d759a2a 177 uint32_t result;
switches 0:0e018d759a2a 178
switches 0:0e018d759a2a 179 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 180 return(result);
switches 0:0e018d759a2a 181 }
switches 0:0e018d759a2a 182
switches 0:0e018d759a2a 183
switches 0:0e018d759a2a 184 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 185 {
switches 0:0e018d759a2a 186 uint32_t result;
switches 0:0e018d759a2a 187
switches 0:0e018d759a2a 188 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 189 return(result);
switches 0:0e018d759a2a 190 }
switches 0:0e018d759a2a 191
switches 0:0e018d759a2a 192 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 193 {
switches 0:0e018d759a2a 194 uint32_t result;
switches 0:0e018d759a2a 195
switches 0:0e018d759a2a 196 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 197 return(result);
switches 0:0e018d759a2a 198 }
switches 0:0e018d759a2a 199
switches 0:0e018d759a2a 200 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 201 {
switches 0:0e018d759a2a 202 uint32_t result;
switches 0:0e018d759a2a 203
switches 0:0e018d759a2a 204 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 205 return(result);
switches 0:0e018d759a2a 206 }
switches 0:0e018d759a2a 207
switches 0:0e018d759a2a 208 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 209 {
switches 0:0e018d759a2a 210 uint32_t result;
switches 0:0e018d759a2a 211
switches 0:0e018d759a2a 212 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 213 return(result);
switches 0:0e018d759a2a 214 }
switches 0:0e018d759a2a 215
switches 0:0e018d759a2a 216 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 217 {
switches 0:0e018d759a2a 218 uint32_t result;
switches 0:0e018d759a2a 219
switches 0:0e018d759a2a 220 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 221 return(result);
switches 0:0e018d759a2a 222 }
switches 0:0e018d759a2a 223
switches 0:0e018d759a2a 224 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 225 {
switches 0:0e018d759a2a 226 uint32_t result;
switches 0:0e018d759a2a 227
switches 0:0e018d759a2a 228 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 229 return(result);
switches 0:0e018d759a2a 230 }
switches 0:0e018d759a2a 231
switches 0:0e018d759a2a 232
switches 0:0e018d759a2a 233 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 234 {
switches 0:0e018d759a2a 235 uint32_t result;
switches 0:0e018d759a2a 236
switches 0:0e018d759a2a 237 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 238 return(result);
switches 0:0e018d759a2a 239 }
switches 0:0e018d759a2a 240
switches 0:0e018d759a2a 241 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 242 {
switches 0:0e018d759a2a 243 uint32_t result;
switches 0:0e018d759a2a 244
switches 0:0e018d759a2a 245 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 246 return(result);
switches 0:0e018d759a2a 247 }
switches 0:0e018d759a2a 248
switches 0:0e018d759a2a 249 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 250 {
switches 0:0e018d759a2a 251 uint32_t result;
switches 0:0e018d759a2a 252
switches 0:0e018d759a2a 253 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 254 return(result);
switches 0:0e018d759a2a 255 }
switches 0:0e018d759a2a 256
switches 0:0e018d759a2a 257 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 258 {
switches 0:0e018d759a2a 259 uint32_t result;
switches 0:0e018d759a2a 260
switches 0:0e018d759a2a 261 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 262 return(result);
switches 0:0e018d759a2a 263 }
switches 0:0e018d759a2a 264
switches 0:0e018d759a2a 265 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 266 {
switches 0:0e018d759a2a 267 uint32_t result;
switches 0:0e018d759a2a 268
switches 0:0e018d759a2a 269 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 270 return(result);
switches 0:0e018d759a2a 271 }
switches 0:0e018d759a2a 272
switches 0:0e018d759a2a 273 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 274 {
switches 0:0e018d759a2a 275 uint32_t result;
switches 0:0e018d759a2a 276
switches 0:0e018d759a2a 277 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 278 return(result);
switches 0:0e018d759a2a 279 }
switches 0:0e018d759a2a 280
switches 0:0e018d759a2a 281 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 282 {
switches 0:0e018d759a2a 283 uint32_t result;
switches 0:0e018d759a2a 284
switches 0:0e018d759a2a 285 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 286 return(result);
switches 0:0e018d759a2a 287 }
switches 0:0e018d759a2a 288
switches 0:0e018d759a2a 289 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 290 {
switches 0:0e018d759a2a 291 uint32_t result;
switches 0:0e018d759a2a 292
switches 0:0e018d759a2a 293 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 294 return(result);
switches 0:0e018d759a2a 295 }
switches 0:0e018d759a2a 296
switches 0:0e018d759a2a 297 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 298 {
switches 0:0e018d759a2a 299 uint32_t result;
switches 0:0e018d759a2a 300
switches 0:0e018d759a2a 301 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 302 return(result);
switches 0:0e018d759a2a 303 }
switches 0:0e018d759a2a 304
switches 0:0e018d759a2a 305 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 306 {
switches 0:0e018d759a2a 307 uint32_t result;
switches 0:0e018d759a2a 308
switches 0:0e018d759a2a 309 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 310 return(result);
switches 0:0e018d759a2a 311 }
switches 0:0e018d759a2a 312
switches 0:0e018d759a2a 313 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 314 {
switches 0:0e018d759a2a 315 uint32_t result;
switches 0:0e018d759a2a 316
switches 0:0e018d759a2a 317 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 318 return(result);
switches 0:0e018d759a2a 319 }
switches 0:0e018d759a2a 320
switches 0:0e018d759a2a 321 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 322 {
switches 0:0e018d759a2a 323 uint32_t result;
switches 0:0e018d759a2a 324
switches 0:0e018d759a2a 325 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 326 return(result);
switches 0:0e018d759a2a 327 }
switches 0:0e018d759a2a 328
switches 0:0e018d759a2a 329 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 330 {
switches 0:0e018d759a2a 331 uint32_t result;
switches 0:0e018d759a2a 332
switches 0:0e018d759a2a 333 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 334 return(result);
switches 0:0e018d759a2a 335 }
switches 0:0e018d759a2a 336
switches 0:0e018d759a2a 337 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 338 {
switches 0:0e018d759a2a 339 uint32_t result;
switches 0:0e018d759a2a 340
switches 0:0e018d759a2a 341 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 342 return(result);
switches 0:0e018d759a2a 343 }
switches 0:0e018d759a2a 344
switches 0:0e018d759a2a 345 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 346 {
switches 0:0e018d759a2a 347 uint32_t result;
switches 0:0e018d759a2a 348
switches 0:0e018d759a2a 349 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 350 return(result);
switches 0:0e018d759a2a 351 }
switches 0:0e018d759a2a 352
switches 0:0e018d759a2a 353 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 354 {
switches 0:0e018d759a2a 355 uint32_t result;
switches 0:0e018d759a2a 356
switches 0:0e018d759a2a 357 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 358 return(result);
switches 0:0e018d759a2a 359 }
switches 0:0e018d759a2a 360
switches 0:0e018d759a2a 361 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 362 {
switches 0:0e018d759a2a 363 uint32_t result;
switches 0:0e018d759a2a 364
switches 0:0e018d759a2a 365 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 366 return(result);
switches 0:0e018d759a2a 367 }
switches 0:0e018d759a2a 368
switches 0:0e018d759a2a 369 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 370 {
switches 0:0e018d759a2a 371 uint32_t result;
switches 0:0e018d759a2a 372
switches 0:0e018d759a2a 373 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 374 return(result);
switches 0:0e018d759a2a 375 }
switches 0:0e018d759a2a 376
switches 0:0e018d759a2a 377 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 378 {
switches 0:0e018d759a2a 379 uint32_t result;
switches 0:0e018d759a2a 380
switches 0:0e018d759a2a 381 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 382 return(result);
switches 0:0e018d759a2a 383 }
switches 0:0e018d759a2a 384
switches 0:0e018d759a2a 385 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 386 {
switches 0:0e018d759a2a 387 uint32_t result;
switches 0:0e018d759a2a 388
switches 0:0e018d759a2a 389 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 390 return(result);
switches 0:0e018d759a2a 391 }
switches 0:0e018d759a2a 392
switches 0:0e018d759a2a 393 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 394 {
switches 0:0e018d759a2a 395 uint32_t result;
switches 0:0e018d759a2a 396
switches 0:0e018d759a2a 397 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 398 return(result);
switches 0:0e018d759a2a 399 }
switches 0:0e018d759a2a 400
switches 0:0e018d759a2a 401 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 402 {
switches 0:0e018d759a2a 403 uint32_t result;
switches 0:0e018d759a2a 404
switches 0:0e018d759a2a 405 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 406 return(result);
switches 0:0e018d759a2a 407 }
switches 0:0e018d759a2a 408
switches 0:0e018d759a2a 409 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 410 {
switches 0:0e018d759a2a 411 uint32_t result;
switches 0:0e018d759a2a 412
switches 0:0e018d759a2a 413 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 414 return(result);
switches 0:0e018d759a2a 415 }
switches 0:0e018d759a2a 416
switches 0:0e018d759a2a 417 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 418 {
switches 0:0e018d759a2a 419 uint32_t result;
switches 0:0e018d759a2a 420
switches 0:0e018d759a2a 421 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 422 return(result);
switches 0:0e018d759a2a 423 }
switches 0:0e018d759a2a 424
switches 0:0e018d759a2a 425 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 426 {
switches 0:0e018d759a2a 427 uint32_t result;
switches 0:0e018d759a2a 428
switches 0:0e018d759a2a 429 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 430 return(result);
switches 0:0e018d759a2a 431 }
switches 0:0e018d759a2a 432
switches 0:0e018d759a2a 433 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
switches 0:0e018d759a2a 434 {
switches 0:0e018d759a2a 435 uint32_t result;
switches 0:0e018d759a2a 436
switches 0:0e018d759a2a 437 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
switches 0:0e018d759a2a 438 return(result);
switches 0:0e018d759a2a 439 }
switches 0:0e018d759a2a 440
switches 0:0e018d759a2a 441 #define __SSAT16(ARG1,ARG2) \
switches 0:0e018d759a2a 442 ({ \
switches 0:0e018d759a2a 443 uint32_t __RES, __ARG1 = (ARG1); \
switches 0:0e018d759a2a 444 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
switches 0:0e018d759a2a 445 __RES; \
switches 0:0e018d759a2a 446 })
switches 0:0e018d759a2a 447
switches 0:0e018d759a2a 448 #define __USAT16(ARG1,ARG2) \
switches 0:0e018d759a2a 449 ({ \
switches 0:0e018d759a2a 450 uint32_t __RES, __ARG1 = (ARG1); \
switches 0:0e018d759a2a 451 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
switches 0:0e018d759a2a 452 __RES; \
switches 0:0e018d759a2a 453 })
switches 0:0e018d759a2a 454
switches 0:0e018d759a2a 455 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
switches 0:0e018d759a2a 456 {
switches 0:0e018d759a2a 457 uint32_t result;
switches 0:0e018d759a2a 458
switches 0:0e018d759a2a 459 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
switches 0:0e018d759a2a 460 return(result);
switches 0:0e018d759a2a 461 }
switches 0:0e018d759a2a 462
switches 0:0e018d759a2a 463 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 464 {
switches 0:0e018d759a2a 465 uint32_t result;
switches 0:0e018d759a2a 466
switches 0:0e018d759a2a 467 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 468 return(result);
switches 0:0e018d759a2a 469 }
switches 0:0e018d759a2a 470
switches 0:0e018d759a2a 471 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
switches 0:0e018d759a2a 472 {
switches 0:0e018d759a2a 473 uint32_t result;
switches 0:0e018d759a2a 474
switches 0:0e018d759a2a 475 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
switches 0:0e018d759a2a 476 return(result);
switches 0:0e018d759a2a 477 }
switches 0:0e018d759a2a 478
switches 0:0e018d759a2a 479 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 480 {
switches 0:0e018d759a2a 481 uint32_t result;
switches 0:0e018d759a2a 482
switches 0:0e018d759a2a 483 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 484 return(result);
switches 0:0e018d759a2a 485 }
switches 0:0e018d759a2a 486
switches 0:0e018d759a2a 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 488 {
switches 0:0e018d759a2a 489 uint32_t result;
switches 0:0e018d759a2a 490
switches 0:0e018d759a2a 491 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 492 return(result);
switches 0:0e018d759a2a 493 }
switches 0:0e018d759a2a 494
switches 0:0e018d759a2a 495 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 496 {
switches 0:0e018d759a2a 497 uint32_t result;
switches 0:0e018d759a2a 498
switches 0:0e018d759a2a 499 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 500 return(result);
switches 0:0e018d759a2a 501 }
switches 0:0e018d759a2a 502
switches 0:0e018d759a2a 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
switches 0:0e018d759a2a 504 {
switches 0:0e018d759a2a 505 uint32_t result;
switches 0:0e018d759a2a 506
switches 0:0e018d759a2a 507 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
switches 0:0e018d759a2a 508 return(result);
switches 0:0e018d759a2a 509 }
switches 0:0e018d759a2a 510
switches 0:0e018d759a2a 511 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
switches 0:0e018d759a2a 512 {
switches 0:0e018d759a2a 513 uint32_t result;
switches 0:0e018d759a2a 514
switches 0:0e018d759a2a 515 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
switches 0:0e018d759a2a 516 return(result);
switches 0:0e018d759a2a 517 }
switches 0:0e018d759a2a 518
switches 0:0e018d759a2a 519 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
switches 0:0e018d759a2a 520 {
switches 0:0e018d759a2a 521 union llreg_u{
switches 0:0e018d759a2a 522 uint32_t w32[2];
switches 0:0e018d759a2a 523 uint64_t w64;
switches 0:0e018d759a2a 524 } llr;
switches 0:0e018d759a2a 525 llr.w64 = acc;
switches 0:0e018d759a2a 526
switches 0:0e018d759a2a 527 #ifndef __ARMEB__ // Little endian
switches 0:0e018d759a2a 528 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
switches 0:0e018d759a2a 529 #else // Big endian
switches 0:0e018d759a2a 530 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
switches 0:0e018d759a2a 531 #endif
switches 0:0e018d759a2a 532
switches 0:0e018d759a2a 533 return(llr.w64);
switches 0:0e018d759a2a 534 }
switches 0:0e018d759a2a 535
switches 0:0e018d759a2a 536 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
switches 0:0e018d759a2a 537 {
switches 0:0e018d759a2a 538 union llreg_u{
switches 0:0e018d759a2a 539 uint32_t w32[2];
switches 0:0e018d759a2a 540 uint64_t w64;
switches 0:0e018d759a2a 541 } llr;
switches 0:0e018d759a2a 542 llr.w64 = acc;
switches 0:0e018d759a2a 543
switches 0:0e018d759a2a 544 #ifndef __ARMEB__ // Little endian
switches 0:0e018d759a2a 545 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
switches 0:0e018d759a2a 546 #else // Big endian
switches 0:0e018d759a2a 547 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
switches 0:0e018d759a2a 548 #endif
switches 0:0e018d759a2a 549
switches 0:0e018d759a2a 550 return(llr.w64);
switches 0:0e018d759a2a 551 }
switches 0:0e018d759a2a 552
switches 0:0e018d759a2a 553 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 554 {
switches 0:0e018d759a2a 555 uint32_t result;
switches 0:0e018d759a2a 556
switches 0:0e018d759a2a 557 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 558 return(result);
switches 0:0e018d759a2a 559 }
switches 0:0e018d759a2a 560
switches 0:0e018d759a2a 561 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 562 {
switches 0:0e018d759a2a 563 uint32_t result;
switches 0:0e018d759a2a 564
switches 0:0e018d759a2a 565 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 566 return(result);
switches 0:0e018d759a2a 567 }
switches 0:0e018d759a2a 568
switches 0:0e018d759a2a 569 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
switches 0:0e018d759a2a 570 {
switches 0:0e018d759a2a 571 uint32_t result;
switches 0:0e018d759a2a 572
switches 0:0e018d759a2a 573 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
switches 0:0e018d759a2a 574 return(result);
switches 0:0e018d759a2a 575 }
switches 0:0e018d759a2a 576
switches 0:0e018d759a2a 577 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
switches 0:0e018d759a2a 578 {
switches 0:0e018d759a2a 579 uint32_t result;
switches 0:0e018d759a2a 580
switches 0:0e018d759a2a 581 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
switches 0:0e018d759a2a 582 return(result);
switches 0:0e018d759a2a 583 }
switches 0:0e018d759a2a 584
switches 0:0e018d759a2a 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
switches 0:0e018d759a2a 586 {
switches 0:0e018d759a2a 587 union llreg_u{
switches 0:0e018d759a2a 588 uint32_t w32[2];
switches 0:0e018d759a2a 589 uint64_t w64;
switches 0:0e018d759a2a 590 } llr;
switches 0:0e018d759a2a 591 llr.w64 = acc;
switches 0:0e018d759a2a 592
switches 0:0e018d759a2a 593 #ifndef __ARMEB__ // Little endian
switches 0:0e018d759a2a 594 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
switches 0:0e018d759a2a 595 #else // Big endian
switches 0:0e018d759a2a 596 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
switches 0:0e018d759a2a 597 #endif
switches 0:0e018d759a2a 598
switches 0:0e018d759a2a 599 return(llr.w64);
switches 0:0e018d759a2a 600 }
switches 0:0e018d759a2a 601
switches 0:0e018d759a2a 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
switches 0:0e018d759a2a 603 {
switches 0:0e018d759a2a 604 union llreg_u{
switches 0:0e018d759a2a 605 uint32_t w32[2];
switches 0:0e018d759a2a 606 uint64_t w64;
switches 0:0e018d759a2a 607 } llr;
switches 0:0e018d759a2a 608 llr.w64 = acc;
switches 0:0e018d759a2a 609
switches 0:0e018d759a2a 610 #ifndef __ARMEB__ // Little endian
switches 0:0e018d759a2a 611 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
switches 0:0e018d759a2a 612 #else // Big endian
switches 0:0e018d759a2a 613 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
switches 0:0e018d759a2a 614 #endif
switches 0:0e018d759a2a 615
switches 0:0e018d759a2a 616 return(llr.w64);
switches 0:0e018d759a2a 617 }
switches 0:0e018d759a2a 618
switches 0:0e018d759a2a 619 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 620 {
switches 0:0e018d759a2a 621 uint32_t result;
switches 0:0e018d759a2a 622
switches 0:0e018d759a2a 623 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 624 return(result);
switches 0:0e018d759a2a 625 }
switches 0:0e018d759a2a 626
switches 0:0e018d759a2a 627 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 628 {
switches 0:0e018d759a2a 629 uint32_t result;
switches 0:0e018d759a2a 630
switches 0:0e018d759a2a 631 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 632 return(result);
switches 0:0e018d759a2a 633 }
switches 0:0e018d759a2a 634
switches 0:0e018d759a2a 635 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 636 {
switches 0:0e018d759a2a 637 uint32_t result;
switches 0:0e018d759a2a 638
switches 0:0e018d759a2a 639 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
switches 0:0e018d759a2a 640 return(result);
switches 0:0e018d759a2a 641 }
switches 0:0e018d759a2a 642
switches 0:0e018d759a2a 643 #define __PKHBT(ARG1,ARG2,ARG3) \
switches 0:0e018d759a2a 644 ({ \
switches 0:0e018d759a2a 645 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
switches 0:0e018d759a2a 646 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
switches 0:0e018d759a2a 647 __RES; \
switches 0:0e018d759a2a 648 })
switches 0:0e018d759a2a 649
switches 0:0e018d759a2a 650 #define __PKHTB(ARG1,ARG2,ARG3) \
switches 0:0e018d759a2a 651 ({ \
switches 0:0e018d759a2a 652 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
switches 0:0e018d759a2a 653 if (ARG3 == 0) \
switches 0:0e018d759a2a 654 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
switches 0:0e018d759a2a 655 else \
switches 0:0e018d759a2a 656 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
switches 0:0e018d759a2a 657 __RES; \
switches 0:0e018d759a2a 658 })
switches 0:0e018d759a2a 659
switches 0:0e018d759a2a 660 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
switches 0:0e018d759a2a 661 {
switches 0:0e018d759a2a 662 int32_t result;
switches 0:0e018d759a2a 663
switches 0:0e018d759a2a 664 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
switches 0:0e018d759a2a 665 return(result);
switches 0:0e018d759a2a 666 }
switches 0:0e018d759a2a 667
switches 0:0e018d759a2a 668
switches 0:0e018d759a2a 669 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
switches 0:0e018d759a2a 670 /* IAR iccarm specific functions */
switches 0:0e018d759a2a 671 #include <cmsis_iar.h>
switches 0:0e018d759a2a 672
switches 0:0e018d759a2a 673
switches 0:0e018d759a2a 674 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
switches 0:0e018d759a2a 675 /* TI CCS specific functions */
switches 0:0e018d759a2a 676 #include <cmsis_ccs.h>
switches 0:0e018d759a2a 677
switches 0:0e018d759a2a 678
switches 0:0e018d759a2a 679 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
switches 0:0e018d759a2a 680 /* TASKING carm specific functions */
switches 0:0e018d759a2a 681 /* not yet supported */
switches 0:0e018d759a2a 682
switches 0:0e018d759a2a 683
switches 0:0e018d759a2a 684 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
switches 0:0e018d759a2a 685 /* Cosmic specific functions */
switches 0:0e018d759a2a 686 #include <cmsis_csm.h>
switches 0:0e018d759a2a 687
switches 0:0e018d759a2a 688 #endif
switches 0:0e018d759a2a 689
switches 0:0e018d759a2a 690 /*@} end of group CMSIS_SIMD_intrinsics */
switches 0:0e018d759a2a 691
switches 0:0e018d759a2a 692
switches 0:0e018d759a2a 693 #ifdef __cplusplus
switches 0:0e018d759a2a 694 }
switches 0:0e018d759a2a 695 #endif
switches 0:0e018d759a2a 696
switches 0:0e018d759a2a 697 #endif /* __CORE_CMSIMD_H */