Greg Steiert / maxim_dev

Maxim mbed development library

Dependents:   sensomed

cmsis/core_cmInstr.h@0:0e018d759a2a, 2016-11-08 (annotated)

Committer:
switches
Date:
Tue Nov 08 18:27:11 2016 +0000
Revision:
0:0e018d759a2a
Initial commit

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switches 0:0e018d759a2a 1 /**************************************************************************//**
switches 0:0e018d759a2a 2 * @file core_cmInstr.h
switches 0:0e018d759a2a 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
switches 0:0e018d759a2a 4 * @version V4.10
switches 0:0e018d759a2a 5 * @date 18. March 2015
switches 0:0e018d759a2a 6 *
switches 0:0e018d759a2a 7 * @note
switches 0:0e018d759a2a 8 *
switches 0:0e018d759a2a 9 ******************************************************************************/
switches 0:0e018d759a2a 10 /* Copyright (c) 2009 - 2014 ARM LIMITED
switches 0:0e018d759a2a 11
switches 0:0e018d759a2a 12 All rights reserved.
switches 0:0e018d759a2a 13 Redistribution and use in source and binary forms, with or without
switches 0:0e018d759a2a 14 modification, are permitted provided that the following conditions are met:
switches 0:0e018d759a2a 15 - Redistributions of source code must retain the above copyright
switches 0:0e018d759a2a 16 notice, this list of conditions and the following disclaimer.
switches 0:0e018d759a2a 17 - Redistributions in binary form must reproduce the above copyright
switches 0:0e018d759a2a 18 notice, this list of conditions and the following disclaimer in the
switches 0:0e018d759a2a 19 documentation and/or other materials provided with the distribution.
switches 0:0e018d759a2a 20 - Neither the name of ARM nor the names of its contributors may be used
switches 0:0e018d759a2a 21 to endorse or promote products derived from this software without
switches 0:0e018d759a2a 22 specific prior written permission.
switches 0:0e018d759a2a 23 *
switches 0:0e018d759a2a 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
switches 0:0e018d759a2a 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
switches 0:0e018d759a2a 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
switches 0:0e018d759a2a 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
switches 0:0e018d759a2a 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
switches 0:0e018d759a2a 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
switches 0:0e018d759a2a 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
switches 0:0e018d759a2a 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
switches 0:0e018d759a2a 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
switches 0:0e018d759a2a 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
switches 0:0e018d759a2a 34 POSSIBILITY OF SUCH DAMAGE.
switches 0:0e018d759a2a 35 ---------------------------------------------------------------------------*/
switches 0:0e018d759a2a 36
switches 0:0e018d759a2a 37
switches 0:0e018d759a2a 38 #ifndef __CORE_CMINSTR_H
switches 0:0e018d759a2a 39 #define __CORE_CMINSTR_H
switches 0:0e018d759a2a 40
switches 0:0e018d759a2a 41
switches 0:0e018d759a2a 42 /* ########################## Core Instruction Access ######################### */
switches 0:0e018d759a2a 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
switches 0:0e018d759a2a 44 Access to dedicated instructions
switches 0:0e018d759a2a 45 @{
switches 0:0e018d759a2a 46 */
switches 0:0e018d759a2a 47
switches 0:0e018d759a2a 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
switches 0:0e018d759a2a 49 /* ARM armcc specific functions */
switches 0:0e018d759a2a 50
switches 0:0e018d759a2a 51 #if (__ARMCC_VERSION < 400677)
switches 0:0e018d759a2a 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
switches 0:0e018d759a2a 53 #endif
switches 0:0e018d759a2a 54
switches 0:0e018d759a2a 55
switches 0:0e018d759a2a 56 /** \brief No Operation
switches 0:0e018d759a2a 57
switches 0:0e018d759a2a 58 No Operation does nothing. This instruction can be used for code alignment purposes.
switches 0:0e018d759a2a 59 */
switches 0:0e018d759a2a 60 #define __NOP __nop
switches 0:0e018d759a2a 61
switches 0:0e018d759a2a 62
switches 0:0e018d759a2a 63 /** \brief Wait For Interrupt
switches 0:0e018d759a2a 64
switches 0:0e018d759a2a 65 Wait For Interrupt is a hint instruction that suspends execution
switches 0:0e018d759a2a 66 until one of a number of events occurs.
switches 0:0e018d759a2a 67 */
switches 0:0e018d759a2a 68 #define __WFI __wfi
switches 0:0e018d759a2a 69
switches 0:0e018d759a2a 70
switches 0:0e018d759a2a 71 /** \brief Wait For Event
switches 0:0e018d759a2a 72
switches 0:0e018d759a2a 73 Wait For Event is a hint instruction that permits the processor to enter
switches 0:0e018d759a2a 74 a low-power state until one of a number of events occurs.
switches 0:0e018d759a2a 75 */
switches 0:0e018d759a2a 76 #define __WFE __wfe
switches 0:0e018d759a2a 77
switches 0:0e018d759a2a 78
switches 0:0e018d759a2a 79 /** \brief Send Event
switches 0:0e018d759a2a 80
switches 0:0e018d759a2a 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
switches 0:0e018d759a2a 82 */
switches 0:0e018d759a2a 83 #define __SEV __sev
switches 0:0e018d759a2a 84
switches 0:0e018d759a2a 85
switches 0:0e018d759a2a 86 /** \brief Instruction Synchronization Barrier
switches 0:0e018d759a2a 87
switches 0:0e018d759a2a 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
switches 0:0e018d759a2a 89 so that all instructions following the ISB are fetched from cache or
switches 0:0e018d759a2a 90 memory, after the instruction has been completed.
switches 0:0e018d759a2a 91 */
switches 0:0e018d759a2a 92 #define __ISB() do {\
switches 0:0e018d759a2a 93 __schedule_barrier();\
switches 0:0e018d759a2a 94 __isb(0xF);\
switches 0:0e018d759a2a 95 __schedule_barrier();\
switches 0:0e018d759a2a 96 } while (0)
switches 0:0e018d759a2a 97
switches 0:0e018d759a2a 98 /** \brief Data Synchronization Barrier
switches 0:0e018d759a2a 99
switches 0:0e018d759a2a 100 This function acts as a special kind of Data Memory Barrier.
switches 0:0e018d759a2a 101 It completes when all explicit memory accesses before this instruction complete.
switches 0:0e018d759a2a 102 */
switches 0:0e018d759a2a 103 #define __DSB() do {\
switches 0:0e018d759a2a 104 __schedule_barrier();\
switches 0:0e018d759a2a 105 __dsb(0xF);\
switches 0:0e018d759a2a 106 __schedule_barrier();\
switches 0:0e018d759a2a 107 } while (0)
switches 0:0e018d759a2a 108
switches 0:0e018d759a2a 109 /** \brief Data Memory Barrier
switches 0:0e018d759a2a 110
switches 0:0e018d759a2a 111 This function ensures the apparent order of the explicit memory operations before
switches 0:0e018d759a2a 112 and after the instruction, without ensuring their completion.
switches 0:0e018d759a2a 113 */
switches 0:0e018d759a2a 114 #define __DMB() do {\
switches 0:0e018d759a2a 115 __schedule_barrier();\
switches 0:0e018d759a2a 116 __dmb(0xF);\
switches 0:0e018d759a2a 117 __schedule_barrier();\
switches 0:0e018d759a2a 118 } while (0)
switches 0:0e018d759a2a 119
switches 0:0e018d759a2a 120 /** \brief Reverse byte order (32 bit)
switches 0:0e018d759a2a 121
switches 0:0e018d759a2a 122 This function reverses the byte order in integer value.
switches 0:0e018d759a2a 123
switches 0:0e018d759a2a 124 \param [in] value Value to reverse
switches 0:0e018d759a2a 125 \return Reversed value
switches 0:0e018d759a2a 126 */
switches 0:0e018d759a2a 127 #define __REV __rev
switches 0:0e018d759a2a 128
switches 0:0e018d759a2a 129
switches 0:0e018d759a2a 130 /** \brief Reverse byte order (16 bit)
switches 0:0e018d759a2a 131
switches 0:0e018d759a2a 132 This function reverses the byte order in two unsigned short values.
switches 0:0e018d759a2a 133
switches 0:0e018d759a2a 134 \param [in] value Value to reverse
switches 0:0e018d759a2a 135 \return Reversed value
switches 0:0e018d759a2a 136 */
switches 0:0e018d759a2a 137 #ifndef __NO_EMBEDDED_ASM
switches 0:0e018d759a2a 138 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
switches 0:0e018d759a2a 139 {
switches 0:0e018d759a2a 140 rev16 r0, r0
switches 0:0e018d759a2a 141 bx lr
switches 0:0e018d759a2a 142 }
switches 0:0e018d759a2a 143 #endif
switches 0:0e018d759a2a 144
switches 0:0e018d759a2a 145 /** \brief Reverse byte order in signed short value
switches 0:0e018d759a2a 146
switches 0:0e018d759a2a 147 This function reverses the byte order in a signed short value with sign extension to integer.
switches 0:0e018d759a2a 148
switches 0:0e018d759a2a 149 \param [in] value Value to reverse
switches 0:0e018d759a2a 150 \return Reversed value
switches 0:0e018d759a2a 151 */
switches 0:0e018d759a2a 152 #ifndef __NO_EMBEDDED_ASM
switches 0:0e018d759a2a 153 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
switches 0:0e018d759a2a 154 {
switches 0:0e018d759a2a 155 revsh r0, r0
switches 0:0e018d759a2a 156 bx lr
switches 0:0e018d759a2a 157 }
switches 0:0e018d759a2a 158 #endif
switches 0:0e018d759a2a 159
switches 0:0e018d759a2a 160
switches 0:0e018d759a2a 161 /** \brief Rotate Right in unsigned value (32 bit)
switches 0:0e018d759a2a 162
switches 0:0e018d759a2a 163 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
switches 0:0e018d759a2a 164
switches 0:0e018d759a2a 165 \param [in] value Value to rotate
switches 0:0e018d759a2a 166 \param [in] value Number of Bits to rotate
switches 0:0e018d759a2a 167 \return Rotated value
switches 0:0e018d759a2a 168 */
switches 0:0e018d759a2a 169 #define __ROR __ror
switches 0:0e018d759a2a 170
switches 0:0e018d759a2a 171
switches 0:0e018d759a2a 172 /** \brief Breakpoint
switches 0:0e018d759a2a 173
switches 0:0e018d759a2a 174 This function causes the processor to enter Debug state.
switches 0:0e018d759a2a 175 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
switches 0:0e018d759a2a 176
switches 0:0e018d759a2a 177 \param [in] value is ignored by the processor.
switches 0:0e018d759a2a 178 If required, a debugger can use it to store additional information about the breakpoint.
switches 0:0e018d759a2a 179 */
switches 0:0e018d759a2a 180 #define __BKPT(value) __breakpoint(value)
switches 0:0e018d759a2a 181
switches 0:0e018d759a2a 182
switches 0:0e018d759a2a 183 /** \brief Reverse bit order of value
switches 0:0e018d759a2a 184
switches 0:0e018d759a2a 185 This function reverses the bit order of the given value.
switches 0:0e018d759a2a 186
switches 0:0e018d759a2a 187 \param [in] value Value to reverse
switches 0:0e018d759a2a 188 \return Reversed value
switches 0:0e018d759a2a 189 */
switches 0:0e018d759a2a 190 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
switches 0:0e018d759a2a 191 #define __RBIT __rbit
switches 0:0e018d759a2a 192 #else
switches 0:0e018d759a2a 193 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
switches 0:0e018d759a2a 194 {
switches 0:0e018d759a2a 195 uint32_t result;
switches 0:0e018d759a2a 196 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
switches 0:0e018d759a2a 197
switches 0:0e018d759a2a 198 result = value; // r will be reversed bits of v; first get LSB of v
switches 0:0e018d759a2a 199 for (value >>= 1; value; value >>= 1)
switches 0:0e018d759a2a 200 {
switches 0:0e018d759a2a 201 result <<= 1;
switches 0:0e018d759a2a 202 result |= value & 1;
switches 0:0e018d759a2a 203 s--;
switches 0:0e018d759a2a 204 }
switches 0:0e018d759a2a 205 result <<= s; // shift when v's highest bits are zero
switches 0:0e018d759a2a 206 return(result);
switches 0:0e018d759a2a 207 }
switches 0:0e018d759a2a 208 #endif
switches 0:0e018d759a2a 209
switches 0:0e018d759a2a 210
switches 0:0e018d759a2a 211 /** \brief Count leading zeros
switches 0:0e018d759a2a 212
switches 0:0e018d759a2a 213 This function counts the number of leading zeros of a data value.
switches 0:0e018d759a2a 214
switches 0:0e018d759a2a 215 \param [in] value Value to count the leading zeros
switches 0:0e018d759a2a 216 \return number of leading zeros in value
switches 0:0e018d759a2a 217 */
switches 0:0e018d759a2a 218 #define __CLZ __clz
switches 0:0e018d759a2a 219
switches 0:0e018d759a2a 220
switches 0:0e018d759a2a 221 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
switches 0:0e018d759a2a 222
switches 0:0e018d759a2a 223 /** \brief LDR Exclusive (8 bit)
switches 0:0e018d759a2a 224
switches 0:0e018d759a2a 225 This function executes a exclusive LDR instruction for 8 bit value.
switches 0:0e018d759a2a 226
switches 0:0e018d759a2a 227 \param [in] ptr Pointer to data
switches 0:0e018d759a2a 228 \return value of type uint8_t at (*ptr)
switches 0:0e018d759a2a 229 */
switches 0:0e018d759a2a 230 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
switches 0:0e018d759a2a 231
switches 0:0e018d759a2a 232
switches 0:0e018d759a2a 233 /** \brief LDR Exclusive (16 bit)
switches 0:0e018d759a2a 234
switches 0:0e018d759a2a 235 This function executes a exclusive LDR instruction for 16 bit values.
switches 0:0e018d759a2a 236
switches 0:0e018d759a2a 237 \param [in] ptr Pointer to data
switches 0:0e018d759a2a 238 \return value of type uint16_t at (*ptr)
switches 0:0e018d759a2a 239 */
switches 0:0e018d759a2a 240 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
switches 0:0e018d759a2a 241
switches 0:0e018d759a2a 242
switches 0:0e018d759a2a 243 /** \brief LDR Exclusive (32 bit)
switches 0:0e018d759a2a 244
switches 0:0e018d759a2a 245 This function executes a exclusive LDR instruction for 32 bit values.
switches 0:0e018d759a2a 246
switches 0:0e018d759a2a 247 \param [in] ptr Pointer to data
switches 0:0e018d759a2a 248 \return value of type uint32_t at (*ptr)
switches 0:0e018d759a2a 249 */
switches 0:0e018d759a2a 250 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
switches 0:0e018d759a2a 251
switches 0:0e018d759a2a 252
switches 0:0e018d759a2a 253 /** \brief STR Exclusive (8 bit)
switches 0:0e018d759a2a 254
switches 0:0e018d759a2a 255 This function executes a exclusive STR instruction for 8 bit values.
switches 0:0e018d759a2a 256
switches 0:0e018d759a2a 257 \param [in] value Value to store
switches 0:0e018d759a2a 258 \param [in] ptr Pointer to location
switches 0:0e018d759a2a 259 \return 0 Function succeeded
switches 0:0e018d759a2a 260 \return 1 Function failed
switches 0:0e018d759a2a 261 */
switches 0:0e018d759a2a 262 #define __STREXB(value, ptr) __strex(value, ptr)
switches 0:0e018d759a2a 263
switches 0:0e018d759a2a 264
switches 0:0e018d759a2a 265 /** \brief STR Exclusive (16 bit)
switches 0:0e018d759a2a 266
switches 0:0e018d759a2a 267 This function executes a exclusive STR instruction for 16 bit values.
switches 0:0e018d759a2a 268
switches 0:0e018d759a2a 269 \param [in] value Value to store
switches 0:0e018d759a2a 270 \param [in] ptr Pointer to location
switches 0:0e018d759a2a 271 \return 0 Function succeeded
switches 0:0e018d759a2a 272 \return 1 Function failed
switches 0:0e018d759a2a 273 */
switches 0:0e018d759a2a 274 #define __STREXH(value, ptr) __strex(value, ptr)
switches 0:0e018d759a2a 275
switches 0:0e018d759a2a 276
switches 0:0e018d759a2a 277 /** \brief STR Exclusive (32 bit)
switches 0:0e018d759a2a 278
switches 0:0e018d759a2a 279 This function executes a exclusive STR instruction for 32 bit values.
switches 0:0e018d759a2a 280
switches 0:0e018d759a2a 281 \param [in] value Value to store
switches 0:0e018d759a2a 282 \param [in] ptr Pointer to location
switches 0:0e018d759a2a 283 \return 0 Function succeeded
switches 0:0e018d759a2a 284 \return 1 Function failed
switches 0:0e018d759a2a 285 */
switches 0:0e018d759a2a 286 #define __STREXW(value, ptr) __strex(value, ptr)
switches 0:0e018d759a2a 287
switches 0:0e018d759a2a 288
switches 0:0e018d759a2a 289 /** \brief Remove the exclusive lock
switches 0:0e018d759a2a 290
switches 0:0e018d759a2a 291 This function removes the exclusive lock which is created by LDREX.
switches 0:0e018d759a2a 292
switches 0:0e018d759a2a 293 */
switches 0:0e018d759a2a 294 #define __CLREX __clrex
switches 0:0e018d759a2a 295
switches 0:0e018d759a2a 296
switches 0:0e018d759a2a 297 /** \brief Signed Saturate
switches 0:0e018d759a2a 298
switches 0:0e018d759a2a 299 This function saturates a signed value.
switches 0:0e018d759a2a 300
switches 0:0e018d759a2a 301 \param [in] value Value to be saturated
switches 0:0e018d759a2a 302 \param [in] sat Bit position to saturate to (1..32)
switches 0:0e018d759a2a 303 \return Saturated value
switches 0:0e018d759a2a 304 */
switches 0:0e018d759a2a 305 #define __SSAT __ssat
switches 0:0e018d759a2a 306
switches 0:0e018d759a2a 307
switches 0:0e018d759a2a 308 /** \brief Unsigned Saturate
switches 0:0e018d759a2a 309
switches 0:0e018d759a2a 310 This function saturates an unsigned value.
switches 0:0e018d759a2a 311
switches 0:0e018d759a2a 312 \param [in] value Value to be saturated
switches 0:0e018d759a2a 313 \param [in] sat Bit position to saturate to (0..31)
switches 0:0e018d759a2a 314 \return Saturated value
switches 0:0e018d759a2a 315 */
switches 0:0e018d759a2a 316 #define __USAT __usat
switches 0:0e018d759a2a 317
switches 0:0e018d759a2a 318
switches 0:0e018d759a2a 319 /** \brief Rotate Right with Extend (32 bit)
switches 0:0e018d759a2a 320
switches 0:0e018d759a2a 321 This function moves each bit of a bitstring right by one bit.
switches 0:0e018d759a2a 322 The carry input is shifted in at the left end of the bitstring.
switches 0:0e018d759a2a 323
switches 0:0e018d759a2a 324 \param [in] value Value to rotate
switches 0:0e018d759a2a 325 \return Rotated value
switches 0:0e018d759a2a 326 */
switches 0:0e018d759a2a 327 #ifndef __NO_EMBEDDED_ASM
switches 0:0e018d759a2a 328 __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
switches 0:0e018d759a2a 329 {
switches 0:0e018d759a2a 330 rrx r0, r0
switches 0:0e018d759a2a 331 bx lr
switches 0:0e018d759a2a 332 }
switches 0:0e018d759a2a 333 #endif
switches 0:0e018d759a2a 334
switches 0:0e018d759a2a 335
switches 0:0e018d759a2a 336 /** \brief LDRT Unprivileged (8 bit)
switches 0:0e018d759a2a 337
switches 0:0e018d759a2a 338 This function executes a Unprivileged LDRT instruction for 8 bit value.
switches 0:0e018d759a2a 339
switches 0:0e018d759a2a 340 \param [in] ptr Pointer to data
switches 0:0e018d759a2a 341 \return value of type uint8_t at (*ptr)
switches 0:0e018d759a2a 342 */
switches 0:0e018d759a2a 343 #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
switches 0:0e018d759a2a 344
switches 0:0e018d759a2a 345
switches 0:0e018d759a2a 346 /** \brief LDRT Unprivileged (16 bit)
switches 0:0e018d759a2a 347
switches 0:0e018d759a2a 348 This function executes a Unprivileged LDRT instruction for 16 bit values.
switches 0:0e018d759a2a 349
switches 0:0e018d759a2a 350 \param [in] ptr Pointer to data
switches 0:0e018d759a2a 351 \return value of type uint16_t at (*ptr)
switches 0:0e018d759a2a 352 */
switches 0:0e018d759a2a 353 #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
switches 0:0e018d759a2a 354
switches 0:0e018d759a2a 355
switches 0:0e018d759a2a 356 /** \brief LDRT Unprivileged (32 bit)
switches 0:0e018d759a2a 357
switches 0:0e018d759a2a 358 This function executes a Unprivileged LDRT instruction for 32 bit values.
switches 0:0e018d759a2a 359
switches 0:0e018d759a2a 360 \param [in] ptr Pointer to data
switches 0:0e018d759a2a 361 \return value of type uint32_t at (*ptr)
switches 0:0e018d759a2a 362 */
switches 0:0e018d759a2a 363 #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
switches 0:0e018d759a2a 364
switches 0:0e018d759a2a 365
switches 0:0e018d759a2a 366 /** \brief STRT Unprivileged (8 bit)
switches 0:0e018d759a2a 367
switches 0:0e018d759a2a 368 This function executes a Unprivileged STRT instruction for 8 bit values.
switches 0:0e018d759a2a 369
switches 0:0e018d759a2a 370 \param [in] value Value to store
switches 0:0e018d759a2a 371 \param [in] ptr Pointer to location
switches 0:0e018d759a2a 372 */
switches 0:0e018d759a2a 373 #define __STRBT(value, ptr) __strt(value, ptr)
switches 0:0e018d759a2a 374
switches 0:0e018d759a2a 375
switches 0:0e018d759a2a 376 /** \brief STRT Unprivileged (16 bit)
switches 0:0e018d759a2a 377
switches 0:0e018d759a2a 378 This function executes a Unprivileged STRT instruction for 16 bit values.
switches 0:0e018d759a2a 379
switches 0:0e018d759a2a 380 \param [in] value Value to store
switches 0:0e018d759a2a 381 \param [in] ptr Pointer to location
switches 0:0e018d759a2a 382 */
switches 0:0e018d759a2a 383 #define __STRHT(value, ptr) __strt(value, ptr)
switches 0:0e018d759a2a 384
switches 0:0e018d759a2a 385
switches 0:0e018d759a2a 386 /** \brief STRT Unprivileged (32 bit)
switches 0:0e018d759a2a 387
switches 0:0e018d759a2a 388 This function executes a Unprivileged STRT instruction for 32 bit values.
switches 0:0e018d759a2a 389
switches 0:0e018d759a2a 390 \param [in] value Value to store
switches 0:0e018d759a2a 391 \param [in] ptr Pointer to location
switches 0:0e018d759a2a 392 */
switches 0:0e018d759a2a 393 #define __STRT(value, ptr) __strt(value, ptr)
switches 0:0e018d759a2a 394
switches 0:0e018d759a2a 395 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
switches 0:0e018d759a2a 396
switches 0:0e018d759a2a 397
switches 0:0e018d759a2a 398 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
switches 0:0e018d759a2a 399 /* GNU gcc specific functions */
switches 0:0e018d759a2a 400
switches 0:0e018d759a2a 401 /* Define macros for porting to both thumb1 and thumb2.
switches 0:0e018d759a2a 402 * For thumb1, use low register (r0-r7), specified by constrant "l"
switches 0:0e018d759a2a 403 * Otherwise, use general registers, specified by constrant "r" */
switches 0:0e018d759a2a 404 #if defined (__thumb__) && !defined (__thumb2__)
switches 0:0e018d759a2a 405 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
switches 0:0e018d759a2a 406 #define __CMSIS_GCC_USE_REG(r) "l" (r)
switches 0:0e018d759a2a 407 #else
switches 0:0e018d759a2a 408 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
switches 0:0e018d759a2a 409 #define __CMSIS_GCC_USE_REG(r) "r" (r)
switches 0:0e018d759a2a 410 #endif
switches 0:0e018d759a2a 411
switches 0:0e018d759a2a 412 /** \brief No Operation
switches 0:0e018d759a2a 413
switches 0:0e018d759a2a 414 No Operation does nothing. This instruction can be used for code alignment purposes.
switches 0:0e018d759a2a 415 */
switches 0:0e018d759a2a 416 __attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
switches 0:0e018d759a2a 417 {
switches 0:0e018d759a2a 418 __ASM volatile ("nop");
switches 0:0e018d759a2a 419 }
switches 0:0e018d759a2a 420
switches 0:0e018d759a2a 421
switches 0:0e018d759a2a 422 /** \brief Wait For Interrupt
switches 0:0e018d759a2a 423
switches 0:0e018d759a2a 424 Wait For Interrupt is a hint instruction that suspends execution
switches 0:0e018d759a2a 425 until one of a number of events occurs.
switches 0:0e018d759a2a 426 */
switches 0:0e018d759a2a 427 __attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
switches 0:0e018d759a2a 428 {
switches 0:0e018d759a2a 429 __ASM volatile ("wfi");
switches 0:0e018d759a2a 430 }
switches 0:0e018d759a2a 431
switches 0:0e018d759a2a 432
switches 0:0e018d759a2a 433 /** \brief Wait For Event
switches 0:0e018d759a2a 434
switches 0:0e018d759a2a 435 Wait For Event is a hint instruction that permits the processor to enter
switches 0:0e018d759a2a 436 a low-power state until one of a number of events occurs.
switches 0:0e018d759a2a 437 */
switches 0:0e018d759a2a 438 __attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
switches 0:0e018d759a2a 439 {
switches 0:0e018d759a2a 440 __ASM volatile ("wfe");
switches 0:0e018d759a2a 441 }
switches 0:0e018d759a2a 442
switches 0:0e018d759a2a 443
switches 0:0e018d759a2a 444 /** \brief Send Event
switches 0:0e018d759a2a 445
switches 0:0e018d759a2a 446 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
switches 0:0e018d759a2a 447 */
switches 0:0e018d759a2a 448 __attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
switches 0:0e018d759a2a 449 {
switches 0:0e018d759a2a 450 __ASM volatile ("sev");
switches 0:0e018d759a2a 451 }
switches 0:0e018d759a2a 452
switches 0:0e018d759a2a 453
switches 0:0e018d759a2a 454 /** \brief Instruction Synchronization Barrier
switches 0:0e018d759a2a 455
switches 0:0e018d759a2a 456 Instruction Synchronization Barrier flushes the pipeline in the processor,
switches 0:0e018d759a2a 457 so that all instructions following the ISB are fetched from cache or
switches 0:0e018d759a2a 458 memory, after the instruction has been completed.
switches 0:0e018d759a2a 459 */
switches 0:0e018d759a2a 460 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
switches 0:0e018d759a2a 461 {
switches 0:0e018d759a2a 462 __ASM volatile ("isb 0xF":::"memory");
switches 0:0e018d759a2a 463 }
switches 0:0e018d759a2a 464
switches 0:0e018d759a2a 465
switches 0:0e018d759a2a 466 /** \brief Data Synchronization Barrier
switches 0:0e018d759a2a 467
switches 0:0e018d759a2a 468 This function acts as a special kind of Data Memory Barrier.
switches 0:0e018d759a2a 469 It completes when all explicit memory accesses before this instruction complete.
switches 0:0e018d759a2a 470 */
switches 0:0e018d759a2a 471 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
switches 0:0e018d759a2a 472 {
switches 0:0e018d759a2a 473 __ASM volatile ("dsb 0xF":::"memory");
switches 0:0e018d759a2a 474 }
switches 0:0e018d759a2a 475
switches 0:0e018d759a2a 476
switches 0:0e018d759a2a 477 /** \brief Data Memory Barrier
switches 0:0e018d759a2a 478
switches 0:0e018d759a2a 479 This function ensures the apparent order of the explicit memory operations before
switches 0:0e018d759a2a 480 and after the instruction, without ensuring their completion.
switches 0:0e018d759a2a 481 */
switches 0:0e018d759a2a 482 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
switches 0:0e018d759a2a 483 {
switches 0:0e018d759a2a 484 __ASM volatile ("dmb 0xF":::"memory");
switches 0:0e018d759a2a 485 }
switches 0:0e018d759a2a 486
switches 0:0e018d759a2a 487
switches 0:0e018d759a2a 488 /** \brief Reverse byte order (32 bit)
switches 0:0e018d759a2a 489
switches 0:0e018d759a2a 490 This function reverses the byte order in integer value.
switches 0:0e018d759a2a 491
switches 0:0e018d759a2a 492 \param [in] value Value to reverse
switches 0:0e018d759a2a 493 \return Reversed value
switches 0:0e018d759a2a 494 */
switches 0:0e018d759a2a 495 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
switches 0:0e018d759a2a 496 {
switches 0:0e018d759a2a 497 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
switches 0:0e018d759a2a 498 return __builtin_bswap32(value);
switches 0:0e018d759a2a 499 #else
switches 0:0e018d759a2a 500 uint32_t result;
switches 0:0e018d759a2a 501
switches 0:0e018d759a2a 502 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
switches 0:0e018d759a2a 503 return(result);
switches 0:0e018d759a2a 504 #endif
switches 0:0e018d759a2a 505 }
switches 0:0e018d759a2a 506
switches 0:0e018d759a2a 507
switches 0:0e018d759a2a 508 /** \brief Reverse byte order (16 bit)
switches 0:0e018d759a2a 509
switches 0:0e018d759a2a 510 This function reverses the byte order in two unsigned short values.
switches 0:0e018d759a2a 511
switches 0:0e018d759a2a 512 \param [in] value Value to reverse
switches 0:0e018d759a2a 513 \return Reversed value
switches 0:0e018d759a2a 514 */
switches 0:0e018d759a2a 515 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
switches 0:0e018d759a2a 516 {
switches 0:0e018d759a2a 517 uint32_t result;
switches 0:0e018d759a2a 518
switches 0:0e018d759a2a 519 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
switches 0:0e018d759a2a 520 return(result);
switches 0:0e018d759a2a 521 }
switches 0:0e018d759a2a 522
switches 0:0e018d759a2a 523
switches 0:0e018d759a2a 524 /** \brief Reverse byte order in signed short value
switches 0:0e018d759a2a 525
switches 0:0e018d759a2a 526 This function reverses the byte order in a signed short value with sign extension to integer.
switches 0:0e018d759a2a 527
switches 0:0e018d759a2a 528 \param [in] value Value to reverse
switches 0:0e018d759a2a 529 \return Reversed value
switches 0:0e018d759a2a 530 */
switches 0:0e018d759a2a 531 __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
switches 0:0e018d759a2a 532 {
switches 0:0e018d759a2a 533 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
switches 0:0e018d759a2a 534 return (short)__builtin_bswap16(value);
switches 0:0e018d759a2a 535 #else
switches 0:0e018d759a2a 536 uint32_t result;
switches 0:0e018d759a2a 537
switches 0:0e018d759a2a 538 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
switches 0:0e018d759a2a 539 return(result);
switches 0:0e018d759a2a 540 #endif
switches 0:0e018d759a2a 541 }
switches 0:0e018d759a2a 542
switches 0:0e018d759a2a 543
switches 0:0e018d759a2a 544 /** \brief Rotate Right in unsigned value (32 bit)
switches 0:0e018d759a2a 545
switches 0:0e018d759a2a 546 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
switches 0:0e018d759a2a 547
switches 0:0e018d759a2a 548 \param [in] value Value to rotate
switches 0:0e018d759a2a 549 \param [in] value Number of Bits to rotate
switches 0:0e018d759a2a 550 \return Rotated value
switches 0:0e018d759a2a 551 */
switches 0:0e018d759a2a 552 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
switches 0:0e018d759a2a 553 {
switches 0:0e018d759a2a 554 return (op1 >> op2) | (op1 << (32 - op2));
switches 0:0e018d759a2a 555 }
switches 0:0e018d759a2a 556
switches 0:0e018d759a2a 557
switches 0:0e018d759a2a 558 /** \brief Breakpoint
switches 0:0e018d759a2a 559
switches 0:0e018d759a2a 560 This function causes the processor to enter Debug state.
switches 0:0e018d759a2a 561 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
switches 0:0e018d759a2a 562
switches 0:0e018d759a2a 563 \param [in] value is ignored by the processor.
switches 0:0e018d759a2a 564 If required, a debugger can use it to store additional information about the breakpoint.
switches 0:0e018d759a2a 565 */
switches 0:0e018d759a2a 566 #define __BKPT(value) __ASM volatile ("bkpt "#value)
switches 0:0e018d759a2a 567
switches 0:0e018d759a2a 568
switches 0:0e018d759a2a 569 /** \brief Reverse bit order of value
switches 0:0e018d759a2a 570
switches 0:0e018d759a2a 571 This function reverses the bit order of the given value.
switches 0:0e018d759a2a 572
switches 0:0e018d759a2a 573 \param [in] value Value to reverse
switches 0:0e018d759a2a 574 \return Reversed value
switches 0:0e018d759a2a 575 */
switches 0:0e018d759a2a 576 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
switches 0:0e018d759a2a 577 {
switches 0:0e018d759a2a 578 uint32_t result;
switches 0:0e018d759a2a 579
switches 0:0e018d759a2a 580 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
switches 0:0e018d759a2a 581 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
switches 0:0e018d759a2a 582 #else
switches 0:0e018d759a2a 583 int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
switches 0:0e018d759a2a 584
switches 0:0e018d759a2a 585 result = value; // r will be reversed bits of v; first get LSB of v
switches 0:0e018d759a2a 586 for (value >>= 1; value; value >>= 1)
switches 0:0e018d759a2a 587 {
switches 0:0e018d759a2a 588 result <<= 1;
switches 0:0e018d759a2a 589 result |= value & 1;
switches 0:0e018d759a2a 590 s--;
switches 0:0e018d759a2a 591 }
switches 0:0e018d759a2a 592 result <<= s; // shift when v's highest bits are zero
switches 0:0e018d759a2a 593 #endif
switches 0:0e018d759a2a 594 return(result);
switches 0:0e018d759a2a 595 }
switches 0:0e018d759a2a 596
switches 0:0e018d759a2a 597
switches 0:0e018d759a2a 598 /** \brief Count leading zeros
switches 0:0e018d759a2a 599
switches 0:0e018d759a2a 600 This function counts the number of leading zeros of a data value.
switches 0:0e018d759a2a 601
switches 0:0e018d759a2a 602 \param [in] value Value to count the leading zeros
switches 0:0e018d759a2a 603 \return number of leading zeros in value
switches 0:0e018d759a2a 604 */
switches 0:0e018d759a2a 605 #define __CLZ __builtin_clz
switches 0:0e018d759a2a 606
switches 0:0e018d759a2a 607
switches 0:0e018d759a2a 608 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
switches 0:0e018d759a2a 609
switches 0:0e018d759a2a 610 /** \brief LDR Exclusive (8 bit)
switches 0:0e018d759a2a 611
switches 0:0e018d759a2a 612 This function executes a exclusive LDR instruction for 8 bit value.
switches 0:0e018d759a2a 613
switches 0:0e018d759a2a 614 \param [in] ptr Pointer to data
switches 0:0e018d759a2a 615 \return value of type uint8_t at (*ptr)
switches 0:0e018d759a2a 616 */
switches 0:0e018d759a2a 617 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
switches 0:0e018d759a2a 618 {
switches 0:0e018d759a2a 619 uint32_t result;
switches 0:0e018d759a2a 620
switches 0:0e018d759a2a 621 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
switches 0:0e018d759a2a 622 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
switches 0:0e018d759a2a 623 #else
switches 0:0e018d759a2a 624 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
switches 0:0e018d759a2a 625 accepted by assembler. So has to use following less efficient pattern.
switches 0:0e018d759a2a 626 */
switches 0:0e018d759a2a 627 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
switches 0:0e018d759a2a 628 #endif
switches 0:0e018d759a2a 629 return ((uint8_t) result); /* Add explicit type cast here */
switches 0:0e018d759a2a 630 }
switches 0:0e018d759a2a 631
switches 0:0e018d759a2a 632
switches 0:0e018d759a2a 633 /** \brief LDR Exclusive (16 bit)
switches 0:0e018d759a2a 634
switches 0:0e018d759a2a 635 This function executes a exclusive LDR instruction for 16 bit values.
switches 0:0e018d759a2a 636
switches 0:0e018d759a2a 637 \param [in] ptr Pointer to data
switches 0:0e018d759a2a 638 \return value of type uint16_t at (*ptr)
switches 0:0e018d759a2a 639 */
switches 0:0e018d759a2a 640 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
switches 0:0e018d759a2a 641 {
switches 0:0e018d759a2a 642 uint32_t result;
switches 0:0e018d759a2a 643
switches 0:0e018d759a2a 644 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
switches 0:0e018d759a2a 645 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
switches 0:0e018d759a2a 646 #else
switches 0:0e018d759a2a 647 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
switches 0:0e018d759a2a 648 accepted by assembler. So has to use following less efficient pattern.
switches 0:0e018d759a2a 649 */
switches 0:0e018d759a2a 650 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
switches 0:0e018d759a2a 651 #endif
switches 0:0e018d759a2a 652 return ((uint16_t) result); /* Add explicit type cast here */
switches 0:0e018d759a2a 653 }
switches 0:0e018d759a2a 654
switches 0:0e018d759a2a 655
switches 0:0e018d759a2a 656 /** \brief LDR Exclusive (32 bit)
switches 0:0e018d759a2a 657
switches 0:0e018d759a2a 658 This function executes a exclusive LDR instruction for 32 bit values.
switches 0:0e018d759a2a 659
switches 0:0e018d759a2a 660 \param [in] ptr Pointer to data
switches 0:0e018d759a2a 661 \return value of type uint32_t at (*ptr)
switches 0:0e018d759a2a 662 */
switches 0:0e018d759a2a 663 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
switches 0:0e018d759a2a 664 {
switches 0:0e018d759a2a 665 uint32_t result;
switches 0:0e018d759a2a 666
switches 0:0e018d759a2a 667 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
switches 0:0e018d759a2a 668 return(result);
switches 0:0e018d759a2a 669 }
switches 0:0e018d759a2a 670
switches 0:0e018d759a2a 671
switches 0:0e018d759a2a 672 /** \brief STR Exclusive (8 bit)
switches 0:0e018d759a2a 673
switches 0:0e018d759a2a 674 This function executes a exclusive STR instruction for 8 bit values.
switches 0:0e018d759a2a 675
switches 0:0e018d759a2a 676 \param [in] value Value to store
switches 0:0e018d759a2a 677 \param [in] ptr Pointer to location
switches 0:0e018d759a2a 678 \return 0 Function succeeded
switches 0:0e018d759a2a 679 \return 1 Function failed
switches 0:0e018d759a2a 680 */
switches 0:0e018d759a2a 681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
switches 0:0e018d759a2a 682 {
switches 0:0e018d759a2a 683 uint32_t result;
switches 0:0e018d759a2a 684
switches 0:0e018d759a2a 685 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
switches 0:0e018d759a2a 686 return(result);
switches 0:0e018d759a2a 687 }
switches 0:0e018d759a2a 688
switches 0:0e018d759a2a 689
switches 0:0e018d759a2a 690 /** \brief STR Exclusive (16 bit)
switches 0:0e018d759a2a 691
switches 0:0e018d759a2a 692 This function executes a exclusive STR instruction for 16 bit values.
switches 0:0e018d759a2a 693
switches 0:0e018d759a2a 694 \param [in] value Value to store
switches 0:0e018d759a2a 695 \param [in] ptr Pointer to location
switches 0:0e018d759a2a 696 \return 0 Function succeeded
switches 0:0e018d759a2a 697 \return 1 Function failed
switches 0:0e018d759a2a 698 */
switches 0:0e018d759a2a 699 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
switches 0:0e018d759a2a 700 {
switches 0:0e018d759a2a 701 uint32_t result;
switches 0:0e018d759a2a 702
switches 0:0e018d759a2a 703 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
switches 0:0e018d759a2a 704 return(result);
switches 0:0e018d759a2a 705 }
switches 0:0e018d759a2a 706
switches 0:0e018d759a2a 707
switches 0:0e018d759a2a 708 /** \brief STR Exclusive (32 bit)
switches 0:0e018d759a2a 709
switches 0:0e018d759a2a 710 This function executes a exclusive STR instruction for 32 bit values.
switches 0:0e018d759a2a 711
switches 0:0e018d759a2a 712 \param [in] value Value to store
switches 0:0e018d759a2a 713 \param [in] ptr Pointer to location
switches 0:0e018d759a2a 714 \return 0 Function succeeded
switches 0:0e018d759a2a 715 \return 1 Function failed
switches 0:0e018d759a2a 716 */
switches 0:0e018d759a2a 717 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
switches 0:0e018d759a2a 718 {
switches 0:0e018d759a2a 719 uint32_t result;
switches 0:0e018d759a2a 720
switches 0:0e018d759a2a 721 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
switches 0:0e018d759a2a 722 return(result);
switches 0:0e018d759a2a 723 }
switches 0:0e018d759a2a 724
switches 0:0e018d759a2a 725
switches 0:0e018d759a2a 726 /** \brief Remove the exclusive lock
switches 0:0e018d759a2a 727
switches 0:0e018d759a2a 728 This function removes the exclusive lock which is created by LDREX.
switches 0:0e018d759a2a 729
switches 0:0e018d759a2a 730 */
switches 0:0e018d759a2a 731 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
switches 0:0e018d759a2a 732 {
switches 0:0e018d759a2a 733 __ASM volatile ("clrex" ::: "memory");
switches 0:0e018d759a2a 734 }
switches 0:0e018d759a2a 735
switches 0:0e018d759a2a 736
switches 0:0e018d759a2a 737 /** \brief Signed Saturate
switches 0:0e018d759a2a 738
switches 0:0e018d759a2a 739 This function saturates a signed value.
switches 0:0e018d759a2a 740
switches 0:0e018d759a2a 741 \param [in] value Value to be saturated
switches 0:0e018d759a2a 742 \param [in] sat Bit position to saturate to (1..32)
switches 0:0e018d759a2a 743 \return Saturated value
switches 0:0e018d759a2a 744 */
switches 0:0e018d759a2a 745 #define __SSAT(ARG1,ARG2) \
switches 0:0e018d759a2a 746 ({ \
switches 0:0e018d759a2a 747 uint32_t __RES, __ARG1 = (ARG1); \
switches 0:0e018d759a2a 748 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
switches 0:0e018d759a2a 749 __RES; \
switches 0:0e018d759a2a 750 })
switches 0:0e018d759a2a 751
switches 0:0e018d759a2a 752
switches 0:0e018d759a2a 753 /** \brief Unsigned Saturate
switches 0:0e018d759a2a 754
switches 0:0e018d759a2a 755 This function saturates an unsigned value.
switches 0:0e018d759a2a 756
switches 0:0e018d759a2a 757 \param [in] value Value to be saturated
switches 0:0e018d759a2a 758 \param [in] sat Bit position to saturate to (0..31)
switches 0:0e018d759a2a 759 \return Saturated value
switches 0:0e018d759a2a 760 */
switches 0:0e018d759a2a 761 #define __USAT(ARG1,ARG2) \
switches 0:0e018d759a2a 762 ({ \
switches 0:0e018d759a2a 763 uint32_t __RES, __ARG1 = (ARG1); \
switches 0:0e018d759a2a 764 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
switches 0:0e018d759a2a 765 __RES; \
switches 0:0e018d759a2a 766 })
switches 0:0e018d759a2a 767
switches 0:0e018d759a2a 768
switches 0:0e018d759a2a 769 /** \brief Rotate Right with Extend (32 bit)
switches 0:0e018d759a2a 770
switches 0:0e018d759a2a 771 This function moves each bit of a bitstring right by one bit.
switches 0:0e018d759a2a 772 The carry input is shifted in at the left end of the bitstring.
switches 0:0e018d759a2a 773
switches 0:0e018d759a2a 774 \param [in] value Value to rotate
switches 0:0e018d759a2a 775 \return Rotated value
switches 0:0e018d759a2a 776 */
switches 0:0e018d759a2a 777 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
switches 0:0e018d759a2a 778 {
switches 0:0e018d759a2a 779 uint32_t result;
switches 0:0e018d759a2a 780
switches 0:0e018d759a2a 781 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
switches 0:0e018d759a2a 782 return(result);
switches 0:0e018d759a2a 783 }
switches 0:0e018d759a2a 784
switches 0:0e018d759a2a 785
switches 0:0e018d759a2a 786 /** \brief LDRT Unprivileged (8 bit)
switches 0:0e018d759a2a 787
switches 0:0e018d759a2a 788 This function executes a Unprivileged LDRT instruction for 8 bit value.
switches 0:0e018d759a2a 789
switches 0:0e018d759a2a 790 \param [in] ptr Pointer to data
switches 0:0e018d759a2a 791 \return value of type uint8_t at (*ptr)
switches 0:0e018d759a2a 792 */
switches 0:0e018d759a2a 793 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
switches 0:0e018d759a2a 794 {
switches 0:0e018d759a2a 795 uint32_t result;
switches 0:0e018d759a2a 796
switches 0:0e018d759a2a 797 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
switches 0:0e018d759a2a 798 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
switches 0:0e018d759a2a 799 #else
switches 0:0e018d759a2a 800 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
switches 0:0e018d759a2a 801 accepted by assembler. So has to use following less efficient pattern.
switches 0:0e018d759a2a 802 */
switches 0:0e018d759a2a 803 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
switches 0:0e018d759a2a 804 #endif
switches 0:0e018d759a2a 805 return ((uint8_t) result); /* Add explicit type cast here */
switches 0:0e018d759a2a 806 }
switches 0:0e018d759a2a 807
switches 0:0e018d759a2a 808
switches 0:0e018d759a2a 809 /** \brief LDRT Unprivileged (16 bit)
switches 0:0e018d759a2a 810
switches 0:0e018d759a2a 811 This function executes a Unprivileged LDRT instruction for 16 bit values.
switches 0:0e018d759a2a 812
switches 0:0e018d759a2a 813 \param [in] ptr Pointer to data
switches 0:0e018d759a2a 814 \return value of type uint16_t at (*ptr)
switches 0:0e018d759a2a 815 */
switches 0:0e018d759a2a 816 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
switches 0:0e018d759a2a 817 {
switches 0:0e018d759a2a 818 uint32_t result;
switches 0:0e018d759a2a 819
switches 0:0e018d759a2a 820 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
switches 0:0e018d759a2a 821 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
switches 0:0e018d759a2a 822 #else
switches 0:0e018d759a2a 823 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
switches 0:0e018d759a2a 824 accepted by assembler. So has to use following less efficient pattern.
switches 0:0e018d759a2a 825 */
switches 0:0e018d759a2a 826 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
switches 0:0e018d759a2a 827 #endif
switches 0:0e018d759a2a 828 return ((uint16_t) result); /* Add explicit type cast here */
switches 0:0e018d759a2a 829 }
switches 0:0e018d759a2a 830
switches 0:0e018d759a2a 831
switches 0:0e018d759a2a 832 /** \brief LDRT Unprivileged (32 bit)
switches 0:0e018d759a2a 833
switches 0:0e018d759a2a 834 This function executes a Unprivileged LDRT instruction for 32 bit values.
switches 0:0e018d759a2a 835
switches 0:0e018d759a2a 836 \param [in] ptr Pointer to data
switches 0:0e018d759a2a 837 \return value of type uint32_t at (*ptr)
switches 0:0e018d759a2a 838 */
switches 0:0e018d759a2a 839 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
switches 0:0e018d759a2a 840 {
switches 0:0e018d759a2a 841 uint32_t result;
switches 0:0e018d759a2a 842
switches 0:0e018d759a2a 843 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
switches 0:0e018d759a2a 844 return(result);
switches 0:0e018d759a2a 845 }
switches 0:0e018d759a2a 846
switches 0:0e018d759a2a 847
switches 0:0e018d759a2a 848 /** \brief STRT Unprivileged (8 bit)
switches 0:0e018d759a2a 849
switches 0:0e018d759a2a 850 This function executes a Unprivileged STRT instruction for 8 bit values.
switches 0:0e018d759a2a 851
switches 0:0e018d759a2a 852 \param [in] value Value to store
switches 0:0e018d759a2a 853 \param [in] ptr Pointer to location
switches 0:0e018d759a2a 854 */
switches 0:0e018d759a2a 855 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
switches 0:0e018d759a2a 856 {
switches 0:0e018d759a2a 857 __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
switches 0:0e018d759a2a 858 }
switches 0:0e018d759a2a 859
switches 0:0e018d759a2a 860
switches 0:0e018d759a2a 861 /** \brief STRT Unprivileged (16 bit)
switches 0:0e018d759a2a 862
switches 0:0e018d759a2a 863 This function executes a Unprivileged STRT instruction for 16 bit values.
switches 0:0e018d759a2a 864
switches 0:0e018d759a2a 865 \param [in] value Value to store
switches 0:0e018d759a2a 866 \param [in] ptr Pointer to location
switches 0:0e018d759a2a 867 */
switches 0:0e018d759a2a 868 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
switches 0:0e018d759a2a 869 {
switches 0:0e018d759a2a 870 __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
switches 0:0e018d759a2a 871 }
switches 0:0e018d759a2a 872
switches 0:0e018d759a2a 873
switches 0:0e018d759a2a 874 /** \brief STRT Unprivileged (32 bit)
switches 0:0e018d759a2a 875
switches 0:0e018d759a2a 876 This function executes a Unprivileged STRT instruction for 32 bit values.
switches 0:0e018d759a2a 877
switches 0:0e018d759a2a 878 \param [in] value Value to store
switches 0:0e018d759a2a 879 \param [in] ptr Pointer to location
switches 0:0e018d759a2a 880 */
switches 0:0e018d759a2a 881 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
switches 0:0e018d759a2a 882 {
switches 0:0e018d759a2a 883 __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
switches 0:0e018d759a2a 884 }
switches 0:0e018d759a2a 885
switches 0:0e018d759a2a 886 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
switches 0:0e018d759a2a 887
switches 0:0e018d759a2a 888
switches 0:0e018d759a2a 889 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
switches 0:0e018d759a2a 890 /* IAR iccarm specific functions */
switches 0:0e018d759a2a 891 #include <cmsis_iar.h>
switches 0:0e018d759a2a 892
switches 0:0e018d759a2a 893
switches 0:0e018d759a2a 894 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
switches 0:0e018d759a2a 895 /* TI CCS specific functions */
switches 0:0e018d759a2a 896 #include <cmsis_ccs.h>
switches 0:0e018d759a2a 897
switches 0:0e018d759a2a 898
switches 0:0e018d759a2a 899 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
switches 0:0e018d759a2a 900 /* TASKING carm specific functions */
switches 0:0e018d759a2a 901 /*
switches 0:0e018d759a2a 902 * The CMSIS functions have been implemented as intrinsics in the compiler.
switches 0:0e018d759a2a 903 * Please use "carm -?i" to get an up to date list of all intrinsics,
switches 0:0e018d759a2a 904 * Including the CMSIS ones.
switches 0:0e018d759a2a 905 */
switches 0:0e018d759a2a 906
switches 0:0e018d759a2a 907
switches 0:0e018d759a2a 908 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
switches 0:0e018d759a2a 909 /* Cosmic specific functions */
switches 0:0e018d759a2a 910 #include <cmsis_csm.h>
switches 0:0e018d759a2a 911
switches 0:0e018d759a2a 912 #endif
switches 0:0e018d759a2a 913
switches 0:0e018d759a2a 914 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
switches 0:0e018d759a2a 915
switches 0:0e018d759a2a 916 #endif /* __CORE_CMINSTR_H */