Greg Steiert / maxim_dev

Maxim mbed development library

Dependents:   sensomed

cmsis/core_cmFunc.h@0:0e018d759a2a, 2016-11-08 (annotated)

Committer:
switches
Date:
Tue Nov 08 18:27:11 2016 +0000
Revision:
0:0e018d759a2a
Initial commit

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switches 0:0e018d759a2a 1 /**************************************************************************//**
switches 0:0e018d759a2a 2 * @file core_cmFunc.h
switches 0:0e018d759a2a 3 * @brief CMSIS Cortex-M Core Function Access Header File
switches 0:0e018d759a2a 4 * @version V4.10
switches 0:0e018d759a2a 5 * @date 18. March 2015
switches 0:0e018d759a2a 6 *
switches 0:0e018d759a2a 7 * @note
switches 0:0e018d759a2a 8 *
switches 0:0e018d759a2a 9 ******************************************************************************/
switches 0:0e018d759a2a 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
switches 0:0e018d759a2a 11
switches 0:0e018d759a2a 12 All rights reserved.
switches 0:0e018d759a2a 13 Redistribution and use in source and binary forms, with or without
switches 0:0e018d759a2a 14 modification, are permitted provided that the following conditions are met:
switches 0:0e018d759a2a 15 - Redistributions of source code must retain the above copyright
switches 0:0e018d759a2a 16 notice, this list of conditions and the following disclaimer.
switches 0:0e018d759a2a 17 - Redistributions in binary form must reproduce the above copyright
switches 0:0e018d759a2a 18 notice, this list of conditions and the following disclaimer in the
switches 0:0e018d759a2a 19 documentation and/or other materials provided with the distribution.
switches 0:0e018d759a2a 20 - Neither the name of ARM nor the names of its contributors may be used
switches 0:0e018d759a2a 21 to endorse or promote products derived from this software without
switches 0:0e018d759a2a 22 specific prior written permission.
switches 0:0e018d759a2a 23 *
switches 0:0e018d759a2a 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
switches 0:0e018d759a2a 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
switches 0:0e018d759a2a 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
switches 0:0e018d759a2a 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
switches 0:0e018d759a2a 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
switches 0:0e018d759a2a 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
switches 0:0e018d759a2a 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
switches 0:0e018d759a2a 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
switches 0:0e018d759a2a 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
switches 0:0e018d759a2a 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
switches 0:0e018d759a2a 34 POSSIBILITY OF SUCH DAMAGE.
switches 0:0e018d759a2a 35 ---------------------------------------------------------------------------*/
switches 0:0e018d759a2a 36
switches 0:0e018d759a2a 37
switches 0:0e018d759a2a 38 #ifndef __CORE_CMFUNC_H
switches 0:0e018d759a2a 39 #define __CORE_CMFUNC_H
switches 0:0e018d759a2a 40
switches 0:0e018d759a2a 41
switches 0:0e018d759a2a 42 /* ########################### Core Function Access ########################### */
switches 0:0e018d759a2a 43 /** \ingroup CMSIS_Core_FunctionInterface
switches 0:0e018d759a2a 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
switches 0:0e018d759a2a 45 @{
switches 0:0e018d759a2a 46 */
switches 0:0e018d759a2a 47
switches 0:0e018d759a2a 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
switches 0:0e018d759a2a 49 /* ARM armcc specific functions */
switches 0:0e018d759a2a 50
switches 0:0e018d759a2a 51 #if (__ARMCC_VERSION < 400677)
switches 0:0e018d759a2a 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
switches 0:0e018d759a2a 53 #endif
switches 0:0e018d759a2a 54
switches 0:0e018d759a2a 55 /* intrinsic void __enable_irq(); */
switches 0:0e018d759a2a 56 /* intrinsic void __disable_irq(); */
switches 0:0e018d759a2a 57
switches 0:0e018d759a2a 58 /** \brief Get Control Register
switches 0:0e018d759a2a 59
switches 0:0e018d759a2a 60 This function returns the content of the Control Register.
switches 0:0e018d759a2a 61
switches 0:0e018d759a2a 62 \return Control Register value
switches 0:0e018d759a2a 63 */
switches 0:0e018d759a2a 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
switches 0:0e018d759a2a 65 {
switches 0:0e018d759a2a 66 register uint32_t __regControl __ASM("control");
switches 0:0e018d759a2a 67 return(__regControl);
switches 0:0e018d759a2a 68 }
switches 0:0e018d759a2a 69
switches 0:0e018d759a2a 70
switches 0:0e018d759a2a 71 /** \brief Set Control Register
switches 0:0e018d759a2a 72
switches 0:0e018d759a2a 73 This function writes the given value to the Control Register.
switches 0:0e018d759a2a 74
switches 0:0e018d759a2a 75 \param [in] control Control Register value to set
switches 0:0e018d759a2a 76 */
switches 0:0e018d759a2a 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
switches 0:0e018d759a2a 78 {
switches 0:0e018d759a2a 79 register uint32_t __regControl __ASM("control");
switches 0:0e018d759a2a 80 __regControl = control;
switches 0:0e018d759a2a 81 }
switches 0:0e018d759a2a 82
switches 0:0e018d759a2a 83
switches 0:0e018d759a2a 84 /** \brief Get IPSR Register
switches 0:0e018d759a2a 85
switches 0:0e018d759a2a 86 This function returns the content of the IPSR Register.
switches 0:0e018d759a2a 87
switches 0:0e018d759a2a 88 \return IPSR Register value
switches 0:0e018d759a2a 89 */
switches 0:0e018d759a2a 90 __STATIC_INLINE uint32_t __get_IPSR(void)
switches 0:0e018d759a2a 91 {
switches 0:0e018d759a2a 92 register uint32_t __regIPSR __ASM("ipsr");
switches 0:0e018d759a2a 93 return(__regIPSR);
switches 0:0e018d759a2a 94 }
switches 0:0e018d759a2a 95
switches 0:0e018d759a2a 96
switches 0:0e018d759a2a 97 /** \brief Get APSR Register
switches 0:0e018d759a2a 98
switches 0:0e018d759a2a 99 This function returns the content of the APSR Register.
switches 0:0e018d759a2a 100
switches 0:0e018d759a2a 101 \return APSR Register value
switches 0:0e018d759a2a 102 */
switches 0:0e018d759a2a 103 __STATIC_INLINE uint32_t __get_APSR(void)
switches 0:0e018d759a2a 104 {
switches 0:0e018d759a2a 105 register uint32_t __regAPSR __ASM("apsr");
switches 0:0e018d759a2a 106 return(__regAPSR);
switches 0:0e018d759a2a 107 }
switches 0:0e018d759a2a 108
switches 0:0e018d759a2a 109
switches 0:0e018d759a2a 110 /** \brief Get xPSR Register
switches 0:0e018d759a2a 111
switches 0:0e018d759a2a 112 This function returns the content of the xPSR Register.
switches 0:0e018d759a2a 113
switches 0:0e018d759a2a 114 \return xPSR Register value
switches 0:0e018d759a2a 115 */
switches 0:0e018d759a2a 116 __STATIC_INLINE uint32_t __get_xPSR(void)
switches 0:0e018d759a2a 117 {
switches 0:0e018d759a2a 118 register uint32_t __regXPSR __ASM("xpsr");
switches 0:0e018d759a2a 119 return(__regXPSR);
switches 0:0e018d759a2a 120 }
switches 0:0e018d759a2a 121
switches 0:0e018d759a2a 122
switches 0:0e018d759a2a 123 /** \brief Get Process Stack Pointer
switches 0:0e018d759a2a 124
switches 0:0e018d759a2a 125 This function returns the current value of the Process Stack Pointer (PSP).
switches 0:0e018d759a2a 126
switches 0:0e018d759a2a 127 \return PSP Register value
switches 0:0e018d759a2a 128 */
switches 0:0e018d759a2a 129 __STATIC_INLINE uint32_t __get_PSP(void)
switches 0:0e018d759a2a 130 {
switches 0:0e018d759a2a 131 register uint32_t __regProcessStackPointer __ASM("psp");
switches 0:0e018d759a2a 132 return(__regProcessStackPointer);
switches 0:0e018d759a2a 133 }
switches 0:0e018d759a2a 134
switches 0:0e018d759a2a 135
switches 0:0e018d759a2a 136 /** \brief Set Process Stack Pointer
switches 0:0e018d759a2a 137
switches 0:0e018d759a2a 138 This function assigns the given value to the Process Stack Pointer (PSP).
switches 0:0e018d759a2a 139
switches 0:0e018d759a2a 140 \param [in] topOfProcStack Process Stack Pointer value to set
switches 0:0e018d759a2a 141 */
switches 0:0e018d759a2a 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
switches 0:0e018d759a2a 143 {
switches 0:0e018d759a2a 144 register uint32_t __regProcessStackPointer __ASM("psp");
switches 0:0e018d759a2a 145 __regProcessStackPointer = topOfProcStack;
switches 0:0e018d759a2a 146 }
switches 0:0e018d759a2a 147
switches 0:0e018d759a2a 148
switches 0:0e018d759a2a 149 /** \brief Get Main Stack Pointer
switches 0:0e018d759a2a 150
switches 0:0e018d759a2a 151 This function returns the current value of the Main Stack Pointer (MSP).
switches 0:0e018d759a2a 152
switches 0:0e018d759a2a 153 \return MSP Register value
switches 0:0e018d759a2a 154 */
switches 0:0e018d759a2a 155 __STATIC_INLINE uint32_t __get_MSP(void)
switches 0:0e018d759a2a 156 {
switches 0:0e018d759a2a 157 register uint32_t __regMainStackPointer __ASM("msp");
switches 0:0e018d759a2a 158 return(__regMainStackPointer);
switches 0:0e018d759a2a 159 }
switches 0:0e018d759a2a 160
switches 0:0e018d759a2a 161
switches 0:0e018d759a2a 162 /** \brief Set Main Stack Pointer
switches 0:0e018d759a2a 163
switches 0:0e018d759a2a 164 This function assigns the given value to the Main Stack Pointer (MSP).
switches 0:0e018d759a2a 165
switches 0:0e018d759a2a 166 \param [in] topOfMainStack Main Stack Pointer value to set
switches 0:0e018d759a2a 167 */
switches 0:0e018d759a2a 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
switches 0:0e018d759a2a 169 {
switches 0:0e018d759a2a 170 register uint32_t __regMainStackPointer __ASM("msp");
switches 0:0e018d759a2a 171 __regMainStackPointer = topOfMainStack;
switches 0:0e018d759a2a 172 }
switches 0:0e018d759a2a 173
switches 0:0e018d759a2a 174
switches 0:0e018d759a2a 175 /** \brief Get Priority Mask
switches 0:0e018d759a2a 176
switches 0:0e018d759a2a 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
switches 0:0e018d759a2a 178
switches 0:0e018d759a2a 179 \return Priority Mask value
switches 0:0e018d759a2a 180 */
switches 0:0e018d759a2a 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
switches 0:0e018d759a2a 182 {
switches 0:0e018d759a2a 183 register uint32_t __regPriMask __ASM("primask");
switches 0:0e018d759a2a 184 return(__regPriMask);
switches 0:0e018d759a2a 185 }
switches 0:0e018d759a2a 186
switches 0:0e018d759a2a 187
switches 0:0e018d759a2a 188 /** \brief Set Priority Mask
switches 0:0e018d759a2a 189
switches 0:0e018d759a2a 190 This function assigns the given value to the Priority Mask Register.
switches 0:0e018d759a2a 191
switches 0:0e018d759a2a 192 \param [in] priMask Priority Mask
switches 0:0e018d759a2a 193 */
switches 0:0e018d759a2a 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
switches 0:0e018d759a2a 195 {
switches 0:0e018d759a2a 196 register uint32_t __regPriMask __ASM("primask");
switches 0:0e018d759a2a 197 __regPriMask = (priMask);
switches 0:0e018d759a2a 198 }
switches 0:0e018d759a2a 199
switches 0:0e018d759a2a 200
switches 0:0e018d759a2a 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
switches 0:0e018d759a2a 202
switches 0:0e018d759a2a 203 /** \brief Enable FIQ
switches 0:0e018d759a2a 204
switches 0:0e018d759a2a 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
switches 0:0e018d759a2a 206 Can only be executed in Privileged modes.
switches 0:0e018d759a2a 207 */
switches 0:0e018d759a2a 208 #define __enable_fault_irq __enable_fiq
switches 0:0e018d759a2a 209
switches 0:0e018d759a2a 210
switches 0:0e018d759a2a 211 /** \brief Disable FIQ
switches 0:0e018d759a2a 212
switches 0:0e018d759a2a 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
switches 0:0e018d759a2a 214 Can only be executed in Privileged modes.
switches 0:0e018d759a2a 215 */
switches 0:0e018d759a2a 216 #define __disable_fault_irq __disable_fiq
switches 0:0e018d759a2a 217
switches 0:0e018d759a2a 218
switches 0:0e018d759a2a 219 /** \brief Get Base Priority
switches 0:0e018d759a2a 220
switches 0:0e018d759a2a 221 This function returns the current value of the Base Priority register.
switches 0:0e018d759a2a 222
switches 0:0e018d759a2a 223 \return Base Priority register value
switches 0:0e018d759a2a 224 */
switches 0:0e018d759a2a 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
switches 0:0e018d759a2a 226 {
switches 0:0e018d759a2a 227 register uint32_t __regBasePri __ASM("basepri");
switches 0:0e018d759a2a 228 return(__regBasePri);
switches 0:0e018d759a2a 229 }
switches 0:0e018d759a2a 230
switches 0:0e018d759a2a 231
switches 0:0e018d759a2a 232 /** \brief Set Base Priority
switches 0:0e018d759a2a 233
switches 0:0e018d759a2a 234 This function assigns the given value to the Base Priority register.
switches 0:0e018d759a2a 235
switches 0:0e018d759a2a 236 \param [in] basePri Base Priority value to set
switches 0:0e018d759a2a 237 */
switches 0:0e018d759a2a 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
switches 0:0e018d759a2a 239 {
switches 0:0e018d759a2a 240 register uint32_t __regBasePri __ASM("basepri");
switches 0:0e018d759a2a 241 __regBasePri = (basePri & 0xff);
switches 0:0e018d759a2a 242 }
switches 0:0e018d759a2a 243
switches 0:0e018d759a2a 244
switches 0:0e018d759a2a 245 /** \brief Set Base Priority with condition
switches 0:0e018d759a2a 246
switches 0:0e018d759a2a 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
switches 0:0e018d759a2a 248 or the new value increases the BASEPRI priority level.
switches 0:0e018d759a2a 249
switches 0:0e018d759a2a 250 \param [in] basePri Base Priority value to set
switches 0:0e018d759a2a 251 */
switches 0:0e018d759a2a 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
switches 0:0e018d759a2a 253 {
switches 0:0e018d759a2a 254 register uint32_t __regBasePriMax __ASM("basepri_max");
switches 0:0e018d759a2a 255 __regBasePriMax = (basePri & 0xff);
switches 0:0e018d759a2a 256 }
switches 0:0e018d759a2a 257
switches 0:0e018d759a2a 258
switches 0:0e018d759a2a 259 /** \brief Get Fault Mask
switches 0:0e018d759a2a 260
switches 0:0e018d759a2a 261 This function returns the current value of the Fault Mask register.
switches 0:0e018d759a2a 262
switches 0:0e018d759a2a 263 \return Fault Mask register value
switches 0:0e018d759a2a 264 */
switches 0:0e018d759a2a 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
switches 0:0e018d759a2a 266 {
switches 0:0e018d759a2a 267 register uint32_t __regFaultMask __ASM("faultmask");
switches 0:0e018d759a2a 268 return(__regFaultMask);
switches 0:0e018d759a2a 269 }
switches 0:0e018d759a2a 270
switches 0:0e018d759a2a 271
switches 0:0e018d759a2a 272 /** \brief Set Fault Mask
switches 0:0e018d759a2a 273
switches 0:0e018d759a2a 274 This function assigns the given value to the Fault Mask register.
switches 0:0e018d759a2a 275
switches 0:0e018d759a2a 276 \param [in] faultMask Fault Mask value to set
switches 0:0e018d759a2a 277 */
switches 0:0e018d759a2a 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
switches 0:0e018d759a2a 279 {
switches 0:0e018d759a2a 280 register uint32_t __regFaultMask __ASM("faultmask");
switches 0:0e018d759a2a 281 __regFaultMask = (faultMask & (uint32_t)1);
switches 0:0e018d759a2a 282 }
switches 0:0e018d759a2a 283
switches 0:0e018d759a2a 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
switches 0:0e018d759a2a 285
switches 0:0e018d759a2a 286
switches 0:0e018d759a2a 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
switches 0:0e018d759a2a 288
switches 0:0e018d759a2a 289 /** \brief Get FPSCR
switches 0:0e018d759a2a 290
switches 0:0e018d759a2a 291 This function returns the current value of the Floating Point Status/Control register.
switches 0:0e018d759a2a 292
switches 0:0e018d759a2a 293 \return Floating Point Status/Control register value
switches 0:0e018d759a2a 294 */
switches 0:0e018d759a2a 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
switches 0:0e018d759a2a 296 {
switches 0:0e018d759a2a 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
switches 0:0e018d759a2a 298 register uint32_t __regfpscr __ASM("fpscr");
switches 0:0e018d759a2a 299 return(__regfpscr);
switches 0:0e018d759a2a 300 #else
switches 0:0e018d759a2a 301 return(0);
switches 0:0e018d759a2a 302 #endif
switches 0:0e018d759a2a 303 }
switches 0:0e018d759a2a 304
switches 0:0e018d759a2a 305
switches 0:0e018d759a2a 306 /** \brief Set FPSCR
switches 0:0e018d759a2a 307
switches 0:0e018d759a2a 308 This function assigns the given value to the Floating Point Status/Control register.
switches 0:0e018d759a2a 309
switches 0:0e018d759a2a 310 \param [in] fpscr Floating Point Status/Control value to set
switches 0:0e018d759a2a 311 */
switches 0:0e018d759a2a 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
switches 0:0e018d759a2a 313 {
switches 0:0e018d759a2a 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
switches 0:0e018d759a2a 315 register uint32_t __regfpscr __ASM("fpscr");
switches 0:0e018d759a2a 316 __regfpscr = (fpscr);
switches 0:0e018d759a2a 317 #endif
switches 0:0e018d759a2a 318 }
switches 0:0e018d759a2a 319
switches 0:0e018d759a2a 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
switches 0:0e018d759a2a 321
switches 0:0e018d759a2a 322
switches 0:0e018d759a2a 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
switches 0:0e018d759a2a 324 /* GNU gcc specific functions */
switches 0:0e018d759a2a 325
switches 0:0e018d759a2a 326 /** \brief Enable IRQ Interrupts
switches 0:0e018d759a2a 327
switches 0:0e018d759a2a 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
switches 0:0e018d759a2a 329 Can only be executed in Privileged modes.
switches 0:0e018d759a2a 330 */
switches 0:0e018d759a2a 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
switches 0:0e018d759a2a 332 {
switches 0:0e018d759a2a 333 __ASM volatile ("cpsie i" : : : "memory");
switches 0:0e018d759a2a 334 }
switches 0:0e018d759a2a 335
switches 0:0e018d759a2a 336
switches 0:0e018d759a2a 337 /** \brief Disable IRQ Interrupts
switches 0:0e018d759a2a 338
switches 0:0e018d759a2a 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
switches 0:0e018d759a2a 340 Can only be executed in Privileged modes.
switches 0:0e018d759a2a 341 */
switches 0:0e018d759a2a 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
switches 0:0e018d759a2a 343 {
switches 0:0e018d759a2a 344 __ASM volatile ("cpsid i" : : : "memory");
switches 0:0e018d759a2a 345 }
switches 0:0e018d759a2a 346
switches 0:0e018d759a2a 347
switches 0:0e018d759a2a 348 /** \brief Get Control Register
switches 0:0e018d759a2a 349
switches 0:0e018d759a2a 350 This function returns the content of the Control Register.
switches 0:0e018d759a2a 351
switches 0:0e018d759a2a 352 \return Control Register value
switches 0:0e018d759a2a 353 */
switches 0:0e018d759a2a 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
switches 0:0e018d759a2a 355 {
switches 0:0e018d759a2a 356 uint32_t result;
switches 0:0e018d759a2a 357
switches 0:0e018d759a2a 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
switches 0:0e018d759a2a 359 return(result);
switches 0:0e018d759a2a 360 }
switches 0:0e018d759a2a 361
switches 0:0e018d759a2a 362
switches 0:0e018d759a2a 363 /** \brief Set Control Register
switches 0:0e018d759a2a 364
switches 0:0e018d759a2a 365 This function writes the given value to the Control Register.
switches 0:0e018d759a2a 366
switches 0:0e018d759a2a 367 \param [in] control Control Register value to set
switches 0:0e018d759a2a 368 */
switches 0:0e018d759a2a 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
switches 0:0e018d759a2a 370 {
switches 0:0e018d759a2a 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
switches 0:0e018d759a2a 372 }
switches 0:0e018d759a2a 373
switches 0:0e018d759a2a 374
switches 0:0e018d759a2a 375 /** \brief Get IPSR Register
switches 0:0e018d759a2a 376
switches 0:0e018d759a2a 377 This function returns the content of the IPSR Register.
switches 0:0e018d759a2a 378
switches 0:0e018d759a2a 379 \return IPSR Register value
switches 0:0e018d759a2a 380 */
switches 0:0e018d759a2a 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
switches 0:0e018d759a2a 382 {
switches 0:0e018d759a2a 383 uint32_t result;
switches 0:0e018d759a2a 384
switches 0:0e018d759a2a 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
switches 0:0e018d759a2a 386 return(result);
switches 0:0e018d759a2a 387 }
switches 0:0e018d759a2a 388
switches 0:0e018d759a2a 389
switches 0:0e018d759a2a 390 /** \brief Get APSR Register
switches 0:0e018d759a2a 391
switches 0:0e018d759a2a 392 This function returns the content of the APSR Register.
switches 0:0e018d759a2a 393
switches 0:0e018d759a2a 394 \return APSR Register value
switches 0:0e018d759a2a 395 */
switches 0:0e018d759a2a 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
switches 0:0e018d759a2a 397 {
switches 0:0e018d759a2a 398 uint32_t result;
switches 0:0e018d759a2a 399
switches 0:0e018d759a2a 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
switches 0:0e018d759a2a 401 return(result);
switches 0:0e018d759a2a 402 }
switches 0:0e018d759a2a 403
switches 0:0e018d759a2a 404
switches 0:0e018d759a2a 405 /** \brief Get xPSR Register
switches 0:0e018d759a2a 406
switches 0:0e018d759a2a 407 This function returns the content of the xPSR Register.
switches 0:0e018d759a2a 408
switches 0:0e018d759a2a 409 \return xPSR Register value
switches 0:0e018d759a2a 410 */
switches 0:0e018d759a2a 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
switches 0:0e018d759a2a 412 {
switches 0:0e018d759a2a 413 uint32_t result;
switches 0:0e018d759a2a 414
switches 0:0e018d759a2a 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
switches 0:0e018d759a2a 416 return(result);
switches 0:0e018d759a2a 417 }
switches 0:0e018d759a2a 418
switches 0:0e018d759a2a 419
switches 0:0e018d759a2a 420 /** \brief Get Process Stack Pointer
switches 0:0e018d759a2a 421
switches 0:0e018d759a2a 422 This function returns the current value of the Process Stack Pointer (PSP).
switches 0:0e018d759a2a 423
switches 0:0e018d759a2a 424 \return PSP Register value
switches 0:0e018d759a2a 425 */
switches 0:0e018d759a2a 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
switches 0:0e018d759a2a 427 {
switches 0:0e018d759a2a 428 register uint32_t result;
switches 0:0e018d759a2a 429
switches 0:0e018d759a2a 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
switches 0:0e018d759a2a 431 return(result);
switches 0:0e018d759a2a 432 }
switches 0:0e018d759a2a 433
switches 0:0e018d759a2a 434
switches 0:0e018d759a2a 435 /** \brief Set Process Stack Pointer
switches 0:0e018d759a2a 436
switches 0:0e018d759a2a 437 This function assigns the given value to the Process Stack Pointer (PSP).
switches 0:0e018d759a2a 438
switches 0:0e018d759a2a 439 \param [in] topOfProcStack Process Stack Pointer value to set
switches 0:0e018d759a2a 440 */
switches 0:0e018d759a2a 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
switches 0:0e018d759a2a 442 {
switches 0:0e018d759a2a 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
switches 0:0e018d759a2a 444 }
switches 0:0e018d759a2a 445
switches 0:0e018d759a2a 446
switches 0:0e018d759a2a 447 /** \brief Get Main Stack Pointer
switches 0:0e018d759a2a 448
switches 0:0e018d759a2a 449 This function returns the current value of the Main Stack Pointer (MSP).
switches 0:0e018d759a2a 450
switches 0:0e018d759a2a 451 \return MSP Register value
switches 0:0e018d759a2a 452 */
switches 0:0e018d759a2a 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
switches 0:0e018d759a2a 454 {
switches 0:0e018d759a2a 455 register uint32_t result;
switches 0:0e018d759a2a 456
switches 0:0e018d759a2a 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
switches 0:0e018d759a2a 458 return(result);
switches 0:0e018d759a2a 459 }
switches 0:0e018d759a2a 460
switches 0:0e018d759a2a 461
switches 0:0e018d759a2a 462 /** \brief Set Main Stack Pointer
switches 0:0e018d759a2a 463
switches 0:0e018d759a2a 464 This function assigns the given value to the Main Stack Pointer (MSP).
switches 0:0e018d759a2a 465
switches 0:0e018d759a2a 466 \param [in] topOfMainStack Main Stack Pointer value to set
switches 0:0e018d759a2a 467 */
switches 0:0e018d759a2a 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
switches 0:0e018d759a2a 469 {
switches 0:0e018d759a2a 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
switches 0:0e018d759a2a 471 }
switches 0:0e018d759a2a 472
switches 0:0e018d759a2a 473
switches 0:0e018d759a2a 474 /** \brief Get Priority Mask
switches 0:0e018d759a2a 475
switches 0:0e018d759a2a 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
switches 0:0e018d759a2a 477
switches 0:0e018d759a2a 478 \return Priority Mask value
switches 0:0e018d759a2a 479 */
switches 0:0e018d759a2a 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
switches 0:0e018d759a2a 481 {
switches 0:0e018d759a2a 482 uint32_t result;
switches 0:0e018d759a2a 483
switches 0:0e018d759a2a 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
switches 0:0e018d759a2a 485 return(result);
switches 0:0e018d759a2a 486 }
switches 0:0e018d759a2a 487
switches 0:0e018d759a2a 488
switches 0:0e018d759a2a 489 /** \brief Set Priority Mask
switches 0:0e018d759a2a 490
switches 0:0e018d759a2a 491 This function assigns the given value to the Priority Mask Register.
switches 0:0e018d759a2a 492
switches 0:0e018d759a2a 493 \param [in] priMask Priority Mask
switches 0:0e018d759a2a 494 */
switches 0:0e018d759a2a 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
switches 0:0e018d759a2a 496 {
switches 0:0e018d759a2a 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
switches 0:0e018d759a2a 498 }
switches 0:0e018d759a2a 499
switches 0:0e018d759a2a 500
switches 0:0e018d759a2a 501 #if (__CORTEX_M >= 0x03)
switches 0:0e018d759a2a 502
switches 0:0e018d759a2a 503 /** \brief Enable FIQ
switches 0:0e018d759a2a 504
switches 0:0e018d759a2a 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
switches 0:0e018d759a2a 506 Can only be executed in Privileged modes.
switches 0:0e018d759a2a 507 */
switches 0:0e018d759a2a 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
switches 0:0e018d759a2a 509 {
switches 0:0e018d759a2a 510 __ASM volatile ("cpsie f" : : : "memory");
switches 0:0e018d759a2a 511 }
switches 0:0e018d759a2a 512
switches 0:0e018d759a2a 513
switches 0:0e018d759a2a 514 /** \brief Disable FIQ
switches 0:0e018d759a2a 515
switches 0:0e018d759a2a 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
switches 0:0e018d759a2a 517 Can only be executed in Privileged modes.
switches 0:0e018d759a2a 518 */
switches 0:0e018d759a2a 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
switches 0:0e018d759a2a 520 {
switches 0:0e018d759a2a 521 __ASM volatile ("cpsid f" : : : "memory");
switches 0:0e018d759a2a 522 }
switches 0:0e018d759a2a 523
switches 0:0e018d759a2a 524
switches 0:0e018d759a2a 525 /** \brief Get Base Priority
switches 0:0e018d759a2a 526
switches 0:0e018d759a2a 527 This function returns the current value of the Base Priority register.
switches 0:0e018d759a2a 528
switches 0:0e018d759a2a 529 \return Base Priority register value
switches 0:0e018d759a2a 530 */
switches 0:0e018d759a2a 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
switches 0:0e018d759a2a 532 {
switches 0:0e018d759a2a 533 uint32_t result;
switches 0:0e018d759a2a 534
switches 0:0e018d759a2a 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
switches 0:0e018d759a2a 536 return(result);
switches 0:0e018d759a2a 537 }
switches 0:0e018d759a2a 538
switches 0:0e018d759a2a 539
switches 0:0e018d759a2a 540 /** \brief Set Base Priority
switches 0:0e018d759a2a 541
switches 0:0e018d759a2a 542 This function assigns the given value to the Base Priority register.
switches 0:0e018d759a2a 543
switches 0:0e018d759a2a 544 \param [in] basePri Base Priority value to set
switches 0:0e018d759a2a 545 */
switches 0:0e018d759a2a 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
switches 0:0e018d759a2a 547 {
switches 0:0e018d759a2a 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
switches 0:0e018d759a2a 549 }
switches 0:0e018d759a2a 550
switches 0:0e018d759a2a 551
switches 0:0e018d759a2a 552 /** \brief Set Base Priority with condition
switches 0:0e018d759a2a 553
switches 0:0e018d759a2a 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
switches 0:0e018d759a2a 555 or the new value increases the BASEPRI priority level.
switches 0:0e018d759a2a 556
switches 0:0e018d759a2a 557 \param [in] basePri Base Priority value to set
switches 0:0e018d759a2a 558 */
switches 0:0e018d759a2a 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
switches 0:0e018d759a2a 560 {
switches 0:0e018d759a2a 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
switches 0:0e018d759a2a 562 }
switches 0:0e018d759a2a 563
switches 0:0e018d759a2a 564
switches 0:0e018d759a2a 565 /** \brief Get Fault Mask
switches 0:0e018d759a2a 566
switches 0:0e018d759a2a 567 This function returns the current value of the Fault Mask register.
switches 0:0e018d759a2a 568
switches 0:0e018d759a2a 569 \return Fault Mask register value
switches 0:0e018d759a2a 570 */
switches 0:0e018d759a2a 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
switches 0:0e018d759a2a 572 {
switches 0:0e018d759a2a 573 uint32_t result;
switches 0:0e018d759a2a 574
switches 0:0e018d759a2a 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
switches 0:0e018d759a2a 576 return(result);
switches 0:0e018d759a2a 577 }
switches 0:0e018d759a2a 578
switches 0:0e018d759a2a 579
switches 0:0e018d759a2a 580 /** \brief Set Fault Mask
switches 0:0e018d759a2a 581
switches 0:0e018d759a2a 582 This function assigns the given value to the Fault Mask register.
switches 0:0e018d759a2a 583
switches 0:0e018d759a2a 584 \param [in] faultMask Fault Mask value to set
switches 0:0e018d759a2a 585 */
switches 0:0e018d759a2a 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
switches 0:0e018d759a2a 587 {
switches 0:0e018d759a2a 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
switches 0:0e018d759a2a 589 }
switches 0:0e018d759a2a 590
switches 0:0e018d759a2a 591 #endif /* (__CORTEX_M >= 0x03) */
switches 0:0e018d759a2a 592
switches 0:0e018d759a2a 593
switches 0:0e018d759a2a 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
switches 0:0e018d759a2a 595
switches 0:0e018d759a2a 596 /** \brief Get FPSCR
switches 0:0e018d759a2a 597
switches 0:0e018d759a2a 598 This function returns the current value of the Floating Point Status/Control register.
switches 0:0e018d759a2a 599
switches 0:0e018d759a2a 600 \return Floating Point Status/Control register value
switches 0:0e018d759a2a 601 */
switches 0:0e018d759a2a 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
switches 0:0e018d759a2a 603 {
switches 0:0e018d759a2a 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
switches 0:0e018d759a2a 605 uint32_t result;
switches 0:0e018d759a2a 606
switches 0:0e018d759a2a 607 /* Empty asm statement works as a scheduling barrier */
switches 0:0e018d759a2a 608 __ASM volatile ("");
switches 0:0e018d759a2a 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
switches 0:0e018d759a2a 610 __ASM volatile ("");
switches 0:0e018d759a2a 611 return(result);
switches 0:0e018d759a2a 612 #else
switches 0:0e018d759a2a 613 return(0);
switches 0:0e018d759a2a 614 #endif
switches 0:0e018d759a2a 615 }
switches 0:0e018d759a2a 616
switches 0:0e018d759a2a 617
switches 0:0e018d759a2a 618 /** \brief Set FPSCR
switches 0:0e018d759a2a 619
switches 0:0e018d759a2a 620 This function assigns the given value to the Floating Point Status/Control register.
switches 0:0e018d759a2a 621
switches 0:0e018d759a2a 622 \param [in] fpscr Floating Point Status/Control value to set
switches 0:0e018d759a2a 623 */
switches 0:0e018d759a2a 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
switches 0:0e018d759a2a 625 {
switches 0:0e018d759a2a 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
switches 0:0e018d759a2a 627 /* Empty asm statement works as a scheduling barrier */
switches 0:0e018d759a2a 628 __ASM volatile ("");
switches 0:0e018d759a2a 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
switches 0:0e018d759a2a 630 __ASM volatile ("");
switches 0:0e018d759a2a 631 #endif
switches 0:0e018d759a2a 632 }
switches 0:0e018d759a2a 633
switches 0:0e018d759a2a 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
switches 0:0e018d759a2a 635
switches 0:0e018d759a2a 636
switches 0:0e018d759a2a 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
switches 0:0e018d759a2a 638 /* IAR iccarm specific functions */
switches 0:0e018d759a2a 639 #include <cmsis_iar.h>
switches 0:0e018d759a2a 640
switches 0:0e018d759a2a 641
switches 0:0e018d759a2a 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
switches 0:0e018d759a2a 643 /* TI CCS specific functions */
switches 0:0e018d759a2a 644 #include <cmsis_ccs.h>
switches 0:0e018d759a2a 645
switches 0:0e018d759a2a 646
switches 0:0e018d759a2a 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
switches 0:0e018d759a2a 648 /* TASKING carm specific functions */
switches 0:0e018d759a2a 649 /*
switches 0:0e018d759a2a 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
switches 0:0e018d759a2a 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
switches 0:0e018d759a2a 652 * Including the CMSIS ones.
switches 0:0e018d759a2a 653 */
switches 0:0e018d759a2a 654
switches 0:0e018d759a2a 655
switches 0:0e018d759a2a 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
switches 0:0e018d759a2a 657 /* Cosmic specific functions */
switches 0:0e018d759a2a 658 #include <cmsis_csm.h>
switches 0:0e018d759a2a 659
switches 0:0e018d759a2a 660 #endif
switches 0:0e018d759a2a 661
switches 0:0e018d759a2a 662 /*@} end of CMSIS_Core_RegAccFunctions */
switches 0:0e018d759a2a 663
switches 0:0e018d759a2a 664 #endif /* __CORE_CMFUNC_H */