Greg Steiert / maxim_dev

Maxim mbed development library

Dependents:   sensomed

cmsis/core_cm3.h@0:0e018d759a2a, 2016-11-08 (annotated)

Committer:
switches
Date:
Tue Nov 08 18:27:11 2016 +0000
Revision:
0:0e018d759a2a
Initial commit

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switches 0:0e018d759a2a 1 /**************************************************************************//**
switches 0:0e018d759a2a 2 * @file core_cm3.h
switches 0:0e018d759a2a 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
switches 0:0e018d759a2a 4 * @version V4.10
switches 0:0e018d759a2a 5 * @date 18. March 2015
switches 0:0e018d759a2a 6 *
switches 0:0e018d759a2a 7 * @note
switches 0:0e018d759a2a 8 *
switches 0:0e018d759a2a 9 ******************************************************************************/
switches 0:0e018d759a2a 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
switches 0:0e018d759a2a 11
switches 0:0e018d759a2a 12 All rights reserved.
switches 0:0e018d759a2a 13 Redistribution and use in source and binary forms, with or without
switches 0:0e018d759a2a 14 modification, are permitted provided that the following conditions are met:
switches 0:0e018d759a2a 15 - Redistributions of source code must retain the above copyright
switches 0:0e018d759a2a 16 notice, this list of conditions and the following disclaimer.
switches 0:0e018d759a2a 17 - Redistributions in binary form must reproduce the above copyright
switches 0:0e018d759a2a 18 notice, this list of conditions and the following disclaimer in the
switches 0:0e018d759a2a 19 documentation and/or other materials provided with the distribution.
switches 0:0e018d759a2a 20 - Neither the name of ARM nor the names of its contributors may be used
switches 0:0e018d759a2a 21 to endorse or promote products derived from this software without
switches 0:0e018d759a2a 22 specific prior written permission.
switches 0:0e018d759a2a 23 *
switches 0:0e018d759a2a 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
switches 0:0e018d759a2a 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
switches 0:0e018d759a2a 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
switches 0:0e018d759a2a 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
switches 0:0e018d759a2a 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
switches 0:0e018d759a2a 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
switches 0:0e018d759a2a 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
switches 0:0e018d759a2a 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
switches 0:0e018d759a2a 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
switches 0:0e018d759a2a 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
switches 0:0e018d759a2a 34 POSSIBILITY OF SUCH DAMAGE.
switches 0:0e018d759a2a 35 ---------------------------------------------------------------------------*/
switches 0:0e018d759a2a 36
switches 0:0e018d759a2a 37
switches 0:0e018d759a2a 38 #if defined ( __ICCARM__ )
switches 0:0e018d759a2a 39 #pragma system_include /* treat file as system include file for MISRA check */
switches 0:0e018d759a2a 40 #endif
switches 0:0e018d759a2a 41
switches 0:0e018d759a2a 42 #ifndef __CORE_CM3_H_GENERIC
switches 0:0e018d759a2a 43 #define __CORE_CM3_H_GENERIC
switches 0:0e018d759a2a 44
switches 0:0e018d759a2a 45 #ifdef __cplusplus
switches 0:0e018d759a2a 46 extern "C" {
switches 0:0e018d759a2a 47 #endif
switches 0:0e018d759a2a 48
switches 0:0e018d759a2a 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
switches 0:0e018d759a2a 50 CMSIS violates the following MISRA-C:2004 rules:
switches 0:0e018d759a2a 51
switches 0:0e018d759a2a 52 \li Required Rule 8.5, object/function definition in header file.<br>
switches 0:0e018d759a2a 53 Function definitions in header files are used to allow 'inlining'.
switches 0:0e018d759a2a 54
switches 0:0e018d759a2a 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
switches 0:0e018d759a2a 56 Unions are used for effective representation of core registers.
switches 0:0e018d759a2a 57
switches 0:0e018d759a2a 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
switches 0:0e018d759a2a 59 Function-like macros are used to allow more efficient code.
switches 0:0e018d759a2a 60 */
switches 0:0e018d759a2a 61
switches 0:0e018d759a2a 62
switches 0:0e018d759a2a 63 /*******************************************************************************
switches 0:0e018d759a2a 64 * CMSIS definitions
switches 0:0e018d759a2a 65 ******************************************************************************/
switches 0:0e018d759a2a 66 /** \ingroup Cortex_M3
switches 0:0e018d759a2a 67 @{
switches 0:0e018d759a2a 68 */
switches 0:0e018d759a2a 69
switches 0:0e018d759a2a 70 /* CMSIS CM3 definitions */
switches 0:0e018d759a2a 71 #define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
switches 0:0e018d759a2a 72 #define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
switches 0:0e018d759a2a 73 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
switches 0:0e018d759a2a 74 __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
switches 0:0e018d759a2a 75
switches 0:0e018d759a2a 76 #define __CORTEX_M (0x03) /*!< Cortex-M Core */
switches 0:0e018d759a2a 77
switches 0:0e018d759a2a 78
switches 0:0e018d759a2a 79 #if defined ( __CC_ARM )
switches 0:0e018d759a2a 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
switches 0:0e018d759a2a 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
switches 0:0e018d759a2a 82 #define __STATIC_INLINE static __inline
switches 0:0e018d759a2a 83
switches 0:0e018d759a2a 84 #elif defined ( __GNUC__ )
switches 0:0e018d759a2a 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
switches 0:0e018d759a2a 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
switches 0:0e018d759a2a 87 #define __STATIC_INLINE static inline
switches 0:0e018d759a2a 88
switches 0:0e018d759a2a 89 #elif defined ( __ICCARM__ )
switches 0:0e018d759a2a 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
switches 0:0e018d759a2a 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
switches 0:0e018d759a2a 92 #define __STATIC_INLINE static inline
switches 0:0e018d759a2a 93
switches 0:0e018d759a2a 94 #elif defined ( __TMS470__ )
switches 0:0e018d759a2a 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
switches 0:0e018d759a2a 96 #define __STATIC_INLINE static inline
switches 0:0e018d759a2a 97
switches 0:0e018d759a2a 98 #elif defined ( __TASKING__ )
switches 0:0e018d759a2a 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
switches 0:0e018d759a2a 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
switches 0:0e018d759a2a 101 #define __STATIC_INLINE static inline
switches 0:0e018d759a2a 102
switches 0:0e018d759a2a 103 #elif defined ( __CSMC__ )
switches 0:0e018d759a2a 104 #define __packed
switches 0:0e018d759a2a 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
switches 0:0e018d759a2a 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
switches 0:0e018d759a2a 107 #define __STATIC_INLINE static inline
switches 0:0e018d759a2a 108
switches 0:0e018d759a2a 109 #endif
switches 0:0e018d759a2a 110
switches 0:0e018d759a2a 111 /** __FPU_USED indicates whether an FPU is used or not.
switches 0:0e018d759a2a 112 This core does not support an FPU at all
switches 0:0e018d759a2a 113 */
switches 0:0e018d759a2a 114 #define __FPU_USED 0
switches 0:0e018d759a2a 115
switches 0:0e018d759a2a 116 #if defined ( __CC_ARM )
switches 0:0e018d759a2a 117 #if defined __TARGET_FPU_VFP
switches 0:0e018d759a2a 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
switches 0:0e018d759a2a 119 #endif
switches 0:0e018d759a2a 120
switches 0:0e018d759a2a 121 #elif defined ( __GNUC__ )
switches 0:0e018d759a2a 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
switches 0:0e018d759a2a 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
switches 0:0e018d759a2a 124 #endif
switches 0:0e018d759a2a 125
switches 0:0e018d759a2a 126 #elif defined ( __ICCARM__ )
switches 0:0e018d759a2a 127 #if defined __ARMVFP__
switches 0:0e018d759a2a 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
switches 0:0e018d759a2a 129 #endif
switches 0:0e018d759a2a 130
switches 0:0e018d759a2a 131 #elif defined ( __TMS470__ )
switches 0:0e018d759a2a 132 #if defined __TI__VFP_SUPPORT____
switches 0:0e018d759a2a 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
switches 0:0e018d759a2a 134 #endif
switches 0:0e018d759a2a 135
switches 0:0e018d759a2a 136 #elif defined ( __TASKING__ )
switches 0:0e018d759a2a 137 #if defined __FPU_VFP__
switches 0:0e018d759a2a 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
switches 0:0e018d759a2a 139 #endif
switches 0:0e018d759a2a 140
switches 0:0e018d759a2a 141 #elif defined ( __CSMC__ ) /* Cosmic */
switches 0:0e018d759a2a 142 #if ( __CSMC__ & 0x400) // FPU present for parser
switches 0:0e018d759a2a 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
switches 0:0e018d759a2a 144 #endif
switches 0:0e018d759a2a 145 #endif
switches 0:0e018d759a2a 146
switches 0:0e018d759a2a 147 #include <stdint.h> /* standard types definitions */
switches 0:0e018d759a2a 148 #include <core_cmInstr.h> /* Core Instruction Access */
switches 0:0e018d759a2a 149 #include <core_cmFunc.h> /* Core Function Access */
switches 0:0e018d759a2a 150
switches 0:0e018d759a2a 151 #ifdef __cplusplus
switches 0:0e018d759a2a 152 }
switches 0:0e018d759a2a 153 #endif
switches 0:0e018d759a2a 154
switches 0:0e018d759a2a 155 #endif /* __CORE_CM3_H_GENERIC */
switches 0:0e018d759a2a 156
switches 0:0e018d759a2a 157 #ifndef __CMSIS_GENERIC
switches 0:0e018d759a2a 158
switches 0:0e018d759a2a 159 #ifndef __CORE_CM3_H_DEPENDANT
switches 0:0e018d759a2a 160 #define __CORE_CM3_H_DEPENDANT
switches 0:0e018d759a2a 161
switches 0:0e018d759a2a 162 #ifdef __cplusplus
switches 0:0e018d759a2a 163 extern "C" {
switches 0:0e018d759a2a 164 #endif
switches 0:0e018d759a2a 165
switches 0:0e018d759a2a 166 /* check device defines and use defaults */
switches 0:0e018d759a2a 167 #if defined __CHECK_DEVICE_DEFINES
switches 0:0e018d759a2a 168 #ifndef __CM3_REV
switches 0:0e018d759a2a 169 #define __CM3_REV 0x0200
switches 0:0e018d759a2a 170 #warning "__CM3_REV not defined in device header file; using default!"
switches 0:0e018d759a2a 171 #endif
switches 0:0e018d759a2a 172
switches 0:0e018d759a2a 173 #ifndef __MPU_PRESENT
switches 0:0e018d759a2a 174 #define __MPU_PRESENT 0
switches 0:0e018d759a2a 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
switches 0:0e018d759a2a 176 #endif
switches 0:0e018d759a2a 177
switches 0:0e018d759a2a 178 #ifndef __NVIC_PRIO_BITS
switches 0:0e018d759a2a 179 #define __NVIC_PRIO_BITS 4
switches 0:0e018d759a2a 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
switches 0:0e018d759a2a 181 #endif
switches 0:0e018d759a2a 182
switches 0:0e018d759a2a 183 #ifndef __Vendor_SysTickConfig
switches 0:0e018d759a2a 184 #define __Vendor_SysTickConfig 0
switches 0:0e018d759a2a 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
switches 0:0e018d759a2a 186 #endif
switches 0:0e018d759a2a 187 #endif
switches 0:0e018d759a2a 188
switches 0:0e018d759a2a 189 /* IO definitions (access restrictions to peripheral registers) */
switches 0:0e018d759a2a 190 /**
switches 0:0e018d759a2a 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
switches 0:0e018d759a2a 192
switches 0:0e018d759a2a 193 <strong>IO Type Qualifiers</strong> are used
switches 0:0e018d759a2a 194 \li to specify the access to peripheral variables.
switches 0:0e018d759a2a 195 \li for automatic generation of peripheral register debug information.
switches 0:0e018d759a2a 196 */
switches 0:0e018d759a2a 197 #ifdef __cplusplus
switches 0:0e018d759a2a 198 #define __I volatile /*!< Defines 'read only' permissions */
switches 0:0e018d759a2a 199 #else
switches 0:0e018d759a2a 200 #define __I volatile const /*!< Defines 'read only' permissions */
switches 0:0e018d759a2a 201 #endif
switches 0:0e018d759a2a 202 #define __O volatile /*!< Defines 'write only' permissions */
switches 0:0e018d759a2a 203 #define __IO volatile /*!< Defines 'read / write' permissions */
switches 0:0e018d759a2a 204
switches 0:0e018d759a2a 205 #ifdef __cplusplus
switches 0:0e018d759a2a 206 #define __IM volatile /*!< Defines 'read only' permissions */
switches 0:0e018d759a2a 207 #else
switches 0:0e018d759a2a 208 #define __IM volatile const /*!< Defines 'read only' permissions */
switches 0:0e018d759a2a 209 #endif
switches 0:0e018d759a2a 210 #define __OM volatile /*!< Defines 'write only' permissions */
switches 0:0e018d759a2a 211 #define __IOM volatile /*!< Defines 'read / write' permissions */
switches 0:0e018d759a2a 212
switches 0:0e018d759a2a 213 /*@} end of group Cortex_M3 */
switches 0:0e018d759a2a 214
switches 0:0e018d759a2a 215
switches 0:0e018d759a2a 216
switches 0:0e018d759a2a 217 /*******************************************************************************
switches 0:0e018d759a2a 218 * Register Abstraction
switches 0:0e018d759a2a 219 Core Register contain:
switches 0:0e018d759a2a 220 - Core Register
switches 0:0e018d759a2a 221 - Core NVIC Register
switches 0:0e018d759a2a 222 - Core SCB Register
switches 0:0e018d759a2a 223 - Core SysTick Register
switches 0:0e018d759a2a 224 - Core Debug Register
switches 0:0e018d759a2a 225 - Core MPU Register
switches 0:0e018d759a2a 226 ******************************************************************************/
switches 0:0e018d759a2a 227 /** \defgroup CMSIS_core_register Defines and Type Definitions
switches 0:0e018d759a2a 228 \brief Type definitions and defines for Cortex-M processor based devices.
switches 0:0e018d759a2a 229 */
switches 0:0e018d759a2a 230
switches 0:0e018d759a2a 231 /** \ingroup CMSIS_core_register
switches 0:0e018d759a2a 232 \defgroup CMSIS_CORE Status and Control Registers
switches 0:0e018d759a2a 233 \brief Core Register type definitions.
switches 0:0e018d759a2a 234 @{
switches 0:0e018d759a2a 235 */
switches 0:0e018d759a2a 236
switches 0:0e018d759a2a 237 /** \brief Union type to access the Application Program Status Register (APSR).
switches 0:0e018d759a2a 238 */
switches 0:0e018d759a2a 239 typedef union
switches 0:0e018d759a2a 240 {
switches 0:0e018d759a2a 241 struct
switches 0:0e018d759a2a 242 {
switches 0:0e018d759a2a 243 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
switches 0:0e018d759a2a 244 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
switches 0:0e018d759a2a 245 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
switches 0:0e018d759a2a 246 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
switches 0:0e018d759a2a 247 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
switches 0:0e018d759a2a 248 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
switches 0:0e018d759a2a 249 } b; /*!< Structure used for bit access */
switches 0:0e018d759a2a 250 uint32_t w; /*!< Type used for word access */
switches 0:0e018d759a2a 251 } APSR_Type;
switches 0:0e018d759a2a 252
switches 0:0e018d759a2a 253 /* APSR Register Definitions */
switches 0:0e018d759a2a 254 #define APSR_N_Pos 31 /*!< APSR: N Position */
switches 0:0e018d759a2a 255 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
switches 0:0e018d759a2a 256
switches 0:0e018d759a2a 257 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
switches 0:0e018d759a2a 258 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
switches 0:0e018d759a2a 259
switches 0:0e018d759a2a 260 #define APSR_C_Pos 29 /*!< APSR: C Position */
switches 0:0e018d759a2a 261 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
switches 0:0e018d759a2a 262
switches 0:0e018d759a2a 263 #define APSR_V_Pos 28 /*!< APSR: V Position */
switches 0:0e018d759a2a 264 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
switches 0:0e018d759a2a 265
switches 0:0e018d759a2a 266 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
switches 0:0e018d759a2a 267 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
switches 0:0e018d759a2a 268
switches 0:0e018d759a2a 269
switches 0:0e018d759a2a 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
switches 0:0e018d759a2a 271 */
switches 0:0e018d759a2a 272 typedef union
switches 0:0e018d759a2a 273 {
switches 0:0e018d759a2a 274 struct
switches 0:0e018d759a2a 275 {
switches 0:0e018d759a2a 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
switches 0:0e018d759a2a 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
switches 0:0e018d759a2a 278 } b; /*!< Structure used for bit access */
switches 0:0e018d759a2a 279 uint32_t w; /*!< Type used for word access */
switches 0:0e018d759a2a 280 } IPSR_Type;
switches 0:0e018d759a2a 281
switches 0:0e018d759a2a 282 /* IPSR Register Definitions */
switches 0:0e018d759a2a 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
switches 0:0e018d759a2a 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
switches 0:0e018d759a2a 285
switches 0:0e018d759a2a 286
switches 0:0e018d759a2a 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
switches 0:0e018d759a2a 288 */
switches 0:0e018d759a2a 289 typedef union
switches 0:0e018d759a2a 290 {
switches 0:0e018d759a2a 291 struct
switches 0:0e018d759a2a 292 {
switches 0:0e018d759a2a 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
switches 0:0e018d759a2a 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
switches 0:0e018d759a2a 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
switches 0:0e018d759a2a 296 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
switches 0:0e018d759a2a 297 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
switches 0:0e018d759a2a 298 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
switches 0:0e018d759a2a 299 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
switches 0:0e018d759a2a 300 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
switches 0:0e018d759a2a 301 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
switches 0:0e018d759a2a 302 } b; /*!< Structure used for bit access */
switches 0:0e018d759a2a 303 uint32_t w; /*!< Type used for word access */
switches 0:0e018d759a2a 304 } xPSR_Type;
switches 0:0e018d759a2a 305
switches 0:0e018d759a2a 306 /* xPSR Register Definitions */
switches 0:0e018d759a2a 307 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
switches 0:0e018d759a2a 308 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
switches 0:0e018d759a2a 309
switches 0:0e018d759a2a 310 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
switches 0:0e018d759a2a 311 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
switches 0:0e018d759a2a 312
switches 0:0e018d759a2a 313 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
switches 0:0e018d759a2a 314 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
switches 0:0e018d759a2a 315
switches 0:0e018d759a2a 316 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
switches 0:0e018d759a2a 317 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
switches 0:0e018d759a2a 318
switches 0:0e018d759a2a 319 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
switches 0:0e018d759a2a 320 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
switches 0:0e018d759a2a 321
switches 0:0e018d759a2a 322 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
switches 0:0e018d759a2a 323 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
switches 0:0e018d759a2a 324
switches 0:0e018d759a2a 325 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
switches 0:0e018d759a2a 326 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
switches 0:0e018d759a2a 327
switches 0:0e018d759a2a 328 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
switches 0:0e018d759a2a 329 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
switches 0:0e018d759a2a 330
switches 0:0e018d759a2a 331
switches 0:0e018d759a2a 332 /** \brief Union type to access the Control Registers (CONTROL).
switches 0:0e018d759a2a 333 */
switches 0:0e018d759a2a 334 typedef union
switches 0:0e018d759a2a 335 {
switches 0:0e018d759a2a 336 struct
switches 0:0e018d759a2a 337 {
switches 0:0e018d759a2a 338 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
switches 0:0e018d759a2a 339 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
switches 0:0e018d759a2a 340 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
switches 0:0e018d759a2a 341 } b; /*!< Structure used for bit access */
switches 0:0e018d759a2a 342 uint32_t w; /*!< Type used for word access */
switches 0:0e018d759a2a 343 } CONTROL_Type;
switches 0:0e018d759a2a 344
switches 0:0e018d759a2a 345 /* CONTROL Register Definitions */
switches 0:0e018d759a2a 346 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
switches 0:0e018d759a2a 347 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
switches 0:0e018d759a2a 348
switches 0:0e018d759a2a 349 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
switches 0:0e018d759a2a 350 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
switches 0:0e018d759a2a 351
switches 0:0e018d759a2a 352 /*@} end of group CMSIS_CORE */
switches 0:0e018d759a2a 353
switches 0:0e018d759a2a 354
switches 0:0e018d759a2a 355 /** \ingroup CMSIS_core_register
switches 0:0e018d759a2a 356 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
switches 0:0e018d759a2a 357 \brief Type definitions for the NVIC Registers
switches 0:0e018d759a2a 358 @{
switches 0:0e018d759a2a 359 */
switches 0:0e018d759a2a 360
switches 0:0e018d759a2a 361 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
switches 0:0e018d759a2a 362 */
switches 0:0e018d759a2a 363 typedef struct
switches 0:0e018d759a2a 364 {
switches 0:0e018d759a2a 365 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
switches 0:0e018d759a2a 366 uint32_t RESERVED0[24];
switches 0:0e018d759a2a 367 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
switches 0:0e018d759a2a 368 uint32_t RSERVED1[24];
switches 0:0e018d759a2a 369 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
switches 0:0e018d759a2a 370 uint32_t RESERVED2[24];
switches 0:0e018d759a2a 371 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
switches 0:0e018d759a2a 372 uint32_t RESERVED3[24];
switches 0:0e018d759a2a 373 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
switches 0:0e018d759a2a 374 uint32_t RESERVED4[56];
switches 0:0e018d759a2a 375 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
switches 0:0e018d759a2a 376 uint32_t RESERVED5[644];
switches 0:0e018d759a2a 377 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
switches 0:0e018d759a2a 378 } NVIC_Type;
switches 0:0e018d759a2a 379
switches 0:0e018d759a2a 380 /* Software Triggered Interrupt Register Definitions */
switches 0:0e018d759a2a 381 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
switches 0:0e018d759a2a 382 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
switches 0:0e018d759a2a 383
switches 0:0e018d759a2a 384 /*@} end of group CMSIS_NVIC */
switches 0:0e018d759a2a 385
switches 0:0e018d759a2a 386
switches 0:0e018d759a2a 387 /** \ingroup CMSIS_core_register
switches 0:0e018d759a2a 388 \defgroup CMSIS_SCB System Control Block (SCB)
switches 0:0e018d759a2a 389 \brief Type definitions for the System Control Block Registers
switches 0:0e018d759a2a 390 @{
switches 0:0e018d759a2a 391 */
switches 0:0e018d759a2a 392
switches 0:0e018d759a2a 393 /** \brief Structure type to access the System Control Block (SCB).
switches 0:0e018d759a2a 394 */
switches 0:0e018d759a2a 395 typedef struct
switches 0:0e018d759a2a 396 {
switches 0:0e018d759a2a 397 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
switches 0:0e018d759a2a 398 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
switches 0:0e018d759a2a 399 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
switches 0:0e018d759a2a 400 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
switches 0:0e018d759a2a 401 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
switches 0:0e018d759a2a 402 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
switches 0:0e018d759a2a 403 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
switches 0:0e018d759a2a 404 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
switches 0:0e018d759a2a 405 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
switches 0:0e018d759a2a 406 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
switches 0:0e018d759a2a 407 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
switches 0:0e018d759a2a 408 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
switches 0:0e018d759a2a 409 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
switches 0:0e018d759a2a 410 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
switches 0:0e018d759a2a 411 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
switches 0:0e018d759a2a 412 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
switches 0:0e018d759a2a 413 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
switches 0:0e018d759a2a 414 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
switches 0:0e018d759a2a 415 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
switches 0:0e018d759a2a 416 uint32_t RESERVED0[5];
switches 0:0e018d759a2a 417 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
switches 0:0e018d759a2a 418 } SCB_Type;
switches 0:0e018d759a2a 419
switches 0:0e018d759a2a 420 /* SCB CPUID Register Definitions */
switches 0:0e018d759a2a 421 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
switches 0:0e018d759a2a 422 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
switches 0:0e018d759a2a 423
switches 0:0e018d759a2a 424 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
switches 0:0e018d759a2a 425 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
switches 0:0e018d759a2a 426
switches 0:0e018d759a2a 427 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
switches 0:0e018d759a2a 428 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
switches 0:0e018d759a2a 429
switches 0:0e018d759a2a 430 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
switches 0:0e018d759a2a 431 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
switches 0:0e018d759a2a 432
switches 0:0e018d759a2a 433 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
switches 0:0e018d759a2a 434 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
switches 0:0e018d759a2a 435
switches 0:0e018d759a2a 436 /* SCB Interrupt Control State Register Definitions */
switches 0:0e018d759a2a 437 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
switches 0:0e018d759a2a 438 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
switches 0:0e018d759a2a 439
switches 0:0e018d759a2a 440 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
switches 0:0e018d759a2a 441 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
switches 0:0e018d759a2a 442
switches 0:0e018d759a2a 443 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
switches 0:0e018d759a2a 444 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
switches 0:0e018d759a2a 445
switches 0:0e018d759a2a 446 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
switches 0:0e018d759a2a 447 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
switches 0:0e018d759a2a 448
switches 0:0e018d759a2a 449 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
switches 0:0e018d759a2a 450 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
switches 0:0e018d759a2a 451
switches 0:0e018d759a2a 452 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
switches 0:0e018d759a2a 453 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
switches 0:0e018d759a2a 454
switches 0:0e018d759a2a 455 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
switches 0:0e018d759a2a 456 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
switches 0:0e018d759a2a 457
switches 0:0e018d759a2a 458 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
switches 0:0e018d759a2a 459 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
switches 0:0e018d759a2a 460
switches 0:0e018d759a2a 461 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
switches 0:0e018d759a2a 462 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
switches 0:0e018d759a2a 463
switches 0:0e018d759a2a 464 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
switches 0:0e018d759a2a 465 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
switches 0:0e018d759a2a 466
switches 0:0e018d759a2a 467 /* SCB Vector Table Offset Register Definitions */
switches 0:0e018d759a2a 468 #if (__CM3_REV < 0x0201) /* core r2p1 */
switches 0:0e018d759a2a 469 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
switches 0:0e018d759a2a 470 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
switches 0:0e018d759a2a 471
switches 0:0e018d759a2a 472 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
switches 0:0e018d759a2a 473 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
switches 0:0e018d759a2a 474 #else
switches 0:0e018d759a2a 475 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
switches 0:0e018d759a2a 476 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
switches 0:0e018d759a2a 477 #endif
switches 0:0e018d759a2a 478
switches 0:0e018d759a2a 479 /* SCB Application Interrupt and Reset Control Register Definitions */
switches 0:0e018d759a2a 480 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
switches 0:0e018d759a2a 481 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
switches 0:0e018d759a2a 482
switches 0:0e018d759a2a 483 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
switches 0:0e018d759a2a 484 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
switches 0:0e018d759a2a 485
switches 0:0e018d759a2a 486 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
switches 0:0e018d759a2a 487 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
switches 0:0e018d759a2a 488
switches 0:0e018d759a2a 489 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
switches 0:0e018d759a2a 490 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
switches 0:0e018d759a2a 491
switches 0:0e018d759a2a 492 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
switches 0:0e018d759a2a 493 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
switches 0:0e018d759a2a 494
switches 0:0e018d759a2a 495 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
switches 0:0e018d759a2a 496 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
switches 0:0e018d759a2a 497
switches 0:0e018d759a2a 498 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
switches 0:0e018d759a2a 499 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
switches 0:0e018d759a2a 500
switches 0:0e018d759a2a 501 /* SCB System Control Register Definitions */
switches 0:0e018d759a2a 502 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
switches 0:0e018d759a2a 503 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
switches 0:0e018d759a2a 504
switches 0:0e018d759a2a 505 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
switches 0:0e018d759a2a 506 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
switches 0:0e018d759a2a 507
switches 0:0e018d759a2a 508 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
switches 0:0e018d759a2a 509 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
switches 0:0e018d759a2a 510
switches 0:0e018d759a2a 511 /* SCB Configuration Control Register Definitions */
switches 0:0e018d759a2a 512 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
switches 0:0e018d759a2a 513 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
switches 0:0e018d759a2a 514
switches 0:0e018d759a2a 515 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
switches 0:0e018d759a2a 516 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
switches 0:0e018d759a2a 517
switches 0:0e018d759a2a 518 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
switches 0:0e018d759a2a 519 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
switches 0:0e018d759a2a 520
switches 0:0e018d759a2a 521 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
switches 0:0e018d759a2a 522 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
switches 0:0e018d759a2a 523
switches 0:0e018d759a2a 524 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
switches 0:0e018d759a2a 525 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
switches 0:0e018d759a2a 526
switches 0:0e018d759a2a 527 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
switches 0:0e018d759a2a 528 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
switches 0:0e018d759a2a 529
switches 0:0e018d759a2a 530 /* SCB System Handler Control and State Register Definitions */
switches 0:0e018d759a2a 531 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
switches 0:0e018d759a2a 532 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
switches 0:0e018d759a2a 533
switches 0:0e018d759a2a 534 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
switches 0:0e018d759a2a 535 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
switches 0:0e018d759a2a 536
switches 0:0e018d759a2a 537 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
switches 0:0e018d759a2a 538 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
switches 0:0e018d759a2a 539
switches 0:0e018d759a2a 540 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
switches 0:0e018d759a2a 541 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
switches 0:0e018d759a2a 542
switches 0:0e018d759a2a 543 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
switches 0:0e018d759a2a 544 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
switches 0:0e018d759a2a 545
switches 0:0e018d759a2a 546 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
switches 0:0e018d759a2a 547 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
switches 0:0e018d759a2a 548
switches 0:0e018d759a2a 549 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
switches 0:0e018d759a2a 550 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
switches 0:0e018d759a2a 551
switches 0:0e018d759a2a 552 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
switches 0:0e018d759a2a 553 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
switches 0:0e018d759a2a 554
switches 0:0e018d759a2a 555 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
switches 0:0e018d759a2a 556 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
switches 0:0e018d759a2a 557
switches 0:0e018d759a2a 558 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
switches 0:0e018d759a2a 559 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
switches 0:0e018d759a2a 560
switches 0:0e018d759a2a 561 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
switches 0:0e018d759a2a 562 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
switches 0:0e018d759a2a 563
switches 0:0e018d759a2a 564 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
switches 0:0e018d759a2a 565 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
switches 0:0e018d759a2a 566
switches 0:0e018d759a2a 567 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
switches 0:0e018d759a2a 568 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
switches 0:0e018d759a2a 569
switches 0:0e018d759a2a 570 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
switches 0:0e018d759a2a 571 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
switches 0:0e018d759a2a 572
switches 0:0e018d759a2a 573 /* SCB Configurable Fault Status Registers Definitions */
switches 0:0e018d759a2a 574 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
switches 0:0e018d759a2a 575 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
switches 0:0e018d759a2a 576
switches 0:0e018d759a2a 577 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
switches 0:0e018d759a2a 578 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
switches 0:0e018d759a2a 579
switches 0:0e018d759a2a 580 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
switches 0:0e018d759a2a 581 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
switches 0:0e018d759a2a 582
switches 0:0e018d759a2a 583 /* SCB Hard Fault Status Registers Definitions */
switches 0:0e018d759a2a 584 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
switches 0:0e018d759a2a 585 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
switches 0:0e018d759a2a 586
switches 0:0e018d759a2a 587 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
switches 0:0e018d759a2a 588 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
switches 0:0e018d759a2a 589
switches 0:0e018d759a2a 590 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
switches 0:0e018d759a2a 591 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
switches 0:0e018d759a2a 592
switches 0:0e018d759a2a 593 /* SCB Debug Fault Status Register Definitions */
switches 0:0e018d759a2a 594 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
switches 0:0e018d759a2a 595 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
switches 0:0e018d759a2a 596
switches 0:0e018d759a2a 597 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
switches 0:0e018d759a2a 598 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
switches 0:0e018d759a2a 599
switches 0:0e018d759a2a 600 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
switches 0:0e018d759a2a 601 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
switches 0:0e018d759a2a 602
switches 0:0e018d759a2a 603 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
switches 0:0e018d759a2a 604 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
switches 0:0e018d759a2a 605
switches 0:0e018d759a2a 606 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
switches 0:0e018d759a2a 607 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
switches 0:0e018d759a2a 608
switches 0:0e018d759a2a 609 /*@} end of group CMSIS_SCB */
switches 0:0e018d759a2a 610
switches 0:0e018d759a2a 611
switches 0:0e018d759a2a 612 /** \ingroup CMSIS_core_register
switches 0:0e018d759a2a 613 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
switches 0:0e018d759a2a 614 \brief Type definitions for the System Control and ID Register not in the SCB
switches 0:0e018d759a2a 615 @{
switches 0:0e018d759a2a 616 */
switches 0:0e018d759a2a 617
switches 0:0e018d759a2a 618 /** \brief Structure type to access the System Control and ID Register not in the SCB.
switches 0:0e018d759a2a 619 */
switches 0:0e018d759a2a 620 typedef struct
switches 0:0e018d759a2a 621 {
switches 0:0e018d759a2a 622 uint32_t RESERVED0[1];
switches 0:0e018d759a2a 623 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
switches 0:0e018d759a2a 624 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
switches 0:0e018d759a2a 625 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
switches 0:0e018d759a2a 626 #else
switches 0:0e018d759a2a 627 uint32_t RESERVED1[1];
switches 0:0e018d759a2a 628 #endif
switches 0:0e018d759a2a 629 } SCnSCB_Type;
switches 0:0e018d759a2a 630
switches 0:0e018d759a2a 631 /* Interrupt Controller Type Register Definitions */
switches 0:0e018d759a2a 632 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
switches 0:0e018d759a2a 633 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
switches 0:0e018d759a2a 634
switches 0:0e018d759a2a 635 /* Auxiliary Control Register Definitions */
switches 0:0e018d759a2a 636
switches 0:0e018d759a2a 637 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
switches 0:0e018d759a2a 638 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
switches 0:0e018d759a2a 639
switches 0:0e018d759a2a 640 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
switches 0:0e018d759a2a 641 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
switches 0:0e018d759a2a 642
switches 0:0e018d759a2a 643 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
switches 0:0e018d759a2a 644 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
switches 0:0e018d759a2a 645
switches 0:0e018d759a2a 646 /*@} end of group CMSIS_SCnotSCB */
switches 0:0e018d759a2a 647
switches 0:0e018d759a2a 648
switches 0:0e018d759a2a 649 /** \ingroup CMSIS_core_register
switches 0:0e018d759a2a 650 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
switches 0:0e018d759a2a 651 \brief Type definitions for the System Timer Registers.
switches 0:0e018d759a2a 652 @{
switches 0:0e018d759a2a 653 */
switches 0:0e018d759a2a 654
switches 0:0e018d759a2a 655 /** \brief Structure type to access the System Timer (SysTick).
switches 0:0e018d759a2a 656 */
switches 0:0e018d759a2a 657 typedef struct
switches 0:0e018d759a2a 658 {
switches 0:0e018d759a2a 659 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
switches 0:0e018d759a2a 660 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
switches 0:0e018d759a2a 661 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
switches 0:0e018d759a2a 662 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
switches 0:0e018d759a2a 663 } SysTick_Type;
switches 0:0e018d759a2a 664
switches 0:0e018d759a2a 665 /* SysTick Control / Status Register Definitions */
switches 0:0e018d759a2a 666 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
switches 0:0e018d759a2a 667 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
switches 0:0e018d759a2a 668
switches 0:0e018d759a2a 669 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
switches 0:0e018d759a2a 670 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
switches 0:0e018d759a2a 671
switches 0:0e018d759a2a 672 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
switches 0:0e018d759a2a 673 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
switches 0:0e018d759a2a 674
switches 0:0e018d759a2a 675 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
switches 0:0e018d759a2a 676 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
switches 0:0e018d759a2a 677
switches 0:0e018d759a2a 678 /* SysTick Reload Register Definitions */
switches 0:0e018d759a2a 679 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
switches 0:0e018d759a2a 680 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
switches 0:0e018d759a2a 681
switches 0:0e018d759a2a 682 /* SysTick Current Register Definitions */
switches 0:0e018d759a2a 683 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
switches 0:0e018d759a2a 684 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
switches 0:0e018d759a2a 685
switches 0:0e018d759a2a 686 /* SysTick Calibration Register Definitions */
switches 0:0e018d759a2a 687 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
switches 0:0e018d759a2a 688 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
switches 0:0e018d759a2a 689
switches 0:0e018d759a2a 690 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
switches 0:0e018d759a2a 691 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
switches 0:0e018d759a2a 692
switches 0:0e018d759a2a 693 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
switches 0:0e018d759a2a 694 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
switches 0:0e018d759a2a 695
switches 0:0e018d759a2a 696 /*@} end of group CMSIS_SysTick */
switches 0:0e018d759a2a 697
switches 0:0e018d759a2a 698
switches 0:0e018d759a2a 699 /** \ingroup CMSIS_core_register
switches 0:0e018d759a2a 700 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
switches 0:0e018d759a2a 701 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
switches 0:0e018d759a2a 702 @{
switches 0:0e018d759a2a 703 */
switches 0:0e018d759a2a 704
switches 0:0e018d759a2a 705 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
switches 0:0e018d759a2a 706 */
switches 0:0e018d759a2a 707 typedef struct
switches 0:0e018d759a2a 708 {
switches 0:0e018d759a2a 709 __O union
switches 0:0e018d759a2a 710 {
switches 0:0e018d759a2a 711 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
switches 0:0e018d759a2a 712 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
switches 0:0e018d759a2a 713 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
switches 0:0e018d759a2a 714 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
switches 0:0e018d759a2a 715 uint32_t RESERVED0[864];
switches 0:0e018d759a2a 716 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
switches 0:0e018d759a2a 717 uint32_t RESERVED1[15];
switches 0:0e018d759a2a 718 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
switches 0:0e018d759a2a 719 uint32_t RESERVED2[15];
switches 0:0e018d759a2a 720 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
switches 0:0e018d759a2a 721 uint32_t RESERVED3[29];
switches 0:0e018d759a2a 722 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
switches 0:0e018d759a2a 723 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
switches 0:0e018d759a2a 724 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
switches 0:0e018d759a2a 725 uint32_t RESERVED4[43];
switches 0:0e018d759a2a 726 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
switches 0:0e018d759a2a 727 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
switches 0:0e018d759a2a 728 uint32_t RESERVED5[6];
switches 0:0e018d759a2a 729 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
switches 0:0e018d759a2a 730 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
switches 0:0e018d759a2a 731 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
switches 0:0e018d759a2a 732 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
switches 0:0e018d759a2a 733 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
switches 0:0e018d759a2a 734 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
switches 0:0e018d759a2a 735 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
switches 0:0e018d759a2a 736 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
switches 0:0e018d759a2a 737 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
switches 0:0e018d759a2a 738 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
switches 0:0e018d759a2a 739 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
switches 0:0e018d759a2a 740 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
switches 0:0e018d759a2a 741 } ITM_Type;
switches 0:0e018d759a2a 742
switches 0:0e018d759a2a 743 /* ITM Trace Privilege Register Definitions */
switches 0:0e018d759a2a 744 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
switches 0:0e018d759a2a 745 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
switches 0:0e018d759a2a 746
switches 0:0e018d759a2a 747 /* ITM Trace Control Register Definitions */
switches 0:0e018d759a2a 748 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
switches 0:0e018d759a2a 749 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
switches 0:0e018d759a2a 750
switches 0:0e018d759a2a 751 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
switches 0:0e018d759a2a 752 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
switches 0:0e018d759a2a 753
switches 0:0e018d759a2a 754 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
switches 0:0e018d759a2a 755 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
switches 0:0e018d759a2a 756
switches 0:0e018d759a2a 757 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
switches 0:0e018d759a2a 758 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
switches 0:0e018d759a2a 759
switches 0:0e018d759a2a 760 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
switches 0:0e018d759a2a 761 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
switches 0:0e018d759a2a 762
switches 0:0e018d759a2a 763 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
switches 0:0e018d759a2a 764 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
switches 0:0e018d759a2a 765
switches 0:0e018d759a2a 766 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
switches 0:0e018d759a2a 767 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
switches 0:0e018d759a2a 768
switches 0:0e018d759a2a 769 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
switches 0:0e018d759a2a 770 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
switches 0:0e018d759a2a 771
switches 0:0e018d759a2a 772 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
switches 0:0e018d759a2a 773 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
switches 0:0e018d759a2a 774
switches 0:0e018d759a2a 775 /* ITM Integration Write Register Definitions */
switches 0:0e018d759a2a 776 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
switches 0:0e018d759a2a 777 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
switches 0:0e018d759a2a 778
switches 0:0e018d759a2a 779 /* ITM Integration Read Register Definitions */
switches 0:0e018d759a2a 780 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
switches 0:0e018d759a2a 781 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
switches 0:0e018d759a2a 782
switches 0:0e018d759a2a 783 /* ITM Integration Mode Control Register Definitions */
switches 0:0e018d759a2a 784 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
switches 0:0e018d759a2a 785 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
switches 0:0e018d759a2a 786
switches 0:0e018d759a2a 787 /* ITM Lock Status Register Definitions */
switches 0:0e018d759a2a 788 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
switches 0:0e018d759a2a 789 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
switches 0:0e018d759a2a 790
switches 0:0e018d759a2a 791 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
switches 0:0e018d759a2a 792 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
switches 0:0e018d759a2a 793
switches 0:0e018d759a2a 794 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
switches 0:0e018d759a2a 795 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
switches 0:0e018d759a2a 796
switches 0:0e018d759a2a 797 /*@}*/ /* end of group CMSIS_ITM */
switches 0:0e018d759a2a 798
switches 0:0e018d759a2a 799
switches 0:0e018d759a2a 800 /** \ingroup CMSIS_core_register
switches 0:0e018d759a2a 801 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
switches 0:0e018d759a2a 802 \brief Type definitions for the Data Watchpoint and Trace (DWT)
switches 0:0e018d759a2a 803 @{
switches 0:0e018d759a2a 804 */
switches 0:0e018d759a2a 805
switches 0:0e018d759a2a 806 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
switches 0:0e018d759a2a 807 */
switches 0:0e018d759a2a 808 typedef struct
switches 0:0e018d759a2a 809 {
switches 0:0e018d759a2a 810 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
switches 0:0e018d759a2a 811 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
switches 0:0e018d759a2a 812 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
switches 0:0e018d759a2a 813 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
switches 0:0e018d759a2a 814 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
switches 0:0e018d759a2a 815 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
switches 0:0e018d759a2a 816 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
switches 0:0e018d759a2a 817 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
switches 0:0e018d759a2a 818 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
switches 0:0e018d759a2a 819 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
switches 0:0e018d759a2a 820 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
switches 0:0e018d759a2a 821 uint32_t RESERVED0[1];
switches 0:0e018d759a2a 822 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
switches 0:0e018d759a2a 823 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
switches 0:0e018d759a2a 824 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
switches 0:0e018d759a2a 825 uint32_t RESERVED1[1];
switches 0:0e018d759a2a 826 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
switches 0:0e018d759a2a 827 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
switches 0:0e018d759a2a 828 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
switches 0:0e018d759a2a 829 uint32_t RESERVED2[1];
switches 0:0e018d759a2a 830 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
switches 0:0e018d759a2a 831 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
switches 0:0e018d759a2a 832 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
switches 0:0e018d759a2a 833 } DWT_Type;
switches 0:0e018d759a2a 834
switches 0:0e018d759a2a 835 /* DWT Control Register Definitions */
switches 0:0e018d759a2a 836 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
switches 0:0e018d759a2a 837 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
switches 0:0e018d759a2a 838
switches 0:0e018d759a2a 839 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
switches 0:0e018d759a2a 840 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
switches 0:0e018d759a2a 841
switches 0:0e018d759a2a 842 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
switches 0:0e018d759a2a 843 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
switches 0:0e018d759a2a 844
switches 0:0e018d759a2a 845 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
switches 0:0e018d759a2a 846 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
switches 0:0e018d759a2a 847
switches 0:0e018d759a2a 848 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
switches 0:0e018d759a2a 849 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
switches 0:0e018d759a2a 850
switches 0:0e018d759a2a 851 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
switches 0:0e018d759a2a 852 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
switches 0:0e018d759a2a 853
switches 0:0e018d759a2a 854 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
switches 0:0e018d759a2a 855 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
switches 0:0e018d759a2a 856
switches 0:0e018d759a2a 857 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
switches 0:0e018d759a2a 858 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
switches 0:0e018d759a2a 859
switches 0:0e018d759a2a 860 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
switches 0:0e018d759a2a 861 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
switches 0:0e018d759a2a 862
switches 0:0e018d759a2a 863 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
switches 0:0e018d759a2a 864 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
switches 0:0e018d759a2a 865
switches 0:0e018d759a2a 866 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
switches 0:0e018d759a2a 867 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
switches 0:0e018d759a2a 868
switches 0:0e018d759a2a 869 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
switches 0:0e018d759a2a 870 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
switches 0:0e018d759a2a 871
switches 0:0e018d759a2a 872 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
switches 0:0e018d759a2a 873 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
switches 0:0e018d759a2a 874
switches 0:0e018d759a2a 875 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
switches 0:0e018d759a2a 876 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
switches 0:0e018d759a2a 877
switches 0:0e018d759a2a 878 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
switches 0:0e018d759a2a 879 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
switches 0:0e018d759a2a 880
switches 0:0e018d759a2a 881 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
switches 0:0e018d759a2a 882 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
switches 0:0e018d759a2a 883
switches 0:0e018d759a2a 884 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
switches 0:0e018d759a2a 885 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
switches 0:0e018d759a2a 886
switches 0:0e018d759a2a 887 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
switches 0:0e018d759a2a 888 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
switches 0:0e018d759a2a 889
switches 0:0e018d759a2a 890 /* DWT CPI Count Register Definitions */
switches 0:0e018d759a2a 891 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
switches 0:0e018d759a2a 892 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
switches 0:0e018d759a2a 893
switches 0:0e018d759a2a 894 /* DWT Exception Overhead Count Register Definitions */
switches 0:0e018d759a2a 895 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
switches 0:0e018d759a2a 896 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
switches 0:0e018d759a2a 897
switches 0:0e018d759a2a 898 /* DWT Sleep Count Register Definitions */
switches 0:0e018d759a2a 899 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
switches 0:0e018d759a2a 900 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
switches 0:0e018d759a2a 901
switches 0:0e018d759a2a 902 /* DWT LSU Count Register Definitions */
switches 0:0e018d759a2a 903 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
switches 0:0e018d759a2a 904 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
switches 0:0e018d759a2a 905
switches 0:0e018d759a2a 906 /* DWT Folded-instruction Count Register Definitions */
switches 0:0e018d759a2a 907 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
switches 0:0e018d759a2a 908 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
switches 0:0e018d759a2a 909
switches 0:0e018d759a2a 910 /* DWT Comparator Mask Register Definitions */
switches 0:0e018d759a2a 911 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
switches 0:0e018d759a2a 912 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
switches 0:0e018d759a2a 913
switches 0:0e018d759a2a 914 /* DWT Comparator Function Register Definitions */
switches 0:0e018d759a2a 915 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
switches 0:0e018d759a2a 916 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
switches 0:0e018d759a2a 917
switches 0:0e018d759a2a 918 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
switches 0:0e018d759a2a 919 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
switches 0:0e018d759a2a 920
switches 0:0e018d759a2a 921 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
switches 0:0e018d759a2a 922 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
switches 0:0e018d759a2a 923
switches 0:0e018d759a2a 924 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
switches 0:0e018d759a2a 925 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
switches 0:0e018d759a2a 926
switches 0:0e018d759a2a 927 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
switches 0:0e018d759a2a 928 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
switches 0:0e018d759a2a 929
switches 0:0e018d759a2a 930 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
switches 0:0e018d759a2a 931 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
switches 0:0e018d759a2a 932
switches 0:0e018d759a2a 933 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
switches 0:0e018d759a2a 934 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
switches 0:0e018d759a2a 935
switches 0:0e018d759a2a 936 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
switches 0:0e018d759a2a 937 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
switches 0:0e018d759a2a 938
switches 0:0e018d759a2a 939 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
switches 0:0e018d759a2a 940 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
switches 0:0e018d759a2a 941
switches 0:0e018d759a2a 942 /*@}*/ /* end of group CMSIS_DWT */
switches 0:0e018d759a2a 943
switches 0:0e018d759a2a 944
switches 0:0e018d759a2a 945 /** \ingroup CMSIS_core_register
switches 0:0e018d759a2a 946 \defgroup CMSIS_TPI Trace Port Interface (TPI)
switches 0:0e018d759a2a 947 \brief Type definitions for the Trace Port Interface (TPI)
switches 0:0e018d759a2a 948 @{
switches 0:0e018d759a2a 949 */
switches 0:0e018d759a2a 950
switches 0:0e018d759a2a 951 /** \brief Structure type to access the Trace Port Interface Register (TPI).
switches 0:0e018d759a2a 952 */
switches 0:0e018d759a2a 953 typedef struct
switches 0:0e018d759a2a 954 {
switches 0:0e018d759a2a 955 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
switches 0:0e018d759a2a 956 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
switches 0:0e018d759a2a 957 uint32_t RESERVED0[2];
switches 0:0e018d759a2a 958 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
switches 0:0e018d759a2a 959 uint32_t RESERVED1[55];
switches 0:0e018d759a2a 960 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
switches 0:0e018d759a2a 961 uint32_t RESERVED2[131];
switches 0:0e018d759a2a 962 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
switches 0:0e018d759a2a 963 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
switches 0:0e018d759a2a 964 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
switches 0:0e018d759a2a 965 uint32_t RESERVED3[759];
switches 0:0e018d759a2a 966 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
switches 0:0e018d759a2a 967 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
switches 0:0e018d759a2a 968 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
switches 0:0e018d759a2a 969 uint32_t RESERVED4[1];
switches 0:0e018d759a2a 970 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
switches 0:0e018d759a2a 971 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
switches 0:0e018d759a2a 972 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
switches 0:0e018d759a2a 973 uint32_t RESERVED5[39];
switches 0:0e018d759a2a 974 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
switches 0:0e018d759a2a 975 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
switches 0:0e018d759a2a 976 uint32_t RESERVED7[8];
switches 0:0e018d759a2a 977 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
switches 0:0e018d759a2a 978 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
switches 0:0e018d759a2a 979 } TPI_Type;
switches 0:0e018d759a2a 980
switches 0:0e018d759a2a 981 /* TPI Asynchronous Clock Prescaler Register Definitions */
switches 0:0e018d759a2a 982 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
switches 0:0e018d759a2a 983 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
switches 0:0e018d759a2a 984
switches 0:0e018d759a2a 985 /* TPI Selected Pin Protocol Register Definitions */
switches 0:0e018d759a2a 986 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
switches 0:0e018d759a2a 987 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
switches 0:0e018d759a2a 988
switches 0:0e018d759a2a 989 /* TPI Formatter and Flush Status Register Definitions */
switches 0:0e018d759a2a 990 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
switches 0:0e018d759a2a 991 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
switches 0:0e018d759a2a 992
switches 0:0e018d759a2a 993 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
switches 0:0e018d759a2a 994 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
switches 0:0e018d759a2a 995
switches 0:0e018d759a2a 996 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
switches 0:0e018d759a2a 997 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
switches 0:0e018d759a2a 998
switches 0:0e018d759a2a 999 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
switches 0:0e018d759a2a 1000 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
switches 0:0e018d759a2a 1001
switches 0:0e018d759a2a 1002 /* TPI Formatter and Flush Control Register Definitions */
switches 0:0e018d759a2a 1003 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
switches 0:0e018d759a2a 1004 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
switches 0:0e018d759a2a 1005
switches 0:0e018d759a2a 1006 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
switches 0:0e018d759a2a 1007 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
switches 0:0e018d759a2a 1008
switches 0:0e018d759a2a 1009 /* TPI TRIGGER Register Definitions */
switches 0:0e018d759a2a 1010 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
switches 0:0e018d759a2a 1011 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
switches 0:0e018d759a2a 1012
switches 0:0e018d759a2a 1013 /* TPI Integration ETM Data Register Definitions (FIFO0) */
switches 0:0e018d759a2a 1014 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
switches 0:0e018d759a2a 1015 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
switches 0:0e018d759a2a 1016
switches 0:0e018d759a2a 1017 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
switches 0:0e018d759a2a 1018 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
switches 0:0e018d759a2a 1019
switches 0:0e018d759a2a 1020 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
switches 0:0e018d759a2a 1021 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
switches 0:0e018d759a2a 1022
switches 0:0e018d759a2a 1023 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
switches 0:0e018d759a2a 1024 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
switches 0:0e018d759a2a 1025
switches 0:0e018d759a2a 1026 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
switches 0:0e018d759a2a 1027 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
switches 0:0e018d759a2a 1028
switches 0:0e018d759a2a 1029 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
switches 0:0e018d759a2a 1030 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
switches 0:0e018d759a2a 1031
switches 0:0e018d759a2a 1032 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
switches 0:0e018d759a2a 1033 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
switches 0:0e018d759a2a 1034
switches 0:0e018d759a2a 1035 /* TPI ITATBCTR2 Register Definitions */
switches 0:0e018d759a2a 1036 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
switches 0:0e018d759a2a 1037 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
switches 0:0e018d759a2a 1038
switches 0:0e018d759a2a 1039 /* TPI Integration ITM Data Register Definitions (FIFO1) */
switches 0:0e018d759a2a 1040 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
switches 0:0e018d759a2a 1041 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
switches 0:0e018d759a2a 1042
switches 0:0e018d759a2a 1043 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
switches 0:0e018d759a2a 1044 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
switches 0:0e018d759a2a 1045
switches 0:0e018d759a2a 1046 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
switches 0:0e018d759a2a 1047 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
switches 0:0e018d759a2a 1048
switches 0:0e018d759a2a 1049 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
switches 0:0e018d759a2a 1050 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
switches 0:0e018d759a2a 1051
switches 0:0e018d759a2a 1052 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
switches 0:0e018d759a2a 1053 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
switches 0:0e018d759a2a 1054
switches 0:0e018d759a2a 1055 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
switches 0:0e018d759a2a 1056 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
switches 0:0e018d759a2a 1057
switches 0:0e018d759a2a 1058 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
switches 0:0e018d759a2a 1059 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
switches 0:0e018d759a2a 1060
switches 0:0e018d759a2a 1061 /* TPI ITATBCTR0 Register Definitions */
switches 0:0e018d759a2a 1062 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
switches 0:0e018d759a2a 1063 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
switches 0:0e018d759a2a 1064
switches 0:0e018d759a2a 1065 /* TPI Integration Mode Control Register Definitions */
switches 0:0e018d759a2a 1066 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
switches 0:0e018d759a2a 1067 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
switches 0:0e018d759a2a 1068
switches 0:0e018d759a2a 1069 /* TPI DEVID Register Definitions */
switches 0:0e018d759a2a 1070 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
switches 0:0e018d759a2a 1071 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
switches 0:0e018d759a2a 1072
switches 0:0e018d759a2a 1073 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
switches 0:0e018d759a2a 1074 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
switches 0:0e018d759a2a 1075
switches 0:0e018d759a2a 1076 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
switches 0:0e018d759a2a 1077 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
switches 0:0e018d759a2a 1078
switches 0:0e018d759a2a 1079 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
switches 0:0e018d759a2a 1080 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
switches 0:0e018d759a2a 1081
switches 0:0e018d759a2a 1082 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
switches 0:0e018d759a2a 1083 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
switches 0:0e018d759a2a 1084
switches 0:0e018d759a2a 1085 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
switches 0:0e018d759a2a 1086 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
switches 0:0e018d759a2a 1087
switches 0:0e018d759a2a 1088 /* TPI DEVTYPE Register Definitions */
switches 0:0e018d759a2a 1089 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
switches 0:0e018d759a2a 1090 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
switches 0:0e018d759a2a 1091
switches 0:0e018d759a2a 1092 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
switches 0:0e018d759a2a 1093 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
switches 0:0e018d759a2a 1094
switches 0:0e018d759a2a 1095 /*@}*/ /* end of group CMSIS_TPI */
switches 0:0e018d759a2a 1096
switches 0:0e018d759a2a 1097
switches 0:0e018d759a2a 1098 #if (__MPU_PRESENT == 1)
switches 0:0e018d759a2a 1099 /** \ingroup CMSIS_core_register
switches 0:0e018d759a2a 1100 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
switches 0:0e018d759a2a 1101 \brief Type definitions for the Memory Protection Unit (MPU)
switches 0:0e018d759a2a 1102 @{
switches 0:0e018d759a2a 1103 */
switches 0:0e018d759a2a 1104
switches 0:0e018d759a2a 1105 /** \brief Structure type to access the Memory Protection Unit (MPU).
switches 0:0e018d759a2a 1106 */
switches 0:0e018d759a2a 1107 typedef struct
switches 0:0e018d759a2a 1108 {
switches 0:0e018d759a2a 1109 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
switches 0:0e018d759a2a 1110 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
switches 0:0e018d759a2a 1111 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
switches 0:0e018d759a2a 1112 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
switches 0:0e018d759a2a 1113 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
switches 0:0e018d759a2a 1114 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
switches 0:0e018d759a2a 1115 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
switches 0:0e018d759a2a 1116 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
switches 0:0e018d759a2a 1117 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
switches 0:0e018d759a2a 1118 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
switches 0:0e018d759a2a 1119 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
switches 0:0e018d759a2a 1120 } MPU_Type;
switches 0:0e018d759a2a 1121
switches 0:0e018d759a2a 1122 /* MPU Type Register */
switches 0:0e018d759a2a 1123 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
switches 0:0e018d759a2a 1124 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
switches 0:0e018d759a2a 1125
switches 0:0e018d759a2a 1126 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
switches 0:0e018d759a2a 1127 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
switches 0:0e018d759a2a 1128
switches 0:0e018d759a2a 1129 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
switches 0:0e018d759a2a 1130 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
switches 0:0e018d759a2a 1131
switches 0:0e018d759a2a 1132 /* MPU Control Register */
switches 0:0e018d759a2a 1133 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
switches 0:0e018d759a2a 1134 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
switches 0:0e018d759a2a 1135
switches 0:0e018d759a2a 1136 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
switches 0:0e018d759a2a 1137 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
switches 0:0e018d759a2a 1138
switches 0:0e018d759a2a 1139 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
switches 0:0e018d759a2a 1140 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
switches 0:0e018d759a2a 1141
switches 0:0e018d759a2a 1142 /* MPU Region Number Register */
switches 0:0e018d759a2a 1143 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
switches 0:0e018d759a2a 1144 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
switches 0:0e018d759a2a 1145
switches 0:0e018d759a2a 1146 /* MPU Region Base Address Register */
switches 0:0e018d759a2a 1147 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
switches 0:0e018d759a2a 1148 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
switches 0:0e018d759a2a 1149
switches 0:0e018d759a2a 1150 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
switches 0:0e018d759a2a 1151 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
switches 0:0e018d759a2a 1152
switches 0:0e018d759a2a 1153 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
switches 0:0e018d759a2a 1154 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
switches 0:0e018d759a2a 1155
switches 0:0e018d759a2a 1156 /* MPU Region Attribute and Size Register */
switches 0:0e018d759a2a 1157 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
switches 0:0e018d759a2a 1158 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
switches 0:0e018d759a2a 1159
switches 0:0e018d759a2a 1160 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
switches 0:0e018d759a2a 1161 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
switches 0:0e018d759a2a 1162
switches 0:0e018d759a2a 1163 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
switches 0:0e018d759a2a 1164 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
switches 0:0e018d759a2a 1165
switches 0:0e018d759a2a 1166 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
switches 0:0e018d759a2a 1167 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
switches 0:0e018d759a2a 1168
switches 0:0e018d759a2a 1169 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
switches 0:0e018d759a2a 1170 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
switches 0:0e018d759a2a 1171
switches 0:0e018d759a2a 1172 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
switches 0:0e018d759a2a 1173 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
switches 0:0e018d759a2a 1174
switches 0:0e018d759a2a 1175 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
switches 0:0e018d759a2a 1176 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
switches 0:0e018d759a2a 1177
switches 0:0e018d759a2a 1178 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
switches 0:0e018d759a2a 1179 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
switches 0:0e018d759a2a 1180
switches 0:0e018d759a2a 1181 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
switches 0:0e018d759a2a 1182 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
switches 0:0e018d759a2a 1183
switches 0:0e018d759a2a 1184 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
switches 0:0e018d759a2a 1185 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
switches 0:0e018d759a2a 1186
switches 0:0e018d759a2a 1187 /*@} end of group CMSIS_MPU */
switches 0:0e018d759a2a 1188 #endif
switches 0:0e018d759a2a 1189
switches 0:0e018d759a2a 1190
switches 0:0e018d759a2a 1191 /** \ingroup CMSIS_core_register
switches 0:0e018d759a2a 1192 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
switches 0:0e018d759a2a 1193 \brief Type definitions for the Core Debug Registers
switches 0:0e018d759a2a 1194 @{
switches 0:0e018d759a2a 1195 */
switches 0:0e018d759a2a 1196
switches 0:0e018d759a2a 1197 /** \brief Structure type to access the Core Debug Register (CoreDebug).
switches 0:0e018d759a2a 1198 */
switches 0:0e018d759a2a 1199 typedef struct
switches 0:0e018d759a2a 1200 {
switches 0:0e018d759a2a 1201 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
switches 0:0e018d759a2a 1202 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
switches 0:0e018d759a2a 1203 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
switches 0:0e018d759a2a 1204 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
switches 0:0e018d759a2a 1205 } CoreDebug_Type;
switches 0:0e018d759a2a 1206
switches 0:0e018d759a2a 1207 /* Debug Halting Control and Status Register */
switches 0:0e018d759a2a 1208 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
switches 0:0e018d759a2a 1209 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
switches 0:0e018d759a2a 1210
switches 0:0e018d759a2a 1211 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
switches 0:0e018d759a2a 1212 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
switches 0:0e018d759a2a 1213
switches 0:0e018d759a2a 1214 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
switches 0:0e018d759a2a 1215 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
switches 0:0e018d759a2a 1216
switches 0:0e018d759a2a 1217 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
switches 0:0e018d759a2a 1218 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
switches 0:0e018d759a2a 1219
switches 0:0e018d759a2a 1220 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
switches 0:0e018d759a2a 1221 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
switches 0:0e018d759a2a 1222
switches 0:0e018d759a2a 1223 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
switches 0:0e018d759a2a 1224 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
switches 0:0e018d759a2a 1225
switches 0:0e018d759a2a 1226 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
switches 0:0e018d759a2a 1227 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
switches 0:0e018d759a2a 1228
switches 0:0e018d759a2a 1229 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
switches 0:0e018d759a2a 1230 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
switches 0:0e018d759a2a 1231
switches 0:0e018d759a2a 1232 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
switches 0:0e018d759a2a 1233 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
switches 0:0e018d759a2a 1234
switches 0:0e018d759a2a 1235 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
switches 0:0e018d759a2a 1236 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
switches 0:0e018d759a2a 1237
switches 0:0e018d759a2a 1238 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
switches 0:0e018d759a2a 1239 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
switches 0:0e018d759a2a 1240
switches 0:0e018d759a2a 1241 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
switches 0:0e018d759a2a 1242 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
switches 0:0e018d759a2a 1243
switches 0:0e018d759a2a 1244 /* Debug Core Register Selector Register */
switches 0:0e018d759a2a 1245 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
switches 0:0e018d759a2a 1246 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
switches 0:0e018d759a2a 1247
switches 0:0e018d759a2a 1248 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
switches 0:0e018d759a2a 1249 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
switches 0:0e018d759a2a 1250
switches 0:0e018d759a2a 1251 /* Debug Exception and Monitor Control Register */
switches 0:0e018d759a2a 1252 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
switches 0:0e018d759a2a 1253 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
switches 0:0e018d759a2a 1254
switches 0:0e018d759a2a 1255 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
switches 0:0e018d759a2a 1256 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
switches 0:0e018d759a2a 1257
switches 0:0e018d759a2a 1258 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
switches 0:0e018d759a2a 1259 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
switches 0:0e018d759a2a 1260
switches 0:0e018d759a2a 1261 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
switches 0:0e018d759a2a 1262 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
switches 0:0e018d759a2a 1263
switches 0:0e018d759a2a 1264 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
switches 0:0e018d759a2a 1265 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
switches 0:0e018d759a2a 1266
switches 0:0e018d759a2a 1267 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
switches 0:0e018d759a2a 1268 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
switches 0:0e018d759a2a 1269
switches 0:0e018d759a2a 1270 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
switches 0:0e018d759a2a 1271 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
switches 0:0e018d759a2a 1272
switches 0:0e018d759a2a 1273 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
switches 0:0e018d759a2a 1274 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
switches 0:0e018d759a2a 1275
switches 0:0e018d759a2a 1276 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
switches 0:0e018d759a2a 1277 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
switches 0:0e018d759a2a 1278
switches 0:0e018d759a2a 1279 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
switches 0:0e018d759a2a 1280 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
switches 0:0e018d759a2a 1281
switches 0:0e018d759a2a 1282 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
switches 0:0e018d759a2a 1283 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
switches 0:0e018d759a2a 1284
switches 0:0e018d759a2a 1285 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
switches 0:0e018d759a2a 1286 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
switches 0:0e018d759a2a 1287
switches 0:0e018d759a2a 1288 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
switches 0:0e018d759a2a 1289 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
switches 0:0e018d759a2a 1290
switches 0:0e018d759a2a 1291 /*@} end of group CMSIS_CoreDebug */
switches 0:0e018d759a2a 1292
switches 0:0e018d759a2a 1293
switches 0:0e018d759a2a 1294 /** \ingroup CMSIS_core_register
switches 0:0e018d759a2a 1295 \defgroup CMSIS_core_base Core Definitions
switches 0:0e018d759a2a 1296 \brief Definitions for base addresses, unions, and structures.
switches 0:0e018d759a2a 1297 @{
switches 0:0e018d759a2a 1298 */
switches 0:0e018d759a2a 1299
switches 0:0e018d759a2a 1300 /* Memory mapping of Cortex-M3 Hardware */
switches 0:0e018d759a2a 1301 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
switches 0:0e018d759a2a 1302 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
switches 0:0e018d759a2a 1303 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
switches 0:0e018d759a2a 1304 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
switches 0:0e018d759a2a 1305 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
switches 0:0e018d759a2a 1306 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
switches 0:0e018d759a2a 1307 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
switches 0:0e018d759a2a 1308 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
switches 0:0e018d759a2a 1309
switches 0:0e018d759a2a 1310 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
switches 0:0e018d759a2a 1311 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
switches 0:0e018d759a2a 1312 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
switches 0:0e018d759a2a 1313 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
switches 0:0e018d759a2a 1314 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
switches 0:0e018d759a2a 1315 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
switches 0:0e018d759a2a 1316 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
switches 0:0e018d759a2a 1317 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
switches 0:0e018d759a2a 1318
switches 0:0e018d759a2a 1319 #if (__MPU_PRESENT == 1)
switches 0:0e018d759a2a 1320 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
switches 0:0e018d759a2a 1321 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
switches 0:0e018d759a2a 1322 #endif
switches 0:0e018d759a2a 1323
switches 0:0e018d759a2a 1324 /*@} */
switches 0:0e018d759a2a 1325
switches 0:0e018d759a2a 1326
switches 0:0e018d759a2a 1327
switches 0:0e018d759a2a 1328 /*******************************************************************************
switches 0:0e018d759a2a 1329 * Hardware Abstraction Layer
switches 0:0e018d759a2a 1330 Core Function Interface contains:
switches 0:0e018d759a2a 1331 - Core NVIC Functions
switches 0:0e018d759a2a 1332 - Core SysTick Functions
switches 0:0e018d759a2a 1333 - Core Debug Functions
switches 0:0e018d759a2a 1334 - Core Register Access Functions
switches 0:0e018d759a2a 1335 ******************************************************************************/
switches 0:0e018d759a2a 1336 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
switches 0:0e018d759a2a 1337 */
switches 0:0e018d759a2a 1338
switches 0:0e018d759a2a 1339
switches 0:0e018d759a2a 1340
switches 0:0e018d759a2a 1341 /* ########################## NVIC functions #################################### */
switches 0:0e018d759a2a 1342 /** \ingroup CMSIS_Core_FunctionInterface
switches 0:0e018d759a2a 1343 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
switches 0:0e018d759a2a 1344 \brief Functions that manage interrupts and exceptions via the NVIC.
switches 0:0e018d759a2a 1345 @{
switches 0:0e018d759a2a 1346 */
switches 0:0e018d759a2a 1347
switches 0:0e018d759a2a 1348 #ifdef CMSIS_NVIC_VIRTUAL
switches 0:0e018d759a2a 1349 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
switches 0:0e018d759a2a 1350 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
switches 0:0e018d759a2a 1351 #endif
switches 0:0e018d759a2a 1352 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
switches 0:0e018d759a2a 1353 #else
switches 0:0e018d759a2a 1354 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
switches 0:0e018d759a2a 1355 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
switches 0:0e018d759a2a 1356 #define NVIC_EnableIRQ __NVIC_EnableIRQ
switches 0:0e018d759a2a 1357 #define NVIC_DisableIRQ __NVIC_DisableIRQ
switches 0:0e018d759a2a 1358 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
switches 0:0e018d759a2a 1359 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
switches 0:0e018d759a2a 1360 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
switches 0:0e018d759a2a 1361 #define NVIC_GetActive __NVIC_GetActive
switches 0:0e018d759a2a 1362 #define NVIC_SetPriority __NVIC_SetPriority
switches 0:0e018d759a2a 1363 #define NVIC_GetPriority __NVIC_GetPriority
switches 0:0e018d759a2a 1364 #define NVIC_SystemReset __NVIC_SystemReset
switches 0:0e018d759a2a 1365 #endif /* CMSIS_NVIC_VIRTUAL */
switches 0:0e018d759a2a 1366
switches 0:0e018d759a2a 1367 #ifdef CMSIS_VECTAB_VIRTUAL
switches 0:0e018d759a2a 1368 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
switches 0:0e018d759a2a 1369 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
switches 0:0e018d759a2a 1370 #endif
switches 0:0e018d759a2a 1371 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
switches 0:0e018d759a2a 1372 #else
switches 0:0e018d759a2a 1373 #define NVIC_SetVector __NVIC_SetVector
switches 0:0e018d759a2a 1374 #define NVIC_GetVector __NVIC_GetVector
switches 0:0e018d759a2a 1375 #endif /* CMSIS_VECTAB_VIRTUAL */
switches 0:0e018d759a2a 1376
switches 0:0e018d759a2a 1377 /** \brief Set Priority Grouping
switches 0:0e018d759a2a 1378
switches 0:0e018d759a2a 1379 The function sets the priority grouping field using the required unlock sequence.
switches 0:0e018d759a2a 1380 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
switches 0:0e018d759a2a 1381 Only values from 0..7 are used.
switches 0:0e018d759a2a 1382 In case of a conflict between priority grouping and available
switches 0:0e018d759a2a 1383 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
switches 0:0e018d759a2a 1384
switches 0:0e018d759a2a 1385 \param [in] PriorityGroup Priority grouping field.
switches 0:0e018d759a2a 1386 */
switches 0:0e018d759a2a 1387 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
switches 0:0e018d759a2a 1388 {
switches 0:0e018d759a2a 1389 uint32_t reg_value;
switches 0:0e018d759a2a 1390 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
switches 0:0e018d759a2a 1391
switches 0:0e018d759a2a 1392 reg_value = SCB->AIRCR; /* read old register configuration */
switches 0:0e018d759a2a 1393 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
switches 0:0e018d759a2a 1394 reg_value = (reg_value |
switches 0:0e018d759a2a 1395 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
switches 0:0e018d759a2a 1396 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
switches 0:0e018d759a2a 1397 SCB->AIRCR = reg_value;
switches 0:0e018d759a2a 1398 }
switches 0:0e018d759a2a 1399
switches 0:0e018d759a2a 1400
switches 0:0e018d759a2a 1401 /** \brief Get Priority Grouping
switches 0:0e018d759a2a 1402
switches 0:0e018d759a2a 1403 The function reads the priority grouping field from the NVIC Interrupt Controller.
switches 0:0e018d759a2a 1404
switches 0:0e018d759a2a 1405 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
switches 0:0e018d759a2a 1406 */
switches 0:0e018d759a2a 1407 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
switches 0:0e018d759a2a 1408 {
switches 0:0e018d759a2a 1409 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
switches 0:0e018d759a2a 1410 }
switches 0:0e018d759a2a 1411
switches 0:0e018d759a2a 1412
switches 0:0e018d759a2a 1413 /** \brief Enable External Interrupt
switches 0:0e018d759a2a 1414
switches 0:0e018d759a2a 1415 The function enables a device-specific interrupt in the NVIC interrupt controller.
switches 0:0e018d759a2a 1416
switches 0:0e018d759a2a 1417 \param [in] IRQn External interrupt number. Value cannot be negative.
switches 0:0e018d759a2a 1418 */
switches 0:0e018d759a2a 1419 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
switches 0:0e018d759a2a 1420 {
switches 0:0e018d759a2a 1421 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
switches 0:0e018d759a2a 1422 }
switches 0:0e018d759a2a 1423
switches 0:0e018d759a2a 1424
switches 0:0e018d759a2a 1425 /** \brief Disable External Interrupt
switches 0:0e018d759a2a 1426
switches 0:0e018d759a2a 1427 The function disables a device-specific interrupt in the NVIC interrupt controller.
switches 0:0e018d759a2a 1428
switches 0:0e018d759a2a 1429 \param [in] IRQn External interrupt number. Value cannot be negative.
switches 0:0e018d759a2a 1430 */
switches 0:0e018d759a2a 1431 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
switches 0:0e018d759a2a 1432 {
switches 0:0e018d759a2a 1433 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
switches 0:0e018d759a2a 1434 }
switches 0:0e018d759a2a 1435
switches 0:0e018d759a2a 1436
switches 0:0e018d759a2a 1437 /** \brief Get Pending Interrupt
switches 0:0e018d759a2a 1438
switches 0:0e018d759a2a 1439 The function reads the pending register in the NVIC and returns the pending bit
switches 0:0e018d759a2a 1440 for the specified interrupt.
switches 0:0e018d759a2a 1441
switches 0:0e018d759a2a 1442 \param [in] IRQn Interrupt number.
switches 0:0e018d759a2a 1443
switches 0:0e018d759a2a 1444 \return 0 Interrupt status is not pending.
switches 0:0e018d759a2a 1445 \return 1 Interrupt status is pending.
switches 0:0e018d759a2a 1446 */
switches 0:0e018d759a2a 1447 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
switches 0:0e018d759a2a 1448 {
switches 0:0e018d759a2a 1449 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
switches 0:0e018d759a2a 1450 }
switches 0:0e018d759a2a 1451
switches 0:0e018d759a2a 1452
switches 0:0e018d759a2a 1453 /** \brief Set Pending Interrupt
switches 0:0e018d759a2a 1454
switches 0:0e018d759a2a 1455 The function sets the pending bit of an external interrupt.
switches 0:0e018d759a2a 1456
switches 0:0e018d759a2a 1457 \param [in] IRQn Interrupt number. Value cannot be negative.
switches 0:0e018d759a2a 1458 */
switches 0:0e018d759a2a 1459 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
switches 0:0e018d759a2a 1460 {
switches 0:0e018d759a2a 1461 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
switches 0:0e018d759a2a 1462 }
switches 0:0e018d759a2a 1463
switches 0:0e018d759a2a 1464
switches 0:0e018d759a2a 1465 /** \brief Clear Pending Interrupt
switches 0:0e018d759a2a 1466
switches 0:0e018d759a2a 1467 The function clears the pending bit of an external interrupt.
switches 0:0e018d759a2a 1468
switches 0:0e018d759a2a 1469 \param [in] IRQn External interrupt number. Value cannot be negative.
switches 0:0e018d759a2a 1470 */
switches 0:0e018d759a2a 1471 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
switches 0:0e018d759a2a 1472 {
switches 0:0e018d759a2a 1473 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
switches 0:0e018d759a2a 1474 }
switches 0:0e018d759a2a 1475
switches 0:0e018d759a2a 1476
switches 0:0e018d759a2a 1477 /** \brief Get Active Interrupt
switches 0:0e018d759a2a 1478
switches 0:0e018d759a2a 1479 The function reads the active register in NVIC and returns the active bit.
switches 0:0e018d759a2a 1480
switches 0:0e018d759a2a 1481 \param [in] IRQn Interrupt number.
switches 0:0e018d759a2a 1482
switches 0:0e018d759a2a 1483 \return 0 Interrupt status is not active.
switches 0:0e018d759a2a 1484 \return 1 Interrupt status is active.
switches 0:0e018d759a2a 1485 */
switches 0:0e018d759a2a 1486 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
switches 0:0e018d759a2a 1487 {
switches 0:0e018d759a2a 1488 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
switches 0:0e018d759a2a 1489 }
switches 0:0e018d759a2a 1490
switches 0:0e018d759a2a 1491
switches 0:0e018d759a2a 1492 /** \brief Set Interrupt Priority
switches 0:0e018d759a2a 1493
switches 0:0e018d759a2a 1494 The function sets the priority of an interrupt.
switches 0:0e018d759a2a 1495
switches 0:0e018d759a2a 1496 \note The priority cannot be set for every core interrupt.
switches 0:0e018d759a2a 1497
switches 0:0e018d759a2a 1498 \param [in] IRQn Interrupt number.
switches 0:0e018d759a2a 1499 \param [in] priority Priority to set.
switches 0:0e018d759a2a 1500 */
switches 0:0e018d759a2a 1501 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
switches 0:0e018d759a2a 1502 {
switches 0:0e018d759a2a 1503 if((int32_t)IRQn < 0) {
switches 0:0e018d759a2a 1504 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
switches 0:0e018d759a2a 1505 }
switches 0:0e018d759a2a 1506 else {
switches 0:0e018d759a2a 1507 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
switches 0:0e018d759a2a 1508 }
switches 0:0e018d759a2a 1509 }
switches 0:0e018d759a2a 1510
switches 0:0e018d759a2a 1511
switches 0:0e018d759a2a 1512 /** \brief Get Interrupt Priority
switches 0:0e018d759a2a 1513
switches 0:0e018d759a2a 1514 The function reads the priority of an interrupt. The interrupt
switches 0:0e018d759a2a 1515 number can be positive to specify an external (device specific)
switches 0:0e018d759a2a 1516 interrupt, or negative to specify an internal (core) interrupt.
switches 0:0e018d759a2a 1517
switches 0:0e018d759a2a 1518
switches 0:0e018d759a2a 1519 \param [in] IRQn Interrupt number.
switches 0:0e018d759a2a 1520 \return Interrupt Priority. Value is aligned automatically to the implemented
switches 0:0e018d759a2a 1521 priority bits of the microcontroller.
switches 0:0e018d759a2a 1522 */
switches 0:0e018d759a2a 1523 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
switches 0:0e018d759a2a 1524 {
switches 0:0e018d759a2a 1525
switches 0:0e018d759a2a 1526 if((int32_t)IRQn < 0) {
switches 0:0e018d759a2a 1527 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
switches 0:0e018d759a2a 1528 }
switches 0:0e018d759a2a 1529 else {
switches 0:0e018d759a2a 1530 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
switches 0:0e018d759a2a 1531 }
switches 0:0e018d759a2a 1532 }
switches 0:0e018d759a2a 1533
switches 0:0e018d759a2a 1534
switches 0:0e018d759a2a 1535 /** \brief Encode Priority
switches 0:0e018d759a2a 1536
switches 0:0e018d759a2a 1537 The function encodes the priority for an interrupt with the given priority group,
switches 0:0e018d759a2a 1538 preemptive priority value, and subpriority value.
switches 0:0e018d759a2a 1539 In case of a conflict between priority grouping and available
switches 0:0e018d759a2a 1540 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
switches 0:0e018d759a2a 1541
switches 0:0e018d759a2a 1542 \param [in] PriorityGroup Used priority group.
switches 0:0e018d759a2a 1543 \param [in] PreemptPriority Preemptive priority value (starting from 0).
switches 0:0e018d759a2a 1544 \param [in] SubPriority Subpriority value (starting from 0).
switches 0:0e018d759a2a 1545 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
switches 0:0e018d759a2a 1546 */
switches 0:0e018d759a2a 1547 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
switches 0:0e018d759a2a 1548 {
switches 0:0e018d759a2a 1549 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
switches 0:0e018d759a2a 1550 uint32_t PreemptPriorityBits;
switches 0:0e018d759a2a 1551 uint32_t SubPriorityBits;
switches 0:0e018d759a2a 1552
switches 0:0e018d759a2a 1553 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
switches 0:0e018d759a2a 1554 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
switches 0:0e018d759a2a 1555
switches 0:0e018d759a2a 1556 return (
switches 0:0e018d759a2a 1557 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
switches 0:0e018d759a2a 1558 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
switches 0:0e018d759a2a 1559 );
switches 0:0e018d759a2a 1560 }
switches 0:0e018d759a2a 1561
switches 0:0e018d759a2a 1562
switches 0:0e018d759a2a 1563 /** \brief Decode Priority
switches 0:0e018d759a2a 1564
switches 0:0e018d759a2a 1565 The function decodes an interrupt priority value with a given priority group to
switches 0:0e018d759a2a 1566 preemptive priority value and subpriority value.
switches 0:0e018d759a2a 1567 In case of a conflict between priority grouping and available
switches 0:0e018d759a2a 1568 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
switches 0:0e018d759a2a 1569
switches 0:0e018d759a2a 1570 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
switches 0:0e018d759a2a 1571 \param [in] PriorityGroup Used priority group.
switches 0:0e018d759a2a 1572 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
switches 0:0e018d759a2a 1573 \param [out] pSubPriority Subpriority value (starting from 0).
switches 0:0e018d759a2a 1574 */
switches 0:0e018d759a2a 1575 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
switches 0:0e018d759a2a 1576 {
switches 0:0e018d759a2a 1577 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
switches 0:0e018d759a2a 1578 uint32_t PreemptPriorityBits;
switches 0:0e018d759a2a 1579 uint32_t SubPriorityBits;
switches 0:0e018d759a2a 1580
switches 0:0e018d759a2a 1581 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
switches 0:0e018d759a2a 1582 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
switches 0:0e018d759a2a 1583
switches 0:0e018d759a2a 1584 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
switches 0:0e018d759a2a 1585 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
switches 0:0e018d759a2a 1586 }
switches 0:0e018d759a2a 1587
switches 0:0e018d759a2a 1588
switches 0:0e018d759a2a 1589 /** \brief System Reset
switches 0:0e018d759a2a 1590
switches 0:0e018d759a2a 1591 The function initiates a system reset request to reset the MCU.
switches 0:0e018d759a2a 1592 */
switches 0:0e018d759a2a 1593 __STATIC_INLINE void __NVIC_SystemReset(void)
switches 0:0e018d759a2a 1594 {
switches 0:0e018d759a2a 1595 __DSB(); /* Ensure all outstanding memory accesses included
switches 0:0e018d759a2a 1596 buffered write are completed before reset */
switches 0:0e018d759a2a 1597 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
switches 0:0e018d759a2a 1598 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
switches 0:0e018d759a2a 1599 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
switches 0:0e018d759a2a 1600 __DSB(); /* Ensure completion of memory access */
switches 0:0e018d759a2a 1601 while(1) { __NOP(); } /* wait until reset */
switches 0:0e018d759a2a 1602 }
switches 0:0e018d759a2a 1603
switches 0:0e018d759a2a 1604 /*@} end of CMSIS_Core_NVICFunctions */
switches 0:0e018d759a2a 1605
switches 0:0e018d759a2a 1606
switches 0:0e018d759a2a 1607
switches 0:0e018d759a2a 1608 /* ################################## SysTick function ############################################ */
switches 0:0e018d759a2a 1609 /** \ingroup CMSIS_Core_FunctionInterface
switches 0:0e018d759a2a 1610 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
switches 0:0e018d759a2a 1611 \brief Functions that configure the System.
switches 0:0e018d759a2a 1612 @{
switches 0:0e018d759a2a 1613 */
switches 0:0e018d759a2a 1614
switches 0:0e018d759a2a 1615 #if (__Vendor_SysTickConfig == 0)
switches 0:0e018d759a2a 1616
switches 0:0e018d759a2a 1617 /** \brief System Tick Configuration
switches 0:0e018d759a2a 1618
switches 0:0e018d759a2a 1619 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
switches 0:0e018d759a2a 1620 Counter is in free running mode to generate periodic interrupts.
switches 0:0e018d759a2a 1621
switches 0:0e018d759a2a 1622 \param [in] ticks Number of ticks between two interrupts.
switches 0:0e018d759a2a 1623
switches 0:0e018d759a2a 1624 \return 0 Function succeeded.
switches 0:0e018d759a2a 1625 \return 1 Function failed.
switches 0:0e018d759a2a 1626
switches 0:0e018d759a2a 1627 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
switches 0:0e018d759a2a 1628 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
switches 0:0e018d759a2a 1629 must contain a vendor-specific implementation of this function.
switches 0:0e018d759a2a 1630
switches 0:0e018d759a2a 1631 */
switches 0:0e018d759a2a 1632 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
switches 0:0e018d759a2a 1633 {
switches 0:0e018d759a2a 1634 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
switches 0:0e018d759a2a 1635
switches 0:0e018d759a2a 1636 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
switches 0:0e018d759a2a 1637 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
switches 0:0e018d759a2a 1638 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
switches 0:0e018d759a2a 1639 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
switches 0:0e018d759a2a 1640 SysTick_CTRL_TICKINT_Msk |
switches 0:0e018d759a2a 1641 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
switches 0:0e018d759a2a 1642 return (0UL); /* Function successful */
switches 0:0e018d759a2a 1643 }
switches 0:0e018d759a2a 1644
switches 0:0e018d759a2a 1645 #endif
switches 0:0e018d759a2a 1646
switches 0:0e018d759a2a 1647 /*@} end of CMSIS_Core_SysTickFunctions */
switches 0:0e018d759a2a 1648
switches 0:0e018d759a2a 1649
switches 0:0e018d759a2a 1650
switches 0:0e018d759a2a 1651 /* ##################################### Debug In/Output function ########################################### */
switches 0:0e018d759a2a 1652 /** \ingroup CMSIS_Core_FunctionInterface
switches 0:0e018d759a2a 1653 \defgroup CMSIS_core_DebugFunctions ITM Functions
switches 0:0e018d759a2a 1654 \brief Functions that access the ITM debug interface.
switches 0:0e018d759a2a 1655 @{
switches 0:0e018d759a2a 1656 */
switches 0:0e018d759a2a 1657
switches 0:0e018d759a2a 1658 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
switches 0:0e018d759a2a 1659 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
switches 0:0e018d759a2a 1660
switches 0:0e018d759a2a 1661
switches 0:0e018d759a2a 1662 /** \brief ITM Send Character
switches 0:0e018d759a2a 1663
switches 0:0e018d759a2a 1664 The function transmits a character via the ITM channel 0, and
switches 0:0e018d759a2a 1665 \li Just returns when no debugger is connected that has booked the output.
switches 0:0e018d759a2a 1666 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
switches 0:0e018d759a2a 1667
switches 0:0e018d759a2a 1668 \param [in] ch Character to transmit.
switches 0:0e018d759a2a 1669
switches 0:0e018d759a2a 1670 \returns Character to transmit.
switches 0:0e018d759a2a 1671 */
switches 0:0e018d759a2a 1672 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
switches 0:0e018d759a2a 1673 {
switches 0:0e018d759a2a 1674 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
switches 0:0e018d759a2a 1675 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
switches 0:0e018d759a2a 1676 {
switches 0:0e018d759a2a 1677 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
switches 0:0e018d759a2a 1678 ITM->PORT[0].u8 = (uint8_t)ch;
switches 0:0e018d759a2a 1679 }
switches 0:0e018d759a2a 1680 return (ch);
switches 0:0e018d759a2a 1681 }
switches 0:0e018d759a2a 1682
switches 0:0e018d759a2a 1683
switches 0:0e018d759a2a 1684 /** \brief ITM Receive Character
switches 0:0e018d759a2a 1685
switches 0:0e018d759a2a 1686 The function inputs a character via the external variable \ref ITM_RxBuffer.
switches 0:0e018d759a2a 1687
switches 0:0e018d759a2a 1688 \return Received character.
switches 0:0e018d759a2a 1689 \return -1 No character pending.
switches 0:0e018d759a2a 1690 */
switches 0:0e018d759a2a 1691 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
switches 0:0e018d759a2a 1692 int32_t ch = -1; /* no character available */
switches 0:0e018d759a2a 1693
switches 0:0e018d759a2a 1694 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
switches 0:0e018d759a2a 1695 ch = ITM_RxBuffer;
switches 0:0e018d759a2a 1696 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
switches 0:0e018d759a2a 1697 }
switches 0:0e018d759a2a 1698
switches 0:0e018d759a2a 1699 return (ch);
switches 0:0e018d759a2a 1700 }
switches 0:0e018d759a2a 1701
switches 0:0e018d759a2a 1702
switches 0:0e018d759a2a 1703 /** \brief ITM Check Character
switches 0:0e018d759a2a 1704
switches 0:0e018d759a2a 1705 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
switches 0:0e018d759a2a 1706
switches 0:0e018d759a2a 1707 \return 0 No character available.
switches 0:0e018d759a2a 1708 \return 1 Character available.
switches 0:0e018d759a2a 1709 */
switches 0:0e018d759a2a 1710 __STATIC_INLINE int32_t ITM_CheckChar (void) {
switches 0:0e018d759a2a 1711
switches 0:0e018d759a2a 1712 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
switches 0:0e018d759a2a 1713 return (0); /* no character available */
switches 0:0e018d759a2a 1714 } else {
switches 0:0e018d759a2a 1715 return (1); /* character available */
switches 0:0e018d759a2a 1716 }
switches 0:0e018d759a2a 1717 }
switches 0:0e018d759a2a 1718
switches 0:0e018d759a2a 1719 /*@} end of CMSIS_core_DebugFunctions */
switches 0:0e018d759a2a 1720
switches 0:0e018d759a2a 1721
switches 0:0e018d759a2a 1722
switches 0:0e018d759a2a 1723
switches 0:0e018d759a2a 1724 #ifdef __cplusplus
switches 0:0e018d759a2a 1725 }
switches 0:0e018d759a2a 1726 #endif
switches 0:0e018d759a2a 1727
switches 0:0e018d759a2a 1728 #endif /* __CORE_CM3_H_DEPENDANT */
switches 0:0e018d759a2a 1729
switches 0:0e018d759a2a 1730 #endif /* __CMSIS_GENERIC */