Greg Steiert / maxim_dev

Maxim mbed development library

Dependents:   sensomed

cmsis/core_cm0plus.h@0:0e018d759a2a, 2016-11-08 (annotated)

Committer:
switches
Date:
Tue Nov 08 18:27:11 2016 +0000
Revision:
0:0e018d759a2a
Initial commit

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switches 0:0e018d759a2a 1 /**************************************************************************//**
switches 0:0e018d759a2a 2 * @file core_cm0plus.h
switches 0:0e018d759a2a 3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
switches 0:0e018d759a2a 4 * @version V4.10
switches 0:0e018d759a2a 5 * @date 18. March 2015
switches 0:0e018d759a2a 6 *
switches 0:0e018d759a2a 7 * @note
switches 0:0e018d759a2a 8 *
switches 0:0e018d759a2a 9 ******************************************************************************/
switches 0:0e018d759a2a 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
switches 0:0e018d759a2a 11
switches 0:0e018d759a2a 12 All rights reserved.
switches 0:0e018d759a2a 13 Redistribution and use in source and binary forms, with or without
switches 0:0e018d759a2a 14 modification, are permitted provided that the following conditions are met:
switches 0:0e018d759a2a 15 - Redistributions of source code must retain the above copyright
switches 0:0e018d759a2a 16 notice, this list of conditions and the following disclaimer.
switches 0:0e018d759a2a 17 - Redistributions in binary form must reproduce the above copyright
switches 0:0e018d759a2a 18 notice, this list of conditions and the following disclaimer in the
switches 0:0e018d759a2a 19 documentation and/or other materials provided with the distribution.
switches 0:0e018d759a2a 20 - Neither the name of ARM nor the names of its contributors may be used
switches 0:0e018d759a2a 21 to endorse or promote products derived from this software without
switches 0:0e018d759a2a 22 specific prior written permission.
switches 0:0e018d759a2a 23 *
switches 0:0e018d759a2a 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
switches 0:0e018d759a2a 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
switches 0:0e018d759a2a 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
switches 0:0e018d759a2a 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
switches 0:0e018d759a2a 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
switches 0:0e018d759a2a 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
switches 0:0e018d759a2a 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
switches 0:0e018d759a2a 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
switches 0:0e018d759a2a 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
switches 0:0e018d759a2a 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
switches 0:0e018d759a2a 34 POSSIBILITY OF SUCH DAMAGE.
switches 0:0e018d759a2a 35 ---------------------------------------------------------------------------*/
switches 0:0e018d759a2a 36
switches 0:0e018d759a2a 37
switches 0:0e018d759a2a 38 #if defined ( __ICCARM__ )
switches 0:0e018d759a2a 39 #pragma system_include /* treat file as system include file for MISRA check */
switches 0:0e018d759a2a 40 #endif
switches 0:0e018d759a2a 41
switches 0:0e018d759a2a 42 #ifndef __CORE_CM0PLUS_H_GENERIC
switches 0:0e018d759a2a 43 #define __CORE_CM0PLUS_H_GENERIC
switches 0:0e018d759a2a 44
switches 0:0e018d759a2a 45 #ifdef __cplusplus
switches 0:0e018d759a2a 46 extern "C" {
switches 0:0e018d759a2a 47 #endif
switches 0:0e018d759a2a 48
switches 0:0e018d759a2a 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
switches 0:0e018d759a2a 50 CMSIS violates the following MISRA-C:2004 rules:
switches 0:0e018d759a2a 51
switches 0:0e018d759a2a 52 \li Required Rule 8.5, object/function definition in header file.<br>
switches 0:0e018d759a2a 53 Function definitions in header files are used to allow 'inlining'.
switches 0:0e018d759a2a 54
switches 0:0e018d759a2a 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
switches 0:0e018d759a2a 56 Unions are used for effective representation of core registers.
switches 0:0e018d759a2a 57
switches 0:0e018d759a2a 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
switches 0:0e018d759a2a 59 Function-like macros are used to allow more efficient code.
switches 0:0e018d759a2a 60 */
switches 0:0e018d759a2a 61
switches 0:0e018d759a2a 62
switches 0:0e018d759a2a 63 /*******************************************************************************
switches 0:0e018d759a2a 64 * CMSIS definitions
switches 0:0e018d759a2a 65 ******************************************************************************/
switches 0:0e018d759a2a 66 /** \ingroup Cortex-M0+
switches 0:0e018d759a2a 67 @{
switches 0:0e018d759a2a 68 */
switches 0:0e018d759a2a 69
switches 0:0e018d759a2a 70 /* CMSIS CM0P definitions */
switches 0:0e018d759a2a 71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
switches 0:0e018d759a2a 72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
switches 0:0e018d759a2a 73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
switches 0:0e018d759a2a 74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
switches 0:0e018d759a2a 75
switches 0:0e018d759a2a 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
switches 0:0e018d759a2a 77
switches 0:0e018d759a2a 78
switches 0:0e018d759a2a 79 #if defined ( __CC_ARM )
switches 0:0e018d759a2a 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
switches 0:0e018d759a2a 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
switches 0:0e018d759a2a 82 #define __STATIC_INLINE static __inline
switches 0:0e018d759a2a 83
switches 0:0e018d759a2a 84 #elif defined ( __GNUC__ )
switches 0:0e018d759a2a 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
switches 0:0e018d759a2a 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
switches 0:0e018d759a2a 87 #define __STATIC_INLINE static inline
switches 0:0e018d759a2a 88
switches 0:0e018d759a2a 89 #elif defined ( __ICCARM__ )
switches 0:0e018d759a2a 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
switches 0:0e018d759a2a 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
switches 0:0e018d759a2a 92 #define __STATIC_INLINE static inline
switches 0:0e018d759a2a 93
switches 0:0e018d759a2a 94 #elif defined ( __TMS470__ )
switches 0:0e018d759a2a 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
switches 0:0e018d759a2a 96 #define __STATIC_INLINE static inline
switches 0:0e018d759a2a 97
switches 0:0e018d759a2a 98 #elif defined ( __TASKING__ )
switches 0:0e018d759a2a 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
switches 0:0e018d759a2a 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
switches 0:0e018d759a2a 101 #define __STATIC_INLINE static inline
switches 0:0e018d759a2a 102
switches 0:0e018d759a2a 103 #elif defined ( __CSMC__ )
switches 0:0e018d759a2a 104 #define __packed
switches 0:0e018d759a2a 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
switches 0:0e018d759a2a 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
switches 0:0e018d759a2a 107 #define __STATIC_INLINE static inline
switches 0:0e018d759a2a 108
switches 0:0e018d759a2a 109 #endif
switches 0:0e018d759a2a 110
switches 0:0e018d759a2a 111 /** __FPU_USED indicates whether an FPU is used or not.
switches 0:0e018d759a2a 112 This core does not support an FPU at all
switches 0:0e018d759a2a 113 */
switches 0:0e018d759a2a 114 #define __FPU_USED 0
switches 0:0e018d759a2a 115
switches 0:0e018d759a2a 116 #if defined ( __CC_ARM )
switches 0:0e018d759a2a 117 #if defined __TARGET_FPU_VFP
switches 0:0e018d759a2a 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
switches 0:0e018d759a2a 119 #endif
switches 0:0e018d759a2a 120
switches 0:0e018d759a2a 121 #elif defined ( __GNUC__ )
switches 0:0e018d759a2a 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
switches 0:0e018d759a2a 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
switches 0:0e018d759a2a 124 #endif
switches 0:0e018d759a2a 125
switches 0:0e018d759a2a 126 #elif defined ( __ICCARM__ )
switches 0:0e018d759a2a 127 #if defined __ARMVFP__
switches 0:0e018d759a2a 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
switches 0:0e018d759a2a 129 #endif
switches 0:0e018d759a2a 130
switches 0:0e018d759a2a 131 #elif defined ( __TMS470__ )
switches 0:0e018d759a2a 132 #if defined __TI__VFP_SUPPORT____
switches 0:0e018d759a2a 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
switches 0:0e018d759a2a 134 #endif
switches 0:0e018d759a2a 135
switches 0:0e018d759a2a 136 #elif defined ( __TASKING__ )
switches 0:0e018d759a2a 137 #if defined __FPU_VFP__
switches 0:0e018d759a2a 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
switches 0:0e018d759a2a 139 #endif
switches 0:0e018d759a2a 140
switches 0:0e018d759a2a 141 #elif defined ( __CSMC__ ) /* Cosmic */
switches 0:0e018d759a2a 142 #if ( __CSMC__ & 0x400) // FPU present for parser
switches 0:0e018d759a2a 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
switches 0:0e018d759a2a 144 #endif
switches 0:0e018d759a2a 145 #endif
switches 0:0e018d759a2a 146
switches 0:0e018d759a2a 147 #include <stdint.h> /* standard types definitions */
switches 0:0e018d759a2a 148 #include <core_cmInstr.h> /* Core Instruction Access */
switches 0:0e018d759a2a 149 #include <core_cmFunc.h> /* Core Function Access */
switches 0:0e018d759a2a 150
switches 0:0e018d759a2a 151 #ifdef __cplusplus
switches 0:0e018d759a2a 152 }
switches 0:0e018d759a2a 153 #endif
switches 0:0e018d759a2a 154
switches 0:0e018d759a2a 155 #endif /* __CORE_CM0PLUS_H_GENERIC */
switches 0:0e018d759a2a 156
switches 0:0e018d759a2a 157 #ifndef __CMSIS_GENERIC
switches 0:0e018d759a2a 158
switches 0:0e018d759a2a 159 #ifndef __CORE_CM0PLUS_H_DEPENDANT
switches 0:0e018d759a2a 160 #define __CORE_CM0PLUS_H_DEPENDANT
switches 0:0e018d759a2a 161
switches 0:0e018d759a2a 162 #ifdef __cplusplus
switches 0:0e018d759a2a 163 extern "C" {
switches 0:0e018d759a2a 164 #endif
switches 0:0e018d759a2a 165
switches 0:0e018d759a2a 166 /* check device defines and use defaults */
switches 0:0e018d759a2a 167 #if defined __CHECK_DEVICE_DEFINES
switches 0:0e018d759a2a 168 #ifndef __CM0PLUS_REV
switches 0:0e018d759a2a 169 #define __CM0PLUS_REV 0x0000
switches 0:0e018d759a2a 170 #warning "__CM0PLUS_REV not defined in device header file; using default!"
switches 0:0e018d759a2a 171 #endif
switches 0:0e018d759a2a 172
switches 0:0e018d759a2a 173 #ifndef __MPU_PRESENT
switches 0:0e018d759a2a 174 #define __MPU_PRESENT 0
switches 0:0e018d759a2a 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
switches 0:0e018d759a2a 176 #endif
switches 0:0e018d759a2a 177
switches 0:0e018d759a2a 178 #ifndef __VTOR_PRESENT
switches 0:0e018d759a2a 179 #define __VTOR_PRESENT 0
switches 0:0e018d759a2a 180 #warning "__VTOR_PRESENT not defined in device header file; using default!"
switches 0:0e018d759a2a 181 #endif
switches 0:0e018d759a2a 182
switches 0:0e018d759a2a 183 #ifndef __NVIC_PRIO_BITS
switches 0:0e018d759a2a 184 #define __NVIC_PRIO_BITS 2
switches 0:0e018d759a2a 185 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
switches 0:0e018d759a2a 186 #endif
switches 0:0e018d759a2a 187
switches 0:0e018d759a2a 188 #ifndef __Vendor_SysTickConfig
switches 0:0e018d759a2a 189 #define __Vendor_SysTickConfig 0
switches 0:0e018d759a2a 190 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
switches 0:0e018d759a2a 191 #endif
switches 0:0e018d759a2a 192 #endif
switches 0:0e018d759a2a 193
switches 0:0e018d759a2a 194 /* IO definitions (access restrictions to peripheral registers) */
switches 0:0e018d759a2a 195 /**
switches 0:0e018d759a2a 196 \defgroup CMSIS_glob_defs CMSIS Global Defines
switches 0:0e018d759a2a 197
switches 0:0e018d759a2a 198 <strong>IO Type Qualifiers</strong> are used
switches 0:0e018d759a2a 199 \li to specify the access to peripheral variables.
switches 0:0e018d759a2a 200 \li for automatic generation of peripheral register debug information.
switches 0:0e018d759a2a 201 */
switches 0:0e018d759a2a 202 #ifdef __cplusplus
switches 0:0e018d759a2a 203 #define __I volatile /*!< Defines 'read only' permissions */
switches 0:0e018d759a2a 204 #else
switches 0:0e018d759a2a 205 #define __I volatile const /*!< Defines 'read only' permissions */
switches 0:0e018d759a2a 206 #endif
switches 0:0e018d759a2a 207 #define __O volatile /*!< Defines 'write only' permissions */
switches 0:0e018d759a2a 208 #define __IO volatile /*!< Defines 'read / write' permissions */
switches 0:0e018d759a2a 209
switches 0:0e018d759a2a 210 #ifdef __cplusplus
switches 0:0e018d759a2a 211 #define __IM volatile /*!< Defines 'read only' permissions */
switches 0:0e018d759a2a 212 #else
switches 0:0e018d759a2a 213 #define __IM volatile const /*!< Defines 'read only' permissions */
switches 0:0e018d759a2a 214 #endif
switches 0:0e018d759a2a 215 #define __OM volatile /*!< Defines 'write only' permissions */
switches 0:0e018d759a2a 216 #define __IOM volatile /*!< Defines 'read / write' permissions */
switches 0:0e018d759a2a 217
switches 0:0e018d759a2a 218 /*@} end of group Cortex-M0+ */
switches 0:0e018d759a2a 219
switches 0:0e018d759a2a 220
switches 0:0e018d759a2a 221
switches 0:0e018d759a2a 222 /*******************************************************************************
switches 0:0e018d759a2a 223 * Register Abstraction
switches 0:0e018d759a2a 224 Core Register contain:
switches 0:0e018d759a2a 225 - Core Register
switches 0:0e018d759a2a 226 - Core NVIC Register
switches 0:0e018d759a2a 227 - Core SCB Register
switches 0:0e018d759a2a 228 - Core SysTick Register
switches 0:0e018d759a2a 229 - Core MPU Register
switches 0:0e018d759a2a 230 ******************************************************************************/
switches 0:0e018d759a2a 231 /** \defgroup CMSIS_core_register Defines and Type Definitions
switches 0:0e018d759a2a 232 \brief Type definitions and defines for Cortex-M processor based devices.
switches 0:0e018d759a2a 233 */
switches 0:0e018d759a2a 234
switches 0:0e018d759a2a 235 /** \ingroup CMSIS_core_register
switches 0:0e018d759a2a 236 \defgroup CMSIS_CORE Status and Control Registers
switches 0:0e018d759a2a 237 \brief Core Register type definitions.
switches 0:0e018d759a2a 238 @{
switches 0:0e018d759a2a 239 */
switches 0:0e018d759a2a 240
switches 0:0e018d759a2a 241 /** \brief Union type to access the Application Program Status Register (APSR).
switches 0:0e018d759a2a 242 */
switches 0:0e018d759a2a 243 typedef union
switches 0:0e018d759a2a 244 {
switches 0:0e018d759a2a 245 struct
switches 0:0e018d759a2a 246 {
switches 0:0e018d759a2a 247 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
switches 0:0e018d759a2a 248 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
switches 0:0e018d759a2a 249 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
switches 0:0e018d759a2a 250 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
switches 0:0e018d759a2a 251 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
switches 0:0e018d759a2a 252 } b; /*!< Structure used for bit access */
switches 0:0e018d759a2a 253 uint32_t w; /*!< Type used for word access */
switches 0:0e018d759a2a 254 } APSR_Type;
switches 0:0e018d759a2a 255
switches 0:0e018d759a2a 256 /* APSR Register Definitions */
switches 0:0e018d759a2a 257 #define APSR_N_Pos 31 /*!< APSR: N Position */
switches 0:0e018d759a2a 258 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
switches 0:0e018d759a2a 259
switches 0:0e018d759a2a 260 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
switches 0:0e018d759a2a 261 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
switches 0:0e018d759a2a 262
switches 0:0e018d759a2a 263 #define APSR_C_Pos 29 /*!< APSR: C Position */
switches 0:0e018d759a2a 264 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
switches 0:0e018d759a2a 265
switches 0:0e018d759a2a 266 #define APSR_V_Pos 28 /*!< APSR: V Position */
switches 0:0e018d759a2a 267 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
switches 0:0e018d759a2a 268
switches 0:0e018d759a2a 269
switches 0:0e018d759a2a 270 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
switches 0:0e018d759a2a 271 */
switches 0:0e018d759a2a 272 typedef union
switches 0:0e018d759a2a 273 {
switches 0:0e018d759a2a 274 struct
switches 0:0e018d759a2a 275 {
switches 0:0e018d759a2a 276 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
switches 0:0e018d759a2a 277 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
switches 0:0e018d759a2a 278 } b; /*!< Structure used for bit access */
switches 0:0e018d759a2a 279 uint32_t w; /*!< Type used for word access */
switches 0:0e018d759a2a 280 } IPSR_Type;
switches 0:0e018d759a2a 281
switches 0:0e018d759a2a 282 /* IPSR Register Definitions */
switches 0:0e018d759a2a 283 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
switches 0:0e018d759a2a 284 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
switches 0:0e018d759a2a 285
switches 0:0e018d759a2a 286
switches 0:0e018d759a2a 287 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
switches 0:0e018d759a2a 288 */
switches 0:0e018d759a2a 289 typedef union
switches 0:0e018d759a2a 290 {
switches 0:0e018d759a2a 291 struct
switches 0:0e018d759a2a 292 {
switches 0:0e018d759a2a 293 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
switches 0:0e018d759a2a 294 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
switches 0:0e018d759a2a 295 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
switches 0:0e018d759a2a 296 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
switches 0:0e018d759a2a 297 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
switches 0:0e018d759a2a 298 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
switches 0:0e018d759a2a 299 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
switches 0:0e018d759a2a 300 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
switches 0:0e018d759a2a 301 } b; /*!< Structure used for bit access */
switches 0:0e018d759a2a 302 uint32_t w; /*!< Type used for word access */
switches 0:0e018d759a2a 303 } xPSR_Type;
switches 0:0e018d759a2a 304
switches 0:0e018d759a2a 305 /* xPSR Register Definitions */
switches 0:0e018d759a2a 306 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
switches 0:0e018d759a2a 307 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
switches 0:0e018d759a2a 308
switches 0:0e018d759a2a 309 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
switches 0:0e018d759a2a 310 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
switches 0:0e018d759a2a 311
switches 0:0e018d759a2a 312 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
switches 0:0e018d759a2a 313 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
switches 0:0e018d759a2a 314
switches 0:0e018d759a2a 315 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
switches 0:0e018d759a2a 316 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
switches 0:0e018d759a2a 317
switches 0:0e018d759a2a 318 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
switches 0:0e018d759a2a 319 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
switches 0:0e018d759a2a 320
switches 0:0e018d759a2a 321 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
switches 0:0e018d759a2a 322 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
switches 0:0e018d759a2a 323
switches 0:0e018d759a2a 324
switches 0:0e018d759a2a 325 /** \brief Union type to access the Control Registers (CONTROL).
switches 0:0e018d759a2a 326 */
switches 0:0e018d759a2a 327 typedef union
switches 0:0e018d759a2a 328 {
switches 0:0e018d759a2a 329 struct
switches 0:0e018d759a2a 330 {
switches 0:0e018d759a2a 331 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
switches 0:0e018d759a2a 332 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
switches 0:0e018d759a2a 333 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
switches 0:0e018d759a2a 334 } b; /*!< Structure used for bit access */
switches 0:0e018d759a2a 335 uint32_t w; /*!< Type used for word access */
switches 0:0e018d759a2a 336 } CONTROL_Type;
switches 0:0e018d759a2a 337
switches 0:0e018d759a2a 338 /* CONTROL Register Definitions */
switches 0:0e018d759a2a 339 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
switches 0:0e018d759a2a 340 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
switches 0:0e018d759a2a 341
switches 0:0e018d759a2a 342 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
switches 0:0e018d759a2a 343 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
switches 0:0e018d759a2a 344
switches 0:0e018d759a2a 345 /*@} end of group CMSIS_CORE */
switches 0:0e018d759a2a 346
switches 0:0e018d759a2a 347
switches 0:0e018d759a2a 348 /** \ingroup CMSIS_core_register
switches 0:0e018d759a2a 349 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
switches 0:0e018d759a2a 350 \brief Type definitions for the NVIC Registers
switches 0:0e018d759a2a 351 @{
switches 0:0e018d759a2a 352 */
switches 0:0e018d759a2a 353
switches 0:0e018d759a2a 354 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
switches 0:0e018d759a2a 355 */
switches 0:0e018d759a2a 356 typedef struct
switches 0:0e018d759a2a 357 {
switches 0:0e018d759a2a 358 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
switches 0:0e018d759a2a 359 uint32_t RESERVED0[31];
switches 0:0e018d759a2a 360 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
switches 0:0e018d759a2a 361 uint32_t RSERVED1[31];
switches 0:0e018d759a2a 362 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
switches 0:0e018d759a2a 363 uint32_t RESERVED2[31];
switches 0:0e018d759a2a 364 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
switches 0:0e018d759a2a 365 uint32_t RESERVED3[31];
switches 0:0e018d759a2a 366 uint32_t RESERVED4[64];
switches 0:0e018d759a2a 367 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
switches 0:0e018d759a2a 368 } NVIC_Type;
switches 0:0e018d759a2a 369
switches 0:0e018d759a2a 370 /*@} end of group CMSIS_NVIC */
switches 0:0e018d759a2a 371
switches 0:0e018d759a2a 372
switches 0:0e018d759a2a 373 /** \ingroup CMSIS_core_register
switches 0:0e018d759a2a 374 \defgroup CMSIS_SCB System Control Block (SCB)
switches 0:0e018d759a2a 375 \brief Type definitions for the System Control Block Registers
switches 0:0e018d759a2a 376 @{
switches 0:0e018d759a2a 377 */
switches 0:0e018d759a2a 378
switches 0:0e018d759a2a 379 /** \brief Structure type to access the System Control Block (SCB).
switches 0:0e018d759a2a 380 */
switches 0:0e018d759a2a 381 typedef struct
switches 0:0e018d759a2a 382 {
switches 0:0e018d759a2a 383 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
switches 0:0e018d759a2a 384 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
switches 0:0e018d759a2a 385 #if (__VTOR_PRESENT == 1)
switches 0:0e018d759a2a 386 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
switches 0:0e018d759a2a 387 #else
switches 0:0e018d759a2a 388 uint32_t RESERVED0;
switches 0:0e018d759a2a 389 #endif
switches 0:0e018d759a2a 390 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
switches 0:0e018d759a2a 391 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
switches 0:0e018d759a2a 392 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
switches 0:0e018d759a2a 393 uint32_t RESERVED1;
switches 0:0e018d759a2a 394 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
switches 0:0e018d759a2a 395 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
switches 0:0e018d759a2a 396 } SCB_Type;
switches 0:0e018d759a2a 397
switches 0:0e018d759a2a 398 /* SCB CPUID Register Definitions */
switches 0:0e018d759a2a 399 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
switches 0:0e018d759a2a 400 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
switches 0:0e018d759a2a 401
switches 0:0e018d759a2a 402 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
switches 0:0e018d759a2a 403 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
switches 0:0e018d759a2a 404
switches 0:0e018d759a2a 405 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
switches 0:0e018d759a2a 406 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
switches 0:0e018d759a2a 407
switches 0:0e018d759a2a 408 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
switches 0:0e018d759a2a 409 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
switches 0:0e018d759a2a 410
switches 0:0e018d759a2a 411 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
switches 0:0e018d759a2a 412 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
switches 0:0e018d759a2a 413
switches 0:0e018d759a2a 414 /* SCB Interrupt Control State Register Definitions */
switches 0:0e018d759a2a 415 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
switches 0:0e018d759a2a 416 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
switches 0:0e018d759a2a 417
switches 0:0e018d759a2a 418 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
switches 0:0e018d759a2a 419 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
switches 0:0e018d759a2a 420
switches 0:0e018d759a2a 421 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
switches 0:0e018d759a2a 422 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
switches 0:0e018d759a2a 423
switches 0:0e018d759a2a 424 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
switches 0:0e018d759a2a 425 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
switches 0:0e018d759a2a 426
switches 0:0e018d759a2a 427 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
switches 0:0e018d759a2a 428 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
switches 0:0e018d759a2a 429
switches 0:0e018d759a2a 430 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
switches 0:0e018d759a2a 431 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
switches 0:0e018d759a2a 432
switches 0:0e018d759a2a 433 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
switches 0:0e018d759a2a 434 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
switches 0:0e018d759a2a 435
switches 0:0e018d759a2a 436 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
switches 0:0e018d759a2a 437 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
switches 0:0e018d759a2a 438
switches 0:0e018d759a2a 439 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
switches 0:0e018d759a2a 440 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
switches 0:0e018d759a2a 441
switches 0:0e018d759a2a 442 #if (__VTOR_PRESENT == 1)
switches 0:0e018d759a2a 443 /* SCB Interrupt Control State Register Definitions */
switches 0:0e018d759a2a 444 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
switches 0:0e018d759a2a 445 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
switches 0:0e018d759a2a 446 #endif
switches 0:0e018d759a2a 447
switches 0:0e018d759a2a 448 /* SCB Application Interrupt and Reset Control Register Definitions */
switches 0:0e018d759a2a 449 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
switches 0:0e018d759a2a 450 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
switches 0:0e018d759a2a 451
switches 0:0e018d759a2a 452 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
switches 0:0e018d759a2a 453 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
switches 0:0e018d759a2a 454
switches 0:0e018d759a2a 455 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
switches 0:0e018d759a2a 456 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
switches 0:0e018d759a2a 457
switches 0:0e018d759a2a 458 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
switches 0:0e018d759a2a 459 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
switches 0:0e018d759a2a 460
switches 0:0e018d759a2a 461 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
switches 0:0e018d759a2a 462 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
switches 0:0e018d759a2a 463
switches 0:0e018d759a2a 464 /* SCB System Control Register Definitions */
switches 0:0e018d759a2a 465 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
switches 0:0e018d759a2a 466 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
switches 0:0e018d759a2a 467
switches 0:0e018d759a2a 468 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
switches 0:0e018d759a2a 469 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
switches 0:0e018d759a2a 470
switches 0:0e018d759a2a 471 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
switches 0:0e018d759a2a 472 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
switches 0:0e018d759a2a 473
switches 0:0e018d759a2a 474 /* SCB Configuration Control Register Definitions */
switches 0:0e018d759a2a 475 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
switches 0:0e018d759a2a 476 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
switches 0:0e018d759a2a 477
switches 0:0e018d759a2a 478 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
switches 0:0e018d759a2a 479 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
switches 0:0e018d759a2a 480
switches 0:0e018d759a2a 481 /* SCB System Handler Control and State Register Definitions */
switches 0:0e018d759a2a 482 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
switches 0:0e018d759a2a 483 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
switches 0:0e018d759a2a 484
switches 0:0e018d759a2a 485 /*@} end of group CMSIS_SCB */
switches 0:0e018d759a2a 486
switches 0:0e018d759a2a 487
switches 0:0e018d759a2a 488 /** \ingroup CMSIS_core_register
switches 0:0e018d759a2a 489 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
switches 0:0e018d759a2a 490 \brief Type definitions for the System Timer Registers.
switches 0:0e018d759a2a 491 @{
switches 0:0e018d759a2a 492 */
switches 0:0e018d759a2a 493
switches 0:0e018d759a2a 494 /** \brief Structure type to access the System Timer (SysTick).
switches 0:0e018d759a2a 495 */
switches 0:0e018d759a2a 496 typedef struct
switches 0:0e018d759a2a 497 {
switches 0:0e018d759a2a 498 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
switches 0:0e018d759a2a 499 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
switches 0:0e018d759a2a 500 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
switches 0:0e018d759a2a 501 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
switches 0:0e018d759a2a 502 } SysTick_Type;
switches 0:0e018d759a2a 503
switches 0:0e018d759a2a 504 /* SysTick Control / Status Register Definitions */
switches 0:0e018d759a2a 505 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
switches 0:0e018d759a2a 506 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
switches 0:0e018d759a2a 507
switches 0:0e018d759a2a 508 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
switches 0:0e018d759a2a 509 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
switches 0:0e018d759a2a 510
switches 0:0e018d759a2a 511 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
switches 0:0e018d759a2a 512 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
switches 0:0e018d759a2a 513
switches 0:0e018d759a2a 514 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
switches 0:0e018d759a2a 515 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
switches 0:0e018d759a2a 516
switches 0:0e018d759a2a 517 /* SysTick Reload Register Definitions */
switches 0:0e018d759a2a 518 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
switches 0:0e018d759a2a 519 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
switches 0:0e018d759a2a 520
switches 0:0e018d759a2a 521 /* SysTick Current Register Definitions */
switches 0:0e018d759a2a 522 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
switches 0:0e018d759a2a 523 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
switches 0:0e018d759a2a 524
switches 0:0e018d759a2a 525 /* SysTick Calibration Register Definitions */
switches 0:0e018d759a2a 526 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
switches 0:0e018d759a2a 527 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
switches 0:0e018d759a2a 528
switches 0:0e018d759a2a 529 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
switches 0:0e018d759a2a 530 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
switches 0:0e018d759a2a 531
switches 0:0e018d759a2a 532 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
switches 0:0e018d759a2a 533 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
switches 0:0e018d759a2a 534
switches 0:0e018d759a2a 535 /*@} end of group CMSIS_SysTick */
switches 0:0e018d759a2a 536
switches 0:0e018d759a2a 537 #if (__MPU_PRESENT == 1)
switches 0:0e018d759a2a 538 /** \ingroup CMSIS_core_register
switches 0:0e018d759a2a 539 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
switches 0:0e018d759a2a 540 \brief Type definitions for the Memory Protection Unit (MPU)
switches 0:0e018d759a2a 541 @{
switches 0:0e018d759a2a 542 */
switches 0:0e018d759a2a 543
switches 0:0e018d759a2a 544 /** \brief Structure type to access the Memory Protection Unit (MPU).
switches 0:0e018d759a2a 545 */
switches 0:0e018d759a2a 546 typedef struct
switches 0:0e018d759a2a 547 {
switches 0:0e018d759a2a 548 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
switches 0:0e018d759a2a 549 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
switches 0:0e018d759a2a 550 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
switches 0:0e018d759a2a 551 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
switches 0:0e018d759a2a 552 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
switches 0:0e018d759a2a 553 } MPU_Type;
switches 0:0e018d759a2a 554
switches 0:0e018d759a2a 555 /* MPU Type Register */
switches 0:0e018d759a2a 556 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
switches 0:0e018d759a2a 557 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
switches 0:0e018d759a2a 558
switches 0:0e018d759a2a 559 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
switches 0:0e018d759a2a 560 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
switches 0:0e018d759a2a 561
switches 0:0e018d759a2a 562 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
switches 0:0e018d759a2a 563 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
switches 0:0e018d759a2a 564
switches 0:0e018d759a2a 565 /* MPU Control Register */
switches 0:0e018d759a2a 566 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
switches 0:0e018d759a2a 567 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
switches 0:0e018d759a2a 568
switches 0:0e018d759a2a 569 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
switches 0:0e018d759a2a 570 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
switches 0:0e018d759a2a 571
switches 0:0e018d759a2a 572 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
switches 0:0e018d759a2a 573 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
switches 0:0e018d759a2a 574
switches 0:0e018d759a2a 575 /* MPU Region Number Register */
switches 0:0e018d759a2a 576 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
switches 0:0e018d759a2a 577 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
switches 0:0e018d759a2a 578
switches 0:0e018d759a2a 579 /* MPU Region Base Address Register */
switches 0:0e018d759a2a 580 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
switches 0:0e018d759a2a 581 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
switches 0:0e018d759a2a 582
switches 0:0e018d759a2a 583 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
switches 0:0e018d759a2a 584 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
switches 0:0e018d759a2a 585
switches 0:0e018d759a2a 586 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
switches 0:0e018d759a2a 587 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
switches 0:0e018d759a2a 588
switches 0:0e018d759a2a 589 /* MPU Region Attribute and Size Register */
switches 0:0e018d759a2a 590 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
switches 0:0e018d759a2a 591 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
switches 0:0e018d759a2a 592
switches 0:0e018d759a2a 593 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
switches 0:0e018d759a2a 594 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
switches 0:0e018d759a2a 595
switches 0:0e018d759a2a 596 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
switches 0:0e018d759a2a 597 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
switches 0:0e018d759a2a 598
switches 0:0e018d759a2a 599 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
switches 0:0e018d759a2a 600 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
switches 0:0e018d759a2a 601
switches 0:0e018d759a2a 602 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
switches 0:0e018d759a2a 603 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
switches 0:0e018d759a2a 604
switches 0:0e018d759a2a 605 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
switches 0:0e018d759a2a 606 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
switches 0:0e018d759a2a 607
switches 0:0e018d759a2a 608 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
switches 0:0e018d759a2a 609 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
switches 0:0e018d759a2a 610
switches 0:0e018d759a2a 611 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
switches 0:0e018d759a2a 612 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
switches 0:0e018d759a2a 613
switches 0:0e018d759a2a 614 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
switches 0:0e018d759a2a 615 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
switches 0:0e018d759a2a 616
switches 0:0e018d759a2a 617 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
switches 0:0e018d759a2a 618 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
switches 0:0e018d759a2a 619
switches 0:0e018d759a2a 620 /*@} end of group CMSIS_MPU */
switches 0:0e018d759a2a 621 #endif
switches 0:0e018d759a2a 622
switches 0:0e018d759a2a 623
switches 0:0e018d759a2a 624 /** \ingroup CMSIS_core_register
switches 0:0e018d759a2a 625 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
switches 0:0e018d759a2a 626 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
switches 0:0e018d759a2a 627 are only accessible over DAP and not via processor. Therefore
switches 0:0e018d759a2a 628 they are not covered by the Cortex-M0 header file.
switches 0:0e018d759a2a 629 @{
switches 0:0e018d759a2a 630 */
switches 0:0e018d759a2a 631 /*@} end of group CMSIS_CoreDebug */
switches 0:0e018d759a2a 632
switches 0:0e018d759a2a 633
switches 0:0e018d759a2a 634 /** \ingroup CMSIS_core_register
switches 0:0e018d759a2a 635 \defgroup CMSIS_core_base Core Definitions
switches 0:0e018d759a2a 636 \brief Definitions for base addresses, unions, and structures.
switches 0:0e018d759a2a 637 @{
switches 0:0e018d759a2a 638 */
switches 0:0e018d759a2a 639
switches 0:0e018d759a2a 640 /* Memory mapping of Cortex-M0+ Hardware */
switches 0:0e018d759a2a 641 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
switches 0:0e018d759a2a 642 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
switches 0:0e018d759a2a 643 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
switches 0:0e018d759a2a 644 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
switches 0:0e018d759a2a 645
switches 0:0e018d759a2a 646 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
switches 0:0e018d759a2a 647 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
switches 0:0e018d759a2a 648 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
switches 0:0e018d759a2a 649
switches 0:0e018d759a2a 650 #if (__MPU_PRESENT == 1)
switches 0:0e018d759a2a 651 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
switches 0:0e018d759a2a 652 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
switches 0:0e018d759a2a 653 #endif
switches 0:0e018d759a2a 654
switches 0:0e018d759a2a 655 /*@} */
switches 0:0e018d759a2a 656
switches 0:0e018d759a2a 657
switches 0:0e018d759a2a 658
switches 0:0e018d759a2a 659 /*******************************************************************************
switches 0:0e018d759a2a 660 * Hardware Abstraction Layer
switches 0:0e018d759a2a 661 Core Function Interface contains:
switches 0:0e018d759a2a 662 - Core NVIC Functions
switches 0:0e018d759a2a 663 - Core SysTick Functions
switches 0:0e018d759a2a 664 - Core Register Access Functions
switches 0:0e018d759a2a 665 ******************************************************************************/
switches 0:0e018d759a2a 666 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
switches 0:0e018d759a2a 667 */
switches 0:0e018d759a2a 668
switches 0:0e018d759a2a 669
switches 0:0e018d759a2a 670
switches 0:0e018d759a2a 671 /* ########################## NVIC functions #################################### */
switches 0:0e018d759a2a 672 /** \ingroup CMSIS_Core_FunctionInterface
switches 0:0e018d759a2a 673 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
switches 0:0e018d759a2a 674 \brief Functions that manage interrupts and exceptions via the NVIC.
switches 0:0e018d759a2a 675 @{
switches 0:0e018d759a2a 676 */
switches 0:0e018d759a2a 677
switches 0:0e018d759a2a 678 /* Interrupt Priorities are WORD accessible only under ARMv6M */
switches 0:0e018d759a2a 679 /* The following MACROS handle generation of the register offset and byte masks */
switches 0:0e018d759a2a 680 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
switches 0:0e018d759a2a 681 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
switches 0:0e018d759a2a 682 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
switches 0:0e018d759a2a 683
switches 0:0e018d759a2a 684
switches 0:0e018d759a2a 685 /** \brief Enable External Interrupt
switches 0:0e018d759a2a 686
switches 0:0e018d759a2a 687 The function enables a device-specific interrupt in the NVIC interrupt controller.
switches 0:0e018d759a2a 688
switches 0:0e018d759a2a 689 \param [in] IRQn External interrupt number. Value cannot be negative.
switches 0:0e018d759a2a 690 */
switches 0:0e018d759a2a 691 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
switches 0:0e018d759a2a 692 {
switches 0:0e018d759a2a 693 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
switches 0:0e018d759a2a 694 }
switches 0:0e018d759a2a 695
switches 0:0e018d759a2a 696
switches 0:0e018d759a2a 697 /** \brief Disable External Interrupt
switches 0:0e018d759a2a 698
switches 0:0e018d759a2a 699 The function disables a device-specific interrupt in the NVIC interrupt controller.
switches 0:0e018d759a2a 700
switches 0:0e018d759a2a 701 \param [in] IRQn External interrupt number. Value cannot be negative.
switches 0:0e018d759a2a 702 */
switches 0:0e018d759a2a 703 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
switches 0:0e018d759a2a 704 {
switches 0:0e018d759a2a 705 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
switches 0:0e018d759a2a 706 }
switches 0:0e018d759a2a 707
switches 0:0e018d759a2a 708
switches 0:0e018d759a2a 709 /** \brief Get Pending Interrupt
switches 0:0e018d759a2a 710
switches 0:0e018d759a2a 711 The function reads the pending register in the NVIC and returns the pending bit
switches 0:0e018d759a2a 712 for the specified interrupt.
switches 0:0e018d759a2a 713
switches 0:0e018d759a2a 714 \param [in] IRQn Interrupt number.
switches 0:0e018d759a2a 715
switches 0:0e018d759a2a 716 \return 0 Interrupt status is not pending.
switches 0:0e018d759a2a 717 \return 1 Interrupt status is pending.
switches 0:0e018d759a2a 718 */
switches 0:0e018d759a2a 719 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
switches 0:0e018d759a2a 720 {
switches 0:0e018d759a2a 721 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
switches 0:0e018d759a2a 722 }
switches 0:0e018d759a2a 723
switches 0:0e018d759a2a 724
switches 0:0e018d759a2a 725 /** \brief Set Pending Interrupt
switches 0:0e018d759a2a 726
switches 0:0e018d759a2a 727 The function sets the pending bit of an external interrupt.
switches 0:0e018d759a2a 728
switches 0:0e018d759a2a 729 \param [in] IRQn Interrupt number. Value cannot be negative.
switches 0:0e018d759a2a 730 */
switches 0:0e018d759a2a 731 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
switches 0:0e018d759a2a 732 {
switches 0:0e018d759a2a 733 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
switches 0:0e018d759a2a 734 }
switches 0:0e018d759a2a 735
switches 0:0e018d759a2a 736
switches 0:0e018d759a2a 737 /** \brief Clear Pending Interrupt
switches 0:0e018d759a2a 738
switches 0:0e018d759a2a 739 The function clears the pending bit of an external interrupt.
switches 0:0e018d759a2a 740
switches 0:0e018d759a2a 741 \param [in] IRQn External interrupt number. Value cannot be negative.
switches 0:0e018d759a2a 742 */
switches 0:0e018d759a2a 743 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
switches 0:0e018d759a2a 744 {
switches 0:0e018d759a2a 745 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
switches 0:0e018d759a2a 746 }
switches 0:0e018d759a2a 747
switches 0:0e018d759a2a 748
switches 0:0e018d759a2a 749 /** \brief Set Interrupt Priority
switches 0:0e018d759a2a 750
switches 0:0e018d759a2a 751 The function sets the priority of an interrupt.
switches 0:0e018d759a2a 752
switches 0:0e018d759a2a 753 \note The priority cannot be set for every core interrupt.
switches 0:0e018d759a2a 754
switches 0:0e018d759a2a 755 \param [in] IRQn Interrupt number.
switches 0:0e018d759a2a 756 \param [in] priority Priority to set.
switches 0:0e018d759a2a 757 */
switches 0:0e018d759a2a 758 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
switches 0:0e018d759a2a 759 {
switches 0:0e018d759a2a 760 if((int32_t)(IRQn) < 0) {
switches 0:0e018d759a2a 761 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
switches 0:0e018d759a2a 762 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
switches 0:0e018d759a2a 763 }
switches 0:0e018d759a2a 764 else {
switches 0:0e018d759a2a 765 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
switches 0:0e018d759a2a 766 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
switches 0:0e018d759a2a 767 }
switches 0:0e018d759a2a 768 }
switches 0:0e018d759a2a 769
switches 0:0e018d759a2a 770
switches 0:0e018d759a2a 771 /** \brief Get Interrupt Priority
switches 0:0e018d759a2a 772
switches 0:0e018d759a2a 773 The function reads the priority of an interrupt. The interrupt
switches 0:0e018d759a2a 774 number can be positive to specify an external (device specific)
switches 0:0e018d759a2a 775 interrupt, or negative to specify an internal (core) interrupt.
switches 0:0e018d759a2a 776
switches 0:0e018d759a2a 777
switches 0:0e018d759a2a 778 \param [in] IRQn Interrupt number.
switches 0:0e018d759a2a 779 \return Interrupt Priority. Value is aligned automatically to the implemented
switches 0:0e018d759a2a 780 priority bits of the microcontroller.
switches 0:0e018d759a2a 781 */
switches 0:0e018d759a2a 782 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
switches 0:0e018d759a2a 783 {
switches 0:0e018d759a2a 784
switches 0:0e018d759a2a 785 if((int32_t)(IRQn) < 0) {
switches 0:0e018d759a2a 786 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
switches 0:0e018d759a2a 787 }
switches 0:0e018d759a2a 788 else {
switches 0:0e018d759a2a 789 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
switches 0:0e018d759a2a 790 }
switches 0:0e018d759a2a 791 }
switches 0:0e018d759a2a 792
switches 0:0e018d759a2a 793
switches 0:0e018d759a2a 794 /** \brief System Reset
switches 0:0e018d759a2a 795
switches 0:0e018d759a2a 796 The function initiates a system reset request to reset the MCU.
switches 0:0e018d759a2a 797 */
switches 0:0e018d759a2a 798 __STATIC_INLINE void NVIC_SystemReset(void)
switches 0:0e018d759a2a 799 {
switches 0:0e018d759a2a 800 __DSB(); /* Ensure all outstanding memory accesses included
switches 0:0e018d759a2a 801 buffered write are completed before reset */
switches 0:0e018d759a2a 802 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
switches 0:0e018d759a2a 803 SCB_AIRCR_SYSRESETREQ_Msk);
switches 0:0e018d759a2a 804 __DSB(); /* Ensure completion of memory access */
switches 0:0e018d759a2a 805 while(1) { __NOP(); } /* wait until reset */
switches 0:0e018d759a2a 806 }
switches 0:0e018d759a2a 807
switches 0:0e018d759a2a 808 /*@} end of CMSIS_Core_NVICFunctions */
switches 0:0e018d759a2a 809
switches 0:0e018d759a2a 810
switches 0:0e018d759a2a 811
switches 0:0e018d759a2a 812 /* ################################## SysTick function ############################################ */
switches 0:0e018d759a2a 813 /** \ingroup CMSIS_Core_FunctionInterface
switches 0:0e018d759a2a 814 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
switches 0:0e018d759a2a 815 \brief Functions that configure the System.
switches 0:0e018d759a2a 816 @{
switches 0:0e018d759a2a 817 */
switches 0:0e018d759a2a 818
switches 0:0e018d759a2a 819 #if (__Vendor_SysTickConfig == 0)
switches 0:0e018d759a2a 820
switches 0:0e018d759a2a 821 /** \brief System Tick Configuration
switches 0:0e018d759a2a 822
switches 0:0e018d759a2a 823 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
switches 0:0e018d759a2a 824 Counter is in free running mode to generate periodic interrupts.
switches 0:0e018d759a2a 825
switches 0:0e018d759a2a 826 \param [in] ticks Number of ticks between two interrupts.
switches 0:0e018d759a2a 827
switches 0:0e018d759a2a 828 \return 0 Function succeeded.
switches 0:0e018d759a2a 829 \return 1 Function failed.
switches 0:0e018d759a2a 830
switches 0:0e018d759a2a 831 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
switches 0:0e018d759a2a 832 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
switches 0:0e018d759a2a 833 must contain a vendor-specific implementation of this function.
switches 0:0e018d759a2a 834
switches 0:0e018d759a2a 835 */
switches 0:0e018d759a2a 836 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
switches 0:0e018d759a2a 837 {
switches 0:0e018d759a2a 838 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
switches 0:0e018d759a2a 839
switches 0:0e018d759a2a 840 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
switches 0:0e018d759a2a 841 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
switches 0:0e018d759a2a 842 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
switches 0:0e018d759a2a 843 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
switches 0:0e018d759a2a 844 SysTick_CTRL_TICKINT_Msk |
switches 0:0e018d759a2a 845 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
switches 0:0e018d759a2a 846 return (0UL); /* Function successful */
switches 0:0e018d759a2a 847 }
switches 0:0e018d759a2a 848
switches 0:0e018d759a2a 849 #endif
switches 0:0e018d759a2a 850
switches 0:0e018d759a2a 851 /*@} end of CMSIS_Core_SysTickFunctions */
switches 0:0e018d759a2a 852
switches 0:0e018d759a2a 853
switches 0:0e018d759a2a 854
switches 0:0e018d759a2a 855
switches 0:0e018d759a2a 856 #ifdef __cplusplus
switches 0:0e018d759a2a 857 }
switches 0:0e018d759a2a 858 #endif
switches 0:0e018d759a2a 859
switches 0:0e018d759a2a 860 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
switches 0:0e018d759a2a 861
switches 0:0e018d759a2a 862 #endif /* __CMSIS_GENERIC */