Greg Steiert / maxim_dev

Maxim mbed development library

Dependents:   sensomed

cmsis/core_caFunc.h@0:0e018d759a2a, 2016-11-08 (annotated)

Committer:
switches
Date:
Tue Nov 08 18:27:11 2016 +0000
Revision:
0:0e018d759a2a
Initial commit

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switches 0:0e018d759a2a 1 /**************************************************************************//**
switches 0:0e018d759a2a 2 * @file core_caFunc.h
switches 0:0e018d759a2a 3 * @brief CMSIS Cortex-A Core Function Access Header File
switches 0:0e018d759a2a 4 * @version V3.10
switches 0:0e018d759a2a 5 * @date 30 Oct 2013
switches 0:0e018d759a2a 6 *
switches 0:0e018d759a2a 7 * @note
switches 0:0e018d759a2a 8 *
switches 0:0e018d759a2a 9 ******************************************************************************/
switches 0:0e018d759a2a 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
switches 0:0e018d759a2a 11
switches 0:0e018d759a2a 12 All rights reserved.
switches 0:0e018d759a2a 13 Redistribution and use in source and binary forms, with or without
switches 0:0e018d759a2a 14 modification, are permitted provided that the following conditions are met:
switches 0:0e018d759a2a 15 - Redistributions of source code must retain the above copyright
switches 0:0e018d759a2a 16 notice, this list of conditions and the following disclaimer.
switches 0:0e018d759a2a 17 - Redistributions in binary form must reproduce the above copyright
switches 0:0e018d759a2a 18 notice, this list of conditions and the following disclaimer in the
switches 0:0e018d759a2a 19 documentation and/or other materials provided with the distribution.
switches 0:0e018d759a2a 20 - Neither the name of ARM nor the names of its contributors may be used
switches 0:0e018d759a2a 21 to endorse or promote products derived from this software without
switches 0:0e018d759a2a 22 specific prior written permission.
switches 0:0e018d759a2a 23 *
switches 0:0e018d759a2a 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
switches 0:0e018d759a2a 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
switches 0:0e018d759a2a 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
switches 0:0e018d759a2a 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
switches 0:0e018d759a2a 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
switches 0:0e018d759a2a 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
switches 0:0e018d759a2a 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
switches 0:0e018d759a2a 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
switches 0:0e018d759a2a 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
switches 0:0e018d759a2a 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
switches 0:0e018d759a2a 34 POSSIBILITY OF SUCH DAMAGE.
switches 0:0e018d759a2a 35 ---------------------------------------------------------------------------*/
switches 0:0e018d759a2a 36
switches 0:0e018d759a2a 37
switches 0:0e018d759a2a 38 #ifndef __CORE_CAFUNC_H__
switches 0:0e018d759a2a 39 #define __CORE_CAFUNC_H__
switches 0:0e018d759a2a 40
switches 0:0e018d759a2a 41
switches 0:0e018d759a2a 42 /* ########################### Core Function Access ########################### */
switches 0:0e018d759a2a 43 /** \ingroup CMSIS_Core_FunctionInterface
switches 0:0e018d759a2a 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
switches 0:0e018d759a2a 45 @{
switches 0:0e018d759a2a 46 */
switches 0:0e018d759a2a 47
switches 0:0e018d759a2a 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
switches 0:0e018d759a2a 49 /* ARM armcc specific functions */
switches 0:0e018d759a2a 50
switches 0:0e018d759a2a 51 #if (__ARMCC_VERSION < 400677)
switches 0:0e018d759a2a 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
switches 0:0e018d759a2a 53 #endif
switches 0:0e018d759a2a 54
switches 0:0e018d759a2a 55 #define MODE_USR 0x10
switches 0:0e018d759a2a 56 #define MODE_FIQ 0x11
switches 0:0e018d759a2a 57 #define MODE_IRQ 0x12
switches 0:0e018d759a2a 58 #define MODE_SVC 0x13
switches 0:0e018d759a2a 59 #define MODE_MON 0x16
switches 0:0e018d759a2a 60 #define MODE_ABT 0x17
switches 0:0e018d759a2a 61 #define MODE_HYP 0x1A
switches 0:0e018d759a2a 62 #define MODE_UND 0x1B
switches 0:0e018d759a2a 63 #define MODE_SYS 0x1F
switches 0:0e018d759a2a 64
switches 0:0e018d759a2a 65 /** \brief Get APSR Register
switches 0:0e018d759a2a 66
switches 0:0e018d759a2a 67 This function returns the content of the APSR Register.
switches 0:0e018d759a2a 68
switches 0:0e018d759a2a 69 \return APSR Register value
switches 0:0e018d759a2a 70 */
switches 0:0e018d759a2a 71 __STATIC_INLINE uint32_t __get_APSR(void)
switches 0:0e018d759a2a 72 {
switches 0:0e018d759a2a 73 register uint32_t __regAPSR __ASM("apsr");
switches 0:0e018d759a2a 74 return(__regAPSR);
switches 0:0e018d759a2a 75 }
switches 0:0e018d759a2a 76
switches 0:0e018d759a2a 77
switches 0:0e018d759a2a 78 /** \brief Get CPSR Register
switches 0:0e018d759a2a 79
switches 0:0e018d759a2a 80 This function returns the content of the CPSR Register.
switches 0:0e018d759a2a 81
switches 0:0e018d759a2a 82 \return CPSR Register value
switches 0:0e018d759a2a 83 */
switches 0:0e018d759a2a 84 __STATIC_INLINE uint32_t __get_CPSR(void)
switches 0:0e018d759a2a 85 {
switches 0:0e018d759a2a 86 register uint32_t __regCPSR __ASM("cpsr");
switches 0:0e018d759a2a 87 return(__regCPSR);
switches 0:0e018d759a2a 88 }
switches 0:0e018d759a2a 89
switches 0:0e018d759a2a 90 /** \brief Set Stack Pointer
switches 0:0e018d759a2a 91
switches 0:0e018d759a2a 92 This function assigns the given value to the current stack pointer.
switches 0:0e018d759a2a 93
switches 0:0e018d759a2a 94 \param [in] topOfStack Stack Pointer value to set
switches 0:0e018d759a2a 95 */
switches 0:0e018d759a2a 96 register uint32_t __regSP __ASM("sp");
switches 0:0e018d759a2a 97 __STATIC_INLINE void __set_SP(uint32_t topOfStack)
switches 0:0e018d759a2a 98 {
switches 0:0e018d759a2a 99 __regSP = topOfStack;
switches 0:0e018d759a2a 100 }
switches 0:0e018d759a2a 101
switches 0:0e018d759a2a 102
switches 0:0e018d759a2a 103 /** \brief Get link register
switches 0:0e018d759a2a 104
switches 0:0e018d759a2a 105 This function returns the value of the link register
switches 0:0e018d759a2a 106
switches 0:0e018d759a2a 107 \return Value of link register
switches 0:0e018d759a2a 108 */
switches 0:0e018d759a2a 109 register uint32_t __reglr __ASM("lr");
switches 0:0e018d759a2a 110 __STATIC_INLINE uint32_t __get_LR(void)
switches 0:0e018d759a2a 111 {
switches 0:0e018d759a2a 112 return(__reglr);
switches 0:0e018d759a2a 113 }
switches 0:0e018d759a2a 114
switches 0:0e018d759a2a 115 /** \brief Set link register
switches 0:0e018d759a2a 116
switches 0:0e018d759a2a 117 This function sets the value of the link register
switches 0:0e018d759a2a 118
switches 0:0e018d759a2a 119 \param [in] lr LR value to set
switches 0:0e018d759a2a 120 */
switches 0:0e018d759a2a 121 __STATIC_INLINE void __set_LR(uint32_t lr)
switches 0:0e018d759a2a 122 {
switches 0:0e018d759a2a 123 __reglr = lr;
switches 0:0e018d759a2a 124 }
switches 0:0e018d759a2a 125
switches 0:0e018d759a2a 126 /** \brief Set Process Stack Pointer
switches 0:0e018d759a2a 127
switches 0:0e018d759a2a 128 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
switches 0:0e018d759a2a 129
switches 0:0e018d759a2a 130 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
switches 0:0e018d759a2a 131 */
switches 0:0e018d759a2a 132 __STATIC_ASM void __set_PSP(uint32_t topOfProcStack)
switches 0:0e018d759a2a 133 {
switches 0:0e018d759a2a 134 ARM
switches 0:0e018d759a2a 135 PRESERVE8
switches 0:0e018d759a2a 136
switches 0:0e018d759a2a 137 BIC R0, R0, #7 ;ensure stack is 8-byte aligned
switches 0:0e018d759a2a 138 MRS R1, CPSR
switches 0:0e018d759a2a 139 CPS #MODE_SYS ;no effect in USR mode
switches 0:0e018d759a2a 140 MOV SP, R0
switches 0:0e018d759a2a 141 MSR CPSR_c, R1 ;no effect in USR mode
switches 0:0e018d759a2a 142 ISB
switches 0:0e018d759a2a 143 BX LR
switches 0:0e018d759a2a 144
switches 0:0e018d759a2a 145 }
switches 0:0e018d759a2a 146
switches 0:0e018d759a2a 147 /** \brief Set User Mode
switches 0:0e018d759a2a 148
switches 0:0e018d759a2a 149 This function changes the processor state to User Mode
switches 0:0e018d759a2a 150 */
switches 0:0e018d759a2a 151 __STATIC_ASM void __set_CPS_USR(void)
switches 0:0e018d759a2a 152 {
switches 0:0e018d759a2a 153 ARM
switches 0:0e018d759a2a 154
switches 0:0e018d759a2a 155 CPS #MODE_USR
switches 0:0e018d759a2a 156 BX LR
switches 0:0e018d759a2a 157 }
switches 0:0e018d759a2a 158
switches 0:0e018d759a2a 159
switches 0:0e018d759a2a 160 /** \brief Enable FIQ
switches 0:0e018d759a2a 161
switches 0:0e018d759a2a 162 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
switches 0:0e018d759a2a 163 Can only be executed in Privileged modes.
switches 0:0e018d759a2a 164 */
switches 0:0e018d759a2a 165 #define __enable_fault_irq __enable_fiq
switches 0:0e018d759a2a 166
switches 0:0e018d759a2a 167
switches 0:0e018d759a2a 168 /** \brief Disable FIQ
switches 0:0e018d759a2a 169
switches 0:0e018d759a2a 170 This function disables FIQ interrupts by setting the F-bit in the CPSR.
switches 0:0e018d759a2a 171 Can only be executed in Privileged modes.
switches 0:0e018d759a2a 172 */
switches 0:0e018d759a2a 173 #define __disable_fault_irq __disable_fiq
switches 0:0e018d759a2a 174
switches 0:0e018d759a2a 175
switches 0:0e018d759a2a 176 /** \brief Get FPSCR
switches 0:0e018d759a2a 177
switches 0:0e018d759a2a 178 This function returns the current value of the Floating Point Status/Control register.
switches 0:0e018d759a2a 179
switches 0:0e018d759a2a 180 \return Floating Point Status/Control register value
switches 0:0e018d759a2a 181 */
switches 0:0e018d759a2a 182 __STATIC_INLINE uint32_t __get_FPSCR(void)
switches 0:0e018d759a2a 183 {
switches 0:0e018d759a2a 184 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
switches 0:0e018d759a2a 185 register uint32_t __regfpscr __ASM("fpscr");
switches 0:0e018d759a2a 186 return(__regfpscr);
switches 0:0e018d759a2a 187 #else
switches 0:0e018d759a2a 188 return(0);
switches 0:0e018d759a2a 189 #endif
switches 0:0e018d759a2a 190 }
switches 0:0e018d759a2a 191
switches 0:0e018d759a2a 192
switches 0:0e018d759a2a 193 /** \brief Set FPSCR
switches 0:0e018d759a2a 194
switches 0:0e018d759a2a 195 This function assigns the given value to the Floating Point Status/Control register.
switches 0:0e018d759a2a 196
switches 0:0e018d759a2a 197 \param [in] fpscr Floating Point Status/Control value to set
switches 0:0e018d759a2a 198 */
switches 0:0e018d759a2a 199 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
switches 0:0e018d759a2a 200 {
switches 0:0e018d759a2a 201 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
switches 0:0e018d759a2a 202 register uint32_t __regfpscr __ASM("fpscr");
switches 0:0e018d759a2a 203 __regfpscr = (fpscr);
switches 0:0e018d759a2a 204 #endif
switches 0:0e018d759a2a 205 }
switches 0:0e018d759a2a 206
switches 0:0e018d759a2a 207 /** \brief Get FPEXC
switches 0:0e018d759a2a 208
switches 0:0e018d759a2a 209 This function returns the current value of the Floating Point Exception Control register.
switches 0:0e018d759a2a 210
switches 0:0e018d759a2a 211 \return Floating Point Exception Control register value
switches 0:0e018d759a2a 212 */
switches 0:0e018d759a2a 213 __STATIC_INLINE uint32_t __get_FPEXC(void)
switches 0:0e018d759a2a 214 {
switches 0:0e018d759a2a 215 #if (__FPU_PRESENT == 1)
switches 0:0e018d759a2a 216 register uint32_t __regfpexc __ASM("fpexc");
switches 0:0e018d759a2a 217 return(__regfpexc);
switches 0:0e018d759a2a 218 #else
switches 0:0e018d759a2a 219 return(0);
switches 0:0e018d759a2a 220 #endif
switches 0:0e018d759a2a 221 }
switches 0:0e018d759a2a 222
switches 0:0e018d759a2a 223
switches 0:0e018d759a2a 224 /** \brief Set FPEXC
switches 0:0e018d759a2a 225
switches 0:0e018d759a2a 226 This function assigns the given value to the Floating Point Exception Control register.
switches 0:0e018d759a2a 227
switches 0:0e018d759a2a 228 \param [in] fpscr Floating Point Exception Control value to set
switches 0:0e018d759a2a 229 */
switches 0:0e018d759a2a 230 __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
switches 0:0e018d759a2a 231 {
switches 0:0e018d759a2a 232 #if (__FPU_PRESENT == 1)
switches 0:0e018d759a2a 233 register uint32_t __regfpexc __ASM("fpexc");
switches 0:0e018d759a2a 234 __regfpexc = (fpexc);
switches 0:0e018d759a2a 235 #endif
switches 0:0e018d759a2a 236 }
switches 0:0e018d759a2a 237
switches 0:0e018d759a2a 238 /** \brief Get CPACR
switches 0:0e018d759a2a 239
switches 0:0e018d759a2a 240 This function returns the current value of the Coprocessor Access Control register.
switches 0:0e018d759a2a 241
switches 0:0e018d759a2a 242 \return Coprocessor Access Control register value
switches 0:0e018d759a2a 243 */
switches 0:0e018d759a2a 244 __STATIC_INLINE uint32_t __get_CPACR(void)
switches 0:0e018d759a2a 245 {
switches 0:0e018d759a2a 246 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
switches 0:0e018d759a2a 247 return __regCPACR;
switches 0:0e018d759a2a 248 }
switches 0:0e018d759a2a 249
switches 0:0e018d759a2a 250 /** \brief Set CPACR
switches 0:0e018d759a2a 251
switches 0:0e018d759a2a 252 This function assigns the given value to the Coprocessor Access Control register.
switches 0:0e018d759a2a 253
switches 0:0e018d759a2a 254 \param [in] cpacr Coprocessor Acccess Control value to set
switches 0:0e018d759a2a 255 */
switches 0:0e018d759a2a 256 __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
switches 0:0e018d759a2a 257 {
switches 0:0e018d759a2a 258 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
switches 0:0e018d759a2a 259 __regCPACR = cpacr;
switches 0:0e018d759a2a 260 __ISB();
switches 0:0e018d759a2a 261 }
switches 0:0e018d759a2a 262
switches 0:0e018d759a2a 263 /** \brief Get CBAR
switches 0:0e018d759a2a 264
switches 0:0e018d759a2a 265 This function returns the value of the Configuration Base Address register.
switches 0:0e018d759a2a 266
switches 0:0e018d759a2a 267 \return Configuration Base Address register value
switches 0:0e018d759a2a 268 */
switches 0:0e018d759a2a 269 __STATIC_INLINE uint32_t __get_CBAR() {
switches 0:0e018d759a2a 270 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
switches 0:0e018d759a2a 271 return(__regCBAR);
switches 0:0e018d759a2a 272 }
switches 0:0e018d759a2a 273
switches 0:0e018d759a2a 274 /** \brief Get TTBR0
switches 0:0e018d759a2a 275
switches 0:0e018d759a2a 276 This function returns the value of the Translation Table Base Register 0.
switches 0:0e018d759a2a 277
switches 0:0e018d759a2a 278 \return Translation Table Base Register 0 value
switches 0:0e018d759a2a 279 */
switches 0:0e018d759a2a 280 __STATIC_INLINE uint32_t __get_TTBR0() {
switches 0:0e018d759a2a 281 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
switches 0:0e018d759a2a 282 return(__regTTBR0);
switches 0:0e018d759a2a 283 }
switches 0:0e018d759a2a 284
switches 0:0e018d759a2a 285 /** \brief Set TTBR0
switches 0:0e018d759a2a 286
switches 0:0e018d759a2a 287 This function assigns the given value to the Translation Table Base Register 0.
switches 0:0e018d759a2a 288
switches 0:0e018d759a2a 289 \param [in] ttbr0 Translation Table Base Register 0 value to set
switches 0:0e018d759a2a 290 */
switches 0:0e018d759a2a 291 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
switches 0:0e018d759a2a 292 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
switches 0:0e018d759a2a 293 __regTTBR0 = ttbr0;
switches 0:0e018d759a2a 294 __ISB();
switches 0:0e018d759a2a 295 }
switches 0:0e018d759a2a 296
switches 0:0e018d759a2a 297 /** \brief Get DACR
switches 0:0e018d759a2a 298
switches 0:0e018d759a2a 299 This function returns the value of the Domain Access Control Register.
switches 0:0e018d759a2a 300
switches 0:0e018d759a2a 301 \return Domain Access Control Register value
switches 0:0e018d759a2a 302 */
switches 0:0e018d759a2a 303 __STATIC_INLINE uint32_t __get_DACR() {
switches 0:0e018d759a2a 304 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
switches 0:0e018d759a2a 305 return(__regDACR);
switches 0:0e018d759a2a 306 }
switches 0:0e018d759a2a 307
switches 0:0e018d759a2a 308 /** \brief Set DACR
switches 0:0e018d759a2a 309
switches 0:0e018d759a2a 310 This function assigns the given value to the Domain Access Control Register.
switches 0:0e018d759a2a 311
switches 0:0e018d759a2a 312 \param [in] dacr Domain Access Control Register value to set
switches 0:0e018d759a2a 313 */
switches 0:0e018d759a2a 314 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
switches 0:0e018d759a2a 315 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
switches 0:0e018d759a2a 316 __regDACR = dacr;
switches 0:0e018d759a2a 317 __ISB();
switches 0:0e018d759a2a 318 }
switches 0:0e018d759a2a 319
switches 0:0e018d759a2a 320 /******************************** Cache and BTAC enable ****************************************************/
switches 0:0e018d759a2a 321
switches 0:0e018d759a2a 322 /** \brief Set SCTLR
switches 0:0e018d759a2a 323
switches 0:0e018d759a2a 324 This function assigns the given value to the System Control Register.
switches 0:0e018d759a2a 325
switches 0:0e018d759a2a 326 \param [in] sctlr System Control Register value to set
switches 0:0e018d759a2a 327 */
switches 0:0e018d759a2a 328 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
switches 0:0e018d759a2a 329 {
switches 0:0e018d759a2a 330 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
switches 0:0e018d759a2a 331 __regSCTLR = sctlr;
switches 0:0e018d759a2a 332 }
switches 0:0e018d759a2a 333
switches 0:0e018d759a2a 334 /** \brief Get SCTLR
switches 0:0e018d759a2a 335
switches 0:0e018d759a2a 336 This function returns the value of the System Control Register.
switches 0:0e018d759a2a 337
switches 0:0e018d759a2a 338 \return System Control Register value
switches 0:0e018d759a2a 339 */
switches 0:0e018d759a2a 340 __STATIC_INLINE uint32_t __get_SCTLR() {
switches 0:0e018d759a2a 341 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
switches 0:0e018d759a2a 342 return(__regSCTLR);
switches 0:0e018d759a2a 343 }
switches 0:0e018d759a2a 344
switches 0:0e018d759a2a 345 /** \brief Enable Caches
switches 0:0e018d759a2a 346
switches 0:0e018d759a2a 347 Enable Caches
switches 0:0e018d759a2a 348 */
switches 0:0e018d759a2a 349 __STATIC_INLINE void __enable_caches(void) {
switches 0:0e018d759a2a 350 // Set I bit 12 to enable I Cache
switches 0:0e018d759a2a 351 // Set C bit 2 to enable D Cache
switches 0:0e018d759a2a 352 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
switches 0:0e018d759a2a 353 }
switches 0:0e018d759a2a 354
switches 0:0e018d759a2a 355 /** \brief Disable Caches
switches 0:0e018d759a2a 356
switches 0:0e018d759a2a 357 Disable Caches
switches 0:0e018d759a2a 358 */
switches 0:0e018d759a2a 359 __STATIC_INLINE void __disable_caches(void) {
switches 0:0e018d759a2a 360 // Clear I bit 12 to disable I Cache
switches 0:0e018d759a2a 361 // Clear C bit 2 to disable D Cache
switches 0:0e018d759a2a 362 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
switches 0:0e018d759a2a 363 __ISB();
switches 0:0e018d759a2a 364 }
switches 0:0e018d759a2a 365
switches 0:0e018d759a2a 366 /** \brief Enable BTAC
switches 0:0e018d759a2a 367
switches 0:0e018d759a2a 368 Enable BTAC
switches 0:0e018d759a2a 369 */
switches 0:0e018d759a2a 370 __STATIC_INLINE void __enable_btac(void) {
switches 0:0e018d759a2a 371 // Set Z bit 11 to enable branch prediction
switches 0:0e018d759a2a 372 __set_SCTLR( __get_SCTLR() | (1 << 11));
switches 0:0e018d759a2a 373 __ISB();
switches 0:0e018d759a2a 374 }
switches 0:0e018d759a2a 375
switches 0:0e018d759a2a 376 /** \brief Disable BTAC
switches 0:0e018d759a2a 377
switches 0:0e018d759a2a 378 Disable BTAC
switches 0:0e018d759a2a 379 */
switches 0:0e018d759a2a 380 __STATIC_INLINE void __disable_btac(void) {
switches 0:0e018d759a2a 381 // Clear Z bit 11 to disable branch prediction
switches 0:0e018d759a2a 382 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
switches 0:0e018d759a2a 383 }
switches 0:0e018d759a2a 384
switches 0:0e018d759a2a 385
switches 0:0e018d759a2a 386 /** \brief Enable MMU
switches 0:0e018d759a2a 387
switches 0:0e018d759a2a 388 Enable MMU
switches 0:0e018d759a2a 389 */
switches 0:0e018d759a2a 390 __STATIC_INLINE void __enable_mmu(void) {
switches 0:0e018d759a2a 391 // Set M bit 0 to enable the MMU
switches 0:0e018d759a2a 392 // Set AFE bit to enable simplified access permissions model
switches 0:0e018d759a2a 393 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
switches 0:0e018d759a2a 394 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
switches 0:0e018d759a2a 395 __ISB();
switches 0:0e018d759a2a 396 }
switches 0:0e018d759a2a 397
switches 0:0e018d759a2a 398 /** \brief Disable MMU
switches 0:0e018d759a2a 399
switches 0:0e018d759a2a 400 Disable MMU
switches 0:0e018d759a2a 401 */
switches 0:0e018d759a2a 402 __STATIC_INLINE void __disable_mmu(void) {
switches 0:0e018d759a2a 403 // Clear M bit 0 to disable the MMU
switches 0:0e018d759a2a 404 __set_SCTLR( __get_SCTLR() & ~1);
switches 0:0e018d759a2a 405 __ISB();
switches 0:0e018d759a2a 406 }
switches 0:0e018d759a2a 407
switches 0:0e018d759a2a 408 /******************************** TLB maintenance operations ************************************************/
switches 0:0e018d759a2a 409 /** \brief Invalidate the whole tlb
switches 0:0e018d759a2a 410
switches 0:0e018d759a2a 411 TLBIALL. Invalidate the whole tlb
switches 0:0e018d759a2a 412 */
switches 0:0e018d759a2a 413
switches 0:0e018d759a2a 414 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
switches 0:0e018d759a2a 415 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
switches 0:0e018d759a2a 416 __TLBIALL = 0;
switches 0:0e018d759a2a 417 __DSB();
switches 0:0e018d759a2a 418 __ISB();
switches 0:0e018d759a2a 419 }
switches 0:0e018d759a2a 420
switches 0:0e018d759a2a 421 /******************************** BTB maintenance operations ************************************************/
switches 0:0e018d759a2a 422 /** \brief Invalidate entire branch predictor array
switches 0:0e018d759a2a 423
switches 0:0e018d759a2a 424 BPIALL. Branch Predictor Invalidate All.
switches 0:0e018d759a2a 425 */
switches 0:0e018d759a2a 426
switches 0:0e018d759a2a 427 __STATIC_INLINE void __v7_inv_btac(void) {
switches 0:0e018d759a2a 428 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
switches 0:0e018d759a2a 429 __BPIALL = 0;
switches 0:0e018d759a2a 430 __DSB(); //ensure completion of the invalidation
switches 0:0e018d759a2a 431 __ISB(); //ensure instruction fetch path sees new state
switches 0:0e018d759a2a 432 }
switches 0:0e018d759a2a 433
switches 0:0e018d759a2a 434
switches 0:0e018d759a2a 435 /******************************** L1 cache operations ******************************************************/
switches 0:0e018d759a2a 436
switches 0:0e018d759a2a 437 /** \brief Invalidate the whole I$
switches 0:0e018d759a2a 438
switches 0:0e018d759a2a 439 ICIALLU. Instruction Cache Invalidate All to PoU
switches 0:0e018d759a2a 440 */
switches 0:0e018d759a2a 441 __STATIC_INLINE void __v7_inv_icache_all(void) {
switches 0:0e018d759a2a 442 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
switches 0:0e018d759a2a 443 __ICIALLU = 0;
switches 0:0e018d759a2a 444 __DSB(); //ensure completion of the invalidation
switches 0:0e018d759a2a 445 __ISB(); //ensure instruction fetch path sees new I cache state
switches 0:0e018d759a2a 446 }
switches 0:0e018d759a2a 447
switches 0:0e018d759a2a 448 /** \brief Clean D$ by MVA
switches 0:0e018d759a2a 449
switches 0:0e018d759a2a 450 DCCMVAC. Data cache clean by MVA to PoC
switches 0:0e018d759a2a 451 */
switches 0:0e018d759a2a 452 __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
switches 0:0e018d759a2a 453 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
switches 0:0e018d759a2a 454 __DCCMVAC = (uint32_t)va;
switches 0:0e018d759a2a 455 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
switches 0:0e018d759a2a 456 }
switches 0:0e018d759a2a 457
switches 0:0e018d759a2a 458 /** \brief Invalidate D$ by MVA
switches 0:0e018d759a2a 459
switches 0:0e018d759a2a 460 DCIMVAC. Data cache invalidate by MVA to PoC
switches 0:0e018d759a2a 461 */
switches 0:0e018d759a2a 462 __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
switches 0:0e018d759a2a 463 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
switches 0:0e018d759a2a 464 __DCIMVAC = (uint32_t)va;
switches 0:0e018d759a2a 465 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
switches 0:0e018d759a2a 466 }
switches 0:0e018d759a2a 467
switches 0:0e018d759a2a 468 /** \brief Clean and Invalidate D$ by MVA
switches 0:0e018d759a2a 469
switches 0:0e018d759a2a 470 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
switches 0:0e018d759a2a 471 */
switches 0:0e018d759a2a 472 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
switches 0:0e018d759a2a 473 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
switches 0:0e018d759a2a 474 __DCCIMVAC = (uint32_t)va;
switches 0:0e018d759a2a 475 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
switches 0:0e018d759a2a 476 }
switches 0:0e018d759a2a 477
switches 0:0e018d759a2a 478 /** \brief Clean and Invalidate the entire data or unified cache
switches 0:0e018d759a2a 479
switches 0:0e018d759a2a 480 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
switches 0:0e018d759a2a 481 */
switches 0:0e018d759a2a 482 #pragma push
switches 0:0e018d759a2a 483 #pragma arm
switches 0:0e018d759a2a 484 __STATIC_ASM void __v7_all_cache(uint32_t op) {
switches 0:0e018d759a2a 485 ARM
switches 0:0e018d759a2a 486
switches 0:0e018d759a2a 487 PUSH {R4-R11}
switches 0:0e018d759a2a 488
switches 0:0e018d759a2a 489 MRC p15, 1, R6, c0, c0, 1 // Read CLIDR
switches 0:0e018d759a2a 490 ANDS R3, R6, #0x07000000 // Extract coherency level
switches 0:0e018d759a2a 491 MOV R3, R3, LSR #23 // Total cache levels << 1
switches 0:0e018d759a2a 492 BEQ Finished // If 0, no need to clean
switches 0:0e018d759a2a 493
switches 0:0e018d759a2a 494 MOV R10, #0 // R10 holds current cache level << 1
switches 0:0e018d759a2a 495 Loop1 ADD R2, R10, R10, LSR #1 // R2 holds cache "Set" position
switches 0:0e018d759a2a 496 MOV R1, R6, LSR R2 // Bottom 3 bits are the Cache-type for this level
switches 0:0e018d759a2a 497 AND R1, R1, #7 // Isolate those lower 3 bits
switches 0:0e018d759a2a 498 CMP R1, #2
switches 0:0e018d759a2a 499 BLT Skip // No cache or only instruction cache at this level
switches 0:0e018d759a2a 500
switches 0:0e018d759a2a 501 MCR p15, 2, R10, c0, c0, 0 // Write the Cache Size selection register
switches 0:0e018d759a2a 502 ISB // ISB to sync the change to the CacheSizeID reg
switches 0:0e018d759a2a 503 MRC p15, 1, R1, c0, c0, 0 // Reads current Cache Size ID register
switches 0:0e018d759a2a 504 AND R2, R1, #7 // Extract the line length field
switches 0:0e018d759a2a 505 ADD R2, R2, #4 // Add 4 for the line length offset (log2 16 bytes)
switches 0:0e018d759a2a 506 LDR R4, =0x3FF
switches 0:0e018d759a2a 507 ANDS R4, R4, R1, LSR #3 // R4 is the max number on the way size (right aligned)
switches 0:0e018d759a2a 508 CLZ R5, R4 // R5 is the bit position of the way size increment
switches 0:0e018d759a2a 509 LDR R7, =0x7FFF
switches 0:0e018d759a2a 510 ANDS R7, R7, R1, LSR #13 // R7 is the max number of the index size (right aligned)
switches 0:0e018d759a2a 511
switches 0:0e018d759a2a 512 Loop2 MOV R9, R4 // R9 working copy of the max way size (right aligned)
switches 0:0e018d759a2a 513
switches 0:0e018d759a2a 514 Loop3 ORR R11, R10, R9, LSL R5 // Factor in the Way number and cache number into R11
switches 0:0e018d759a2a 515 ORR R11, R11, R7, LSL R2 // Factor in the Set number
switches 0:0e018d759a2a 516 CMP R0, #0
switches 0:0e018d759a2a 517 BNE Dccsw
switches 0:0e018d759a2a 518 MCR p15, 0, R11, c7, c6, 2 // DCISW. Invalidate by Set/Way
switches 0:0e018d759a2a 519 B cont
switches 0:0e018d759a2a 520 Dccsw CMP R0, #1
switches 0:0e018d759a2a 521 BNE Dccisw
switches 0:0e018d759a2a 522 MCR p15, 0, R11, c7, c10, 2 // DCCSW. Clean by Set/Way
switches 0:0e018d759a2a 523 B cont
switches 0:0e018d759a2a 524 Dccisw MCR p15, 0, R11, c7, c14, 2 // DCCISW. Clean and Invalidate by Set/Way
switches 0:0e018d759a2a 525 cont SUBS R9, R9, #1 // Decrement the Way number
switches 0:0e018d759a2a 526 BGE Loop3
switches 0:0e018d759a2a 527 SUBS R7, R7, #1 // Decrement the Set number
switches 0:0e018d759a2a 528 BGE Loop2
switches 0:0e018d759a2a 529 Skip ADD R10, R10, #2 // Increment the cache number
switches 0:0e018d759a2a 530 CMP R3, R10
switches 0:0e018d759a2a 531 BGT Loop1
switches 0:0e018d759a2a 532
switches 0:0e018d759a2a 533 Finished
switches 0:0e018d759a2a 534 DSB
switches 0:0e018d759a2a 535 POP {R4-R11}
switches 0:0e018d759a2a 536 BX lr
switches 0:0e018d759a2a 537
switches 0:0e018d759a2a 538 }
switches 0:0e018d759a2a 539 #pragma pop
switches 0:0e018d759a2a 540
switches 0:0e018d759a2a 541
switches 0:0e018d759a2a 542 /** \brief Invalidate the whole D$
switches 0:0e018d759a2a 543
switches 0:0e018d759a2a 544 DCISW. Invalidate by Set/Way
switches 0:0e018d759a2a 545 */
switches 0:0e018d759a2a 546
switches 0:0e018d759a2a 547 __STATIC_INLINE void __v7_inv_dcache_all(void) {
switches 0:0e018d759a2a 548 __v7_all_cache(0);
switches 0:0e018d759a2a 549 }
switches 0:0e018d759a2a 550
switches 0:0e018d759a2a 551 /** \brief Clean the whole D$
switches 0:0e018d759a2a 552
switches 0:0e018d759a2a 553 DCCSW. Clean by Set/Way
switches 0:0e018d759a2a 554 */
switches 0:0e018d759a2a 555
switches 0:0e018d759a2a 556 __STATIC_INLINE void __v7_clean_dcache_all(void) {
switches 0:0e018d759a2a 557 __v7_all_cache(1);
switches 0:0e018d759a2a 558 }
switches 0:0e018d759a2a 559
switches 0:0e018d759a2a 560 /** \brief Clean and invalidate the whole D$
switches 0:0e018d759a2a 561
switches 0:0e018d759a2a 562 DCCISW. Clean and Invalidate by Set/Way
switches 0:0e018d759a2a 563 */
switches 0:0e018d759a2a 564
switches 0:0e018d759a2a 565 __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
switches 0:0e018d759a2a 566 __v7_all_cache(2);
switches 0:0e018d759a2a 567 }
switches 0:0e018d759a2a 568
switches 0:0e018d759a2a 569 #include "core_ca_mmu.h"
switches 0:0e018d759a2a 570
switches 0:0e018d759a2a 571 #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
switches 0:0e018d759a2a 572
switches 0:0e018d759a2a 573 #define __inline inline
switches 0:0e018d759a2a 574
switches 0:0e018d759a2a 575 inline static uint32_t __disable_irq_iar() {
switches 0:0e018d759a2a 576 int irq_dis = __get_CPSR() & 0x80; // 7bit CPSR.I
switches 0:0e018d759a2a 577 __disable_irq();
switches 0:0e018d759a2a 578 return irq_dis;
switches 0:0e018d759a2a 579 }
switches 0:0e018d759a2a 580
switches 0:0e018d759a2a 581 #define MODE_USR 0x10
switches 0:0e018d759a2a 582 #define MODE_FIQ 0x11
switches 0:0e018d759a2a 583 #define MODE_IRQ 0x12
switches 0:0e018d759a2a 584 #define MODE_SVC 0x13
switches 0:0e018d759a2a 585 #define MODE_MON 0x16
switches 0:0e018d759a2a 586 #define MODE_ABT 0x17
switches 0:0e018d759a2a 587 #define MODE_HYP 0x1A
switches 0:0e018d759a2a 588 #define MODE_UND 0x1B
switches 0:0e018d759a2a 589 #define MODE_SYS 0x1F
switches 0:0e018d759a2a 590
switches 0:0e018d759a2a 591 /** \brief Set Process Stack Pointer
switches 0:0e018d759a2a 592
switches 0:0e018d759a2a 593 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
switches 0:0e018d759a2a 594
switches 0:0e018d759a2a 595 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
switches 0:0e018d759a2a 596 */
switches 0:0e018d759a2a 597 // from rt_CMSIS.c
switches 0:0e018d759a2a 598 __arm static inline void __set_PSP(uint32_t topOfProcStack) {
switches 0:0e018d759a2a 599 __asm(
switches 0:0e018d759a2a 600 " ARM\n"
switches 0:0e018d759a2a 601 // " PRESERVE8\n"
switches 0:0e018d759a2a 602
switches 0:0e018d759a2a 603 " BIC R0, R0, #7 ;ensure stack is 8-byte aligned \n"
switches 0:0e018d759a2a 604 " MRS R1, CPSR \n"
switches 0:0e018d759a2a 605 " CPS #0x1F ;no effect in USR mode \n" // MODE_SYS
switches 0:0e018d759a2a 606 " MOV SP, R0 \n"
switches 0:0e018d759a2a 607 " MSR CPSR_c, R1 ;no effect in USR mode \n"
switches 0:0e018d759a2a 608 " ISB \n"
switches 0:0e018d759a2a 609 " BX LR \n");
switches 0:0e018d759a2a 610 }
switches 0:0e018d759a2a 611
switches 0:0e018d759a2a 612 /** \brief Set User Mode
switches 0:0e018d759a2a 613
switches 0:0e018d759a2a 614 This function changes the processor state to User Mode
switches 0:0e018d759a2a 615 */
switches 0:0e018d759a2a 616 // from rt_CMSIS.c
switches 0:0e018d759a2a 617 __arm static inline void __set_CPS_USR(void) {
switches 0:0e018d759a2a 618 __asm(
switches 0:0e018d759a2a 619 " ARM \n"
switches 0:0e018d759a2a 620
switches 0:0e018d759a2a 621 " CPS #0x10 \n" // MODE_USR
switches 0:0e018d759a2a 622 " BX LR\n");
switches 0:0e018d759a2a 623 }
switches 0:0e018d759a2a 624
switches 0:0e018d759a2a 625 /** \brief Set TTBR0
switches 0:0e018d759a2a 626
switches 0:0e018d759a2a 627 This function assigns the given value to the Translation Table Base Register 0.
switches 0:0e018d759a2a 628
switches 0:0e018d759a2a 629 \param [in] ttbr0 Translation Table Base Register 0 value to set
switches 0:0e018d759a2a 630 */
switches 0:0e018d759a2a 631 // from mmu_Renesas_RZ_A1.c
switches 0:0e018d759a2a 632 __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
switches 0:0e018d759a2a 633 __MCR(15, 0, ttbr0, 2, 0, 0); // reg to cp15
switches 0:0e018d759a2a 634 __ISB();
switches 0:0e018d759a2a 635 }
switches 0:0e018d759a2a 636
switches 0:0e018d759a2a 637 /** \brief Set DACR
switches 0:0e018d759a2a 638
switches 0:0e018d759a2a 639 This function assigns the given value to the Domain Access Control Register.
switches 0:0e018d759a2a 640
switches 0:0e018d759a2a 641 \param [in] dacr Domain Access Control Register value to set
switches 0:0e018d759a2a 642 */
switches 0:0e018d759a2a 643 // from mmu_Renesas_RZ_A1.c
switches 0:0e018d759a2a 644 __STATIC_INLINE void __set_DACR(uint32_t dacr) {
switches 0:0e018d759a2a 645 __MCR(15, 0, dacr, 3, 0, 0); // reg to cp15
switches 0:0e018d759a2a 646 __ISB();
switches 0:0e018d759a2a 647 }
switches 0:0e018d759a2a 648
switches 0:0e018d759a2a 649
switches 0:0e018d759a2a 650 /******************************** Cache and BTAC enable ****************************************************/
switches 0:0e018d759a2a 651 /** \brief Set SCTLR
switches 0:0e018d759a2a 652
switches 0:0e018d759a2a 653 This function assigns the given value to the System Control Register.
switches 0:0e018d759a2a 654
switches 0:0e018d759a2a 655 \param [in] sctlr System Control Register value to set
switches 0:0e018d759a2a 656 */
switches 0:0e018d759a2a 657 // from __enable_mmu()
switches 0:0e018d759a2a 658 __STATIC_INLINE void __set_SCTLR(uint32_t sctlr) {
switches 0:0e018d759a2a 659 __MCR(15, 0, sctlr, 1, 0, 0); // reg to cp15
switches 0:0e018d759a2a 660 }
switches 0:0e018d759a2a 661
switches 0:0e018d759a2a 662 /** \brief Get SCTLR
switches 0:0e018d759a2a 663
switches 0:0e018d759a2a 664 This function returns the value of the System Control Register.
switches 0:0e018d759a2a 665
switches 0:0e018d759a2a 666 \return System Control Register value
switches 0:0e018d759a2a 667 */
switches 0:0e018d759a2a 668 // from __enable_mmu()
switches 0:0e018d759a2a 669 __STATIC_INLINE uint32_t __get_SCTLR() {
switches 0:0e018d759a2a 670 uint32_t __regSCTLR = __MRC(15, 0, 1, 0, 0);
switches 0:0e018d759a2a 671 return __regSCTLR;
switches 0:0e018d759a2a 672 }
switches 0:0e018d759a2a 673
switches 0:0e018d759a2a 674 /** \brief Enable Caches
switches 0:0e018d759a2a 675
switches 0:0e018d759a2a 676 Enable Caches
switches 0:0e018d759a2a 677 */
switches 0:0e018d759a2a 678 // from system_Renesas_RZ_A1.c
switches 0:0e018d759a2a 679 __STATIC_INLINE void __enable_caches(void) {
switches 0:0e018d759a2a 680 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
switches 0:0e018d759a2a 681 }
switches 0:0e018d759a2a 682
switches 0:0e018d759a2a 683 /** \brief Enable BTAC
switches 0:0e018d759a2a 684
switches 0:0e018d759a2a 685 Enable BTAC
switches 0:0e018d759a2a 686 */
switches 0:0e018d759a2a 687 // from system_Renesas_RZ_A1.c
switches 0:0e018d759a2a 688 __STATIC_INLINE void __enable_btac(void) {
switches 0:0e018d759a2a 689 __set_SCTLR( __get_SCTLR() | (1 << 11));
switches 0:0e018d759a2a 690 __ISB();
switches 0:0e018d759a2a 691 }
switches 0:0e018d759a2a 692
switches 0:0e018d759a2a 693 /** \brief Enable MMU
switches 0:0e018d759a2a 694
switches 0:0e018d759a2a 695 Enable MMU
switches 0:0e018d759a2a 696 */
switches 0:0e018d759a2a 697 // from system_Renesas_RZ_A1.c
switches 0:0e018d759a2a 698 __STATIC_INLINE void __enable_mmu(void) {
switches 0:0e018d759a2a 699 // Set M bit 0 to enable the MMU
switches 0:0e018d759a2a 700 // Set AFE bit to enable simplified access permissions model
switches 0:0e018d759a2a 701 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
switches 0:0e018d759a2a 702 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
switches 0:0e018d759a2a 703 __ISB();
switches 0:0e018d759a2a 704 }
switches 0:0e018d759a2a 705
switches 0:0e018d759a2a 706 /******************************** TLB maintenance operations ************************************************/
switches 0:0e018d759a2a 707 /** \brief Invalidate the whole tlb
switches 0:0e018d759a2a 708
switches 0:0e018d759a2a 709 TLBIALL. Invalidate the whole tlb
switches 0:0e018d759a2a 710 */
switches 0:0e018d759a2a 711 // from system_Renesas_RZ_A1.c
switches 0:0e018d759a2a 712 __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
switches 0:0e018d759a2a 713 uint32_t val = 0;
switches 0:0e018d759a2a 714 __MCR(15, 0, val, 8, 7, 0); // reg to cp15
switches 0:0e018d759a2a 715 __MCR(15, 0, val, 8, 6, 0); // reg to cp15
switches 0:0e018d759a2a 716 __MCR(15, 0, val, 8, 5, 0); // reg to cp15
switches 0:0e018d759a2a 717 __DSB();
switches 0:0e018d759a2a 718 __ISB();
switches 0:0e018d759a2a 719 }
switches 0:0e018d759a2a 720
switches 0:0e018d759a2a 721 /******************************** BTB maintenance operations ************************************************/
switches 0:0e018d759a2a 722 /** \brief Invalidate entire branch predictor array
switches 0:0e018d759a2a 723
switches 0:0e018d759a2a 724 BPIALL. Branch Predictor Invalidate All.
switches 0:0e018d759a2a 725 */
switches 0:0e018d759a2a 726 // from system_Renesas_RZ_A1.c
switches 0:0e018d759a2a 727 __STATIC_INLINE void __v7_inv_btac(void) {
switches 0:0e018d759a2a 728 uint32_t val = 0;
switches 0:0e018d759a2a 729 __MCR(15, 0, val, 7, 5, 6); // reg to cp15
switches 0:0e018d759a2a 730 __DSB(); //ensure completion of the invalidation
switches 0:0e018d759a2a 731 __ISB(); //ensure instruction fetch path sees new state
switches 0:0e018d759a2a 732 }
switches 0:0e018d759a2a 733
switches 0:0e018d759a2a 734
switches 0:0e018d759a2a 735 /******************************** L1 cache operations ******************************************************/
switches 0:0e018d759a2a 736
switches 0:0e018d759a2a 737 /** \brief Invalidate the whole I$
switches 0:0e018d759a2a 738
switches 0:0e018d759a2a 739 ICIALLU. Instruction Cache Invalidate All to PoU
switches 0:0e018d759a2a 740 */
switches 0:0e018d759a2a 741 // from system_Renesas_RZ_A1.c
switches 0:0e018d759a2a 742 __STATIC_INLINE void __v7_inv_icache_all(void) {
switches 0:0e018d759a2a 743 uint32_t val = 0;
switches 0:0e018d759a2a 744 __MCR(15, 0, val, 7, 5, 0); // reg to cp15
switches 0:0e018d759a2a 745 __DSB(); //ensure completion of the invalidation
switches 0:0e018d759a2a 746 __ISB(); //ensure instruction fetch path sees new I cache state
switches 0:0e018d759a2a 747 }
switches 0:0e018d759a2a 748
switches 0:0e018d759a2a 749 // from __v7_inv_dcache_all()
switches 0:0e018d759a2a 750 __arm static inline void __v7_all_cache(uint32_t op) {
switches 0:0e018d759a2a 751 __asm(
switches 0:0e018d759a2a 752 " ARM \n"
switches 0:0e018d759a2a 753
switches 0:0e018d759a2a 754 " PUSH {R4-R11} \n"
switches 0:0e018d759a2a 755
switches 0:0e018d759a2a 756 " MRC p15, 1, R6, c0, c0, 1\n" // Read CLIDR
switches 0:0e018d759a2a 757 " ANDS R3, R6, #0x07000000\n" // Extract coherency level
switches 0:0e018d759a2a 758 " MOV R3, R3, LSR #23\n" // Total cache levels << 1
switches 0:0e018d759a2a 759 " BEQ Finished\n" // If 0, no need to clean
switches 0:0e018d759a2a 760
switches 0:0e018d759a2a 761 " MOV R10, #0\n" // R10 holds current cache level << 1
switches 0:0e018d759a2a 762 "Loop1: ADD R2, R10, R10, LSR #1\n" // R2 holds cache "Set" position
switches 0:0e018d759a2a 763 " MOV R1, R6, LSR R2 \n" // Bottom 3 bits are the Cache-type for this level
switches 0:0e018d759a2a 764 " AND R1, R1, #7 \n" // Isolate those lower 3 bits
switches 0:0e018d759a2a 765 " CMP R1, #2 \n"
switches 0:0e018d759a2a 766 " BLT Skip \n" // No cache or only instruction cache at this level
switches 0:0e018d759a2a 767
switches 0:0e018d759a2a 768 " MCR p15, 2, R10, c0, c0, 0 \n" // Write the Cache Size selection register
switches 0:0e018d759a2a 769 " ISB \n" // ISB to sync the change to the CacheSizeID reg
switches 0:0e018d759a2a 770 " MRC p15, 1, R1, c0, c0, 0 \n" // Reads current Cache Size ID register
switches 0:0e018d759a2a 771 " AND R2, R1, #7 \n" // Extract the line length field
switches 0:0e018d759a2a 772 " ADD R2, R2, #4 \n" // Add 4 for the line length offset (log2 16 bytes)
switches 0:0e018d759a2a 773 " movw R4, #0x3FF \n"
switches 0:0e018d759a2a 774 " ANDS R4, R4, R1, LSR #3 \n" // R4 is the max number on the way size (right aligned)
switches 0:0e018d759a2a 775 " CLZ R5, R4 \n" // R5 is the bit position of the way size increment
switches 0:0e018d759a2a 776 " movw R7, #0x7FFF \n"
switches 0:0e018d759a2a 777 " ANDS R7, R7, R1, LSR #13 \n" // R7 is the max number of the index size (right aligned)
switches 0:0e018d759a2a 778
switches 0:0e018d759a2a 779 "Loop2: MOV R9, R4 \n" // R9 working copy of the max way size (right aligned)
switches 0:0e018d759a2a 780
switches 0:0e018d759a2a 781 "Loop3: ORR R11, R10, R9, LSL R5 \n" // Factor in the Way number and cache number into R11
switches 0:0e018d759a2a 782 " ORR R11, R11, R7, LSL R2 \n" // Factor in the Set number
switches 0:0e018d759a2a 783 " CMP R0, #0 \n"
switches 0:0e018d759a2a 784 " BNE Dccsw \n"
switches 0:0e018d759a2a 785 " MCR p15, 0, R11, c7, c6, 2 \n" // DCISW. Invalidate by Set/Way
switches 0:0e018d759a2a 786 " B cont \n"
switches 0:0e018d759a2a 787 "Dccsw: CMP R0, #1 \n"
switches 0:0e018d759a2a 788 " BNE Dccisw \n"
switches 0:0e018d759a2a 789 " MCR p15, 0, R11, c7, c10, 2 \n" // DCCSW. Clean by Set/Way
switches 0:0e018d759a2a 790 " B cont \n"
switches 0:0e018d759a2a 791 "Dccisw: MCR p15, 0, R11, c7, c14, 2 \n" // DCCISW, Clean and Invalidate by Set/Way
switches 0:0e018d759a2a 792 "cont: SUBS R9, R9, #1 \n" // Decrement the Way number
switches 0:0e018d759a2a 793 " BGE Loop3 \n"
switches 0:0e018d759a2a 794 " SUBS R7, R7, #1 \n" // Decrement the Set number
switches 0:0e018d759a2a 795 " BGE Loop2 \n"
switches 0:0e018d759a2a 796 "Skip: ADD R10, R10, #2 \n" // increment the cache number
switches 0:0e018d759a2a 797 " CMP R3, R10 \n"
switches 0:0e018d759a2a 798 " BGT Loop1 \n"
switches 0:0e018d759a2a 799
switches 0:0e018d759a2a 800 "Finished: \n"
switches 0:0e018d759a2a 801 " DSB \n"
switches 0:0e018d759a2a 802 " POP {R4-R11} \n"
switches 0:0e018d759a2a 803 " BX lr \n" );
switches 0:0e018d759a2a 804 }
switches 0:0e018d759a2a 805
switches 0:0e018d759a2a 806 /** \brief Invalidate the whole D$
switches 0:0e018d759a2a 807
switches 0:0e018d759a2a 808 DCISW. Invalidate by Set/Way
switches 0:0e018d759a2a 809 */
switches 0:0e018d759a2a 810 // from system_Renesas_RZ_A1.c
switches 0:0e018d759a2a 811 __STATIC_INLINE void __v7_inv_dcache_all(void) {
switches 0:0e018d759a2a 812 __v7_all_cache(0);
switches 0:0e018d759a2a 813 }
switches 0:0e018d759a2a 814 /** \brief Clean and Invalidate D$ by MVA
switches 0:0e018d759a2a 815
switches 0:0e018d759a2a 816 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
switches 0:0e018d759a2a 817 */
switches 0:0e018d759a2a 818 __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
switches 0:0e018d759a2a 819 __MCR(15, 0, (uint32_t)va, 7, 14, 1);
switches 0:0e018d759a2a 820 __DMB();
switches 0:0e018d759a2a 821 }
switches 0:0e018d759a2a 822
switches 0:0e018d759a2a 823 #include "core_ca_mmu.h"
switches 0:0e018d759a2a 824
switches 0:0e018d759a2a 825 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
switches 0:0e018d759a2a 826 /* GNU gcc specific functions */
switches 0:0e018d759a2a 827
switches 0:0e018d759a2a 828 #define MODE_USR 0x10
switches 0:0e018d759a2a 829 #define MODE_FIQ 0x11
switches 0:0e018d759a2a 830 #define MODE_IRQ 0x12
switches 0:0e018d759a2a 831 #define MODE_SVC 0x13
switches 0:0e018d759a2a 832 #define MODE_MON 0x16
switches 0:0e018d759a2a 833 #define MODE_ABT 0x17
switches 0:0e018d759a2a 834 #define MODE_HYP 0x1A
switches 0:0e018d759a2a 835 #define MODE_UND 0x1B
switches 0:0e018d759a2a 836 #define MODE_SYS 0x1F
switches 0:0e018d759a2a 837
switches 0:0e018d759a2a 838
switches 0:0e018d759a2a 839 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
switches 0:0e018d759a2a 840 {
switches 0:0e018d759a2a 841 __ASM volatile ("cpsie i");
switches 0:0e018d759a2a 842 }
switches 0:0e018d759a2a 843
switches 0:0e018d759a2a 844 /** \brief Disable IRQ Interrupts
switches 0:0e018d759a2a 845
switches 0:0e018d759a2a 846 This function disables IRQ interrupts by setting the I-bit in the CPSR.
switches 0:0e018d759a2a 847 Can only be executed in Privileged modes.
switches 0:0e018d759a2a 848 */
switches 0:0e018d759a2a 849 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __disable_irq(void)
switches 0:0e018d759a2a 850 {
switches 0:0e018d759a2a 851 uint32_t result;
switches 0:0e018d759a2a 852
switches 0:0e018d759a2a 853 __ASM volatile ("mrs %0, cpsr" : "=r" (result));
switches 0:0e018d759a2a 854 __ASM volatile ("cpsid i");
switches 0:0e018d759a2a 855 return(result & 0x80);
switches 0:0e018d759a2a 856 }
switches 0:0e018d759a2a 857
switches 0:0e018d759a2a 858
switches 0:0e018d759a2a 859 /** \brief Get APSR Register
switches 0:0e018d759a2a 860
switches 0:0e018d759a2a 861 This function returns the content of the APSR Register.
switches 0:0e018d759a2a 862
switches 0:0e018d759a2a 863 \return APSR Register value
switches 0:0e018d759a2a 864 */
switches 0:0e018d759a2a 865 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
switches 0:0e018d759a2a 866 {
switches 0:0e018d759a2a 867 #if 1
switches 0:0e018d759a2a 868 register uint32_t __regAPSR;
switches 0:0e018d759a2a 869 __ASM volatile ("mrs %0, apsr" : "=r" (__regAPSR) );
switches 0:0e018d759a2a 870 #else
switches 0:0e018d759a2a 871 register uint32_t __regAPSR __ASM("apsr");
switches 0:0e018d759a2a 872 #endif
switches 0:0e018d759a2a 873 return(__regAPSR);
switches 0:0e018d759a2a 874 }
switches 0:0e018d759a2a 875
switches 0:0e018d759a2a 876
switches 0:0e018d759a2a 877 /** \brief Get CPSR Register
switches 0:0e018d759a2a 878
switches 0:0e018d759a2a 879 This function returns the content of the CPSR Register.
switches 0:0e018d759a2a 880
switches 0:0e018d759a2a 881 \return CPSR Register value
switches 0:0e018d759a2a 882 */
switches 0:0e018d759a2a 883 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void)
switches 0:0e018d759a2a 884 {
switches 0:0e018d759a2a 885 #if 1
switches 0:0e018d759a2a 886 register uint32_t __regCPSR;
switches 0:0e018d759a2a 887 __ASM volatile ("mrs %0, cpsr" : "=r" (__regCPSR));
switches 0:0e018d759a2a 888 #else
switches 0:0e018d759a2a 889 register uint32_t __regCPSR __ASM("cpsr");
switches 0:0e018d759a2a 890 #endif
switches 0:0e018d759a2a 891 return(__regCPSR);
switches 0:0e018d759a2a 892 }
switches 0:0e018d759a2a 893
switches 0:0e018d759a2a 894 #if 0
switches 0:0e018d759a2a 895 /** \brief Set Stack Pointer
switches 0:0e018d759a2a 896
switches 0:0e018d759a2a 897 This function assigns the given value to the current stack pointer.
switches 0:0e018d759a2a 898
switches 0:0e018d759a2a 899 \param [in] topOfStack Stack Pointer value to set
switches 0:0e018d759a2a 900 */
switches 0:0e018d759a2a 901 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SP(uint32_t topOfStack)
switches 0:0e018d759a2a 902 {
switches 0:0e018d759a2a 903 register uint32_t __regSP __ASM("sp");
switches 0:0e018d759a2a 904 __regSP = topOfStack;
switches 0:0e018d759a2a 905 }
switches 0:0e018d759a2a 906 #endif
switches 0:0e018d759a2a 907
switches 0:0e018d759a2a 908 /** \brief Get link register
switches 0:0e018d759a2a 909
switches 0:0e018d759a2a 910 This function returns the value of the link register
switches 0:0e018d759a2a 911
switches 0:0e018d759a2a 912 \return Value of link register
switches 0:0e018d759a2a 913 */
switches 0:0e018d759a2a 914 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_LR(void)
switches 0:0e018d759a2a 915 {
switches 0:0e018d759a2a 916 register uint32_t __reglr __ASM("lr");
switches 0:0e018d759a2a 917 return(__reglr);
switches 0:0e018d759a2a 918 }
switches 0:0e018d759a2a 919
switches 0:0e018d759a2a 920 #if 0
switches 0:0e018d759a2a 921 /** \brief Set link register
switches 0:0e018d759a2a 922
switches 0:0e018d759a2a 923 This function sets the value of the link register
switches 0:0e018d759a2a 924
switches 0:0e018d759a2a 925 \param [in] lr LR value to set
switches 0:0e018d759a2a 926 */
switches 0:0e018d759a2a 927 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_LR(uint32_t lr)
switches 0:0e018d759a2a 928 {
switches 0:0e018d759a2a 929 register uint32_t __reglr __ASM("lr");
switches 0:0e018d759a2a 930 __reglr = lr;
switches 0:0e018d759a2a 931 }
switches 0:0e018d759a2a 932 #endif
switches 0:0e018d759a2a 933
switches 0:0e018d759a2a 934 /** \brief Set Process Stack Pointer
switches 0:0e018d759a2a 935
switches 0:0e018d759a2a 936 This function assigns the given value to the USR/SYS Stack Pointer (PSP).
switches 0:0e018d759a2a 937
switches 0:0e018d759a2a 938 \param [in] topOfProcStack USR/SYS Stack Pointer value to set
switches 0:0e018d759a2a 939 */
switches 0:0e018d759a2a 940 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
switches 0:0e018d759a2a 941 {
switches 0:0e018d759a2a 942 __asm__ volatile (
switches 0:0e018d759a2a 943 ".ARM;"
switches 0:0e018d759a2a 944 ".eabi_attribute Tag_ABI_align8_preserved,1;"
switches 0:0e018d759a2a 945
switches 0:0e018d759a2a 946 "BIC R0, R0, #7;" /* ;ensure stack is 8-byte aligned */
switches 0:0e018d759a2a 947 "MRS R1, CPSR;"
switches 0:0e018d759a2a 948 "CPS %0;" /* ;no effect in USR mode */
switches 0:0e018d759a2a 949 "MOV SP, R0;"
switches 0:0e018d759a2a 950 "MSR CPSR_c, R1;" /* ;no effect in USR mode */
switches 0:0e018d759a2a 951 "ISB;"
switches 0:0e018d759a2a 952 //"BX LR;"
switches 0:0e018d759a2a 953 :
switches 0:0e018d759a2a 954 : "i"(MODE_SYS)
switches 0:0e018d759a2a 955 : "r0", "r1");
switches 0:0e018d759a2a 956 return;
switches 0:0e018d759a2a 957 }
switches 0:0e018d759a2a 958
switches 0:0e018d759a2a 959 /** \brief Set User Mode
switches 0:0e018d759a2a 960
switches 0:0e018d759a2a 961 This function changes the processor state to User Mode
switches 0:0e018d759a2a 962 */
switches 0:0e018d759a2a 963 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPS_USR(void)
switches 0:0e018d759a2a 964 {
switches 0:0e018d759a2a 965 __asm__ volatile (
switches 0:0e018d759a2a 966 ".ARM;"
switches 0:0e018d759a2a 967
switches 0:0e018d759a2a 968 "CPS %0;"
switches 0:0e018d759a2a 969 //"BX LR;"
switches 0:0e018d759a2a 970 :
switches 0:0e018d759a2a 971 : "i"(MODE_USR)
switches 0:0e018d759a2a 972 : );
switches 0:0e018d759a2a 973 return;
switches 0:0e018d759a2a 974 }
switches 0:0e018d759a2a 975
switches 0:0e018d759a2a 976
switches 0:0e018d759a2a 977 /** \brief Enable FIQ
switches 0:0e018d759a2a 978
switches 0:0e018d759a2a 979 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
switches 0:0e018d759a2a 980 Can only be executed in Privileged modes.
switches 0:0e018d759a2a 981 */
switches 0:0e018d759a2a 982 #define __enable_fault_irq() __asm__ volatile ("cpsie f")
switches 0:0e018d759a2a 983
switches 0:0e018d759a2a 984
switches 0:0e018d759a2a 985 /** \brief Disable FIQ
switches 0:0e018d759a2a 986
switches 0:0e018d759a2a 987 This function disables FIQ interrupts by setting the F-bit in the CPSR.
switches 0:0e018d759a2a 988 Can only be executed in Privileged modes.
switches 0:0e018d759a2a 989 */
switches 0:0e018d759a2a 990 #define __disable_fault_irq() __asm__ volatile ("cpsid f")
switches 0:0e018d759a2a 991
switches 0:0e018d759a2a 992
switches 0:0e018d759a2a 993 /** \brief Get FPSCR
switches 0:0e018d759a2a 994
switches 0:0e018d759a2a 995 This function returns the current value of the Floating Point Status/Control register.
switches 0:0e018d759a2a 996
switches 0:0e018d759a2a 997 \return Floating Point Status/Control register value
switches 0:0e018d759a2a 998 */
switches 0:0e018d759a2a 999 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
switches 0:0e018d759a2a 1000 {
switches 0:0e018d759a2a 1001 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
switches 0:0e018d759a2a 1002 #if 1
switches 0:0e018d759a2a 1003 uint32_t result;
switches 0:0e018d759a2a 1004
switches 0:0e018d759a2a 1005 __ASM volatile ("vmrs %0, fpscr" : "=r" (result) );
switches 0:0e018d759a2a 1006 return (result);
switches 0:0e018d759a2a 1007 #else
switches 0:0e018d759a2a 1008 register uint32_t __regfpscr __ASM("fpscr");
switches 0:0e018d759a2a 1009 return(__regfpscr);
switches 0:0e018d759a2a 1010 #endif
switches 0:0e018d759a2a 1011 #else
switches 0:0e018d759a2a 1012 return(0);
switches 0:0e018d759a2a 1013 #endif
switches 0:0e018d759a2a 1014 }
switches 0:0e018d759a2a 1015
switches 0:0e018d759a2a 1016
switches 0:0e018d759a2a 1017 /** \brief Set FPSCR
switches 0:0e018d759a2a 1018
switches 0:0e018d759a2a 1019 This function assigns the given value to the Floating Point Status/Control register.
switches 0:0e018d759a2a 1020
switches 0:0e018d759a2a 1021 \param [in] fpscr Floating Point Status/Control value to set
switches 0:0e018d759a2a 1022 */
switches 0:0e018d759a2a 1023 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
switches 0:0e018d759a2a 1024 {
switches 0:0e018d759a2a 1025 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
switches 0:0e018d759a2a 1026 #if 1
switches 0:0e018d759a2a 1027 __ASM volatile ("vmsr fpscr, %0" : : "r" (fpscr) );
switches 0:0e018d759a2a 1028 #else
switches 0:0e018d759a2a 1029 register uint32_t __regfpscr __ASM("fpscr");
switches 0:0e018d759a2a 1030 __regfpscr = (fpscr);
switches 0:0e018d759a2a 1031 #endif
switches 0:0e018d759a2a 1032 #endif
switches 0:0e018d759a2a 1033 }
switches 0:0e018d759a2a 1034
switches 0:0e018d759a2a 1035 /** \brief Get FPEXC
switches 0:0e018d759a2a 1036
switches 0:0e018d759a2a 1037 This function returns the current value of the Floating Point Exception Control register.
switches 0:0e018d759a2a 1038
switches 0:0e018d759a2a 1039 \return Floating Point Exception Control register value
switches 0:0e018d759a2a 1040 */
switches 0:0e018d759a2a 1041 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void)
switches 0:0e018d759a2a 1042 {
switches 0:0e018d759a2a 1043 #if (__FPU_PRESENT == 1)
switches 0:0e018d759a2a 1044 #if 1
switches 0:0e018d759a2a 1045 uint32_t result;
switches 0:0e018d759a2a 1046
switches 0:0e018d759a2a 1047 __ASM volatile ("vmrs %0, fpexc" : "=r" (result));
switches 0:0e018d759a2a 1048 return (result);
switches 0:0e018d759a2a 1049 #else
switches 0:0e018d759a2a 1050 register uint32_t __regfpexc __ASM("fpexc");
switches 0:0e018d759a2a 1051 return(__regfpexc);
switches 0:0e018d759a2a 1052 #endif
switches 0:0e018d759a2a 1053 #else
switches 0:0e018d759a2a 1054 return(0);
switches 0:0e018d759a2a 1055 #endif
switches 0:0e018d759a2a 1056 }
switches 0:0e018d759a2a 1057
switches 0:0e018d759a2a 1058
switches 0:0e018d759a2a 1059 /** \brief Set FPEXC
switches 0:0e018d759a2a 1060
switches 0:0e018d759a2a 1061 This function assigns the given value to the Floating Point Exception Control register.
switches 0:0e018d759a2a 1062
switches 0:0e018d759a2a 1063 \param [in] fpscr Floating Point Exception Control value to set
switches 0:0e018d759a2a 1064 */
switches 0:0e018d759a2a 1065 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
switches 0:0e018d759a2a 1066 {
switches 0:0e018d759a2a 1067 #if (__FPU_PRESENT == 1)
switches 0:0e018d759a2a 1068 #if 1
switches 0:0e018d759a2a 1069 __ASM volatile ("vmsr fpexc, %0" : : "r" (fpexc));
switches 0:0e018d759a2a 1070 #else
switches 0:0e018d759a2a 1071 register uint32_t __regfpexc __ASM("fpexc");
switches 0:0e018d759a2a 1072 __regfpexc = (fpexc);
switches 0:0e018d759a2a 1073 #endif
switches 0:0e018d759a2a 1074 #endif
switches 0:0e018d759a2a 1075 }
switches 0:0e018d759a2a 1076
switches 0:0e018d759a2a 1077 /** \brief Get CPACR
switches 0:0e018d759a2a 1078
switches 0:0e018d759a2a 1079 This function returns the current value of the Coprocessor Access Control register.
switches 0:0e018d759a2a 1080
switches 0:0e018d759a2a 1081 \return Coprocessor Access Control register value
switches 0:0e018d759a2a 1082 */
switches 0:0e018d759a2a 1083 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPACR(void)
switches 0:0e018d759a2a 1084 {
switches 0:0e018d759a2a 1085 #if 1
switches 0:0e018d759a2a 1086 register uint32_t __regCPACR;
switches 0:0e018d759a2a 1087 __ASM volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r" (__regCPACR));
switches 0:0e018d759a2a 1088 #else
switches 0:0e018d759a2a 1089 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
switches 0:0e018d759a2a 1090 #endif
switches 0:0e018d759a2a 1091 return __regCPACR;
switches 0:0e018d759a2a 1092 }
switches 0:0e018d759a2a 1093
switches 0:0e018d759a2a 1094 /** \brief Set CPACR
switches 0:0e018d759a2a 1095
switches 0:0e018d759a2a 1096 This function assigns the given value to the Coprocessor Access Control register.
switches 0:0e018d759a2a 1097
switches 0:0e018d759a2a 1098 \param [in] cpacr Coprocessor Acccess Control value to set
switches 0:0e018d759a2a 1099 */
switches 0:0e018d759a2a 1100 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPACR(uint32_t cpacr)
switches 0:0e018d759a2a 1101 {
switches 0:0e018d759a2a 1102 #if 1
switches 0:0e018d759a2a 1103 __ASM volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r" (cpacr));
switches 0:0e018d759a2a 1104 #else
switches 0:0e018d759a2a 1105 register uint32_t __regCPACR __ASM("cp15:0:c1:c0:2");
switches 0:0e018d759a2a 1106 __regCPACR = cpacr;
switches 0:0e018d759a2a 1107 #endif
switches 0:0e018d759a2a 1108 __ISB();
switches 0:0e018d759a2a 1109 }
switches 0:0e018d759a2a 1110
switches 0:0e018d759a2a 1111 /** \brief Get CBAR
switches 0:0e018d759a2a 1112
switches 0:0e018d759a2a 1113 This function returns the value of the Configuration Base Address register.
switches 0:0e018d759a2a 1114
switches 0:0e018d759a2a 1115 \return Configuration Base Address register value
switches 0:0e018d759a2a 1116 */
switches 0:0e018d759a2a 1117 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CBAR() {
switches 0:0e018d759a2a 1118 #if 1
switches 0:0e018d759a2a 1119 register uint32_t __regCBAR;
switches 0:0e018d759a2a 1120 __ASM volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (__regCBAR));
switches 0:0e018d759a2a 1121 #else
switches 0:0e018d759a2a 1122 register uint32_t __regCBAR __ASM("cp15:4:c15:c0:0");
switches 0:0e018d759a2a 1123 #endif
switches 0:0e018d759a2a 1124 return(__regCBAR);
switches 0:0e018d759a2a 1125 }
switches 0:0e018d759a2a 1126
switches 0:0e018d759a2a 1127 /** \brief Get TTBR0
switches 0:0e018d759a2a 1128
switches 0:0e018d759a2a 1129 This function returns the value of the Translation Table Base Register 0.
switches 0:0e018d759a2a 1130
switches 0:0e018d759a2a 1131 \return Translation Table Base Register 0 value
switches 0:0e018d759a2a 1132 */
switches 0:0e018d759a2a 1133 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_TTBR0() {
switches 0:0e018d759a2a 1134 #if 1
switches 0:0e018d759a2a 1135 register uint32_t __regTTBR0;
switches 0:0e018d759a2a 1136 __ASM volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r" (__regTTBR0));
switches 0:0e018d759a2a 1137 #else
switches 0:0e018d759a2a 1138 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
switches 0:0e018d759a2a 1139 #endif
switches 0:0e018d759a2a 1140 return(__regTTBR0);
switches 0:0e018d759a2a 1141 }
switches 0:0e018d759a2a 1142
switches 0:0e018d759a2a 1143 /** \brief Set TTBR0
switches 0:0e018d759a2a 1144
switches 0:0e018d759a2a 1145 This function assigns the given value to the Translation Table Base Register 0.
switches 0:0e018d759a2a 1146
switches 0:0e018d759a2a 1147 \param [in] ttbr0 Translation Table Base Register 0 value to set
switches 0:0e018d759a2a 1148 */
switches 0:0e018d759a2a 1149 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_TTBR0(uint32_t ttbr0) {
switches 0:0e018d759a2a 1150 #if 1
switches 0:0e018d759a2a 1151 __ASM volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (ttbr0));
switches 0:0e018d759a2a 1152 #else
switches 0:0e018d759a2a 1153 register uint32_t __regTTBR0 __ASM("cp15:0:c2:c0:0");
switches 0:0e018d759a2a 1154 __regTTBR0 = ttbr0;
switches 0:0e018d759a2a 1155 #endif
switches 0:0e018d759a2a 1156 __ISB();
switches 0:0e018d759a2a 1157 }
switches 0:0e018d759a2a 1158
switches 0:0e018d759a2a 1159 /** \brief Get DACR
switches 0:0e018d759a2a 1160
switches 0:0e018d759a2a 1161 This function returns the value of the Domain Access Control Register.
switches 0:0e018d759a2a 1162
switches 0:0e018d759a2a 1163 \return Domain Access Control Register value
switches 0:0e018d759a2a 1164 */
switches 0:0e018d759a2a 1165 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_DACR() {
switches 0:0e018d759a2a 1166 #if 1
switches 0:0e018d759a2a 1167 register uint32_t __regDACR;
switches 0:0e018d759a2a 1168 __ASM volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r" (__regDACR));
switches 0:0e018d759a2a 1169 #else
switches 0:0e018d759a2a 1170 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
switches 0:0e018d759a2a 1171 #endif
switches 0:0e018d759a2a 1172 return(__regDACR);
switches 0:0e018d759a2a 1173 }
switches 0:0e018d759a2a 1174
switches 0:0e018d759a2a 1175 /** \brief Set DACR
switches 0:0e018d759a2a 1176
switches 0:0e018d759a2a 1177 This function assigns the given value to the Domain Access Control Register.
switches 0:0e018d759a2a 1178
switches 0:0e018d759a2a 1179 \param [in] dacr Domain Access Control Register value to set
switches 0:0e018d759a2a 1180 */
switches 0:0e018d759a2a 1181 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_DACR(uint32_t dacr) {
switches 0:0e018d759a2a 1182 #if 1
switches 0:0e018d759a2a 1183 __ASM volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (dacr));
switches 0:0e018d759a2a 1184 #else
switches 0:0e018d759a2a 1185 register uint32_t __regDACR __ASM("cp15:0:c3:c0:0");
switches 0:0e018d759a2a 1186 __regDACR = dacr;
switches 0:0e018d759a2a 1187 #endif
switches 0:0e018d759a2a 1188 __ISB();
switches 0:0e018d759a2a 1189 }
switches 0:0e018d759a2a 1190
switches 0:0e018d759a2a 1191 /******************************** Cache and BTAC enable ****************************************************/
switches 0:0e018d759a2a 1192
switches 0:0e018d759a2a 1193 /** \brief Set SCTLR
switches 0:0e018d759a2a 1194
switches 0:0e018d759a2a 1195 This function assigns the given value to the System Control Register.
switches 0:0e018d759a2a 1196
switches 0:0e018d759a2a 1197 \param [in] sctlr System Control Register value to set
switches 0:0e018d759a2a 1198 */
switches 0:0e018d759a2a 1199 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_SCTLR(uint32_t sctlr)
switches 0:0e018d759a2a 1200 {
switches 0:0e018d759a2a 1201 #if 1
switches 0:0e018d759a2a 1202 __ASM volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (sctlr));
switches 0:0e018d759a2a 1203 #else
switches 0:0e018d759a2a 1204 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
switches 0:0e018d759a2a 1205 __regSCTLR = sctlr;
switches 0:0e018d759a2a 1206 #endif
switches 0:0e018d759a2a 1207 }
switches 0:0e018d759a2a 1208
switches 0:0e018d759a2a 1209 /** \brief Get SCTLR
switches 0:0e018d759a2a 1210
switches 0:0e018d759a2a 1211 This function returns the value of the System Control Register.
switches 0:0e018d759a2a 1212
switches 0:0e018d759a2a 1213 \return System Control Register value
switches 0:0e018d759a2a 1214 */
switches 0:0e018d759a2a 1215 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_SCTLR() {
switches 0:0e018d759a2a 1216 #if 1
switches 0:0e018d759a2a 1217 register uint32_t __regSCTLR;
switches 0:0e018d759a2a 1218 __ASM volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (__regSCTLR));
switches 0:0e018d759a2a 1219 #else
switches 0:0e018d759a2a 1220 register uint32_t __regSCTLR __ASM("cp15:0:c1:c0:0");
switches 0:0e018d759a2a 1221 #endif
switches 0:0e018d759a2a 1222 return(__regSCTLR);
switches 0:0e018d759a2a 1223 }
switches 0:0e018d759a2a 1224
switches 0:0e018d759a2a 1225 /** \brief Enable Caches
switches 0:0e018d759a2a 1226
switches 0:0e018d759a2a 1227 Enable Caches
switches 0:0e018d759a2a 1228 */
switches 0:0e018d759a2a 1229 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_caches(void) {
switches 0:0e018d759a2a 1230 // Set I bit 12 to enable I Cache
switches 0:0e018d759a2a 1231 // Set C bit 2 to enable D Cache
switches 0:0e018d759a2a 1232 __set_SCTLR( __get_SCTLR() | (1 << 12) | (1 << 2));
switches 0:0e018d759a2a 1233 }
switches 0:0e018d759a2a 1234
switches 0:0e018d759a2a 1235 /** \brief Disable Caches
switches 0:0e018d759a2a 1236
switches 0:0e018d759a2a 1237 Disable Caches
switches 0:0e018d759a2a 1238 */
switches 0:0e018d759a2a 1239 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_caches(void) {
switches 0:0e018d759a2a 1240 // Clear I bit 12 to disable I Cache
switches 0:0e018d759a2a 1241 // Clear C bit 2 to disable D Cache
switches 0:0e018d759a2a 1242 __set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
switches 0:0e018d759a2a 1243 __ISB();
switches 0:0e018d759a2a 1244 }
switches 0:0e018d759a2a 1245
switches 0:0e018d759a2a 1246 /** \brief Enable BTAC
switches 0:0e018d759a2a 1247
switches 0:0e018d759a2a 1248 Enable BTAC
switches 0:0e018d759a2a 1249 */
switches 0:0e018d759a2a 1250 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_btac(void) {
switches 0:0e018d759a2a 1251 // Set Z bit 11 to enable branch prediction
switches 0:0e018d759a2a 1252 __set_SCTLR( __get_SCTLR() | (1 << 11));
switches 0:0e018d759a2a 1253 __ISB();
switches 0:0e018d759a2a 1254 }
switches 0:0e018d759a2a 1255
switches 0:0e018d759a2a 1256 /** \brief Disable BTAC
switches 0:0e018d759a2a 1257
switches 0:0e018d759a2a 1258 Disable BTAC
switches 0:0e018d759a2a 1259 */
switches 0:0e018d759a2a 1260 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_btac(void) {
switches 0:0e018d759a2a 1261 // Clear Z bit 11 to disable branch prediction
switches 0:0e018d759a2a 1262 __set_SCTLR( __get_SCTLR() & ~(1 << 11));
switches 0:0e018d759a2a 1263 }
switches 0:0e018d759a2a 1264
switches 0:0e018d759a2a 1265
switches 0:0e018d759a2a 1266 /** \brief Enable MMU
switches 0:0e018d759a2a 1267
switches 0:0e018d759a2a 1268 Enable MMU
switches 0:0e018d759a2a 1269 */
switches 0:0e018d759a2a 1270 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_mmu(void) {
switches 0:0e018d759a2a 1271 // Set M bit 0 to enable the MMU
switches 0:0e018d759a2a 1272 // Set AFE bit to enable simplified access permissions model
switches 0:0e018d759a2a 1273 // Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
switches 0:0e018d759a2a 1274 __set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) | 1 | (1 << 29));
switches 0:0e018d759a2a 1275 __ISB();
switches 0:0e018d759a2a 1276 }
switches 0:0e018d759a2a 1277
switches 0:0e018d759a2a 1278 /** \brief Disable MMU
switches 0:0e018d759a2a 1279
switches 0:0e018d759a2a 1280 Disable MMU
switches 0:0e018d759a2a 1281 */
switches 0:0e018d759a2a 1282 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_mmu(void) {
switches 0:0e018d759a2a 1283 // Clear M bit 0 to disable the MMU
switches 0:0e018d759a2a 1284 __set_SCTLR( __get_SCTLR() & ~1);
switches 0:0e018d759a2a 1285 __ISB();
switches 0:0e018d759a2a 1286 }
switches 0:0e018d759a2a 1287
switches 0:0e018d759a2a 1288 /******************************** TLB maintenance operations ************************************************/
switches 0:0e018d759a2a 1289 /** \brief Invalidate the whole tlb
switches 0:0e018d759a2a 1290
switches 0:0e018d759a2a 1291 TLBIALL. Invalidate the whole tlb
switches 0:0e018d759a2a 1292 */
switches 0:0e018d759a2a 1293
switches 0:0e018d759a2a 1294 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ca9u_inv_tlb_all(void) {
switches 0:0e018d759a2a 1295 #if 1
switches 0:0e018d759a2a 1296 __ASM volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
switches 0:0e018d759a2a 1297 #else
switches 0:0e018d759a2a 1298 register uint32_t __TLBIALL __ASM("cp15:0:c8:c7:0");
switches 0:0e018d759a2a 1299 __TLBIALL = 0;
switches 0:0e018d759a2a 1300 #endif
switches 0:0e018d759a2a 1301 __DSB();
switches 0:0e018d759a2a 1302 __ISB();
switches 0:0e018d759a2a 1303 }
switches 0:0e018d759a2a 1304
switches 0:0e018d759a2a 1305 /******************************** BTB maintenance operations ************************************************/
switches 0:0e018d759a2a 1306 /** \brief Invalidate entire branch predictor array
switches 0:0e018d759a2a 1307
switches 0:0e018d759a2a 1308 BPIALL. Branch Predictor Invalidate All.
switches 0:0e018d759a2a 1309 */
switches 0:0e018d759a2a 1310
switches 0:0e018d759a2a 1311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_btac(void) {
switches 0:0e018d759a2a 1312 #if 1
switches 0:0e018d759a2a 1313 __ASM volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
switches 0:0e018d759a2a 1314 #else
switches 0:0e018d759a2a 1315 register uint32_t __BPIALL __ASM("cp15:0:c7:c5:6");
switches 0:0e018d759a2a 1316 __BPIALL = 0;
switches 0:0e018d759a2a 1317 #endif
switches 0:0e018d759a2a 1318 __DSB(); //ensure completion of the invalidation
switches 0:0e018d759a2a 1319 __ISB(); //ensure instruction fetch path sees new state
switches 0:0e018d759a2a 1320 }
switches 0:0e018d759a2a 1321
switches 0:0e018d759a2a 1322
switches 0:0e018d759a2a 1323 /******************************** L1 cache operations ******************************************************/
switches 0:0e018d759a2a 1324
switches 0:0e018d759a2a 1325 /** \brief Invalidate the whole I$
switches 0:0e018d759a2a 1326
switches 0:0e018d759a2a 1327 ICIALLU. Instruction Cache Invalidate All to PoU
switches 0:0e018d759a2a 1328 */
switches 0:0e018d759a2a 1329 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_icache_all(void) {
switches 0:0e018d759a2a 1330 #if 1
switches 0:0e018d759a2a 1331 __ASM volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
switches 0:0e018d759a2a 1332 #else
switches 0:0e018d759a2a 1333 register uint32_t __ICIALLU __ASM("cp15:0:c7:c5:0");
switches 0:0e018d759a2a 1334 __ICIALLU = 0;
switches 0:0e018d759a2a 1335 #endif
switches 0:0e018d759a2a 1336 __DSB(); //ensure completion of the invalidation
switches 0:0e018d759a2a 1337 __ISB(); //ensure instruction fetch path sees new I cache state
switches 0:0e018d759a2a 1338 }
switches 0:0e018d759a2a 1339
switches 0:0e018d759a2a 1340 /** \brief Clean D$ by MVA
switches 0:0e018d759a2a 1341
switches 0:0e018d759a2a 1342 DCCMVAC. Data cache clean by MVA to PoC
switches 0:0e018d759a2a 1343 */
switches 0:0e018d759a2a 1344 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_mva(void *va) {
switches 0:0e018d759a2a 1345 #if 1
switches 0:0e018d759a2a 1346 __ASM volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" ((uint32_t)va));
switches 0:0e018d759a2a 1347 #else
switches 0:0e018d759a2a 1348 register uint32_t __DCCMVAC __ASM("cp15:0:c7:c10:1");
switches 0:0e018d759a2a 1349 __DCCMVAC = (uint32_t)va;
switches 0:0e018d759a2a 1350 #endif
switches 0:0e018d759a2a 1351 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
switches 0:0e018d759a2a 1352 }
switches 0:0e018d759a2a 1353
switches 0:0e018d759a2a 1354 /** \brief Invalidate D$ by MVA
switches 0:0e018d759a2a 1355
switches 0:0e018d759a2a 1356 DCIMVAC. Data cache invalidate by MVA to PoC
switches 0:0e018d759a2a 1357 */
switches 0:0e018d759a2a 1358 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_mva(void *va) {
switches 0:0e018d759a2a 1359 #if 1
switches 0:0e018d759a2a 1360 __ASM volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" ((uint32_t)va));
switches 0:0e018d759a2a 1361 #else
switches 0:0e018d759a2a 1362 register uint32_t __DCIMVAC __ASM("cp15:0:c7:c6:1");
switches 0:0e018d759a2a 1363 __DCIMVAC = (uint32_t)va;
switches 0:0e018d759a2a 1364 #endif
switches 0:0e018d759a2a 1365 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
switches 0:0e018d759a2a 1366 }
switches 0:0e018d759a2a 1367
switches 0:0e018d759a2a 1368 /** \brief Clean and Invalidate D$ by MVA
switches 0:0e018d759a2a 1369
switches 0:0e018d759a2a 1370 DCCIMVAC. Data cache clean and invalidate by MVA to PoC
switches 0:0e018d759a2a 1371 */
switches 0:0e018d759a2a 1372 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
switches 0:0e018d759a2a 1373 #if 1
switches 0:0e018d759a2a 1374 __ASM volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" ((uint32_t)va));
switches 0:0e018d759a2a 1375 #else
switches 0:0e018d759a2a 1376 register uint32_t __DCCIMVAC __ASM("cp15:0:c7:c14:1");
switches 0:0e018d759a2a 1377 __DCCIMVAC = (uint32_t)va;
switches 0:0e018d759a2a 1378 #endif
switches 0:0e018d759a2a 1379 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
switches 0:0e018d759a2a 1380 }
switches 0:0e018d759a2a 1381
switches 0:0e018d759a2a 1382 /** \brief Clean and Invalidate the entire data or unified cache
switches 0:0e018d759a2a 1383
switches 0:0e018d759a2a 1384 Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
switches 0:0e018d759a2a 1385 */
switches 0:0e018d759a2a 1386 extern void __v7_all_cache(uint32_t op);
switches 0:0e018d759a2a 1387
switches 0:0e018d759a2a 1388
switches 0:0e018d759a2a 1389 /** \brief Invalidate the whole D$
switches 0:0e018d759a2a 1390
switches 0:0e018d759a2a 1391 DCISW. Invalidate by Set/Way
switches 0:0e018d759a2a 1392 */
switches 0:0e018d759a2a 1393
switches 0:0e018d759a2a 1394 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_inv_dcache_all(void) {
switches 0:0e018d759a2a 1395 __v7_all_cache(0);
switches 0:0e018d759a2a 1396 }
switches 0:0e018d759a2a 1397
switches 0:0e018d759a2a 1398 /** \brief Clean the whole D$
switches 0:0e018d759a2a 1399
switches 0:0e018d759a2a 1400 DCCSW. Clean by Set/Way
switches 0:0e018d759a2a 1401 */
switches 0:0e018d759a2a 1402
switches 0:0e018d759a2a 1403 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_dcache_all(void) {
switches 0:0e018d759a2a 1404 __v7_all_cache(1);
switches 0:0e018d759a2a 1405 }
switches 0:0e018d759a2a 1406
switches 0:0e018d759a2a 1407 /** \brief Clean and invalidate the whole D$
switches 0:0e018d759a2a 1408
switches 0:0e018d759a2a 1409 DCCISW. Clean and Invalidate by Set/Way
switches 0:0e018d759a2a 1410 */
switches 0:0e018d759a2a 1411
switches 0:0e018d759a2a 1412 __attribute__( ( always_inline ) ) __STATIC_INLINE void __v7_clean_inv_dcache_all(void) {
switches 0:0e018d759a2a 1413 __v7_all_cache(2);
switches 0:0e018d759a2a 1414 }
switches 0:0e018d759a2a 1415
switches 0:0e018d759a2a 1416 #include "core_ca_mmu.h"
switches 0:0e018d759a2a 1417
switches 0:0e018d759a2a 1418 #elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
switches 0:0e018d759a2a 1419
switches 0:0e018d759a2a 1420 #error TASKING Compiler support not implemented for Cortex-A
switches 0:0e018d759a2a 1421
switches 0:0e018d759a2a 1422 #endif
switches 0:0e018d759a2a 1423
switches 0:0e018d759a2a 1424 /*@} end of CMSIS_Core_RegAccFunctions */
switches 0:0e018d759a2a 1425
switches 0:0e018d759a2a 1426
switches 0:0e018d759a2a 1427 #endif /* __CORE_CAFUNC_H__ */