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targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc_ex.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:: <>
Date:: Fri Sep 02 15:07:44 2016 +0100
Revision:: 144:ef7eb2e8f9f7
Parent:: 0:9b334a45a8ff

This updates the lib to the mbed lib v125

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f3xx_hal_adc_ex.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.3.0
<>	144:ef7eb2e8f9f7	6	* @date 01-July-2016
<>	144:ef7eb2e8f9f7	7	* @brief Header file containing functions prototypes of ADC HAL library.
<>	144:ef7eb2e8f9f7	8	******************************************************************************
<>	144:ef7eb2e8f9f7	9	* @attention
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	12	*
<>	144:ef7eb2e8f9f7	13	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	14	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	18	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	19	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	21	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	22	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	23	*
<>	144:ef7eb2e8f9f7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	34	*
<>	144:ef7eb2e8f9f7	35	******************************************************************************
<>	144:ef7eb2e8f9f7	36	*/
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	39	#ifndef __STM32F3xx_ADC_EX_H
<>	144:ef7eb2e8f9f7	40	#define __STM32F3xx_ADC_EX_H
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	43	extern "C" {
<>	144:ef7eb2e8f9f7	44	#endif
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	47	#include "stm32f3xx_hal_def.h"
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	/** @addtogroup STM32F3xx_HAL_Driver
<>	144:ef7eb2e8f9f7	50	* @{
<>	144:ef7eb2e8f9f7	51	*/
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	/** @addtogroup ADCEx ADCEx
<>	144:ef7eb2e8f9f7	54	* @{
<>	144:ef7eb2e8f9f7	55	*/
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	58	/** @defgroup ADCEx_Exported_Types ADCEx Exported Types
<>	144:ef7eb2e8f9f7	59	* @{
<>	144:ef7eb2e8f9f7	60	*/
<>	144:ef7eb2e8f9f7	61	struct __ADC_HandleTypeDef;
<>	144:ef7eb2e8f9f7	62
<>	144:ef7eb2e8f9f7	63	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	64	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	65	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	66	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	67	/**
<>	144:ef7eb2e8f9f7	68	* @brief Structure definition of ADC initialization and regular group
<>	144:ef7eb2e8f9f7	69	* @note Parameters of this structure are shared within 2 scopes:
<>	144:ef7eb2e8f9f7	70	* - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, DataAlign,
<>	144:ef7eb2e8f9f7	71	* ScanConvMode, EOCSelection, LowPowerAutoWait.
<>	144:ef7eb2e8f9f7	72	* - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv, DMAContinuousRequests, Overrun.
<>	144:ef7eb2e8f9f7	73	* @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
<>	144:ef7eb2e8f9f7	74	* ADC state can be either:
<>	144:ef7eb2e8f9f7	75	* - For all parameters: ADC disabled
<>	144:ef7eb2e8f9f7	76	* - For all parameters except 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on regular group.
<>	144:ef7eb2e8f9f7	77	* - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on regular and injected groups.
<>	144:ef7eb2e8f9f7	78	* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
<>	144:ef7eb2e8f9f7	79	* without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
<>	144:ef7eb2e8f9f7	80	*/
<>	144:ef7eb2e8f9f7	81	typedef struct
<>	144:ef7eb2e8f9f7	82	{
<>	144:ef7eb2e8f9f7	83	uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from AHB clock or asynchronous clock derived from ADC dedicated PLL 72MHz) and clock prescaler.
<>	144:ef7eb2e8f9f7	84	The clock is common for all the ADCs.
<>	144:ef7eb2e8f9f7	85	This parameter can be a value of @ref ADCEx_ClockPrescaler
<>	144:ef7eb2e8f9f7	86	Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
<>	144:ef7eb2e8f9f7	87	AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
<>	144:ef7eb2e8f9f7	88	Note: In case of usage of the ADC dedicated PLL clock, this clock must be preliminarily enabled and prescaler set at RCC top level.
<>	144:ef7eb2e8f9f7	89	Note: This parameter can be modified only if all ADCs of the common ADC group are disabled (for products with several ADCs) */
<>	144:ef7eb2e8f9f7	90	uint32_t Resolution; /*!< Configures the ADC resolution.
<>	144:ef7eb2e8f9f7	91	This parameter can be a value of @ref ADCEx_Resolution */
<>	144:ef7eb2e8f9f7	92	uint32_t DataAlign; /*!< Specifies ADC data alignment to right (for resolution 12 bits: MSB on register bit 11 and LSB on register bit 0) (default setting)
<>	144:ef7eb2e8f9f7	93	or to left (for resolution 12 bits, if offset disabled: MSB on register bit 15 and LSB on register bit 4, if offset enabled: MSB on register bit 14 and LSB on register bit 3).
<>	144:ef7eb2e8f9f7	94	See reference manual for alignments with other resolutions.
<>	144:ef7eb2e8f9f7	95	This parameter can be a value of @ref ADCEx_Data_align */
<>	144:ef7eb2e8f9f7	96	uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
<>	144:ef7eb2e8f9f7	97	This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
<>	144:ef7eb2e8f9f7	98	If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
<>	144:ef7eb2e8f9f7	99	Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
<>	144:ef7eb2e8f9f7	100	If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
<>	144:ef7eb2e8f9f7	101	Scan direction is upward: from rank1 to rank 'n'.
<>	144:ef7eb2e8f9f7	102	This parameter can be a value of @ref ADCEx_Scan_mode */
<>	144:ef7eb2e8f9f7	103	uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
<>	144:ef7eb2e8f9f7	104	This parameter can be a value of @ref ADCEx_EOCSelection. */
<>	144:ef7eb2e8f9f7	105	uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: ADC conversions are performed only when necessary.
<>	144:ef7eb2e8f9f7	106	New conversion starts only when the previous conversion (for regular group) or previous sequence (for injected group) has been treated by user software.
<>	144:ef7eb2e8f9f7	107	This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications.
<>	144:ef7eb2e8f9f7	108	This parameter can be set to ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	109	Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer.
<>	144:ef7eb2e8f9f7	110	Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed
<>	144:ef7eb2e8f9f7	111	and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
<>	144:ef7eb2e8f9f7	112	uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
<>	144:ef7eb2e8f9f7	113	after the selected trigger occurred (software start or external trigger).
<>	144:ef7eb2e8f9f7	114	This parameter can be set to ENABLE or DISABLE. */
<>	144:ef7eb2e8f9f7	115	uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
<>	144:ef7eb2e8f9f7	116	To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
<>	144:ef7eb2e8f9f7	117	This parameter must be a number between Min_Data = 1 and Max_Data = 16.
<>	144:ef7eb2e8f9f7	118	Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
<>	144:ef7eb2e8f9f7	119	uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
<>	144:ef7eb2e8f9f7	120	Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
<>	144:ef7eb2e8f9f7	121	Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
<>	144:ef7eb2e8f9f7	122	This parameter can be set to ENABLE or DISABLE. */
<>	144:ef7eb2e8f9f7	123	uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
<>	144:ef7eb2e8f9f7	124	If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
<>	144:ef7eb2e8f9f7	125	This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
<>	144:ef7eb2e8f9f7	126	uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
<>	144:ef7eb2e8f9f7	127	If set to ADC_SOFTWARE_START, external triggers are disabled.
<>	144:ef7eb2e8f9f7	128	This parameter can be a value of @ref ADCEx_External_trigger_source_Regular
<>	144:ef7eb2e8f9f7	129	Caution: For devices with several ADCs, external trigger source is common to ADC common group (for example: ADC1&ADC2, ADC3&ADC4, if available) */
<>	144:ef7eb2e8f9f7	130	uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
<>	144:ef7eb2e8f9f7	131	If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
<>	144:ef7eb2e8f9f7	132	This parameter can be a value of @ref ADCEx_External_trigger_edge_Regular */
<>	144:ef7eb2e8f9f7	133	uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
<>	144:ef7eb2e8f9f7	134	or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
<>	144:ef7eb2e8f9f7	135	Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
<>	144:ef7eb2e8f9f7	136	This parameter can be set to ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	137	Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
<>	144:ef7eb2e8f9f7	138	uint32_t Overrun; /*!< Select the behaviour in case of overrun: data overwritten (default) or preserved.
<>	144:ef7eb2e8f9f7	139	This parameter is for regular group only.
<>	144:ef7eb2e8f9f7	140	This parameter can be a value of @ref ADCEx_Overrun
<>	144:ef7eb2e8f9f7	141	Note: Case of overrun set to data preserved and usage with end on conversion interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved into function HAL_ADC_ConvCpltCallback() (called before end of conversion flags clear).
<>	144:ef7eb2e8f9f7	142	Note: Error reporting in function of conversion mode:
<>	144:ef7eb2e8f9f7	143	- Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data overwritten, user can willingly not read the conversion data each time, this is not considered as an erroneous case.
<>	144:ef7eb2e8f9f7	144	- Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register, any data missed would be abnormal). */
<>	144:ef7eb2e8f9f7	145	}ADC_InitTypeDef;
<>	144:ef7eb2e8f9f7	146
<>	144:ef7eb2e8f9f7	147	/**
<>	144:ef7eb2e8f9f7	148	* @brief Structure definition of ADC channel for regular group
<>	144:ef7eb2e8f9f7	149	* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
<>	144:ef7eb2e8f9f7	150	* ADC state can be either:
<>	144:ef7eb2e8f9f7	151	* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
<>	144:ef7eb2e8f9f7	152	* - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
<>	144:ef7eb2e8f9f7	153	* - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups.
<>	144:ef7eb2e8f9f7	154	* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
<>	144:ef7eb2e8f9f7	155	* without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
<>	144:ef7eb2e8f9f7	156	*/
<>	144:ef7eb2e8f9f7	157	typedef struct
<>	144:ef7eb2e8f9f7	158	{
<>	144:ef7eb2e8f9f7	159	uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
<>	144:ef7eb2e8f9f7	160	This parameter can be a value of @ref ADCEx_channels
<>	144:ef7eb2e8f9f7	161	Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
<>	144:ef7eb2e8f9f7	162	uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
<>	144:ef7eb2e8f9f7	163	This parameter can be a value of @ref ADCEx_regular_rank
<>	144:ef7eb2e8f9f7	164	Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
<>	144:ef7eb2e8f9f7	165	uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
<>	144:ef7eb2e8f9f7	166	Unit: ADC clock cycles
<>	144:ef7eb2e8f9f7	167	Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
<>	144:ef7eb2e8f9f7	168	This parameter can be a value of @ref ADCEx_sampling_times
<>	144:ef7eb2e8f9f7	169	Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
<>	144:ef7eb2e8f9f7	170	If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
<>	144:ef7eb2e8f9f7	171	Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
<>	144:ef7eb2e8f9f7	172	sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
<>	144:ef7eb2e8f9f7	173	Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 2.2us min). */
<>	144:ef7eb2e8f9f7	174	uint32_t SingleDiff; /*!< Selection of single-ended or differential input.
<>	144:ef7eb2e8f9f7	175	In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
<>	144:ef7eb2e8f9f7	176	Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
<>	144:ef7eb2e8f9f7	177	This parameter must be a value of @ref ADCEx_SingleDifferential
<>	144:ef7eb2e8f9f7	178	Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
<>	144:ef7eb2e8f9f7	179	If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
<>	144:ef7eb2e8f9f7	180	Note: Channels 1 to 14 are available in differential mode. Channels 15, 16, 17, 18 can be used only in single-ended mode.
<>	144:ef7eb2e8f9f7	181	Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
<>	144:ef7eb2e8f9f7	182	Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
<>	144:ef7eb2e8f9f7	183	If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) */
<>	144:ef7eb2e8f9f7	184	uint32_t OffsetNumber; /*!< Selects the offset number
<>	144:ef7eb2e8f9f7	185	This parameter can be a value of @ref ADCEx_OffsetNumber
<>	144:ef7eb2e8f9f7	186	Caution: Only one channel is allowed per channel. If another channel was on this offset number, the offset will be changed to the new channel */
<>	144:ef7eb2e8f9f7	187	uint32_t Offset; /*!< Defines the offset to be subtracted from the raw converted data when convert channels.
<>	144:ef7eb2e8f9f7	188	Offset value must be a positive number.
<>	144:ef7eb2e8f9f7	189	Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
<>	144:ef7eb2e8f9f7	190	Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
<>	144:ef7eb2e8f9f7	191	}ADC_ChannelConfTypeDef;
<>	144:ef7eb2e8f9f7	192
<>	144:ef7eb2e8f9f7	193	/**
<>	144:ef7eb2e8f9f7	194	* @brief Structure definition of ADC injected group and ADC channel for injected group
<>	144:ef7eb2e8f9f7	195	* @note Parameters of this structure are shared within 2 scopes:
<>	144:ef7eb2e8f9f7	196	* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
<>	144:ef7eb2e8f9f7	197	* - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
<>	144:ef7eb2e8f9f7	198	* AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
<>	144:ef7eb2e8f9f7	199	* @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
<>	144:ef7eb2e8f9f7	200	* ADC state can be either:
<>	144:ef7eb2e8f9f7	201	* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
<>	144:ef7eb2e8f9f7	202	* - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext': ADC enabled without conversion on going on injected group.
<>	144:ef7eb2e8f9f7	203	* - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
<>	144:ef7eb2e8f9f7	204	* - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going on regular and injected groups.
<>	144:ef7eb2e8f9f7	205	* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
<>	144:ef7eb2e8f9f7	206	* without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
<>	144:ef7eb2e8f9f7	207	*/
<>	144:ef7eb2e8f9f7	208	typedef struct
<>	144:ef7eb2e8f9f7	209	{
<>	144:ef7eb2e8f9f7	210	uint32_t InjectedChannel; /*!< Configure the ADC injected channel
<>	144:ef7eb2e8f9f7	211	This parameter can be a value of @ref ADCEx_channels
<>	144:ef7eb2e8f9f7	212	Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
<>	144:ef7eb2e8f9f7	213	uint32_t InjectedRank; /*!< The rank in the regular group sequencer
<>	144:ef7eb2e8f9f7	214	This parameter must be a value of @ref ADCEx_injected_rank
<>	144:ef7eb2e8f9f7	215	Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
<>	144:ef7eb2e8f9f7	216	uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
<>	144:ef7eb2e8f9f7	217	Unit: ADC clock cycles
<>	144:ef7eb2e8f9f7	218	Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
<>	144:ef7eb2e8f9f7	219	This parameter can be a value of @ref ADCEx_sampling_times
<>	144:ef7eb2e8f9f7	220	Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
<>	144:ef7eb2e8f9f7	221	If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
<>	144:ef7eb2e8f9f7	222	Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
<>	144:ef7eb2e8f9f7	223	sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
<>	144:ef7eb2e8f9f7	224	Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 2.2us min). */
<>	144:ef7eb2e8f9f7	225	uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input.
<>	144:ef7eb2e8f9f7	226	In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
<>	144:ef7eb2e8f9f7	227	Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
<>	144:ef7eb2e8f9f7	228	This parameter must be a value of @ref ADCEx_SingleDifferential
<>	144:ef7eb2e8f9f7	229	Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
<>	144:ef7eb2e8f9f7	230	If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
<>	144:ef7eb2e8f9f7	231	Note: Channels 1 to 14 are available in differential mode. Channels 15, 16, 17, 18 can be used only in single-ended mode.
<>	144:ef7eb2e8f9f7	232	Note: When configuring a channel 'i' in differential mode, the channel 'i-1' is not usable separately.
<>	144:ef7eb2e8f9f7	233	Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
<>	144:ef7eb2e8f9f7	234	If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) */
<>	144:ef7eb2e8f9f7	235	uint32_t InjectedOffsetNumber; /*!< Selects the offset number
<>	144:ef7eb2e8f9f7	236	This parameter can be a value of @ref ADCEx_OffsetNumber
<>	144:ef7eb2e8f9f7	237	Caution: Only one channel is allowed per offset number. If another channel was on this offset number, the offset will be changed to the new channel. */
<>	144:ef7eb2e8f9f7	238	uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data.
<>	144:ef7eb2e8f9f7	239	Offset value must be a positive number.
<>	144:ef7eb2e8f9f7	240	Depending of ADC resolution selected (12, 10, 8 or 6 bits),
<>	144:ef7eb2e8f9f7	241	this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
<>	144:ef7eb2e8f9f7	242	uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
<>	144:ef7eb2e8f9f7	243	To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
<>	144:ef7eb2e8f9f7	244	This parameter must be a number between Min_Data = 1 and Max_Data = 4.
<>	144:ef7eb2e8f9f7	245	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<>	144:ef7eb2e8f9f7	246	configure a channel on injected group can impact the configuration of other channels previously set. */
<>	144:ef7eb2e8f9f7	247	uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
<>	144:ef7eb2e8f9f7	248	Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
<>	144:ef7eb2e8f9f7	249	Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
<>	144:ef7eb2e8f9f7	250	This parameter can be set to ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	251	Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
<>	144:ef7eb2e8f9f7	252	Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
<>	144:ef7eb2e8f9f7	253	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<>	144:ef7eb2e8f9f7	254	configure a channel on injected group can impact the configuration of other channels previously set. */
<>	144:ef7eb2e8f9f7	255	uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
<>	144:ef7eb2e8f9f7	256	This parameter can be set to ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	257	Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
<>	144:ef7eb2e8f9f7	258	Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
<>	144:ef7eb2e8f9f7	259	Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
<>	144:ef7eb2e8f9f7	260	To maintain JAUTO always enabled, DMA must be configured in circular mode.
<>	144:ef7eb2e8f9f7	261	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<>	144:ef7eb2e8f9f7	262	configure a channel on injected group can impact the configuration of other channels previously set. */
<>	144:ef7eb2e8f9f7	263	uint32_t QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled.
<>	144:ef7eb2e8f9f7	264	This parameter can be set to ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	265	If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
<>	144:ef7eb2e8f9f7	266	new injected context is set when queue is full, error is triggered by interruption and through function 'HAL_ADCEx_InjectedQueueOverflowCallback'.
<>	144:ef7eb2e8f9f7	267	Caution: This feature request that the sequence is fully configured before injected conversion start.
<>	144:ef7eb2e8f9f7	268	Therefore, configure channels with HAL_ADCEx_InjectedConfigChannel() as many times as value of 'InjectedNbrOfConversion' parameter.
<>	144:ef7eb2e8f9f7	269	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<>	144:ef7eb2e8f9f7	270	configure a channel on injected group can impact the configuration of other channels previously set.
<>	144:ef7eb2e8f9f7	271	Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
<>	144:ef7eb2e8f9f7	272	uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
<>	144:ef7eb2e8f9f7	273	If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
<>	144:ef7eb2e8f9f7	274	This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
<>	144:ef7eb2e8f9f7	275	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<>	144:ef7eb2e8f9f7	276	configure a channel on injected group can impact the configuration of other channels previously set. */
<>	144:ef7eb2e8f9f7	277	uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
<>	144:ef7eb2e8f9f7	278	This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
<>	144:ef7eb2e8f9f7	279	If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
<>	144:ef7eb2e8f9f7	280	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<>	144:ef7eb2e8f9f7	281	configure a channel on injected group can impact the configuration of other channels previously set. */
<>	144:ef7eb2e8f9f7	282	}ADC_InjectionConfTypeDef;
<>	144:ef7eb2e8f9f7	283
<>	144:ef7eb2e8f9f7	284	/**
<>	144:ef7eb2e8f9f7	285	* @brief ADC Injection Configuration
<>	144:ef7eb2e8f9f7	286	*/
<>	144:ef7eb2e8f9f7	287	typedef struct
<>	144:ef7eb2e8f9f7	288	{
<>	144:ef7eb2e8f9f7	289	uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each
<>	144:ef7eb2e8f9f7	290	HAL_ADCEx_InjectedConfigChannel() call to finally initialize
<>	144:ef7eb2e8f9f7	291	JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
<>	144:ef7eb2e8f9f7	292
<>	144:ef7eb2e8f9f7	293	uint32_t ChannelCount; /!< Number of channels in the injected sequence /
<>	144:ef7eb2e8f9f7	294	}ADC_InjectionConfigTypeDef;
<>	144:ef7eb2e8f9f7	295
<>	144:ef7eb2e8f9f7	296	/**
<>	144:ef7eb2e8f9f7	297	* @brief Structure definition of ADC analog watchdog
<>	144:ef7eb2e8f9f7	298	* @note The setting of these parameters with function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
<>	144:ef7eb2e8f9f7	299	* ADC state can be either: ADC disabled or ADC enabled without conversion on going on regular and injected groups.
<>	144:ef7eb2e8f9f7	300	*/
<>	144:ef7eb2e8f9f7	301	typedef struct
<>	144:ef7eb2e8f9f7	302	{
<>	144:ef7eb2e8f9f7	303	uint32_t WatchdogNumber; /*!< Selects which ADC analog watchdog to apply to the selected channel.
<>	144:ef7eb2e8f9f7	304	For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
<>	144:ef7eb2e8f9f7	305	For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
<>	144:ef7eb2e8f9f7	306	This parameter can be a value of @ref ADCEx_analog_watchdog_number. */
<>	144:ef7eb2e8f9f7	307	uint32_t WatchdogMode; /*!< For Analog Watchdog 1: Configures the ADC analog watchdog mode: single channel/overall group of channels, regular/injected group.
<>	144:ef7eb2e8f9f7	308	For Analog Watchdog 2 and 3: There is no configuration for overall group of channels as AWD1. Set value 'ADC_ANALOGWATCHDOG_NONE' to reset channels group programmed with parameter 'Channel', set any other value to not use this parameter.
<>	144:ef7eb2e8f9f7	309	This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */
<>	144:ef7eb2e8f9f7	310	uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
<>	144:ef7eb2e8f9f7	311	For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel. Only 1 channel can be monitored.
<>	144:ef7eb2e8f9f7	312	For Analog Watchdog 2 and 3: Several channels can be monitored (successive calls of HAL_ADC_AnalogWDGConfig() must be done, one for each channel.
<>	144:ef7eb2e8f9f7	313	Channels group reset can be done by setting WatchdogMode to 'ADC_ANALOGWATCHDOG_NONE').
<>	144:ef7eb2e8f9f7	314	This parameter can be a value of @ref ADCEx_channels. */
<>	144:ef7eb2e8f9f7	315	uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
<>	144:ef7eb2e8f9f7	316	This parameter can be set to ENABLE or DISABLE */
<>	144:ef7eb2e8f9f7	317	uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
<>	144:ef7eb2e8f9f7	318	Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
<>	144:ef7eb2e8f9f7	319	Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
<>	144:ef7eb2e8f9f7	320	the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
<>	144:ef7eb2e8f9f7	321	uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
<>	144:ef7eb2e8f9f7	322	Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
<>	144:ef7eb2e8f9f7	323	Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
<>	144:ef7eb2e8f9f7	324	the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */
<>	144:ef7eb2e8f9f7	325	}ADC_AnalogWDGConfTypeDef;
<>	144:ef7eb2e8f9f7	326
<>	144:ef7eb2e8f9f7	327	/**
<>	144:ef7eb2e8f9f7	328	* @brief Structure definition of ADC multimode
<>	144:ef7eb2e8f9f7	329	* @note The setting of these parameters with function HAL_ADCEx_MultiModeConfigChannel() is conditioned to ADCs state (both ADCs of the common group).
<>	144:ef7eb2e8f9f7	330	* ADC state can be either:
<>	144:ef7eb2e8f9f7	331	* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'DMAAccessMode')
<>	144:ef7eb2e8f9f7	332	* - For parameter 'DMAAccessMode': ADC enabled without conversion on going on regular group.
<>	144:ef7eb2e8f9f7	333	* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
<>	144:ef7eb2e8f9f7	334	* without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
<>	144:ef7eb2e8f9f7	335	*/
<>	144:ef7eb2e8f9f7	336	typedef struct
<>	144:ef7eb2e8f9f7	337	{
<>	144:ef7eb2e8f9f7	338	uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
<>	144:ef7eb2e8f9f7	339	This parameter can be a value of @ref ADCEx_Common_mode */
<>	144:ef7eb2e8f9f7	340	uint32_t DMAAccessMode; /*!< Configures the DMA mode for multi ADC mode:
<>	144:ef7eb2e8f9f7	341	selection whether 2 DMA channels (each ADC use its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master)
<>	144:ef7eb2e8f9f7	342	This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multimode
<>	144:ef7eb2e8f9f7	343	Caution: Limitations with multimode DMA access enabled (1 DMA channel used): In case of dual mode in high speed (more than 5Msps) or high activity of DMA by other peripherals, there is a risk of DMA overrun.
<>	144:ef7eb2e8f9f7	344	Therefore, it is recommended to disable multimode DMA access: each ADC uses its own DMA channel.
<>	144:ef7eb2e8f9f7	345	Refer to device errata sheet for more details. */
<>	144:ef7eb2e8f9f7	346	uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
<>	144:ef7eb2e8f9f7	347	This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases
<>	144:ef7eb2e8f9f7	348	Delay range depends on selected resolution: from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits
<>	144:ef7eb2e8f9f7	349	from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits */
<>	144:ef7eb2e8f9f7	350	}ADC_MultiModeTypeDef;
<>	144:ef7eb2e8f9f7	351	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	352	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	353	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	354	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	355
<>	144:ef7eb2e8f9f7	356
<>	144:ef7eb2e8f9f7	357	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
<>	144:ef7eb2e8f9f7	358	/**
<>	144:ef7eb2e8f9f7	359	* @brief Structure definition of ADC and regular group initialization
<>	144:ef7eb2e8f9f7	360	* @note Parameters of this structure are shared within 2 scopes:
<>	144:ef7eb2e8f9f7	361	* - Scope entire ADC (affects regular and injected groups): DataAlign, ScanConvMode.
<>	144:ef7eb2e8f9f7	362	* - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
<>	144:ef7eb2e8f9f7	363	* @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
<>	144:ef7eb2e8f9f7	364	* ADC can be either disabled or enabled without conversion on going on regular group.
<>	144:ef7eb2e8f9f7	365	*/
<>	144:ef7eb2e8f9f7	366	typedef struct
<>	144:ef7eb2e8f9f7	367	{
<>	144:ef7eb2e8f9f7	368	uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
<>	144:ef7eb2e8f9f7	369	or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
<>	144:ef7eb2e8f9f7	370	This parameter can be a value of @ref ADCEx_Data_align */
<>	144:ef7eb2e8f9f7	371	uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
<>	144:ef7eb2e8f9f7	372	This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
<>	144:ef7eb2e8f9f7	373	If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
<>	144:ef7eb2e8f9f7	374	Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
<>	144:ef7eb2e8f9f7	375	If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
<>	144:ef7eb2e8f9f7	376	Scan direction is upward: from rank1 to rank 'n'.
<>	144:ef7eb2e8f9f7	377	This parameter can be a value of @ref ADCEx_Scan_mode
<>	144:ef7eb2e8f9f7	378	Note: For regular group, this parameter should be enabled in conversion either by polling (HAL_ADC_Start with Discontinuous mode and NbrOfDiscConversion=1)
<>	144:ef7eb2e8f9f7	379	or by DMA (HAL_ADC_Start_DMA), but not by interruption (HAL_ADC_Start_IT): in scan mode, interruption is triggered only on the
<>	144:ef7eb2e8f9f7	380	the last conversion of the sequence. All previous conversions would be overwritten by the last one.
<>	144:ef7eb2e8f9f7	381	Injected group used with scan mode has not this constraint: each rank has its own result register, no data is overwritten. */
<>	144:ef7eb2e8f9f7	382	uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
<>	144:ef7eb2e8f9f7	383	after the selected trigger occurred (software start or external trigger).
<>	144:ef7eb2e8f9f7	384	This parameter can be set to ENABLE or DISABLE. */
<>	144:ef7eb2e8f9f7	385	uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
<>	144:ef7eb2e8f9f7	386	To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
<>	144:ef7eb2e8f9f7	387	This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
<>	144:ef7eb2e8f9f7	388	uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
<>	144:ef7eb2e8f9f7	389	Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
<>	144:ef7eb2e8f9f7	390	Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
<>	144:ef7eb2e8f9f7	391	This parameter can be set to ENABLE or DISABLE. */
<>	144:ef7eb2e8f9f7	392	uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
<>	144:ef7eb2e8f9f7	393	If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
<>	144:ef7eb2e8f9f7	394	This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
<>	144:ef7eb2e8f9f7	395	uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
<>	144:ef7eb2e8f9f7	396	If set to ADC_SOFTWARE_START, external triggers are disabled.
<>	144:ef7eb2e8f9f7	397	If set to external trigger source, triggering is on event rising edge.
<>	144:ef7eb2e8f9f7	398	This parameter can be a value of @ref ADCEx_External_trigger_source_Regular */
<>	144:ef7eb2e8f9f7	399	}ADC_InitTypeDef;
<>	144:ef7eb2e8f9f7	400
<>	144:ef7eb2e8f9f7	401	/**
<>	144:ef7eb2e8f9f7	402	* @brief Structure definition of ADC channel for regular group
<>	144:ef7eb2e8f9f7	403	* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
<>	144:ef7eb2e8f9f7	404	* ADC can be either disabled or enabled without conversion on going on regular group.
<>	144:ef7eb2e8f9f7	405	*/
<>	144:ef7eb2e8f9f7	406	typedef struct
<>	144:ef7eb2e8f9f7	407	{
<>	144:ef7eb2e8f9f7	408	uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
<>	144:ef7eb2e8f9f7	409	This parameter can be a value of @ref ADCEx_channels
<>	144:ef7eb2e8f9f7	410	Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
<>	144:ef7eb2e8f9f7	411	uint32_t Rank; /*!< Specifies the rank in the regular group sequencer
<>	144:ef7eb2e8f9f7	412	This parameter can be a value of @ref ADCEx_regular_rank
<>	144:ef7eb2e8f9f7	413	Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
<>	144:ef7eb2e8f9f7	414	uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
<>	144:ef7eb2e8f9f7	415	Unit: ADC clock cycles
<>	144:ef7eb2e8f9f7	416	Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
<>	144:ef7eb2e8f9f7	417	This parameter can be a value of @ref ADCEx_sampling_times
<>	144:ef7eb2e8f9f7	418	Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
<>	144:ef7eb2e8f9f7	419	If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
<>	144:ef7eb2e8f9f7	420	Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
<>	144:ef7eb2e8f9f7	421	sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
<>	144:ef7eb2e8f9f7	422	Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17.1us min). */
<>	144:ef7eb2e8f9f7	423	}ADC_ChannelConfTypeDef;
<>	144:ef7eb2e8f9f7	424
<>	144:ef7eb2e8f9f7	425	/**
<>	144:ef7eb2e8f9f7	426	* @brief ADC Configuration injected Channel structure definition
<>	144:ef7eb2e8f9f7	427	* @note Parameters of this structure are shared within 2 scopes:
<>	144:ef7eb2e8f9f7	428	* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
<>	144:ef7eb2e8f9f7	429	* - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
<>	144:ef7eb2e8f9f7	430	* AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
<>	144:ef7eb2e8f9f7	431	* @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
<>	144:ef7eb2e8f9f7	432	* ADC state can be either:
<>	144:ef7eb2e8f9f7	433	* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'ExternalTrigInjecConv')
<>	144:ef7eb2e8f9f7	434	* - For all except parameters 'ExternalTrigInjecConv': ADC enabled without conversion on going on injected group.
<>	144:ef7eb2e8f9f7	435	*/
<>	144:ef7eb2e8f9f7	436	typedef struct
<>	144:ef7eb2e8f9f7	437	{
<>	144:ef7eb2e8f9f7	438	uint32_t InjectedChannel; /*!< Selection of ADC channel to configure
<>	144:ef7eb2e8f9f7	439	This parameter can be a value of @ref ADCEx_channels
<>	144:ef7eb2e8f9f7	440	Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
<>	144:ef7eb2e8f9f7	441	uint32_t InjectedRank; /*!< Rank in the injected group sequencer
<>	144:ef7eb2e8f9f7	442	This parameter must be a value of @ref ADCEx_injected_rank
<>	144:ef7eb2e8f9f7	443	Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
<>	144:ef7eb2e8f9f7	444	uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
<>	144:ef7eb2e8f9f7	445	Unit: ADC clock cycles
<>	144:ef7eb2e8f9f7	446	Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits).
<>	144:ef7eb2e8f9f7	447	This parameter can be a value of @ref ADCEx_sampling_times
<>	144:ef7eb2e8f9f7	448	Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
<>	144:ef7eb2e8f9f7	449	If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
<>	144:ef7eb2e8f9f7	450	Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
<>	144:ef7eb2e8f9f7	451	sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
<>	144:ef7eb2e8f9f7	452	Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: 5us to 17.1us min). */
<>	144:ef7eb2e8f9f7	453	uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
<>	144:ef7eb2e8f9f7	454	Offset value must be a positive number.
<>	144:ef7eb2e8f9f7	455	Depending of ADC resolution selected (12, 10, 8 or 6 bits),
<>	144:ef7eb2e8f9f7	456	this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
<>	144:ef7eb2e8f9f7	457	uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
<>	144:ef7eb2e8f9f7	458	To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
<>	144:ef7eb2e8f9f7	459	This parameter must be a number between Min_Data = 1 and Max_Data = 4.
<>	144:ef7eb2e8f9f7	460	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<>	144:ef7eb2e8f9f7	461	configure a channel on injected group can impact the configuration of other channels previously set. */
<>	144:ef7eb2e8f9f7	462	uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
<>	144:ef7eb2e8f9f7	463	Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
<>	144:ef7eb2e8f9f7	464	Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
<>	144:ef7eb2e8f9f7	465	This parameter can be set to ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	466	Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
<>	144:ef7eb2e8f9f7	467	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<>	144:ef7eb2e8f9f7	468	configure a channel on injected group can impact the configuration of other channels previously set. */
<>	144:ef7eb2e8f9f7	469	uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
<>	144:ef7eb2e8f9f7	470	This parameter can be set to ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	471	Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
<>	144:ef7eb2e8f9f7	472	Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
<>	144:ef7eb2e8f9f7	473	Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
<>	144:ef7eb2e8f9f7	474	To maintain JAUTO always enabled, DMA must be configured in circular mode.
<>	144:ef7eb2e8f9f7	475	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<>	144:ef7eb2e8f9f7	476	configure a channel on injected group can impact the configuration of other channels previously set. */
<>	144:ef7eb2e8f9f7	477	uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
<>	144:ef7eb2e8f9f7	478	If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
<>	144:ef7eb2e8f9f7	479	If set to external trigger source, triggering is on event rising edge.
<>	144:ef7eb2e8f9f7	480	This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
<>	144:ef7eb2e8f9f7	481	Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
<>	144:ef7eb2e8f9f7	482	If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
<>	144:ef7eb2e8f9f7	483	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<>	144:ef7eb2e8f9f7	484	configure a channel on injected group can impact the configuration of other channels previously set. */
<>	144:ef7eb2e8f9f7	485	}ADC_InjectionConfTypeDef;
<>	144:ef7eb2e8f9f7	486
<>	144:ef7eb2e8f9f7	487	/**
<>	144:ef7eb2e8f9f7	488	* @brief ADC Configuration analog watchdog definition
<>	144:ef7eb2e8f9f7	489	* @note The setting of these parameters with function is conditioned to ADC state.
<>	144:ef7eb2e8f9f7	490	* ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
<>	144:ef7eb2e8f9f7	491	*/
<>	144:ef7eb2e8f9f7	492	typedef struct
<>	144:ef7eb2e8f9f7	493	{
<>	144:ef7eb2e8f9f7	494	uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
<>	144:ef7eb2e8f9f7	495	This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */
<>	144:ef7eb2e8f9f7	496	uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
<>	144:ef7eb2e8f9f7	497	This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
<>	144:ef7eb2e8f9f7	498	This parameter can be a value of @ref ADCEx_channels. */
<>	144:ef7eb2e8f9f7	499	uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
<>	144:ef7eb2e8f9f7	500	This parameter can be set to ENABLE or DISABLE */
<>	144:ef7eb2e8f9f7	501	uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
<>	144:ef7eb2e8f9f7	502	This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
<>	144:ef7eb2e8f9f7	503	uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
<>	144:ef7eb2e8f9f7	504	This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
<>	144:ef7eb2e8f9f7	505	uint32_t WatchdogNumber; /!< Reserved for future use, can be set to 0 /
<>	144:ef7eb2e8f9f7	506	}ADC_AnalogWDGConfTypeDef;
<>	144:ef7eb2e8f9f7	507	#endif /* STM32F373xC \|\| STM32F378xx */
<>	144:ef7eb2e8f9f7	508	/**
<>	144:ef7eb2e8f9f7	509	* @}
<>	144:ef7eb2e8f9f7	510	*/
<>	144:ef7eb2e8f9f7	511
<>	144:ef7eb2e8f9f7	512	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	513
<>	144:ef7eb2e8f9f7	514	/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
<>	144:ef7eb2e8f9f7	515	* @{
<>	144:ef7eb2e8f9f7	516	*/
<>	144:ef7eb2e8f9f7	517
<>	144:ef7eb2e8f9f7	518	/** @defgroup ADCEx_Error_Code ADC Extended Error Code
<>	144:ef7eb2e8f9f7	519	* @{
<>	144:ef7eb2e8f9f7	520	*/
<>	144:ef7eb2e8f9f7	521	#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /!< No error /
<>	144:ef7eb2e8f9f7	522	#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
<>	144:ef7eb2e8f9f7	523	enable/disable, erroneous state */
<>	144:ef7eb2e8f9f7	524	#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /!< Overrun error /
<>	144:ef7eb2e8f9f7	525	#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /!< DMA transfer error /
<>	144:ef7eb2e8f9f7	526	#define HAL_ADC_ERROR_JQOVF ((uint32_t)0x08) /!< Injected context queue overflow error /
<>	144:ef7eb2e8f9f7	527	/**
<>	144:ef7eb2e8f9f7	528	* @}
<>	144:ef7eb2e8f9f7	529	*/
<>	144:ef7eb2e8f9f7	530
<>	144:ef7eb2e8f9f7	531	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	532	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	533	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	534	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	535	/** @defgroup ADCEx_ClockPrescaler ADC Extended Clock Prescaler
<>	144:ef7eb2e8f9f7	536	* @{
<>	144:ef7eb2e8f9f7	537	*/
<>	144:ef7eb2e8f9f7	538	#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /!< ADC asynchronous clock derived from ADC dedicated PLL /
<>	144:ef7eb2e8f9f7	539
<>	144:ef7eb2e8f9f7	540	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	541	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	542	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
<>	144:ef7eb2e8f9f7	543	#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC12_CCR_CKMODE_0) /!< ADC synchronous clock derived from AHB clock without prescaler /
<>	144:ef7eb2e8f9f7	544	#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC12_CCR_CKMODE_1) /!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 /
<>	144:ef7eb2e8f9f7	545	#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC12_CCR_CKMODE) /!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 /
<>	144:ef7eb2e8f9f7	546	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	547	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	548	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
<>	144:ef7eb2e8f9f7	549
<>	144:ef7eb2e8f9f7	550	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	551	#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC1_CCR_CKMODE_0) /!< ADC synchronous clock derived from AHB clock without prescaler /
<>	144:ef7eb2e8f9f7	552	#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC1_CCR_CKMODE_1) /!< ADC synchronous clock derived from AHB clock divided by a prescaler of 2 /
<>	144:ef7eb2e8f9f7	553	#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC1_CCR_CKMODE) /!< ADC synchronous clock derived from AHB clock divided by a prescaler of 4 /
<>	144:ef7eb2e8f9f7	554	#endif /* STM32F301x8 \|\| STM32F318xx \|\| STM32F302x8 */
<>	144:ef7eb2e8f9f7	555
<>	144:ef7eb2e8f9f7	556	#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) \|\| \
<>	144:ef7eb2e8f9f7	557	((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) \|\| \
<>	144:ef7eb2e8f9f7	558	((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	559	((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) )
<>	144:ef7eb2e8f9f7	560	/**
<>	144:ef7eb2e8f9f7	561	* @}
<>	144:ef7eb2e8f9f7	562	*/
<>	144:ef7eb2e8f9f7	563
<>	144:ef7eb2e8f9f7	564	/** @defgroup ADCEx_Resolution ADC Extended Resolution
<>	144:ef7eb2e8f9f7	565	* @{
<>	144:ef7eb2e8f9f7	566	*/
<>	144:ef7eb2e8f9f7	567	#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /!< ADC 12-bit resolution /
<>	144:ef7eb2e8f9f7	568	#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR_RES_0) /!< ADC 10-bit resolution /
<>	144:ef7eb2e8f9f7	569	#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR_RES_1) /!< ADC 8-bit resolution /
<>	144:ef7eb2e8f9f7	570	#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR_RES) /!< ADC 6-bit resolution /
<>	144:ef7eb2e8f9f7	571	/**
<>	144:ef7eb2e8f9f7	572	* @}
<>	144:ef7eb2e8f9f7	573	*/
<>	144:ef7eb2e8f9f7	574
<>	144:ef7eb2e8f9f7	575	/** @defgroup ADCEx_Data_align ADC Extended Data Alignment
<>	144:ef7eb2e8f9f7	576	* @{
<>	144:ef7eb2e8f9f7	577	*/
<>	144:ef7eb2e8f9f7	578	#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	579	#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR_ALIGN)
<>	144:ef7eb2e8f9f7	580	/**
<>	144:ef7eb2e8f9f7	581	* @}
<>	144:ef7eb2e8f9f7	582	*/
<>	144:ef7eb2e8f9f7	583
<>	144:ef7eb2e8f9f7	584	/** @defgroup ADCEx_Scan_mode ADC Extended Scan Mode
<>	144:ef7eb2e8f9f7	585	* @{
<>	144:ef7eb2e8f9f7	586	*/
<>	144:ef7eb2e8f9f7	587	#define ADC_SCAN_DISABLE ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	588	#define ADC_SCAN_ENABLE ((uint32_t)0x00000001)
<>	144:ef7eb2e8f9f7	589	/**
<>	144:ef7eb2e8f9f7	590	* @}
<>	144:ef7eb2e8f9f7	591	*/
<>	144:ef7eb2e8f9f7	592
<>	144:ef7eb2e8f9f7	593	/** @defgroup ADCEx_External_trigger_edge_Regular ADC Extended External trigger enable and polarity selection for regular group
<>	144:ef7eb2e8f9f7	594	* @{
<>	144:ef7eb2e8f9f7	595	*/
<>	144:ef7eb2e8f9f7	596	#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	597	#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR_EXTEN_0)
<>	144:ef7eb2e8f9f7	598	#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR_EXTEN_1)
<>	144:ef7eb2e8f9f7	599	#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR_EXTEN)
<>	144:ef7eb2e8f9f7	600	/**
<>	144:ef7eb2e8f9f7	601	* @}
<>	144:ef7eb2e8f9f7	602	*/
<>	144:ef7eb2e8f9f7	603
<>	144:ef7eb2e8f9f7	604	/** @defgroup ADCEx_External_trigger_source_Regular ADC Extended External trigger selection for regular group
<>	144:ef7eb2e8f9f7	605	* @{
<>	144:ef7eb2e8f9f7	606	*/
<>	144:ef7eb2e8f9f7	607	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	608	defined(STM32F303xC) \|\| defined(STM32F358xx)
<>	144:ef7eb2e8f9f7	609	/!< List of external triggers with generic trigger name, independently of /
<>	144:ef7eb2e8f9f7	610	/* ADC target (caution: applies to other ADCs sharing the same common group), */
<>	144:ef7eb2e8f9f7	611	/* sorted by trigger name: */
<>	144:ef7eb2e8f9f7	612
<>	144:ef7eb2e8f9f7	613	/!< External triggers of regular group for ADC1&ADC2 only /
<>	144:ef7eb2e8f9f7	614	#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
<>	144:ef7eb2e8f9f7	615	#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
<>	144:ef7eb2e8f9f7	616	#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
<>	144:ef7eb2e8f9f7	617	#define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4
<>	144:ef7eb2e8f9f7	618	#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4
<>	144:ef7eb2e8f9f7	619	#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO
<>	144:ef7eb2e8f9f7	620	#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
<>	144:ef7eb2e8f9f7	621
<>	144:ef7eb2e8f9f7	622	/!< External triggers of regular group for ADC3&ADC4 only /
<>	144:ef7eb2e8f9f7	623	#define ADC_EXTERNALTRIGCONV_T2_CC1 ADC3_4_EXTERNALTRIG_T2_CC1
<>	144:ef7eb2e8f9f7	624	#define ADC_EXTERNALTRIGCONV_T2_CC3 ADC3_4_EXTERNALTRIG_T2_CC3
<>	144:ef7eb2e8f9f7	625	#define ADC_EXTERNALTRIGCONV_T3_CC1 ADC3_4_EXTERNALTRIG_T3_CC1
<>	144:ef7eb2e8f9f7	626	#define ADC_EXTERNALTRIGCONV_T4_CC1 ADC3_4_EXTERNALTRIG_T4_CC1
<>	144:ef7eb2e8f9f7	627	#define ADC_EXTERNALTRIGCONV_T7_TRGO ADC3_4_EXTERNALTRIG_T7_TRGO
<>	144:ef7eb2e8f9f7	628	#define ADC_EXTERNALTRIGCONV_T8_CC1 ADC3_4_EXTERNALTRIG_T8_CC1
<>	144:ef7eb2e8f9f7	629	#define ADC_EXTERNALTRIGCONV_EXT_IT2 ADC3_4_EXTERNALTRIG_EXT_IT2
<>	144:ef7eb2e8f9f7	630
<>	144:ef7eb2e8f9f7	631	/!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4 /
<>	144:ef7eb2e8f9f7	632	/* Note: Triggers affected to group ADC1_2 by default, redirected to group */
<>	144:ef7eb2e8f9f7	633	/* ADC3_4 by driver when needed. */
<>	144:ef7eb2e8f9f7	634	#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3
<>	144:ef7eb2e8f9f7	635	#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO
<>	144:ef7eb2e8f9f7	636	#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2
<>	144:ef7eb2e8f9f7	637	#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO
<>	144:ef7eb2e8f9f7	638	#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
<>	144:ef7eb2e8f9f7	639	#define ADC_EXTERNALTRIGCONV_T4_TRGO ADC1_2_EXTERNALTRIG_T4_TRGO
<>	144:ef7eb2e8f9f7	640	#define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO
<>	144:ef7eb2e8f9f7	641	#define ADC_EXTERNALTRIGCONV_T8_TRGO2 ADC1_2_EXTERNALTRIG_T8_TRGO2
<>	144:ef7eb2e8f9f7	642	#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
<>	144:ef7eb2e8f9f7	643
<>	144:ef7eb2e8f9f7	644	#define ADC_SOFTWARE_START ((uint32_t)0x00000001)
<>	144:ef7eb2e8f9f7	645
<>	144:ef7eb2e8f9f7	646	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
<>	144:ef7eb2e8f9f7	647	/* ADC external triggers specific to device STM303xE: mask to differentiate */
<>	144:ef7eb2e8f9f7	648	/* standard triggers from specific timer 20, needed for reallocation of */
<>	144:ef7eb2e8f9f7	649	/* triggers common to ADC1&2/ADC3&4 and to avoid mixing with standard */
<>	144:ef7eb2e8f9f7	650	/* triggers without remap. */
<>	144:ef7eb2e8f9f7	651	#define ADC_EXTERNALTRIGCONV_T20_MASK 0x1000
<>	144:ef7eb2e8f9f7	652
<>	144:ef7eb2e8f9f7	653	/!< List of external triggers specific to device STM303xE: using Timer20 /
<>	144:ef7eb2e8f9f7	654	/* with ADC trigger input remap. */
<>	144:ef7eb2e8f9f7	655	/* To remap ADC trigger from other timers/ExtLine to timer20: use macro */
<>	144:ef7eb2e8f9f7	656	/* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */
<>	144:ef7eb2e8f9f7	657
<>	144:ef7eb2e8f9f7	658	/!< External triggers of regular group for ADC1&ADC2 only, specific to /
<>	144:ef7eb2e8f9f7	659	/* device STM303xE: : using Timer20 with ADC trigger input remap */
<>	144:ef7eb2e8f9f7	660	#define ADC_EXTERNALTRIGCONV_T20_CC2 ADC_EXTERNALTRIGCONV_T6_TRGO /!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT13) /
<>	144:ef7eb2e8f9f7	661	#define ADC_EXTERNALTRIGCONV_T20_CC3 ADC_EXTERNALTRIGCONV_T3_CC4 /!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT15) /
<>	144:ef7eb2e8f9f7	662
<>	144:ef7eb2e8f9f7	663	/!< External triggers of regular group for ADC3&ADC4 only, specific to /
<>	144:ef7eb2e8f9f7	664	/* device STM303xE: : using Timer20 with ADC trigger input remap */
<>	144:ef7eb2e8f9f7	665	/* None */
<>	144:ef7eb2e8f9f7	666
<>	144:ef7eb2e8f9f7	667	/!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4, specific to /
<>	144:ef7eb2e8f9f7	668	/* device STM303xE: : using Timer20 with ADC trigger input remap */
<>	144:ef7eb2e8f9f7	669	/* Note: Triggers affected to group ADC1_2 by default, redirected to group */
<>	144:ef7eb2e8f9f7	670	/* ADC3_4 by driver when needed. */
<>	144:ef7eb2e8f9f7	671	#define ADC_EXTERNALTRIGCONV_T20_CC1 (ADC_EXTERNALTRIGCONV_T4_CC4 \| ADC_EXTERNALTRIGCONV_T20_MASK) /!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT5) /
<>	144:ef7eb2e8f9f7	672	/!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT15) /
<>	144:ef7eb2e8f9f7	673	#define ADC_EXTERNALTRIGCONV_T20_TRGO (ADC_EXTERNALTRIGCONV_T1_CC3 \| ADC_EXTERNALTRIGCONV_T20_MASK) /!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT2) /
<>	144:ef7eb2e8f9f7	674	/!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT5) /
<>	144:ef7eb2e8f9f7	675	#define ADC_EXTERNALTRIGCONV_T20_TRGO2 (ADC_EXTERNALTRIGCONV_T2_CC2 \| ADC_EXTERNALTRIGCONV_T20_MASK) /!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT3) /
<>	144:ef7eb2e8f9f7	676	/!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_EXT6) /
<>	144:ef7eb2e8f9f7	677	#endif /* STM32F303xE \|\| STM32F398xx */
<>	144:ef7eb2e8f9f7	678
<>	144:ef7eb2e8f9f7	679	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	680	/* STM32F303xC \|\| STM32F358xx */
<>	144:ef7eb2e8f9f7	681
<>	144:ef7eb2e8f9f7	682	#if defined(STM32F302xE) \|\| \
<>	144:ef7eb2e8f9f7	683	defined(STM32F302xC)
<>	144:ef7eb2e8f9f7	684	/!< List of external triggers with generic trigger name, independently of /
<>	144:ef7eb2e8f9f7	685	/* ADC target (caution: applies to other ADCs sharing the same common group), */
<>	144:ef7eb2e8f9f7	686	/* sorted by trigger name: */
<>	144:ef7eb2e8f9f7	687
<>	144:ef7eb2e8f9f7	688	/!< External triggers of regular group for ADC1&ADC2 /
<>	144:ef7eb2e8f9f7	689	#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
<>	144:ef7eb2e8f9f7	690	#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
<>	144:ef7eb2e8f9f7	691	#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3
<>	144:ef7eb2e8f9f7	692	#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO
<>	144:ef7eb2e8f9f7	693	#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2
<>	144:ef7eb2e8f9f7	694	#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
<>	144:ef7eb2e8f9f7	695	#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO
<>	144:ef7eb2e8f9f7	696	#define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4
<>	144:ef7eb2e8f9f7	697	#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
<>	144:ef7eb2e8f9f7	698	#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4
<>	144:ef7eb2e8f9f7	699	#define ADC_EXTERNALTRIGCONV_T4_TRGO ADC1_2_EXTERNALTRIG_T4_TRGO
<>	144:ef7eb2e8f9f7	700	#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO
<>	144:ef7eb2e8f9f7	701	#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
<>	144:ef7eb2e8f9f7	702	#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
<>	144:ef7eb2e8f9f7	703	#define ADC_SOFTWARE_START ((uint32_t)0x00000001)
<>	144:ef7eb2e8f9f7	704
<>	144:ef7eb2e8f9f7	705	#if defined(STM32F302xE)
<>	144:ef7eb2e8f9f7	706	/* ADC external triggers specific to device STM302xE: mask to differentiate */
<>	144:ef7eb2e8f9f7	707	/* standard triggers from specific timer 20, needed for reallocation of */
<>	144:ef7eb2e8f9f7	708	/* triggers common to ADC1&2 and to avoind mixing with standard */
<>	144:ef7eb2e8f9f7	709	/* triggers without remap. */
<>	144:ef7eb2e8f9f7	710	#define ADC_EXTERNALTRIGCONV_T20_MASK 0x1000
<>	144:ef7eb2e8f9f7	711
<>	144:ef7eb2e8f9f7	712	/!< List of external triggers specific to device STM302xE: using Timer20 /
<>	144:ef7eb2e8f9f7	713	/* with ADC trigger input remap. */
<>	144:ef7eb2e8f9f7	714	/* To remap ADC trigger from other timers/ExtLine to timer20: use macro */
<>	144:ef7eb2e8f9f7	715	/* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */
<>	144:ef7eb2e8f9f7	716
<>	144:ef7eb2e8f9f7	717	/!< External triggers of regular group for ADC1&ADC2 only, specific to /
<>	144:ef7eb2e8f9f7	718	/* device STM302xE: : using Timer20 with ADC trigger input remap */
<>	144:ef7eb2e8f9f7	719	#define ADC_EXTERNALTRIGCONV_T20_CC2 ADC_EXTERNALTRIGCONV_T6_TRGO /!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT13) /
<>	144:ef7eb2e8f9f7	720	#define ADC_EXTERNALTRIGCONV_T20_CC3 ADC_EXTERNALTRIGCONV_T3_CC4 /!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_EXT15) /
<>	144:ef7eb2e8f9f7	721	#endif /* STM32F302xE */
<>	144:ef7eb2e8f9f7	722
<>	144:ef7eb2e8f9f7	723	#endif /* STM32F302xE \|\| */
<>	144:ef7eb2e8f9f7	724	/* STM32F302xC */
<>	144:ef7eb2e8f9f7	725
<>	144:ef7eb2e8f9f7	726	#if defined(STM32F303x8) \|\| defined(STM32F328xx)
<>	144:ef7eb2e8f9f7	727	/!< List of external triggers with generic trigger name, independently of /
<>	144:ef7eb2e8f9f7	728	/* ADC target (caution: applies to other ADCs sharing the same common group), */
<>	144:ef7eb2e8f9f7	729	/* sorted by trigger name: */
<>	144:ef7eb2e8f9f7	730
<>	144:ef7eb2e8f9f7	731	/!< External triggers of regular group for ADC1&ADC2 /
<>	144:ef7eb2e8f9f7	732	#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
<>	144:ef7eb2e8f9f7	733	#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
<>	144:ef7eb2e8f9f7	734	#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3
<>	144:ef7eb2e8f9f7	735	#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO
<>	144:ef7eb2e8f9f7	736	#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2
<>	144:ef7eb2e8f9f7	737	#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
<>	144:ef7eb2e8f9f7	738	#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO
<>	144:ef7eb2e8f9f7	739	#define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4
<>	144:ef7eb2e8f9f7	740	#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
<>	144:ef7eb2e8f9f7	741	#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC1_2_EXTERNALTRIG_T4_CC4
<>	144:ef7eb2e8f9f7	742	#define ADC_EXTERNALTRIGCONV_T4_TRGO ADC1_2_EXTERNALTRIG_T4_TRGO
<>	144:ef7eb2e8f9f7	743	#define ADC_EXTERNALTRIGCONV_T8_TRGO ADC1_2_EXTERNALTRIG_T8_TRGO
<>	144:ef7eb2e8f9f7	744	#define ADC_EXTERNALTRIGCONV_T8_TRGO2 ADC1_2_EXTERNALTRIG_T8_TRGO2
<>	144:ef7eb2e8f9f7	745	#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO
<>	144:ef7eb2e8f9f7	746	#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
<>	144:ef7eb2e8f9f7	747	#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
<>	144:ef7eb2e8f9f7	748	#define ADC_SOFTWARE_START ((uint32_t)0x00000001)
<>	144:ef7eb2e8f9f7	749
<>	144:ef7eb2e8f9f7	750	#endif /* STM32F303x8 \|\| STM32F328xx */
<>	144:ef7eb2e8f9f7	751
<>	144:ef7eb2e8f9f7	752	#if defined(STM32F334x8)
<>	144:ef7eb2e8f9f7	753	/!< List of external triggers with generic trigger name, independently of /
<>	144:ef7eb2e8f9f7	754	/* ADC target (caution: applies to other ADCs sharing the same common group), */
<>	144:ef7eb2e8f9f7	755	/* sorted by trigger name: */
<>	144:ef7eb2e8f9f7	756
<>	144:ef7eb2e8f9f7	757	/!< External triggers of regular group for ADC1&ADC2 /
<>	144:ef7eb2e8f9f7	758	#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_2_EXTERNALTRIG_T1_CC1
<>	144:ef7eb2e8f9f7	759	#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_2_EXTERNALTRIG_T1_CC2
<>	144:ef7eb2e8f9f7	760	#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_2_EXTERNALTRIG_T1_CC3
<>	144:ef7eb2e8f9f7	761	#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_2_EXTERNALTRIG_T1_TRGO
<>	144:ef7eb2e8f9f7	762	#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_2_EXTERNALTRIG_T1_TRGO2
<>	144:ef7eb2e8f9f7	763	#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC1_2_EXTERNALTRIG_T2_CC2
<>	144:ef7eb2e8f9f7	764	#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_2_EXTERNALTRIG_T2_TRGO
<>	144:ef7eb2e8f9f7	765	#define ADC_EXTERNALTRIGCONV_T3_CC4 ADC1_2_EXTERNALTRIG_T3_CC4
<>	144:ef7eb2e8f9f7	766	#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC1_2_EXTERNALTRIG_T3_TRGO
<>	144:ef7eb2e8f9f7	767	#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_2_EXTERNALTRIG_T6_TRGO
<>	144:ef7eb2e8f9f7	768	#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_2_EXTERNALTRIG_T15_TRGO
<>	144:ef7eb2e8f9f7	769	#define ADC_EXTERNALTRIGCONVHRTIM_TRG1 ADC1_2_EXTERNALTRIG_HRTIM_TRG1
<>	144:ef7eb2e8f9f7	770	#define ADC_EXTERNALTRIGCONVHRTIM_TRG3 ADC1_2_EXTERNALTRIG_HRTIM_TRG3
<>	144:ef7eb2e8f9f7	771	#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_2_EXTERNALTRIG_EXT_IT11
<>	144:ef7eb2e8f9f7	772	#define ADC_SOFTWARE_START ((uint32_t)0x00000001)
<>	144:ef7eb2e8f9f7	773	#endif /* STM32F334x8 */
<>	144:ef7eb2e8f9f7	774
<>	144:ef7eb2e8f9f7	775	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	776	/* List of external triggers with generic trigger name, sorted by trigger */
<>	144:ef7eb2e8f9f7	777	/* name: */
<>	144:ef7eb2e8f9f7	778
<>	144:ef7eb2e8f9f7	779	/* External triggers of regular group for ADC1 */
<>	144:ef7eb2e8f9f7	780	#define ADC_EXTERNALTRIGCONV_T1_CC1 ADC1_EXTERNALTRIG_T1_CC1
<>	144:ef7eb2e8f9f7	781	#define ADC_EXTERNALTRIGCONV_T1_CC2 ADC1_EXTERNALTRIG_T1_CC2
<>	144:ef7eb2e8f9f7	782	#define ADC_EXTERNALTRIGCONV_T1_CC3 ADC1_EXTERNALTRIG_T1_CC3
<>	144:ef7eb2e8f9f7	783	#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC1_EXTERNALTRIG_EXT_IT11
<>	144:ef7eb2e8f9f7	784	#define ADC_EXTERNALTRIGCONV_T1_TRGO ADC1_EXTERNALTRIG_T1_TRGO
<>	144:ef7eb2e8f9f7	785	#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ADC1_EXTERNALTRIG_T1_TRGO2
<>	144:ef7eb2e8f9f7	786	#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC1_EXTERNALTRIG_T2_TRGO
<>	144:ef7eb2e8f9f7	787	#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC1_EXTERNALTRIG_T6_TRGO
<>	144:ef7eb2e8f9f7	788	#define ADC_EXTERNALTRIGCONV_T15_TRGO ADC1_EXTERNALTRIG_T15_TRGO
<>	144:ef7eb2e8f9f7	789	#define ADC_SOFTWARE_START ((uint32_t)0x00000001)
<>	144:ef7eb2e8f9f7	790	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	791	/**
<>	144:ef7eb2e8f9f7	792	* @}
<>	144:ef7eb2e8f9f7	793	*/
<>	144:ef7eb2e8f9f7	794
<>	144:ef7eb2e8f9f7	795	/** @defgroup ADCEx_EOCSelection ADC Extended End of Regular Sequence/Conversion
<>	144:ef7eb2e8f9f7	796	* @{
<>	144:ef7eb2e8f9f7	797	*/
<>	144:ef7eb2e8f9f7	798	#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
<>	144:ef7eb2e8f9f7	799	#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
<>	144:ef7eb2e8f9f7	800	#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC \| ADC_ISR_EOS)) /!< reserved for future use /
<>	144:ef7eb2e8f9f7	801	/**
<>	144:ef7eb2e8f9f7	802	* @}
<>	144:ef7eb2e8f9f7	803	*/
<>	144:ef7eb2e8f9f7	804
<>	144:ef7eb2e8f9f7	805	/** @defgroup ADCEx_Overrun ADC Extended overrun
<>	144:ef7eb2e8f9f7	806	* @{
<>	144:ef7eb2e8f9f7	807	*/
<>	144:ef7eb2e8f9f7	808	#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)0x00000000) /!< Default setting, to be used for compatibility with other STM32 devices /
<>	144:ef7eb2e8f9f7	809	#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000001)
<>	144:ef7eb2e8f9f7	810	/**
<>	144:ef7eb2e8f9f7	811	* @}
<>	144:ef7eb2e8f9f7	812	*/
<>	144:ef7eb2e8f9f7	813
<>	144:ef7eb2e8f9f7	814	/** @defgroup ADCEx_channels ADC Extended Channels
<>	144:ef7eb2e8f9f7	815	* @{
<>	144:ef7eb2e8f9f7	816	*/
<>	144:ef7eb2e8f9f7	817	/* Note: Depending on devices, some channels may not be available on package */
<>	144:ef7eb2e8f9f7	818	/* pins. Refer to device datasheet for channels availability. */
<>	144:ef7eb2e8f9f7	819	#define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ10_0))
<>	144:ef7eb2e8f9f7	820	#define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ10_1))
<>	144:ef7eb2e8f9f7	821	#define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ10_1 \| ADC_SQR3_SQ10_0))
<>	144:ef7eb2e8f9f7	822	#define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ10_2))
<>	144:ef7eb2e8f9f7	823	#define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ10_2 \| ADC_SQR3_SQ10_0))
<>	144:ef7eb2e8f9f7	824	#define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ10_2 \| ADC_SQR3_SQ10_1))
<>	144:ef7eb2e8f9f7	825	#define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ10_2 \| ADC_SQR3_SQ10_1 \| ADC_SQR3_SQ10_0))
<>	144:ef7eb2e8f9f7	826	#define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ10_3))
<>	144:ef7eb2e8f9f7	827	#define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ10_3 \| ADC_SQR3_SQ10_0))
<>	144:ef7eb2e8f9f7	828	#define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ10_3 \| ADC_SQR3_SQ10_1))
<>	144:ef7eb2e8f9f7	829	#define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ10_3 \| ADC_SQR3_SQ10_1 \| ADC_SQR3_SQ10_0))
<>	144:ef7eb2e8f9f7	830	#define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ10_3 \| ADC_SQR3_SQ10_2))
<>	144:ef7eb2e8f9f7	831	#define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ10_3 \| ADC_SQR3_SQ10_2 \| ADC_SQR3_SQ10_0))
<>	144:ef7eb2e8f9f7	832	#define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ10_3 \| ADC_SQR3_SQ10_2 \| ADC_SQR3_SQ10_1))
<>	144:ef7eb2e8f9f7	833	#define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ10_3 \| ADC_SQR3_SQ10_2 \| ADC_SQR3_SQ10_1 \| ADC_SQR3_SQ10_0))
<>	144:ef7eb2e8f9f7	834	#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ10_4))
<>	144:ef7eb2e8f9f7	835	#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ10_4 \| ADC_SQR3_SQ10_0))
<>	144:ef7eb2e8f9f7	836	#define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ10_4 \| ADC_SQR3_SQ10_1))
<>	144:ef7eb2e8f9f7	837
<>	144:ef7eb2e8f9f7	838	/* Note: Vopamp1, TempSensor and Vbat internal channels available on ADC1 only */
<>	144:ef7eb2e8f9f7	839	#define ADC_CHANNEL_VOPAMP1 ADC_CHANNEL_15
<>	144:ef7eb2e8f9f7	840	#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16
<>	144:ef7eb2e8f9f7	841	#define ADC_CHANNEL_VBAT ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	842
<>	144:ef7eb2e8f9f7	843	/* Note: Vopamp2/3/4 internal channels available on ADC2/3/4 respectively */
<>	144:ef7eb2e8f9f7	844	#define ADC_CHANNEL_VOPAMP2 ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	845	#define ADC_CHANNEL_VOPAMP3 ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	846	#define ADC_CHANNEL_VOPAMP4 ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	847
<>	144:ef7eb2e8f9f7	848	/* Note: VrefInt internal channels available on all ADCs, but only */
<>	144:ef7eb2e8f9f7	849	/* one ADC is allowed to be connected to VrefInt at the same time. */
<>	144:ef7eb2e8f9f7	850	#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_18)
<>	144:ef7eb2e8f9f7	851	/**
<>	144:ef7eb2e8f9f7	852	* @}
<>	144:ef7eb2e8f9f7	853	*/
<>	144:ef7eb2e8f9f7	854
<>	144:ef7eb2e8f9f7	855	/** @defgroup ADCEx_sampling_times ADC Extended Sampling Times
<>	144:ef7eb2e8f9f7	856	* @{
<>	144:ef7eb2e8f9f7	857	*/
<>	144:ef7eb2e8f9f7	858	#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /!< Sampling time 1.5 ADC clock cycle /
<>	144:ef7eb2e8f9f7	859	#define ADC_SAMPLETIME_2CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_0) /!< Sampling time 2.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	860	#define ADC_SAMPLETIME_4CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_1) /!< Sampling time 4.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	861	#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_1 \| ADC_SMPR2_SMP10_0)) /!< Sampling time 7.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	862	#define ADC_SAMPLETIME_19CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_2) /!< Sampling time 19.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	863	#define ADC_SAMPLETIME_61CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 \| ADC_SMPR2_SMP10_0)) /!< Sampling time 61.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	864	#define ADC_SAMPLETIME_181CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 \| ADC_SMPR2_SMP10_1)) /!< Sampling time 181.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	865	#define ADC_SAMPLETIME_601CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10) /!< Sampling time 601.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	866	/**
<>	144:ef7eb2e8f9f7	867	* @}
<>	144:ef7eb2e8f9f7	868	*/
<>	144:ef7eb2e8f9f7	869
<>	144:ef7eb2e8f9f7	870	/** @defgroup ADCEx_SingleDifferential ADC Extended Single-ended/Differential input mode
<>	144:ef7eb2e8f9f7	871	* @{
<>	144:ef7eb2e8f9f7	872	*/
<>	144:ef7eb2e8f9f7	873	#define ADC_SINGLE_ENDED ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	874	#define ADC_DIFFERENTIAL_ENDED ((uint32_t)0x00000001)
<>	144:ef7eb2e8f9f7	875	/**
<>	144:ef7eb2e8f9f7	876	* @}
<>	144:ef7eb2e8f9f7	877	*/
<>	144:ef7eb2e8f9f7	878
<>	144:ef7eb2e8f9f7	879	/** @defgroup ADCEx_OffsetNumber ADC Extended Offset Number
<>	144:ef7eb2e8f9f7	880	* @{
<>	144:ef7eb2e8f9f7	881	*/
<>	144:ef7eb2e8f9f7	882	#define ADC_OFFSET_NONE ((uint32_t)0x00)
<>	144:ef7eb2e8f9f7	883	#define ADC_OFFSET_1 ((uint32_t)0x01)
<>	144:ef7eb2e8f9f7	884	#define ADC_OFFSET_2 ((uint32_t)0x02)
<>	144:ef7eb2e8f9f7	885	#define ADC_OFFSET_3 ((uint32_t)0x03)
<>	144:ef7eb2e8f9f7	886	#define ADC_OFFSET_4 ((uint32_t)0x04)
<>	144:ef7eb2e8f9f7	887	/**
<>	144:ef7eb2e8f9f7	888	* @}
<>	144:ef7eb2e8f9f7	889	*/
<>	144:ef7eb2e8f9f7	890
<>	144:ef7eb2e8f9f7	891	/** @defgroup ADCEx_regular_rank ADC Extended rank into regular group
<>	144:ef7eb2e8f9f7	892	* @{
<>	144:ef7eb2e8f9f7	893	*/
<>	144:ef7eb2e8f9f7	894	#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)
<>	144:ef7eb2e8f9f7	895	#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)
<>	144:ef7eb2e8f9f7	896	#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)
<>	144:ef7eb2e8f9f7	897	#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)
<>	144:ef7eb2e8f9f7	898	#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)
<>	144:ef7eb2e8f9f7	899	#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)
<>	144:ef7eb2e8f9f7	900	#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)
<>	144:ef7eb2e8f9f7	901	#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)
<>	144:ef7eb2e8f9f7	902	#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)
<>	144:ef7eb2e8f9f7	903	#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)
<>	144:ef7eb2e8f9f7	904	#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)
<>	144:ef7eb2e8f9f7	905	#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)
<>	144:ef7eb2e8f9f7	906	#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)
<>	144:ef7eb2e8f9f7	907	#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)
<>	144:ef7eb2e8f9f7	908	#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)
<>	144:ef7eb2e8f9f7	909	#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)
<>	144:ef7eb2e8f9f7	910	/**
<>	144:ef7eb2e8f9f7	911	* @}
<>	144:ef7eb2e8f9f7	912	*/
<>	144:ef7eb2e8f9f7	913
<>	144:ef7eb2e8f9f7	914	/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
<>	144:ef7eb2e8f9f7	915	* @{
<>	144:ef7eb2e8f9f7	916	*/
<>	144:ef7eb2e8f9f7	917	#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
<>	144:ef7eb2e8f9f7	918	#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
<>	144:ef7eb2e8f9f7	919	#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
<>	144:ef7eb2e8f9f7	920	#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)
<>	144:ef7eb2e8f9f7	921	/**
<>	144:ef7eb2e8f9f7	922	* @}
<>	144:ef7eb2e8f9f7	923	*/
<>	144:ef7eb2e8f9f7	924
<>	144:ef7eb2e8f9f7	925	/** @defgroup ADCEx_External_trigger_edge_Injected External Trigger Edge of Injected Group
<>	144:ef7eb2e8f9f7	926	* @{
<>	144:ef7eb2e8f9f7	927	*/
<>	144:ef7eb2e8f9f7	928	#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	929	#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_JSQR_JEXTEN_0)
<>	144:ef7eb2e8f9f7	930	#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_JSQR_JEXTEN_1)
<>	144:ef7eb2e8f9f7	931	#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_JSQR_JEXTEN)
<>	144:ef7eb2e8f9f7	932	/**
<>	144:ef7eb2e8f9f7	933	* @}
<>	144:ef7eb2e8f9f7	934	*/
<>	144:ef7eb2e8f9f7	935
<>	144:ef7eb2e8f9f7	936	/** @defgroup ADCEx_External_trigger_source_Injected External Trigger Source of Injected Group
<>	144:ef7eb2e8f9f7	937	* @{
<>	144:ef7eb2e8f9f7	938	*/
<>	144:ef7eb2e8f9f7	939	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	940	defined(STM32F303xC) \|\| defined(STM32F358xx)
<>	144:ef7eb2e8f9f7	941	/* List of external triggers with generic trigger name, independently of ADC */
<>	144:ef7eb2e8f9f7	942	/* target (caution: applies to other ADCs sharing the same common group), */
<>	144:ef7eb2e8f9f7	943	/* sorted by trigger name: */
<>	144:ef7eb2e8f9f7	944
<>	144:ef7eb2e8f9f7	945	/* External triggers of injected group for ADC1&ADC2 only */
<>	144:ef7eb2e8f9f7	946	#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
<>	144:ef7eb2e8f9f7	947	#define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1
<>	144:ef7eb2e8f9f7	948	#define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3
<>	144:ef7eb2e8f9f7	949	#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
<>	144:ef7eb2e8f9f7	950	#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO
<>	144:ef7eb2e8f9f7	951	#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
<>	144:ef7eb2e8f9f7	952
<>	144:ef7eb2e8f9f7	953	/* External triggers of injected group for ADC3&ADC4 only */
<>	144:ef7eb2e8f9f7	954	#define ADC_EXTERNALTRIGINJECCONV_T1_CC3 ADC3_4_EXTERNALTRIGINJEC_T1_CC3
<>	144:ef7eb2e8f9f7	955	#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ADC3_4_EXTERNALTRIGINJEC_T4_CC3
<>	144:ef7eb2e8f9f7	956	#define ADC_EXTERNALTRIGINJECCONV_T4_CC4 ADC3_4_EXTERNALTRIGINJEC_T4_CC4
<>	144:ef7eb2e8f9f7	957	#define ADC_EXTERNALTRIGINJECCONV_T7_TRGO ADC3_4_EXTERNALTRIGINJEC_T7_TRGO
<>	144:ef7eb2e8f9f7	958	#define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ADC3_4_EXTERNALTRIGINJEC_T8_CC2
<>	144:ef7eb2e8f9f7	959
<>	144:ef7eb2e8f9f7	960	/* External triggers of injected group for ADC1&ADC2, ADC3&ADC4 */
<>	144:ef7eb2e8f9f7	961	/* Note: Triggers affected to group ADC1_2 by default, redirected to group */
<>	144:ef7eb2e8f9f7	962	/* ADC3_4 by driver when needed. */
<>	144:ef7eb2e8f9f7	963	#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4
<>	144:ef7eb2e8f9f7	964	#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO
<>	144:ef7eb2e8f9f7	965	#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2
<>	144:ef7eb2e8f9f7	966	#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
<>	144:ef7eb2e8f9f7	967	#define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO
<>	144:ef7eb2e8f9f7	968	#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
<>	144:ef7eb2e8f9f7	969	#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4
<>	144:ef7eb2e8f9f7	970	#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO ADC1_2_EXTERNALTRIGINJEC_T8_TRGO
<>	144:ef7eb2e8f9f7	971	#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2
<>	144:ef7eb2e8f9f7	972	#define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
<>	144:ef7eb2e8f9f7	973
<>	144:ef7eb2e8f9f7	974	#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)
<>	144:ef7eb2e8f9f7	975
<>	144:ef7eb2e8f9f7	976	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
<>	144:ef7eb2e8f9f7	977	/!< List of external triggers specific to device STM303xE: using Timer20 /
<>	144:ef7eb2e8f9f7	978	/* with ADC trigger input remap. */
<>	144:ef7eb2e8f9f7	979	/* To remap ADC trigger from other timers/ExtLine to timer20: use macro */
<>	144:ef7eb2e8f9f7	980	/* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */
<>	144:ef7eb2e8f9f7	981
<>	144:ef7eb2e8f9f7	982	/!< External triggers of injected group for ADC1&ADC2 only, specific to /
<>	144:ef7eb2e8f9f7	983	/* device STM303xE: : using Timer20 with ADC trigger input remap */
<>	144:ef7eb2e8f9f7	984	#define ADC_EXTERNALTRIGINJECCONV_T20_CC4 ADC_EXTERNALTRIGINJECCONV_T3_CC1 /!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT13) /
<>	144:ef7eb2e8f9f7	985
<>	144:ef7eb2e8f9f7	986	/!< External triggers of injected group for ADC3&ADC4 only, specific to /
<>	144:ef7eb2e8f9f7	987	/* device STM303xE: : using Timer20 with ADC trigger input remap */
<>	144:ef7eb2e8f9f7	988	#define ADC_EXTERNALTRIGINJECCONV_T20_CC2 ADC_EXTERNALTRIGINJECCONV_T7_TRGO /!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT14) /
<>	144:ef7eb2e8f9f7	989
<>	144:ef7eb2e8f9f7	990	/!< External triggers of regular group for ADC1&ADC2, ADC3&ADC4, specific to /
<>	144:ef7eb2e8f9f7	991	/* device STM303xE: : using Timer20 with ADC trigger input remap */
<>	144:ef7eb2e8f9f7	992	/* Note: Triggers affected to group ADC1_2 by default, redirected to group */
<>	144:ef7eb2e8f9f7	993	/* ADC3_4 by driver when needed. */
<>	144:ef7eb2e8f9f7	994	#define ADC_EXTERNALTRIGINJECCONV_T20_TRGO (ADC_EXTERNALTRIGINJECCONV_T2_CC1 \| ADC_EXTERNALTRIGCONV_T20_MASK) /!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT3) /
<>	144:ef7eb2e8f9f7	995	/!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT5) /
<>	144:ef7eb2e8f9f7	996	#define ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 (ADC_EXTERNALTRIGINJECCONV_EXT_IT15 \| ADC_EXTERNALTRIGCONV_T20_MASK) /!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT6) /
<>	144:ef7eb2e8f9f7	997	/!< For ADC3&ADC4: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC34_JEXT11) /
<>	144:ef7eb2e8f9f7	998	#endif /* STM32F303xE \|\| STM32F398xx */
<>	144:ef7eb2e8f9f7	999
<>	144:ef7eb2e8f9f7	1000	#if defined(STM32F303xC) \|\| defined(STM32F358xx)
<>	144:ef7eb2e8f9f7	1001	#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) \|\| \
<>	144:ef7eb2e8f9f7	1002	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) \|\| \
<>	144:ef7eb2e8f9f7	1003	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \|\| \
<>	144:ef7eb2e8f9f7	1004	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	1005	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) \|\| \
<>	144:ef7eb2e8f9f7	1006	\
<>	144:ef7eb2e8f9f7	1007	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) \|\| \
<>	144:ef7eb2e8f9f7	1008	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) \|\| \
<>	144:ef7eb2e8f9f7	1009	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	1010	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) \|\| \
<>	144:ef7eb2e8f9f7	1011	\
<>	144:ef7eb2e8f9f7	1012	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \|\| \
<>	144:ef7eb2e8f9f7	1013	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	1014	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	1015	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	1016	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) \|\| \
<>	144:ef7eb2e8f9f7	1017	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	1018	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	1019	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) \|\| \
<>	144:ef7eb2e8f9f7	1020	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	1021	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	1022	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	1023	\
<>	144:ef7eb2e8f9f7	1024	((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
<>	144:ef7eb2e8f9f7	1025	#endif /* STM32F303xC \|\| STM32F358xx */
<>	144:ef7eb2e8f9f7	1026
<>	144:ef7eb2e8f9f7	1027	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
<>	144:ef7eb2e8f9f7	1028	#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) \|\| \
<>	144:ef7eb2e8f9f7	1029	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) \|\| \
<>	144:ef7eb2e8f9f7	1030	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \|\| \
<>	144:ef7eb2e8f9f7	1031	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	1032	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) \|\| \
<>	144:ef7eb2e8f9f7	1033	\
<>	144:ef7eb2e8f9f7	1034	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) \|\| \
<>	144:ef7eb2e8f9f7	1035	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) \|\| \
<>	144:ef7eb2e8f9f7	1036	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	1037	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) \|\| \
<>	144:ef7eb2e8f9f7	1038	\
<>	144:ef7eb2e8f9f7	1039	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \|\| \
<>	144:ef7eb2e8f9f7	1040	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	1041	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	1042	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	1043	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) \|\| \
<>	144:ef7eb2e8f9f7	1044	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	1045	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	1046	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) \|\| \
<>	144:ef7eb2e8f9f7	1047	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	1048	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	1049	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	1050	\
<>	144:ef7eb2e8f9f7	1051	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC4) \|\| \
<>	144:ef7eb2e8f9f7	1052	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC2) \|\| \
<>	144:ef7eb2e8f9f7	1053	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	1054	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	1055	\
<>	144:ef7eb2e8f9f7	1056	((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
<>	144:ef7eb2e8f9f7	1057	#endif /* STM32F303xE \|\| STM32F398xx */
<>	144:ef7eb2e8f9f7	1058
<>	144:ef7eb2e8f9f7	1059	#endif /* STM32F303xC \|\| STM32F303xE \|\| STM32F398xx \|\| STM32F358xx */
<>	144:ef7eb2e8f9f7	1060
<>	144:ef7eb2e8f9f7	1061	#if defined(STM32F302xE) \|\| \
<>	144:ef7eb2e8f9f7	1062	defined(STM32F302xC)
<>	144:ef7eb2e8f9f7	1063	/!< List of external triggers with generic trigger name, independently of /
<>	144:ef7eb2e8f9f7	1064	/* ADC target (caution: applies to other ADCs sharing the same common group), */
<>	144:ef7eb2e8f9f7	1065	/* sorted by trigger name: */
<>	144:ef7eb2e8f9f7	1066
<>	144:ef7eb2e8f9f7	1067	/* External triggers of injected group for ADC1&ADC2 */
<>	144:ef7eb2e8f9f7	1068	#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4
<>	144:ef7eb2e8f9f7	1069	#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO
<>	144:ef7eb2e8f9f7	1070	#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2
<>	144:ef7eb2e8f9f7	1071	#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
<>	144:ef7eb2e8f9f7	1072	#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
<>	144:ef7eb2e8f9f7	1073	#define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1
<>	144:ef7eb2e8f9f7	1074	#define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3
<>	144:ef7eb2e8f9f7	1075	#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
<>	144:ef7eb2e8f9f7	1076	#define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO
<>	144:ef7eb2e8f9f7	1077	#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
<>	144:ef7eb2e8f9f7	1078	#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO
<>	144:ef7eb2e8f9f7	1079	#define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
<>	144:ef7eb2e8f9f7	1080	#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
<>	144:ef7eb2e8f9f7	1081
<>	144:ef7eb2e8f9f7	1082	#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)
<>	144:ef7eb2e8f9f7	1083
<>	144:ef7eb2e8f9f7	1084	#if defined(STM32F302xE)
<>	144:ef7eb2e8f9f7	1085	/!< List of external triggers specific to device STM302xE: using Timer20 /
<>	144:ef7eb2e8f9f7	1086	/* with ADC trigger input remap. */
<>	144:ef7eb2e8f9f7	1087	/* To remap ADC trigger from other timers/ExtLine to timer20: use macro */
<>	144:ef7eb2e8f9f7	1088	/* " __HAL_REMAPADCTRIGGER_ENABLE(...) " with parameters described below: */
<>	144:ef7eb2e8f9f7	1089
<>	144:ef7eb2e8f9f7	1090	/!< External triggers of injected group for ADC1&ADC2 only, specific to /
<>	144:ef7eb2e8f9f7	1091	/* device STM302xE: : using Timer20 with ADC trigger input remap */
<>	144:ef7eb2e8f9f7	1092	#define ADC_EXTERNALTRIGINJECCONV_T20_CC4 ADC_EXTERNALTRIGINJECCONV_T3_CC1 /!< Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT13) /
<>	144:ef7eb2e8f9f7	1093	#define ADC_EXTERNALTRIGINJECCONV_T20_TRGO (ADC_EXTERNALTRIGINJECCONV_T2_CC1 \| ADC_EXTERNALTRIGCONV_T20_MASK) /!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT3) /
<>	144:ef7eb2e8f9f7	1094	#define ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 (ADC_EXTERNALTRIGINJECCONV_EXT_IT15 \| ADC_EXTERNALTRIGCONV_T20_MASK) /!< For ADC1&ADC2: Remap trigger using macro __HAL_REMAPADCTRIGGER_ENABLE(HAL_REMAPADCTRIGGER_ADC12_JEXT6) /
<>	144:ef7eb2e8f9f7	1095	#endif /* STM32F302xE */
<>	144:ef7eb2e8f9f7	1096
<>	144:ef7eb2e8f9f7	1097	#endif /* STM32F302xE \|\| */
<>	144:ef7eb2e8f9f7	1098	/* STM32F302xC */
<>	144:ef7eb2e8f9f7	1099
<>	144:ef7eb2e8f9f7	1100	#if defined(STM32F303x8) \|\| defined(STM32F328xx)
<>	144:ef7eb2e8f9f7	1101	/!< List of external triggers with generic trigger name, independently of /
<>	144:ef7eb2e8f9f7	1102	/* ADC target (caution: applies to other ADCs sharing the same common group), */
<>	144:ef7eb2e8f9f7	1103	/* sorted by trigger name: */
<>	144:ef7eb2e8f9f7	1104
<>	144:ef7eb2e8f9f7	1105	/* External triggers of injected group for ADC1&ADC2 */
<>	144:ef7eb2e8f9f7	1106	#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4
<>	144:ef7eb2e8f9f7	1107	#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO
<>	144:ef7eb2e8f9f7	1108	#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2
<>	144:ef7eb2e8f9f7	1109	#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
<>	144:ef7eb2e8f9f7	1110	#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
<>	144:ef7eb2e8f9f7	1111	#define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1
<>	144:ef7eb2e8f9f7	1112	#define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3
<>	144:ef7eb2e8f9f7	1113	#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
<>	144:ef7eb2e8f9f7	1114	#define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO
<>	144:ef7eb2e8f9f7	1115	#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC1_2_EXTERNALTRIGINJEC_T4_TRGO
<>	144:ef7eb2e8f9f7	1116	#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO
<>	144:ef7eb2e8f9f7	1117	#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ADC1_2_EXTERNALTRIGINJEC_T8_CC4
<>	144:ef7eb2e8f9f7	1118	#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO ADC1_2_EXTERNALTRIGINJEC_T8_TRGO
<>	144:ef7eb2e8f9f7	1119	#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2
<>	144:ef7eb2e8f9f7	1120	#define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
<>	144:ef7eb2e8f9f7	1121	#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
<>	144:ef7eb2e8f9f7	1122
<>	144:ef7eb2e8f9f7	1123	#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)
<>	144:ef7eb2e8f9f7	1124	#endif /* STM32F303x8 \|\| STM32F328xx */
<>	144:ef7eb2e8f9f7	1125
<>	144:ef7eb2e8f9f7	1126	#if defined(STM32F334x8)
<>	144:ef7eb2e8f9f7	1127	/!< List of external triggers with generic trigger name, independently of /
<>	144:ef7eb2e8f9f7	1128	/* ADC target (caution: applies to other ADCs sharing the same common group), */
<>	144:ef7eb2e8f9f7	1129	/* sorted by trigger name: */
<>	144:ef7eb2e8f9f7	1130
<>	144:ef7eb2e8f9f7	1131	/* External triggers of injected group for ADC1&ADC2 */
<>	144:ef7eb2e8f9f7	1132	#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_2_EXTERNALTRIGINJEC_T1_CC4
<>	144:ef7eb2e8f9f7	1133	#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_2_EXTERNALTRIGINJEC_T1_TRGO
<>	144:ef7eb2e8f9f7	1134	#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2
<>	144:ef7eb2e8f9f7	1135	#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC1_2_EXTERNALTRIGINJEC_T2_CC1
<>	144:ef7eb2e8f9f7	1136	#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC1_2_EXTERNALTRIGINJEC_T2_TRGO
<>	144:ef7eb2e8f9f7	1137	#define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ADC1_2_EXTERNALTRIGINJEC_T3_CC1
<>	144:ef7eb2e8f9f7	1138	#define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ADC1_2_EXTERNALTRIGINJEC_T3_CC3
<>	144:ef7eb2e8f9f7	1139	#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC1_2_EXTERNALTRIGINJEC_T3_CC4
<>	144:ef7eb2e8f9f7	1140	#define ADC_EXTERNALTRIGINJECCONV_T3_TRGO ADC1_2_EXTERNALTRIGINJEC_T3_TRGO
<>	144:ef7eb2e8f9f7	1141	#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_2_EXTERNALTRIGINJEC_T6_TRGO
<>	144:ef7eb2e8f9f7	1142	#define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_2_EXTERNALTRIGINJEC_T15_TRGO
<>	144:ef7eb2e8f9f7	1143	#define ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG2 ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG2
<>	144:ef7eb2e8f9f7	1144	#define ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG4 ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG4
<>	144:ef7eb2e8f9f7	1145	#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_2_EXTERNALTRIGINJEC_EXT_IT15
<>	144:ef7eb2e8f9f7	1146
<>	144:ef7eb2e8f9f7	1147	#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)
<>	144:ef7eb2e8f9f7	1148	#endif /* STM32F334x8 */
<>	144:ef7eb2e8f9f7	1149
<>	144:ef7eb2e8f9f7	1150	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	1151	/* List of external triggers with generic trigger name, sorted by trigger */
<>	144:ef7eb2e8f9f7	1152	/* name: */
<>	144:ef7eb2e8f9f7	1153
<>	144:ef7eb2e8f9f7	1154	/* External triggers of injected group for ADC1 */
<>	144:ef7eb2e8f9f7	1155	#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ADC1_EXTERNALTRIGINJEC_T1_CC4
<>	144:ef7eb2e8f9f7	1156	#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ADC1_EXTERNALTRIGINJEC_T1_TRGO
<>	144:ef7eb2e8f9f7	1157	#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ADC1_EXTERNALTRIGINJEC_T1_TRGO2
<>	144:ef7eb2e8f9f7	1158	#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ADC1_EXTERNALTRIGINJEC_T6_TRGO
<>	144:ef7eb2e8f9f7	1159	#define ADC_EXTERNALTRIGINJECCONV_T15_TRGO ADC1_EXTERNALTRIGINJEC_T15_TRGO
<>	144:ef7eb2e8f9f7	1160	#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC1_EXTERNALTRIGINJEC_EXT_IT15
<>	144:ef7eb2e8f9f7	1161
<>	144:ef7eb2e8f9f7	1162	#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001)
<>	144:ef7eb2e8f9f7	1163	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	1164	/**
<>	144:ef7eb2e8f9f7	1165	* @}
<>	144:ef7eb2e8f9f7	1166	*/
<>	144:ef7eb2e8f9f7	1167
<>	144:ef7eb2e8f9f7	1168
<>	144:ef7eb2e8f9f7	1169	/** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
<>	144:ef7eb2e8f9f7	1170	* @{
<>	144:ef7eb2e8f9f7	1171	*/
<>	144:ef7eb2e8f9f7	1172	#define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000))
<>	144:ef7eb2e8f9f7	1173	#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC12_CCR_MULTI_0))
<>	144:ef7eb2e8f9f7	1174	#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC12_CCR_MULTI_1))
<>	144:ef7eb2e8f9f7	1175	#define ADC_DUALMODE_REGINTERL_INJECSIMULT ((uint32_t)(ADC12_CCR_MULTI_1 \| ADC12_CCR_MULTI_0))
<>	144:ef7eb2e8f9f7	1176	#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC12_CCR_MULTI_2 \| ADC12_CCR_MULTI_0))
<>	144:ef7eb2e8f9f7	1177	#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC12_CCR_MULTI_2 \| ADC12_CCR_MULTI_1))
<>	144:ef7eb2e8f9f7	1178	#define ADC_DUALMODE_INTERL ((uint32_t)(ADC12_CCR_MULTI_2 \| ADC12_CCR_MULTI_1 \| ADC12_CCR_MULTI_0))
<>	144:ef7eb2e8f9f7	1179	#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC12_CCR_MULTI_3 \| ADC12_CCR_MULTI_0))
<>	144:ef7eb2e8f9f7	1180	/**
<>	144:ef7eb2e8f9f7	1181	* @}
<>	144:ef7eb2e8f9f7	1182	*/
<>	144:ef7eb2e8f9f7	1183
<>	144:ef7eb2e8f9f7	1184
<>	144:ef7eb2e8f9f7	1185	/** @defgroup ADCEx_Direct_memory_access_mode_for_multimode ADC Extended DMA Mode for Dual ADC Mode
<>	144:ef7eb2e8f9f7	1186	* @{
<>	144:ef7eb2e8f9f7	1187	*/
<>	144:ef7eb2e8f9f7	1188	#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000) /!< DMA multimode disabled: each ADC will use its own DMA channel /
<>	144:ef7eb2e8f9f7	1189	#define ADC_DMAACCESSMODE_12_10_BITS ((uint32_t)ADC12_CCR_MDMA_1) /!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution /
<>	144:ef7eb2e8f9f7	1190	#define ADC_DMAACCESSMODE_8_6_BITS ((uint32_t)ADC12_CCR_MDMA) /!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution /
<>	144:ef7eb2e8f9f7	1191	/**
<>	144:ef7eb2e8f9f7	1192	* @}
<>	144:ef7eb2e8f9f7	1193	*/
<>	144:ef7eb2e8f9f7	1194
<>	144:ef7eb2e8f9f7	1195	/** @defgroup ADCEx_delay_between_2_sampling_phases ADC Extended Delay Between 2 Sampling Phases
<>	144:ef7eb2e8f9f7	1196	* @{
<>	144:ef7eb2e8f9f7	1197	*/
<>	144:ef7eb2e8f9f7	1198	#define ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000))
<>	144:ef7eb2e8f9f7	1199	#define ADC_TWOSAMPLINGDELAY_2CYCLES ((uint32_t)(ADC12_CCR_DELAY_0))
<>	144:ef7eb2e8f9f7	1200	#define ADC_TWOSAMPLINGDELAY_3CYCLES ((uint32_t)(ADC12_CCR_DELAY_1))
<>	144:ef7eb2e8f9f7	1201	#define ADC_TWOSAMPLINGDELAY_4CYCLES ((uint32_t)(ADC12_CCR_DELAY_1 \| ADC12_CCR_DELAY_0))
<>	144:ef7eb2e8f9f7	1202	#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)(ADC12_CCR_DELAY_2))
<>	144:ef7eb2e8f9f7	1203	#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)(ADC12_CCR_DELAY_2 \| ADC12_CCR_DELAY_0))
<>	144:ef7eb2e8f9f7	1204	#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)(ADC12_CCR_DELAY_2 \| ADC12_CCR_DELAY_1))
<>	144:ef7eb2e8f9f7	1205	#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC12_CCR_DELAY_2 \| ADC12_CCR_DELAY_1 \| ADC12_CCR_DELAY_0))
<>	144:ef7eb2e8f9f7	1206	#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)(ADC12_CCR_DELAY_3))
<>	144:ef7eb2e8f9f7	1207	#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC12_CCR_DELAY_3 \| ADC12_CCR_DELAY_0))
<>	144:ef7eb2e8f9f7	1208	#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC12_CCR_DELAY_3 \| ADC12_CCR_DELAY_1))
<>	144:ef7eb2e8f9f7	1209	#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC12_CCR_DELAY_3 \| ADC12_CCR_DELAY_1 \| ADC12_CCR_DELAY_0))
<>	144:ef7eb2e8f9f7	1210	/**
<>	144:ef7eb2e8f9f7	1211	* @}
<>	144:ef7eb2e8f9f7	1212	*/
<>	144:ef7eb2e8f9f7	1213
<>	144:ef7eb2e8f9f7	1214	/** @defgroup ADCEx_analog_watchdog_number ADC Extended Analog Watchdog Selection
<>	144:ef7eb2e8f9f7	1215	* @{
<>	144:ef7eb2e8f9f7	1216	*/
<>	144:ef7eb2e8f9f7	1217	#define ADC_ANALOGWATCHDOG_1 ((uint32_t)0x00000001)
<>	144:ef7eb2e8f9f7	1218	#define ADC_ANALOGWATCHDOG_2 ((uint32_t)0x00000002)
<>	144:ef7eb2e8f9f7	1219	#define ADC_ANALOGWATCHDOG_3 ((uint32_t)0x00000003)
<>	144:ef7eb2e8f9f7	1220	/**
<>	144:ef7eb2e8f9f7	1221	* @}
<>	144:ef7eb2e8f9f7	1222	*/
<>	144:ef7eb2e8f9f7	1223
<>	144:ef7eb2e8f9f7	1224	/** @defgroup ADCEx_analog_watchdog_mode ADC Extended Analog Watchdog Mode
<>	144:ef7eb2e8f9f7	1225	* @{
<>	144:ef7eb2e8f9f7	1226	*/
<>	144:ef7eb2e8f9f7	1227	#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000)
<>	144:ef7eb2e8f9f7	1228	#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR_AWD1SGL \| ADC_CFGR_AWD1EN))
<>	144:ef7eb2e8f9f7	1229	#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CFGR_AWD1SGL \| ADC_CFGR_JAWD1EN))
<>	144:ef7eb2e8f9f7	1230	#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CFGR_AWD1SGL \| ADC_CFGR_AWD1EN \| ADC_CFGR_JAWD1EN))
<>	144:ef7eb2e8f9f7	1231	#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR_AWD1EN)
<>	144:ef7eb2e8f9f7	1232	#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CFGR_JAWD1EN)
<>	144:ef7eb2e8f9f7	1233	#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CFGR_AWD1EN \| ADC_CFGR_JAWD1EN))
<>	144:ef7eb2e8f9f7	1234	/**
<>	144:ef7eb2e8f9f7	1235	* @}
<>	144:ef7eb2e8f9f7	1236	*/
<>	144:ef7eb2e8f9f7	1237
<>	144:ef7eb2e8f9f7	1238	/** @defgroup ADC_conversion_group ADC Conversion Group
<>	144:ef7eb2e8f9f7	1239	* @{
<>	144:ef7eb2e8f9f7	1240	*/
<>	144:ef7eb2e8f9f7	1241	#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC \| ADC_FLAG_EOS))
<>	144:ef7eb2e8f9f7	1242	#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC \| ADC_FLAG_JEOS))
<>	144:ef7eb2e8f9f7	1243	#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_JEOC \| ADC_FLAG_JEOS))
<>	144:ef7eb2e8f9f7	1244
<>	144:ef7eb2e8f9f7	1245	/**
<>	144:ef7eb2e8f9f7	1246	* @}
<>	144:ef7eb2e8f9f7	1247	*/
<>	144:ef7eb2e8f9f7	1248
<>	144:ef7eb2e8f9f7	1249	/** @defgroup ADCEx_Event_type ADC Extended Event Type
<>	144:ef7eb2e8f9f7	1250	* @{
<>	144:ef7eb2e8f9f7	1251	*/
<>	144:ef7eb2e8f9f7	1252	#define ADC_AWD1_EVENT ((uint32_t)ADC_FLAG_AWD1) /!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices) /
<>	144:ef7eb2e8f9f7	1253	#define ADC_AWD2_EVENT ((uint32_t)ADC_FLAG_AWD2) /!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families) /
<>	144:ef7eb2e8f9f7	1254	#define ADC_AWD3_EVENT ((uint32_t)ADC_FLAG_AWD3) /!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families) /
<>	144:ef7eb2e8f9f7	1255	#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /!< ADC overrun event /
<>	144:ef7eb2e8f9f7	1256	#define ADC_JQOVF_EVENT ((uint32_t)ADC_FLAG_JQOVF) /!< ADC Injected Context Queue Overflow event /
<>	144:ef7eb2e8f9f7	1257
<>	144:ef7eb2e8f9f7	1258	#define ADC_AWD_EVENT ADC_AWD1_EVENT /* ADC Analog watchdog 1 event: Alternate naming for compatibility with other STM32 devices having only 1 analog watchdog */
<>	144:ef7eb2e8f9f7	1259	/**
<>	144:ef7eb2e8f9f7	1260	* @}
<>	144:ef7eb2e8f9f7	1261	*/
<>	144:ef7eb2e8f9f7	1262
<>	144:ef7eb2e8f9f7	1263	/** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition
<>	144:ef7eb2e8f9f7	1264	* @{
<>	144:ef7eb2e8f9f7	1265	*/
<>	144:ef7eb2e8f9f7	1266	#define ADC_IT_RDY ADC_IER_RDY /!< ADC Ready (ADRDY) interrupt source /
<>	144:ef7eb2e8f9f7	1267	#define ADC_IT_EOSMP ADC_IER_EOSMP /!< ADC End of Sampling interrupt source /
<>	144:ef7eb2e8f9f7	1268	#define ADC_IT_EOC ADC_IER_EOC /!< ADC End of Regular Conversion interrupt source /
<>	144:ef7eb2e8f9f7	1269	#define ADC_IT_EOS ADC_IER_EOS /!< ADC End of Regular sequence of Conversions interrupt source /
<>	144:ef7eb2e8f9f7	1270	#define ADC_IT_OVR ADC_IER_OVR /!< ADC overrun interrupt source /
<>	144:ef7eb2e8f9f7	1271	#define ADC_IT_JEOC ADC_IER_JEOC /!< ADC End of Injected Conversion interrupt source /
<>	144:ef7eb2e8f9f7	1272	#define ADC_IT_JEOS ADC_IER_JEOS /!< ADC End of Injected sequence of Conversions interrupt source /
<>	144:ef7eb2e8f9f7	1273	#define ADC_IT_AWD1 ADC_IER_AWD1 /!< ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices) /
<>	144:ef7eb2e8f9f7	1274	#define ADC_IT_AWD2 ADC_IER_AWD2 /!< ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices) /
<>	144:ef7eb2e8f9f7	1275	#define ADC_IT_AWD3 ADC_IER_AWD3 /!< ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices) /
<>	144:ef7eb2e8f9f7	1276	#define ADC_IT_JQOVF ADC_IER_JQOVF /!< ADC Injected Context Queue Overflow interrupt source /
<>	144:ef7eb2e8f9f7	1277
<>	144:ef7eb2e8f9f7	1278	#define ADC_IT_AWD ADC_IT_AWD1 /* ADC Analog watchdog 1 interrupt source: Alternate naming for compatibility with other STM32 devices having only 1 analog watchdog */
<>	144:ef7eb2e8f9f7	1279	/**
<>	144:ef7eb2e8f9f7	1280	* @}
<>	144:ef7eb2e8f9f7	1281	*/
<>	144:ef7eb2e8f9f7	1282
<>	144:ef7eb2e8f9f7	1283	/** @defgroup ADCEx_flags_definition ADC Extended Flags Definition
<>	144:ef7eb2e8f9f7	1284	* @{
<>	144:ef7eb2e8f9f7	1285	*/
<>	144:ef7eb2e8f9f7	1286	#define ADC_FLAG_RDY ADC_ISR_ADRD /!< ADC Ready (ADRDY) flag /
<>	144:ef7eb2e8f9f7	1287	#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /!< ADC End of Sampling flag /
<>	144:ef7eb2e8f9f7	1288	#define ADC_FLAG_EOC ADC_ISR_EOC /!< ADC End of Regular Conversion flag /
<>	144:ef7eb2e8f9f7	1289	#define ADC_FLAG_EOS ADC_ISR_EOS /!< ADC End of Regular sequence of Conversions flag /
<>	144:ef7eb2e8f9f7	1290	#define ADC_FLAG_OVR ADC_ISR_OVR /!< ADC overrun flag /
<>	144:ef7eb2e8f9f7	1291	#define ADC_FLAG_JEOC ADC_ISR_JEOC /!< ADC End of Injected Conversion flag /
<>	144:ef7eb2e8f9f7	1292	#define ADC_FLAG_JEOS ADC_ISR_JEOS /!< ADC End of Injected sequence of Conversions flag /
<>	144:ef7eb2e8f9f7	1293	#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /!< ADC Analog watchdog 1 flag (main analog watchdog, present on all STM32 devices) /
<>	144:ef7eb2e8f9f7	1294	#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /!< ADC Analog watchdog 2 flag (additional analog watchdog, present only on STM32F3 devices) /
<>	144:ef7eb2e8f9f7	1295	#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /!< ADC Analog watchdog 3 flag (additional analog watchdog, present only on STM32F3 devices) /
<>	144:ef7eb2e8f9f7	1296	#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /!< ADC Injected Context Queue Overflow flag /
<>	144:ef7eb2e8f9f7	1297
<>	144:ef7eb2e8f9f7	1298	#define ADC_FLAG_AWD ADC_FLAG_AWD1 /* ADC Analog watchdog 1 flag: Alternate naming for compatibility with other STM32 devices having only 1 analog watchdog */
<>	144:ef7eb2e8f9f7	1299	/**
<>	144:ef7eb2e8f9f7	1300	* @}
<>	144:ef7eb2e8f9f7	1301	*/
<>	144:ef7eb2e8f9f7	1302
<>	144:ef7eb2e8f9f7	1303	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	1304	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	1305	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	1306	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	1307
<>	144:ef7eb2e8f9f7	1308
<>	144:ef7eb2e8f9f7	1309	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
<>	144:ef7eb2e8f9f7	1310	/** @defgroup ADCEx_Data_align ADC Extended Data Alignment
<>	144:ef7eb2e8f9f7	1311	* @{
<>	144:ef7eb2e8f9f7	1312	*/
<>	144:ef7eb2e8f9f7	1313	#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	1314	#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
<>	144:ef7eb2e8f9f7	1315	/**
<>	144:ef7eb2e8f9f7	1316	* @}
<>	144:ef7eb2e8f9f7	1317	*/
<>	144:ef7eb2e8f9f7	1318
<>	144:ef7eb2e8f9f7	1319	/** @defgroup ADCEx_Scan_mode ADC Extended Scan Mode
<>	144:ef7eb2e8f9f7	1320	* @{
<>	144:ef7eb2e8f9f7	1321	*/
<>	144:ef7eb2e8f9f7	1322	#define ADC_SCAN_DISABLE ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	1323	#define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
<>	144:ef7eb2e8f9f7	1324	/**
<>	144:ef7eb2e8f9f7	1325	* @}
<>	144:ef7eb2e8f9f7	1326	*/
<>	144:ef7eb2e8f9f7	1327
<>	144:ef7eb2e8f9f7	1328	/** @defgroup ADCEx_External_trigger_edge_Regular ADC Extended External trigger enable for regular group
<>	144:ef7eb2e8f9f7	1329	* @{
<>	144:ef7eb2e8f9f7	1330	*/
<>	144:ef7eb2e8f9f7	1331	#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	1332	#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTTRIG)
<>	144:ef7eb2e8f9f7	1333	/**
<>	144:ef7eb2e8f9f7	1334	* @}
<>	144:ef7eb2e8f9f7	1335	*/
<>	144:ef7eb2e8f9f7	1336
<>	144:ef7eb2e8f9f7	1337	/** @defgroup ADCEx_External_trigger_source_Regular ADC Extended External trigger selection for regular group
<>	144:ef7eb2e8f9f7	1338	* @{
<>	144:ef7eb2e8f9f7	1339	*/
<>	144:ef7eb2e8f9f7	1340	/* List of external triggers with generic trigger name, sorted by trigger */
<>	144:ef7eb2e8f9f7	1341	/* name: */
<>	144:ef7eb2e8f9f7	1342
<>	144:ef7eb2e8f9f7	1343	/* External triggers of regular group for ADC1 */
<>	144:ef7eb2e8f9f7	1344	#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC_EXTERNALTRIG_T2_CC2
<>	144:ef7eb2e8f9f7	1345	#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC_EXTERNALTRIG_T3_TRGO
<>	144:ef7eb2e8f9f7	1346	#define ADC_EXTERNALTRIGCONV_T4_CC2 ADC_EXTERNALTRIG_T4_CC2
<>	144:ef7eb2e8f9f7	1347	#define ADC_EXTERNALTRIGCONV_T19_TRGO ADC_EXTERNALTRIG_T19_TRGO
<>	144:ef7eb2e8f9f7	1348	#define ADC_EXTERNALTRIGCONV_T19_CC3 ADC_EXTERNALTRIG_T19_CC3
<>	144:ef7eb2e8f9f7	1349	#define ADC_EXTERNALTRIGCONV_T19_CC4 ADC_EXTERNALTRIG_T19_CC4
<>	144:ef7eb2e8f9f7	1350	#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11
<>	144:ef7eb2e8f9f7	1351	#define ADC_SOFTWARE_START ADC_SWSTART
<>	144:ef7eb2e8f9f7	1352	/**
<>	144:ef7eb2e8f9f7	1353	* @}
<>	144:ef7eb2e8f9f7	1354	*/
<>	144:ef7eb2e8f9f7	1355
<>	144:ef7eb2e8f9f7	1356	/** @defgroup ADCEx_channels ADC Extended Channels
<>	144:ef7eb2e8f9f7	1357	* @{
<>	144:ef7eb2e8f9f7	1358	*/
<>	144:ef7eb2e8f9f7	1359	/* Note: Depending on devices, some channels may not be available on package */
<>	144:ef7eb2e8f9f7	1360	/* pins. Refer to device datasheet for channels availability. */
<>	144:ef7eb2e8f9f7	1361	#define ADC_CHANNEL_0 ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	1362	#define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ1_0))
<>	144:ef7eb2e8f9f7	1363	#define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ1_1))
<>	144:ef7eb2e8f9f7	1364	#define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ1_1 \| ADC_SQR3_SQ1_0))
<>	144:ef7eb2e8f9f7	1365	#define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ1_2))
<>	144:ef7eb2e8f9f7	1366	#define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_0))
<>	144:ef7eb2e8f9f7	1367	#define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_1))
<>	144:ef7eb2e8f9f7	1368	#define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_1 \| ADC_SQR3_SQ1_0))
<>	144:ef7eb2e8f9f7	1369	#define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ1_3))
<>	144:ef7eb2e8f9f7	1370	#define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_0))
<>	144:ef7eb2e8f9f7	1371	#define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_1))
<>	144:ef7eb2e8f9f7	1372	#define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_1 \| ADC_SQR3_SQ1_0))
<>	144:ef7eb2e8f9f7	1373	#define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_2))
<>	144:ef7eb2e8f9f7	1374	#define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_0))
<>	144:ef7eb2e8f9f7	1375	#define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_1))
<>	144:ef7eb2e8f9f7	1376	#define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ1_3 \| ADC_SQR3_SQ1_2 \| ADC_SQR3_SQ1_1 \| ADC_SQR3_SQ1_0))
<>	144:ef7eb2e8f9f7	1377	#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ1_4))
<>	144:ef7eb2e8f9f7	1378	#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ1_4 \| ADC_SQR3_SQ1_0))
<>	144:ef7eb2e8f9f7	1379	#define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ1_4 \| ADC_SQR3_SQ1_1))
<>	144:ef7eb2e8f9f7	1380
<>	144:ef7eb2e8f9f7	1381	#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16
<>	144:ef7eb2e8f9f7	1382	#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	1383	#define ADC_CHANNEL_VBAT ADC_CHANNEL_18
<>	144:ef7eb2e8f9f7	1384	/**
<>	144:ef7eb2e8f9f7	1385	* @}
<>	144:ef7eb2e8f9f7	1386	*/
<>	144:ef7eb2e8f9f7	1387
<>	144:ef7eb2e8f9f7	1388	/** @defgroup ADCEx_sampling_times ADC Extended Sampling Times
<>	144:ef7eb2e8f9f7	1389	* @{
<>	144:ef7eb2e8f9f7	1390	*/
<>	144:ef7eb2e8f9f7	1391	#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /!< Sampling time 1.5 ADC clock cycle /
<>	144:ef7eb2e8f9f7	1392	#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_0) /!< Sampling time 7.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1393	#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_1) /!< Sampling time 13.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1394	#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_1 \| ADC_SMPR2_SMP0_0)) /!< Sampling time 28.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1395	#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0_2) /!< Sampling time 41.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1396	#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 \| ADC_SMPR2_SMP0_0)) /!< Sampling time 55.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1397	#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP0_2 \| ADC_SMPR2_SMP0_1)) /!< Sampling time 71.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1398	#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t) ADC_SMPR2_SMP0) /!< Sampling time 239.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	1399	/**
<>	144:ef7eb2e8f9f7	1400	* @}
<>	144:ef7eb2e8f9f7	1401	*/
<>	144:ef7eb2e8f9f7	1402
<>	144:ef7eb2e8f9f7	1403	/** @defgroup ADCEx_regular_rank ADC Extended rank into regular group
<>	144:ef7eb2e8f9f7	1404	* @{
<>	144:ef7eb2e8f9f7	1405	*/
<>	144:ef7eb2e8f9f7	1406	#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)
<>	144:ef7eb2e8f9f7	1407	#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)
<>	144:ef7eb2e8f9f7	1408	#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)
<>	144:ef7eb2e8f9f7	1409	#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)
<>	144:ef7eb2e8f9f7	1410	#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)
<>	144:ef7eb2e8f9f7	1411	#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)
<>	144:ef7eb2e8f9f7	1412	#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)
<>	144:ef7eb2e8f9f7	1413	#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)
<>	144:ef7eb2e8f9f7	1414	#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)
<>	144:ef7eb2e8f9f7	1415	#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)
<>	144:ef7eb2e8f9f7	1416	#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)
<>	144:ef7eb2e8f9f7	1417	#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)
<>	144:ef7eb2e8f9f7	1418	#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)
<>	144:ef7eb2e8f9f7	1419	#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)
<>	144:ef7eb2e8f9f7	1420	#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)
<>	144:ef7eb2e8f9f7	1421	#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)
<>	144:ef7eb2e8f9f7	1422	/**
<>	144:ef7eb2e8f9f7	1423	* @}
<>	144:ef7eb2e8f9f7	1424	*/
<>	144:ef7eb2e8f9f7	1425
<>	144:ef7eb2e8f9f7	1426	/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
<>	144:ef7eb2e8f9f7	1427	* @{
<>	144:ef7eb2e8f9f7	1428	*/
<>	144:ef7eb2e8f9f7	1429	#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
<>	144:ef7eb2e8f9f7	1430	#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
<>	144:ef7eb2e8f9f7	1431	#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
<>	144:ef7eb2e8f9f7	1432	#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)
<>	144:ef7eb2e8f9f7	1433	/**
<>	144:ef7eb2e8f9f7	1434	* @}
<>	144:ef7eb2e8f9f7	1435	*/
<>	144:ef7eb2e8f9f7	1436
<>	144:ef7eb2e8f9f7	1437	/** @defgroup ADCEx_External_trigger_edge_Injected External Trigger Edge of Injected Group
<>	144:ef7eb2e8f9f7	1438	* @{
<>	144:ef7eb2e8f9f7	1439	*/
<>	144:ef7eb2e8f9f7	1440	#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	1441	#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_CR2_JEXTTRIG)
<>	144:ef7eb2e8f9f7	1442	/**
<>	144:ef7eb2e8f9f7	1443	* @}
<>	144:ef7eb2e8f9f7	1444	*/
<>	144:ef7eb2e8f9f7	1445
<>	144:ef7eb2e8f9f7	1446	/** @defgroup ADCEx_External_trigger_source_Injected External Trigger Source of Injected Group
<>	144:ef7eb2e8f9f7	1447	* @{
<>	144:ef7eb2e8f9f7	1448	*/
<>	144:ef7eb2e8f9f7	1449	/* External triggers for injected groups of ADC1 */
<>	144:ef7eb2e8f9f7	1450	#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ADC_EXTERNALTRIGINJEC_T2_CC1
<>	144:ef7eb2e8f9f7	1451	#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ADC_EXTERNALTRIGINJEC_T2_TRGO
<>	144:ef7eb2e8f9f7	1452	#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ADC_EXTERNALTRIGINJEC_T3_CC4
<>	144:ef7eb2e8f9f7	1453	#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ADC_EXTERNALTRIGINJEC_T4_TRGO
<>	144:ef7eb2e8f9f7	1454	#define ADC_EXTERNALTRIGINJECCONV_T19_CC1 ADC_EXTERNALTRIGINJEC_T19_CC1
<>	144:ef7eb2e8f9f7	1455	#define ADC_EXTERNALTRIGINJECCONV_T19_CC2 ADC_EXTERNALTRIGINJEC_T19_CC2
<>	144:ef7eb2e8f9f7	1456	#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ADC_EXTERNALTRIGINJEC_EXT_IT15
<>	144:ef7eb2e8f9f7	1457	#define ADC_INJECTED_SOFTWARE_START ADC_JSWSTART
<>	144:ef7eb2e8f9f7	1458	/**
<>	144:ef7eb2e8f9f7	1459	* @}
<>	144:ef7eb2e8f9f7	1460	*/
<>	144:ef7eb2e8f9f7	1461
<>	144:ef7eb2e8f9f7	1462
<>	144:ef7eb2e8f9f7	1463	/** @defgroup ADCEx_analog_watchdog_mode ADC Extended analog watchdog mode
<>	144:ef7eb2e8f9f7	1464	* @{
<>	144:ef7eb2e8f9f7	1465	*/
<>	144:ef7eb2e8f9f7	1466	#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	1467	#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN))
<>	144:ef7eb2e8f9f7	1468	#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_JAWDEN))
<>	144:ef7eb2e8f9f7	1469	#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
<>	144:ef7eb2e8f9f7	1470	#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN)
<>	144:ef7eb2e8f9f7	1471	#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN)
<>	144:ef7eb2e8f9f7	1472	#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
<>	144:ef7eb2e8f9f7	1473	/**
<>	144:ef7eb2e8f9f7	1474	* @}
<>	144:ef7eb2e8f9f7	1475	*/
<>	144:ef7eb2e8f9f7	1476
<>	144:ef7eb2e8f9f7	1477	/** @defgroup ADC_conversion_group ADC Conversion Group
<>	144:ef7eb2e8f9f7	1478	* @{
<>	144:ef7eb2e8f9f7	1479	*/
<>	144:ef7eb2e8f9f7	1480	#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
<>	144:ef7eb2e8f9f7	1481	#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
<>	144:ef7eb2e8f9f7	1482	#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC \| ADC_FLAG_JEOC))
<>	144:ef7eb2e8f9f7	1483	/**
<>	144:ef7eb2e8f9f7	1484	* @}
<>	144:ef7eb2e8f9f7	1485	*/
<>	144:ef7eb2e8f9f7	1486
<>	144:ef7eb2e8f9f7	1487	/** @defgroup ADCEx_Event_type ADC Extended Event Type
<>	144:ef7eb2e8f9f7	1488	* @{
<>	144:ef7eb2e8f9f7	1489	*/
<>	144:ef7eb2e8f9f7	1490	#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /!< ADC Analog watchdog event /
<>	144:ef7eb2e8f9f7	1491	/**
<>	144:ef7eb2e8f9f7	1492	* @}
<>	144:ef7eb2e8f9f7	1493	*/
<>	144:ef7eb2e8f9f7	1494
<>	144:ef7eb2e8f9f7	1495	/** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition
<>	144:ef7eb2e8f9f7	1496	* @{
<>	144:ef7eb2e8f9f7	1497	*/
<>	144:ef7eb2e8f9f7	1498	#define ADC_IT_EOC ADC_CR1_EOCIE /!< ADC End of Regular Conversion interrupt source /
<>	144:ef7eb2e8f9f7	1499	#define ADC_IT_JEOC ADC_CR1_JEOCIE /!< ADC End of Injected Conversion interrupt source /
<>	144:ef7eb2e8f9f7	1500	#define ADC_IT_AWD ADC_CR1_AWDIE /!< ADC Analog watchdog interrupt source /
<>	144:ef7eb2e8f9f7	1501	/**
<>	144:ef7eb2e8f9f7	1502	* @}
<>	144:ef7eb2e8f9f7	1503	*/
<>	144:ef7eb2e8f9f7	1504
<>	144:ef7eb2e8f9f7	1505	/** @defgroup ADCEx_flags_definition ADC Extended Flags Definition
<>	144:ef7eb2e8f9f7	1506	* @{
<>	144:ef7eb2e8f9f7	1507	*/
<>	144:ef7eb2e8f9f7	1508	#define ADC_FLAG_AWD ADC_SR_AWD /!< ADC Analog watchdog flag /
<>	144:ef7eb2e8f9f7	1509	#define ADC_FLAG_EOC ADC_SR_EOC /!< ADC End of Regular conversion flag /
<>	144:ef7eb2e8f9f7	1510	#define ADC_FLAG_JEOC ADC_SR_JEOC /!< ADC End of Injected conversion flag /
<>	144:ef7eb2e8f9f7	1511	#define ADC_FLAG_JSTRT ADC_SR_JSTRT /!< ADC Injected group start flag /
<>	144:ef7eb2e8f9f7	1512	#define ADC_FLAG_STRT ADC_SR_STRT /!< ADC Regular group start flag /
<>	144:ef7eb2e8f9f7	1513
<>	144:ef7eb2e8f9f7	1514	/**
<>	144:ef7eb2e8f9f7	1515	* @}
<>	144:ef7eb2e8f9f7	1516	*/
<>	144:ef7eb2e8f9f7	1517	#endif /* STM32F373xC \|\| STM32F378xx */
<>	144:ef7eb2e8f9f7	1518
<>	144:ef7eb2e8f9f7	1519	/**
<>	144:ef7eb2e8f9f7	1520	* @}
<>	144:ef7eb2e8f9f7	1521	*/
<>	144:ef7eb2e8f9f7	1522
<>	144:ef7eb2e8f9f7	1523
<>	144:ef7eb2e8f9f7	1524
<>	144:ef7eb2e8f9f7	1525	/* Private constants ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1526
<>	144:ef7eb2e8f9f7	1527	/** @addtogroup ADCEx_Private_Constants ADCEx Private Constants
<>	144:ef7eb2e8f9f7	1528	* @{
<>	144:ef7eb2e8f9f7	1529	*/
<>	144:ef7eb2e8f9f7	1530
<>	144:ef7eb2e8f9f7	1531	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	1532	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	1533	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	1534	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	1535
<>	144:ef7eb2e8f9f7	1536
<>	144:ef7eb2e8f9f7	1537	/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group
<>	144:ef7eb2e8f9f7	1538	* @{
<>	144:ef7eb2e8f9f7	1539	*/
<>	144:ef7eb2e8f9f7	1540	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	1541	defined(STM32F303xC) \|\| defined(STM32F358xx)
<>	144:ef7eb2e8f9f7	1542	/* List of external triggers for common groups ADC1&ADC2 and/or ADC3&ADC4: */
<>	144:ef7eb2e8f9f7	1543	/* (used internally by HAL driver. To not use into HAL structure parameters) */
<>	144:ef7eb2e8f9f7	1544
<>	144:ef7eb2e8f9f7	1545	/* External triggers of regular group for ADC1 & ADC2 */
<>	144:ef7eb2e8f9f7	1546	#define ADC1_2_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	1547	#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
<>	144:ef7eb2e8f9f7	1548	#define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
<>	144:ef7eb2e8f9f7	1549	#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1550	#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
<>	144:ef7eb2e8f9f7	1551	#define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1552	#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1))
<>	144:ef7eb2e8f9f7	1553	#define ADC1_2_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1554	#define ADC1_2_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3)
<>	144:ef7eb2e8f9f7	1555	#define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1556	#define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_1))
<>	144:ef7eb2e8f9f7	1557	#define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1558	#define ADC1_2_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2))
<>	144:ef7eb2e8f9f7	1559	#define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1560	#define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1))
<>	144:ef7eb2e8f9f7	1561	#define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL)
<>	144:ef7eb2e8f9f7	1562
<>	144:ef7eb2e8f9f7	1563	/* External triggers of regular group for ADC3 & ADC4 */
<>	144:ef7eb2e8f9f7	1564	#define ADC3_4_EXTERNALTRIG_T3_CC1 ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	1565	#define ADC3_4_EXTERNALTRIG_T2_CC3 ((uint32_t)ADC_CFGR_EXTSEL_0)
<>	144:ef7eb2e8f9f7	1566	#define ADC3_4_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
<>	144:ef7eb2e8f9f7	1567	#define ADC3_4_EXTERNALTRIG_T8_CC1 ((uint32_t)(ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1568	#define ADC3_4_EXTERNALTRIG_T8_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
<>	144:ef7eb2e8f9f7	1569	#define ADC3_4_EXTERNALTRIG_EXT_IT2 ((uint32_t)(ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1570	#define ADC3_4_EXTERNALTRIG_T4_CC1 ((uint32_t)(ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1))
<>	144:ef7eb2e8f9f7	1571	#define ADC3_4_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1572	#define ADC3_4_EXTERNALTRIG_T8_TRGO2 ((uint32_t)ADC_CFGR_EXTSEL_3)
<>	144:ef7eb2e8f9f7	1573	#define ADC3_4_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1574	#define ADC3_4_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_1))
<>	144:ef7eb2e8f9f7	1575	#define ADC3_4_EXTERNALTRIG_T3_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1576	#define ADC3_4_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2))
<>	144:ef7eb2e8f9f7	1577	#define ADC3_4_EXTERNALTRIG_T7_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1578	#define ADC3_4_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1))
<>	144:ef7eb2e8f9f7	1579	#define ADC3_4_EXTERNALTRIG_T2_CC1 ((uint32_t)ADC_CFGR_EXTSEL)
<>	144:ef7eb2e8f9f7	1580	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	1581	/* STM32F303xC \|\| STM32F358xx */
<>	144:ef7eb2e8f9f7	1582
<>	144:ef7eb2e8f9f7	1583	#if defined(STM32F302xE) \|\| \
<>	144:ef7eb2e8f9f7	1584	defined(STM32F302xC)
<>	144:ef7eb2e8f9f7	1585	/* List of external triggers of common group ADC1&ADC2: */
<>	144:ef7eb2e8f9f7	1586	/* (used internally by HAL driver. To not use into HAL structure parameters) */
<>	144:ef7eb2e8f9f7	1587	#define ADC1_2_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	1588	#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
<>	144:ef7eb2e8f9f7	1589	#define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
<>	144:ef7eb2e8f9f7	1590	#define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1591	#define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_1))
<>	144:ef7eb2e8f9f7	1592	#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1593	#define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1594	#define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL)
<>	144:ef7eb2e8f9f7	1595	#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
<>	144:ef7eb2e8f9f7	1596	#define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1597	#define ADC1_2_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2))
<>	144:ef7eb2e8f9f7	1598	#define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1599	#define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1))
<>	144:ef7eb2e8f9f7	1600	#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1))
<>	144:ef7eb2e8f9f7	1601	#endif /* STM32F302xE \|\| */
<>	144:ef7eb2e8f9f7	1602	/* STM32F302xC */
<>	144:ef7eb2e8f9f7	1603
<>	144:ef7eb2e8f9f7	1604	#if defined(STM32F303x8) \|\| defined(STM32F328xx)
<>	144:ef7eb2e8f9f7	1605	/* List of external triggers of common group ADC1&ADC2: */
<>	144:ef7eb2e8f9f7	1606	/* (used internally by HAL driver. To not use into HAL structure parameters) */
<>	144:ef7eb2e8f9f7	1607	#define ADC1_2_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	1608	#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
<>	144:ef7eb2e8f9f7	1609	#define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
<>	144:ef7eb2e8f9f7	1610	#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1611	#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
<>	144:ef7eb2e8f9f7	1612	#define ADC1_2_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1613	#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1))
<>	144:ef7eb2e8f9f7	1614	#define ADC1_2_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1615	#define ADC1_2_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3)
<>	144:ef7eb2e8f9f7	1616	#define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1617	#define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_1))
<>	144:ef7eb2e8f9f7	1618	#define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1619	#define ADC1_2_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2))
<>	144:ef7eb2e8f9f7	1620	#define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1621	#define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1))
<>	144:ef7eb2e8f9f7	1622	#define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL)
<>	144:ef7eb2e8f9f7	1623	#endif /* STM32F303x8 \|\| STM32F328xx */
<>	144:ef7eb2e8f9f7	1624
<>	144:ef7eb2e8f9f7	1625	#if defined(STM32F334x8)
<>	144:ef7eb2e8f9f7	1626	/* List of external triggers of common group ADC1&ADC2: */
<>	144:ef7eb2e8f9f7	1627	/* (used internally by HAL driver. To not use into HAL structure parameters) */
<>	144:ef7eb2e8f9f7	1628	#define ADC1_2_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	1629	#define ADC1_2_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
<>	144:ef7eb2e8f9f7	1630	#define ADC1_2_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
<>	144:ef7eb2e8f9f7	1631	#define ADC1_2_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1632	#define ADC1_2_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
<>	144:ef7eb2e8f9f7	1633	#define ADC1_2_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1))
<>	144:ef7eb2e8f9f7	1634	#define ADC1_2_EXTERNALTRIG_HRTIM_TRG1 ((uint32_t)(ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1635	#define ADC1_2_EXTERNALTRIG_HRTIM_TRG3 ((uint32_t) ADC_CFGR_EXTSEL_3)
<>	144:ef7eb2e8f9f7	1636	#define ADC1_2_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1637	#define ADC1_2_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_1))
<>	144:ef7eb2e8f9f7	1638	#define ADC1_2_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1639	#define ADC1_2_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1640	#define ADC1_2_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1))
<>	144:ef7eb2e8f9f7	1641	#define ADC1_2_EXTERNALTRIG_T3_CC4 ((uint32_t)ADC_CFGR_EXTSEL)
<>	144:ef7eb2e8f9f7	1642	#endif /* STM32F334x8 */
<>	144:ef7eb2e8f9f7	1643
<>	144:ef7eb2e8f9f7	1644	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	1645	/* List of external triggers of regular group for ADC1: */
<>	144:ef7eb2e8f9f7	1646	/* (used internally by HAL driver. To not use into HAL structure parameters) */
<>	144:ef7eb2e8f9f7	1647	#define ADC1_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	1648	#define ADC1_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
<>	144:ef7eb2e8f9f7	1649	#define ADC1_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
<>	144:ef7eb2e8f9f7	1650	#define ADC1_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1))
<>	144:ef7eb2e8f9f7	1651	#define ADC1_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1652	#define ADC1_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_1))
<>	144:ef7eb2e8f9f7	1653	#define ADC1_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_1 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1654	#define ADC1_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1655	#define ADC1_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 \| ADC_CFGR_EXTSEL_2 \| ADC_CFGR_EXTSEL_1))
<>	144:ef7eb2e8f9f7	1656	#define ADC_SOFTWARE_START ((uint32_t)0x00000001)
<>	144:ef7eb2e8f9f7	1657	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	1658	/**
<>	144:ef7eb2e8f9f7	1659	* @}
<>	144:ef7eb2e8f9f7	1660	*/
<>	144:ef7eb2e8f9f7	1661
<>	144:ef7eb2e8f9f7	1662
<>	144:ef7eb2e8f9f7	1663	/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group
<>	144:ef7eb2e8f9f7	1664	* @{
<>	144:ef7eb2e8f9f7	1665	*/
<>	144:ef7eb2e8f9f7	1666	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	1667	defined(STM32F303xC) \|\| defined(STM32F358xx)
<>	144:ef7eb2e8f9f7	1668	/* List of external triggers sorted of groups ADC1&ADC2 and/or ADC3&ADC4: */
<>	144:ef7eb2e8f9f7	1669	/* (used internally by HAL driver. To not use into HAL structure parameters) */
<>	144:ef7eb2e8f9f7	1670
<>	144:ef7eb2e8f9f7	1671	/* External triggers for injected groups of ADC1 & ADC2 */
<>	144:ef7eb2e8f9f7	1672	#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	1673	#define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
<>	144:ef7eb2e8f9f7	1674	#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
<>	144:ef7eb2e8f9f7	1675	#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1676	#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
<>	144:ef7eb2e8f9f7	1677	#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1678	#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1))
<>	144:ef7eb2e8f9f7	1679	#define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1680	#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
<>	144:ef7eb2e8f9f7	1681	#define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1682	#define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_1))
<>	144:ef7eb2e8f9f7	1683	#define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1684	#define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2))
<>	144:ef7eb2e8f9f7	1685	#define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1686	#define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1))
<>	144:ef7eb2e8f9f7	1687	#define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
<>	144:ef7eb2e8f9f7	1688
<>	144:ef7eb2e8f9f7	1689	/* External triggers for injected groups of ADC3 & ADC4 */
<>	144:ef7eb2e8f9f7	1690	/* Note: External triggers JEXT2 and JEXT5 are the same (TIM4_CC3 event). */
<>	144:ef7eb2e8f9f7	1691	/* JEXT2 is the main trigger, JEXT5 could be redirected to another */
<>	144:ef7eb2e8f9f7	1692	/* in future devices. */
<>	144:ef7eb2e8f9f7	1693	/* However, this channel is implemented with a SW offset of 0x10000 for */
<>	144:ef7eb2e8f9f7	1694	/* differentiation between similar triggers of common groups ADC1&ADC2, */
<>	144:ef7eb2e8f9f7	1695	/* ADC3&ADC4 (Differentiation processed into macro */
<>	144:ef7eb2e8f9f7	1696	/* ADC_JSQR_JEXTSEL_SET) */
<>	144:ef7eb2e8f9f7	1697	#define ADC3_4_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	1698	#define ADC3_4_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
<>	144:ef7eb2e8f9f7	1699	#define ADC3_4_EXTERNALTRIGINJEC_T4_CC3 ((uint32_t)ADC_JSQR_JEXTSEL_1 \| 0x10000)
<>	144:ef7eb2e8f9f7	1700	#define ADC3_4_EXTERNALTRIGINJEC_T8_CC2 ((uint32_t)(ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1701	#define ADC3_4_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
<>	144:ef7eb2e8f9f7	1702
<>	144:ef7eb2e8f9f7	1703	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
<>	144:ef7eb2e8f9f7	1704	#define ADC3_4_EXTERNALTRIGINJEC_T20_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1705	#endif /* STM32F303xE \|\| STM32F398xx */
<>	144:ef7eb2e8f9f7	1706
<>	144:ef7eb2e8f9f7	1707	#define ADC3_4_EXTERNALTRIGINJEC_T4_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1))
<>	144:ef7eb2e8f9f7	1708	#define ADC3_4_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1709	#define ADC3_4_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
<>	144:ef7eb2e8f9f7	1710	#define ADC3_4_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1711	#define ADC3_4_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_1))
<>	144:ef7eb2e8f9f7	1712	#define ADC3_4_EXTERNALTRIGINJEC_T1_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1713	#define ADC3_4_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2))
<>	144:ef7eb2e8f9f7	1714	#define ADC3_4_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1715	#define ADC3_4_EXTERNALTRIGINJEC_T7_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1))
<>	144:ef7eb2e8f9f7	1716	#define ADC3_4_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
<>	144:ef7eb2e8f9f7	1717	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	1718	/* STM32F303xC \|\| STM32F358xx */
<>	144:ef7eb2e8f9f7	1719
<>	144:ef7eb2e8f9f7	1720	#if defined(STM32F302xE) \|\| \
<>	144:ef7eb2e8f9f7	1721	defined(STM32F302xC)
<>	144:ef7eb2e8f9f7	1722	/* List of external triggers of group ADC1&ADC2: */
<>	144:ef7eb2e8f9f7	1723	/* (used internally by HAL driver. To not use into HAL structure parameters) */
<>	144:ef7eb2e8f9f7	1724	#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	1725	#define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
<>	144:ef7eb2e8f9f7	1726	#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
<>	144:ef7eb2e8f9f7	1727	#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1728	#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
<>	144:ef7eb2e8f9f7	1729	#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1730	#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1))
<>	144:ef7eb2e8f9f7	1731	#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
<>	144:ef7eb2e8f9f7	1732	#define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1733	#define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2))
<>	144:ef7eb2e8f9f7	1734	#define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1735	#define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1))
<>	144:ef7eb2e8f9f7	1736	#define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
<>	144:ef7eb2e8f9f7	1737	#endif /* STM32F302xE \|\| */
<>	144:ef7eb2e8f9f7	1738	/* STM32F302xC */
<>	144:ef7eb2e8f9f7	1739
<>	144:ef7eb2e8f9f7	1740	#if defined(STM32F303x8) \|\| defined(STM32F328xx)
<>	144:ef7eb2e8f9f7	1741	/* List of external triggers of group ADC1&ADC2: */
<>	144:ef7eb2e8f9f7	1742	/* (used internally by HAL driver. To not use into HAL structure parameters) */
<>	144:ef7eb2e8f9f7	1743	#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	1744	#define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
<>	144:ef7eb2e8f9f7	1745	#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
<>	144:ef7eb2e8f9f7	1746	#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1747	#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
<>	144:ef7eb2e8f9f7	1748	#define ADC1_2_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1749	#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1))
<>	144:ef7eb2e8f9f7	1750	#define ADC1_2_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1751	#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
<>	144:ef7eb2e8f9f7	1752	#define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1753	#define ADC1_2_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_1))
<>	144:ef7eb2e8f9f7	1754	#define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1755	#define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2))
<>	144:ef7eb2e8f9f7	1756	#define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1757	#define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1))
<>	144:ef7eb2e8f9f7	1758	#define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
<>	144:ef7eb2e8f9f7	1759	#endif /* STM32F303x8 \|\| STM32F328xx */
<>	144:ef7eb2e8f9f7	1760
<>	144:ef7eb2e8f9f7	1761	#if defined(STM32F334x8)
<>	144:ef7eb2e8f9f7	1762	/* List of external triggers of group ADC1&ADC2: */
<>	144:ef7eb2e8f9f7	1763	/* (used internally by HAL driver. To not use into HAL structure parameters) */
<>	144:ef7eb2e8f9f7	1764	#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	1765	#define ADC1_2_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
<>	144:ef7eb2e8f9f7	1766	#define ADC1_2_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1)
<>	144:ef7eb2e8f9f7	1767	#define ADC1_2_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1768	#define ADC1_2_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2)
<>	144:ef7eb2e8f9f7	1769	#define ADC1_2_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1))
<>	144:ef7eb2e8f9f7	1770	#define ADC1_2_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
<>	144:ef7eb2e8f9f7	1771	#define ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1772	#define ADC1_2_EXTERNALTRIGINJEC_HRTIM_TRG4 ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_1))
<>	144:ef7eb2e8f9f7	1773	#define ADC1_2_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1774	#define ADC1_2_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2))
<>	144:ef7eb2e8f9f7	1775	#define ADC1_2_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1776	#define ADC1_2_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1))
<>	144:ef7eb2e8f9f7	1777	#define ADC1_2_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
<>	144:ef7eb2e8f9f7	1778	#endif /* STM32F334x8 */
<>	144:ef7eb2e8f9f7	1779
<>	144:ef7eb2e8f9f7	1780	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	1781	/* List of external triggers of injected group for ADC1: */
<>	144:ef7eb2e8f9f7	1782	/* (used internally by HAL driver. To not use into HAL structure parameters) */
<>	144:ef7eb2e8f9f7	1783	#define ADC1_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	1784	#define ADC1_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0)
<>	144:ef7eb2e8f9f7	1785	#define ADC1_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1))
<>	144:ef7eb2e8f9f7	1786	#define ADC1_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3)
<>	144:ef7eb2e8f9f7	1787	#define ADC1_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1))
<>	144:ef7eb2e8f9f7	1788	#define ADC1_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL)
<>	144:ef7eb2e8f9f7	1789	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	1790	/**
<>	144:ef7eb2e8f9f7	1791	* @}
<>	144:ef7eb2e8f9f7	1792	*/
<>	144:ef7eb2e8f9f7	1793
<>	144:ef7eb2e8f9f7	1794	#define ADC_FLAG_ALL (ADC_FLAG_RDY \| ADC_FLAG_EOSMP \| ADC_FLAG_EOC \| ADC_FLAG_EOS \| \
<>	144:ef7eb2e8f9f7	1795	ADC_FLAG_JEOC \| ADC_FLAG_JEOS \| ADC_FLAG_OVR \| ADC_FLAG_AWD1 \| \
<>	144:ef7eb2e8f9f7	1796	ADC_FLAG_AWD2 \| ADC_FLAG_AWD3 \| ADC_FLAG_JQOVF)
<>	144:ef7eb2e8f9f7	1797
<>	144:ef7eb2e8f9f7	1798	/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
<>	144:ef7eb2e8f9f7	1799	#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_JEOC \| ADC_FLAG_JEOS \| \
<>	144:ef7eb2e8f9f7	1800	ADC_FLAG_OVR \| ADC_FLAG_AWD1 \| ADC_FLAG_AWD2 \| ADC_FLAG_AWD3 \| \
<>	144:ef7eb2e8f9f7	1801	ADC_FLAG_JQOVF)
<>	144:ef7eb2e8f9f7	1802
<>	144:ef7eb2e8f9f7	1803	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	1804	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	1805	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	1806	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	1807
<>	144:ef7eb2e8f9f7	1808
<>	144:ef7eb2e8f9f7	1809	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
<>	144:ef7eb2e8f9f7	1810
<>	144:ef7eb2e8f9f7	1811	/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Regular ADC Extended Internal HAL driver trigger selection for regular group
<>	144:ef7eb2e8f9f7	1812	* @{
<>	144:ef7eb2e8f9f7	1813	*/
<>	144:ef7eb2e8f9f7	1814	/* List of external triggers of regular group for ADC1: */
<>	144:ef7eb2e8f9f7	1815	/* (used internally by HAL driver. To not use into HAL structure parameters) */
<>	144:ef7eb2e8f9f7	1816
<>	144:ef7eb2e8f9f7	1817	/* External triggers of regular group for ADC1 */
<>	144:ef7eb2e8f9f7	1818	#define ADC_EXTERNALTRIG_T19_TRGO ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	1819	#define ADC_EXTERNALTRIG_T19_CC3 ((uint32_t)ADC_CR2_EXTSEL_0)
<>	144:ef7eb2e8f9f7	1820	#define ADC_EXTERNALTRIG_T19_CC4 ((uint32_t)ADC_CR2_EXTSEL_1)
<>	144:ef7eb2e8f9f7	1821	#define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1822	#define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_2)
<>	144:ef7eb2e8f9f7	1823	#define ADC_EXTERNALTRIG_T4_CC2 ((uint32_t)(ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1824	#define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1))
<>	144:ef7eb2e8f9f7	1825	#define ADC_SWSTART ((uint32_t)(ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
<>	144:ef7eb2e8f9f7	1826	/**
<>	144:ef7eb2e8f9f7	1827	* @}
<>	144:ef7eb2e8f9f7	1828	*/
<>	144:ef7eb2e8f9f7	1829
<>	144:ef7eb2e8f9f7	1830	/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADC Extended Internal HAL driver trigger selection for injected group
<>	144:ef7eb2e8f9f7	1831	* @{
<>	144:ef7eb2e8f9f7	1832	*/
<>	144:ef7eb2e8f9f7	1833	/* List of external triggers of injected group for ADC1: */
<>	144:ef7eb2e8f9f7	1834	/* (used internally by HAL driver. To not use into HAL structure parameters) */
<>	144:ef7eb2e8f9f7	1835
<>	144:ef7eb2e8f9f7	1836	/* External triggers of injected group for ADC1 */
<>	144:ef7eb2e8f9f7	1837	#define ADC_EXTERNALTRIGINJEC_T19_CC1 ((uint32_t) 0x00000000)
<>	144:ef7eb2e8f9f7	1838	#define ADC_EXTERNALTRIGINJEC_T19_CC2 ((uint32_t) ADC_CR2_JEXTSEL_0)
<>	144:ef7eb2e8f9f7	1839	#define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t) ADC_CR2_JEXTSEL_1)
<>	144:ef7eb2e8f9f7	1840	#define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 \| ADC_CR2_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1841	#define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t) ADC_CR2_JEXTSEL_2)
<>	144:ef7eb2e8f9f7	1842	#define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 \| ADC_CR2_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1843	#define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_CR2_JEXTSEL_2 \| ADC_CR2_JEXTSEL_1))
<>	144:ef7eb2e8f9f7	1844	#define ADC_JSWSTART ((uint32_t)(ADC_CR2_JEXTSEL_2 \| ADC_CR2_JEXTSEL_1 \| ADC_CR2_JEXTSEL_0))
<>	144:ef7eb2e8f9f7	1845	/**
<>	144:ef7eb2e8f9f7	1846	* @}
<>	144:ef7eb2e8f9f7	1847	*/
<>	144:ef7eb2e8f9f7	1848
<>	144:ef7eb2e8f9f7	1849	/** @defgroup ADCEx_sampling_times_all_channels ADC Extended Sampling Times All Channels
<>	144:ef7eb2e8f9f7	1850	* @{
<>	144:ef7eb2e8f9f7	1851	*/
<>	144:ef7eb2e8f9f7	1852	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
<>	144:ef7eb2e8f9f7	1853	(ADC_SMPR2_SMP9_2 \| ADC_SMPR2_SMP8_2 \| ADC_SMPR2_SMP7_2 \| ADC_SMPR2_SMP6_2 \| \
<>	144:ef7eb2e8f9f7	1854	ADC_SMPR2_SMP5_2 \| ADC_SMPR2_SMP4_2 \| ADC_SMPR2_SMP3_2 \| ADC_SMPR2_SMP2_2 \| \
<>	144:ef7eb2e8f9f7	1855	ADC_SMPR2_SMP1_2 \| ADC_SMPR2_SMP0_2)
<>	144:ef7eb2e8f9f7	1856	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
<>	144:ef7eb2e8f9f7	1857	(ADC_SMPR1_SMP17_2 \| ADC_SMPR1_SMP16_2 \| ADC_SMPR1_SMP15_2 \| ADC_SMPR1_SMP14_2 \| \
<>	144:ef7eb2e8f9f7	1858	ADC_SMPR1_SMP13_2 \| ADC_SMPR1_SMP12_2 \| ADC_SMPR1_SMP11_2 \| ADC_SMPR1_SMP10_2 )
<>	144:ef7eb2e8f9f7	1859
<>	144:ef7eb2e8f9f7	1860	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
<>	144:ef7eb2e8f9f7	1861	(ADC_SMPR2_SMP9_1 \| ADC_SMPR2_SMP8_1 \| ADC_SMPR2_SMP7_1 \| ADC_SMPR2_SMP6_1 \| \
<>	144:ef7eb2e8f9f7	1862	ADC_SMPR2_SMP5_1 \| ADC_SMPR2_SMP4_1 \| ADC_SMPR2_SMP3_1 \| ADC_SMPR2_SMP2_1 \| \
<>	144:ef7eb2e8f9f7	1863	ADC_SMPR2_SMP1_1 \| ADC_SMPR2_SMP0_1)
<>	144:ef7eb2e8f9f7	1864	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
<>	144:ef7eb2e8f9f7	1865	(ADC_SMPR1_SMP17_1 \| ADC_SMPR1_SMP16_1 \| ADC_SMPR1_SMP15_1 \| ADC_SMPR1_SMP14_1 \| \
<>	144:ef7eb2e8f9f7	1866	ADC_SMPR1_SMP13_1 \| ADC_SMPR1_SMP12_1 \| ADC_SMPR1_SMP11_1 \| ADC_SMPR1_SMP10_1 )
<>	144:ef7eb2e8f9f7	1867
<>	144:ef7eb2e8f9f7	1868	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
<>	144:ef7eb2e8f9f7	1869	(ADC_SMPR2_SMP9_0 \| ADC_SMPR2_SMP8_0 \| ADC_SMPR2_SMP7_0 \| ADC_SMPR2_SMP6_0 \| \
<>	144:ef7eb2e8f9f7	1870	ADC_SMPR2_SMP5_0 \| ADC_SMPR2_SMP4_0 \| ADC_SMPR2_SMP3_0 \| ADC_SMPR2_SMP2_0 \| \
<>	144:ef7eb2e8f9f7	1871	ADC_SMPR2_SMP1_0 \| ADC_SMPR2_SMP0_0)
<>	144:ef7eb2e8f9f7	1872	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
<>	144:ef7eb2e8f9f7	1873	(ADC_SMPR1_SMP17_0 \| ADC_SMPR1_SMP16_0 \| ADC_SMPR1_SMP15_0 \| ADC_SMPR1_SMP14_0 \| \
<>	144:ef7eb2e8f9f7	1874	ADC_SMPR1_SMP13_0 \| ADC_SMPR1_SMP12_0 \| ADC_SMPR1_SMP11_0 \| ADC_SMPR1_SMP10_0 )
<>	144:ef7eb2e8f9f7	1875
<>	144:ef7eb2e8f9f7	1876	#define ADC_SAMPLETIME_1CYCLE5_SMPR2ALLCHANNELS ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	1877	#define ADC_SAMPLETIME_7CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
<>	144:ef7eb2e8f9f7	1878	#define ADC_SAMPLETIME_13CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
<>	144:ef7eb2e8f9f7	1879	#define ADC_SAMPLETIME_28CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
<>	144:ef7eb2e8f9f7	1880	#define ADC_SAMPLETIME_41CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2)
<>	144:ef7eb2e8f9f7	1881	#define ADC_SAMPLETIME_55CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
<>	144:ef7eb2e8f9f7	1882	#define ADC_SAMPLETIME_71CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1)
<>	144:ef7eb2e8f9f7	1883	#define ADC_SAMPLETIME_239CYCLES5_SMPR2ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0)
<>	144:ef7eb2e8f9f7	1884
<>	144:ef7eb2e8f9f7	1885	#define ADC_SAMPLETIME_1CYCLE5_SMPR1ALLCHANNELS ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	1886	#define ADC_SAMPLETIME_7CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
<>	144:ef7eb2e8f9f7	1887	#define ADC_SAMPLETIME_13CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
<>	144:ef7eb2e8f9f7	1888	#define ADC_SAMPLETIME_28CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
<>	144:ef7eb2e8f9f7	1889	#define ADC_SAMPLETIME_41CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2)
<>	144:ef7eb2e8f9f7	1890	#define ADC_SAMPLETIME_55CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
<>	144:ef7eb2e8f9f7	1891	#define ADC_SAMPLETIME_71CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1)
<>	144:ef7eb2e8f9f7	1892	#define ADC_SAMPLETIME_239CYCLES5_SMPR1ALLCHANNELS (ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \| ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0)
<>	144:ef7eb2e8f9f7	1893
<>	144:ef7eb2e8f9f7	1894	/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
<>	144:ef7eb2e8f9f7	1895	#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC \| ADC_FLAG_JEOC \| ADC_FLAG_AWD )
<>	144:ef7eb2e8f9f7	1896	/**
<>	144:ef7eb2e8f9f7	1897	* @}
<>	144:ef7eb2e8f9f7	1898	*/
<>	144:ef7eb2e8f9f7	1899
<>	144:ef7eb2e8f9f7	1900	#endif /* STM32F373xC \|\| STM32F378xx */
<>	144:ef7eb2e8f9f7	1901
<>	144:ef7eb2e8f9f7	1902	/**
<>	144:ef7eb2e8f9f7	1903	* @}
<>	144:ef7eb2e8f9f7	1904	*/
<>	144:ef7eb2e8f9f7	1905
<>	144:ef7eb2e8f9f7	1906	/* Exported macro ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1907
<>	144:ef7eb2e8f9f7	1908	/** @defgroup ADCEx_Exported_Macros ADCEx Exported Macros
<>	144:ef7eb2e8f9f7	1909	* @{
<>	144:ef7eb2e8f9f7	1910	*/
<>	144:ef7eb2e8f9f7	1911	/* Macro for internal HAL driver usage, and possibly can be used into code of */
<>	144:ef7eb2e8f9f7	1912	/* final user. */
<>	144:ef7eb2e8f9f7	1913
<>	144:ef7eb2e8f9f7	1914	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	1915	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	1916	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	1917	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	1918
<>	144:ef7eb2e8f9f7	1919	/**
<>	144:ef7eb2e8f9f7	1920	* @brief Enable the ADC peripheral
<>	144:ef7eb2e8f9f7	1921	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	1922	* @note ADC enable requires a delay for ADC stabilization time
<>	144:ef7eb2e8f9f7	1923	* (refer to device datasheet, parameter tSTAB)
<>	144:ef7eb2e8f9f7	1924	* @note On STM32F3 devices, some hardware constraints must be strictly
<>	144:ef7eb2e8f9f7	1925	* respected before using this macro:
<>	144:ef7eb2e8f9f7	1926	* - ADC internal voltage regulator must be preliminarily enabled.
<>	144:ef7eb2e8f9f7	1927	* This is performed by function HAL_ADC_Init().
<>	144:ef7eb2e8f9f7	1928	* - ADC state requirements: ADC must be disabled, no conversion on
<>	144:ef7eb2e8f9f7	1929	* going, no calibration on going.
<>	144:ef7eb2e8f9f7	1930	* These checks are performed by functions HAL_ADC_start_xxx().
<>	144:ef7eb2e8f9f7	1931	* @retval None
<>	144:ef7eb2e8f9f7	1932	*/
<>	144:ef7eb2e8f9f7	1933	#define __HAL_ADC_ENABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	1934	(SET_BIT((__HANDLE__)->Instance->CR, ADC_CR_ADEN))
<>	144:ef7eb2e8f9f7	1935
<>	144:ef7eb2e8f9f7	1936	/**
<>	144:ef7eb2e8f9f7	1937	* @brief Disable the ADC peripheral
<>	144:ef7eb2e8f9f7	1938	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	1939	* @note On STM32F3 devices, some hardware constraints must be strictly
<>	144:ef7eb2e8f9f7	1940	* respected before using this macro:
<>	144:ef7eb2e8f9f7	1941	* - ADC state requirements: ADC must be enabled, no conversion on
<>	144:ef7eb2e8f9f7	1942	* going.
<>	144:ef7eb2e8f9f7	1943	* These checks are performed by functions HAL_ADC_start_xxx().
<>	144:ef7eb2e8f9f7	1944	* @retval None
<>	144:ef7eb2e8f9f7	1945	*/
<>	144:ef7eb2e8f9f7	1946	#define __HAL_ADC_DISABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	1947	do{ \
<>	144:ef7eb2e8f9f7	1948	SET_BIT((__HANDLE__)->Instance->CR, ADC_CR_ADDIS); \
<>	144:ef7eb2e8f9f7	1949	__HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP \| ADC_FLAG_RDY)); \
<>	144:ef7eb2e8f9f7	1950	} while(0)
<>	144:ef7eb2e8f9f7	1951
<>	144:ef7eb2e8f9f7	1952	/**
<>	144:ef7eb2e8f9f7	1953	* @brief Enable the ADC end of conversion interrupt.
<>	144:ef7eb2e8f9f7	1954	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	1955	* @param __INTERRUPT__: ADC Interrupt
<>	144:ef7eb2e8f9f7	1956	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	1957	* @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source
<>	144:ef7eb2e8f9f7	1958	* @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
<>	144:ef7eb2e8f9f7	1959	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
<>	144:ef7eb2e8f9f7	1960	* @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
<>	144:ef7eb2e8f9f7	1961	* @arg ADC_IT_OVR: ADC overrun interrupt source
<>	144:ef7eb2e8f9f7	1962	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
<>	144:ef7eb2e8f9f7	1963	* @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source
<>	144:ef7eb2e8f9f7	1964	* @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices)
<>	144:ef7eb2e8f9f7	1965	* @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices)
<>	144:ef7eb2e8f9f7	1966	* @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices)
<>	144:ef7eb2e8f9f7	1967	* @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
<>	144:ef7eb2e8f9f7	1968	* @retval None
<>	144:ef7eb2e8f9f7	1969	*/
<>	144:ef7eb2e8f9f7	1970	#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
<>	144:ef7eb2e8f9f7	1971	(SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)))
<>	144:ef7eb2e8f9f7	1972
<>	144:ef7eb2e8f9f7	1973	/**
<>	144:ef7eb2e8f9f7	1974	* @brief Disable the ADC end of conversion interrupt.
<>	144:ef7eb2e8f9f7	1975	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	1976	* @param __INTERRUPT__: ADC Interrupt
<>	144:ef7eb2e8f9f7	1977	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	1978	* @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source
<>	144:ef7eb2e8f9f7	1979	* @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
<>	144:ef7eb2e8f9f7	1980	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
<>	144:ef7eb2e8f9f7	1981	* @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
<>	144:ef7eb2e8f9f7	1982	* @arg ADC_IT_OVR: ADC overrun interrupt source
<>	144:ef7eb2e8f9f7	1983	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
<>	144:ef7eb2e8f9f7	1984	* @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source
<>	144:ef7eb2e8f9f7	1985	* @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices)
<>	144:ef7eb2e8f9f7	1986	* @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices)
<>	144:ef7eb2e8f9f7	1987	* @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices)
<>	144:ef7eb2e8f9f7	1988	* @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
<>	144:ef7eb2e8f9f7	1989	* @retval None
<>	144:ef7eb2e8f9f7	1990	*/
<>	144:ef7eb2e8f9f7	1991	#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
<>	144:ef7eb2e8f9f7	1992	(CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)))
<>	144:ef7eb2e8f9f7	1993
<>	144:ef7eb2e8f9f7	1994	/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
<>	144:ef7eb2e8f9f7	1995	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	1996	* @param __INTERRUPT__: ADC interrupt source to check
<>	144:ef7eb2e8f9f7	1997	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	1998	* @arg ADC_IT_RDY: ADC Ready (ADRDY) interrupt source
<>	144:ef7eb2e8f9f7	1999	* @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
<>	144:ef7eb2e8f9f7	2000	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
<>	144:ef7eb2e8f9f7	2001	* @arg ADC_IT_EOS: ADC End of Regular sequence of Conversions interrupt source
<>	144:ef7eb2e8f9f7	2002	* @arg ADC_IT_OVR: ADC overrun interrupt source
<>	144:ef7eb2e8f9f7	2003	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
<>	144:ef7eb2e8f9f7	2004	* @arg ADC_IT_JEOS: ADC End of Injected sequence of Conversions interrupt source
<>	144:ef7eb2e8f9f7	2005	* @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt source (main analog watchdog, present on all STM32 devices)
<>	144:ef7eb2e8f9f7	2006	* @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt source (additional analog watchdog, present only on STM32F3 devices)
<>	144:ef7eb2e8f9f7	2007	* @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt source (additional analog watchdog, present only on STM32F3 devices)
<>	144:ef7eb2e8f9f7	2008	* @arg ADC_IT_JQOVF: ADC Injected Context Queue Overflow interrupt source
<>	144:ef7eb2e8f9f7	2009	* @retval State of interruption (SET or RESET)
<>	144:ef7eb2e8f9f7	2010	*/
<>	144:ef7eb2e8f9f7	2011	#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
<>	144:ef7eb2e8f9f7	2012	(((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	2013
<>	144:ef7eb2e8f9f7	2014	/**
<>	144:ef7eb2e8f9f7	2015	* @brief Get the selected ADC's flag status.
<>	144:ef7eb2e8f9f7	2016	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2017	* @param __FLAG__: ADC flag
<>	144:ef7eb2e8f9f7	2018	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	2019	* @arg ADC_FLAG_RDY: ADC Ready (ADRDY) flag
<>	144:ef7eb2e8f9f7	2020	* @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
<>	144:ef7eb2e8f9f7	2021	* @arg ADC_FLAG_EOC: ADC End of Regular Conversion flag
<>	144:ef7eb2e8f9f7	2022	* @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
<>	144:ef7eb2e8f9f7	2023	* @arg ADC_FLAG_OVR: ADC overrun flag
<>	144:ef7eb2e8f9f7	2024	* @arg ADC_FLAG_JEOC: ADC End of Injected Conversion flag
<>	144:ef7eb2e8f9f7	2025	* @arg ADC_FLAG_JEOS: ADC End of Injected sequence of Conversions flag
<>	144:ef7eb2e8f9f7	2026	* @arg ADC_FLAG_AWD1: ADC Analog watchdog 1 flag (main analog watchdog, present on all STM32 devices)
<>	144:ef7eb2e8f9f7	2027	* @arg ADC_FLAG_AWD2: ADC Analog watchdog 2 flag (additional analog watchdog, present only on STM32F3 devices)
<>	144:ef7eb2e8f9f7	2028	* @arg ADC_FLAG_AWD3: ADC Analog watchdog 3 flag (additional analog watchdog, present only on STM32F3 devices)
<>	144:ef7eb2e8f9f7	2029	* @arg ADC_FLAG_JQOVF: ADC Injected Context Queue Overflow flag
<>	144:ef7eb2e8f9f7	2030	* @retval None
<>	144:ef7eb2e8f9f7	2031	*/
<>	144:ef7eb2e8f9f7	2032	#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
<>	144:ef7eb2e8f9f7	2033	((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
<>	144:ef7eb2e8f9f7	2034
<>	144:ef7eb2e8f9f7	2035	/**
<>	144:ef7eb2e8f9f7	2036	* @brief Clear the ADC's pending flags
<>	144:ef7eb2e8f9f7	2037	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2038	* @param __FLAG__: ADC flag
<>	144:ef7eb2e8f9f7	2039	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	2040	* @arg ADC_FLAG_RDY: ADC Ready (ADRDY) flag
<>	144:ef7eb2e8f9f7	2041	* @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
<>	144:ef7eb2e8f9f7	2042	* @arg ADC_FLAG_EOC: ADC End of Regular Conversion flag
<>	144:ef7eb2e8f9f7	2043	* @arg ADC_FLAG_EOS: ADC End of Regular sequence of Conversions flag
<>	144:ef7eb2e8f9f7	2044	* @arg ADC_FLAG_OVR: ADC overrun flag
<>	144:ef7eb2e8f9f7	2045	* @arg ADC_FLAG_JEOC: ADC End of Injected Conversion flag
<>	144:ef7eb2e8f9f7	2046	* @arg ADC_FLAG_JEOS: ADC End of Injected sequence of Conversions flag
<>	144:ef7eb2e8f9f7	2047	* @arg ADC_FLAG_AWD1: ADC Analog watchdog 1 flag (main analog watchdog, present on all STM32 devices)
<>	144:ef7eb2e8f9f7	2048	* @arg ADC_FLAG_AWD2: ADC Analog watchdog 2 flag (additional analog watchdog, present only on STM32F3 devices)
<>	144:ef7eb2e8f9f7	2049	* @arg ADC_FLAG_AWD3: ADC Analog watchdog 3 flag (additional analog watchdog, present only on STM32F3 devices)
<>	144:ef7eb2e8f9f7	2050	* @arg ADC_FLAG_JQOVF: ADC Injected Context Queue Overflow flag
<>	144:ef7eb2e8f9f7	2051	* @retval None
<>	144:ef7eb2e8f9f7	2052	*/
<>	144:ef7eb2e8f9f7	2053	/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of */
<>	144:ef7eb2e8f9f7	2054	/* register ISR). */
<>	144:ef7eb2e8f9f7	2055	#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
<>	144:ef7eb2e8f9f7	2056	(WRITE_REG((__HANDLE__)->Instance->ISR, (__FLAG__)))
<>	144:ef7eb2e8f9f7	2057
<>	144:ef7eb2e8f9f7	2058	/** @brief Reset ADC handle state
<>	144:ef7eb2e8f9f7	2059	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2060	* @retval None
<>	144:ef7eb2e8f9f7	2061	*/
<>	144:ef7eb2e8f9f7	2062	#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2063	((__HANDLE__)->State = HAL_ADC_STATE_RESET)
<>	144:ef7eb2e8f9f7	2064	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	2065	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	2066	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	2067	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	2068
<>	144:ef7eb2e8f9f7	2069
<>	144:ef7eb2e8f9f7	2070	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
<>	144:ef7eb2e8f9f7	2071
<>	144:ef7eb2e8f9f7	2072	/**
<>	144:ef7eb2e8f9f7	2073	* @brief Enable the ADC peripheral
<>	144:ef7eb2e8f9f7	2074	* @note ADC enable requires a delay for ADC stabilization time
<>	144:ef7eb2e8f9f7	2075	* (refer to device datasheet, parameter tSTAB)
<>	144:ef7eb2e8f9f7	2076	* @note On STM32F37x devices, if ADC is already enabled this macro trigs
<>	144:ef7eb2e8f9f7	2077	* a conversion SW start on regular group.
<>	144:ef7eb2e8f9f7	2078	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2079	* @retval None
<>	144:ef7eb2e8f9f7	2080	*/
<>	144:ef7eb2e8f9f7	2081	#define __HAL_ADC_ENABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2082	(SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
<>	144:ef7eb2e8f9f7	2083
<>	144:ef7eb2e8f9f7	2084	/**
<>	144:ef7eb2e8f9f7	2085	* @brief Disable the ADC peripheral
<>	144:ef7eb2e8f9f7	2086	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2087	* @retval None
<>	144:ef7eb2e8f9f7	2088	*/
<>	144:ef7eb2e8f9f7	2089	#define __HAL_ADC_DISABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2090	(CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
<>	144:ef7eb2e8f9f7	2091
<>	144:ef7eb2e8f9f7	2092	/** @brief Enable the ADC end of conversion interrupt.
<>	144:ef7eb2e8f9f7	2093	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2094	* @param __INTERRUPT__: ADC Interrupt
<>	144:ef7eb2e8f9f7	2095	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	2096	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
<>	144:ef7eb2e8f9f7	2097	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
<>	144:ef7eb2e8f9f7	2098	* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
<>	144:ef7eb2e8f9f7	2099	* @retval None
<>	144:ef7eb2e8f9f7	2100	*/
<>	144:ef7eb2e8f9f7	2101	#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
<>	144:ef7eb2e8f9f7	2102	(SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
<>	144:ef7eb2e8f9f7	2103
<>	144:ef7eb2e8f9f7	2104	/** @brief Disable the ADC end of conversion interrupt.
<>	144:ef7eb2e8f9f7	2105	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2106	* @param __INTERRUPT__: ADC Interrupt
<>	144:ef7eb2e8f9f7	2107	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	2108	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
<>	144:ef7eb2e8f9f7	2109	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
<>	144:ef7eb2e8f9f7	2110	* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
<>	144:ef7eb2e8f9f7	2111	* @retval None
<>	144:ef7eb2e8f9f7	2112	*/
<>	144:ef7eb2e8f9f7	2113	#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
<>	144:ef7eb2e8f9f7	2114	(CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
<>	144:ef7eb2e8f9f7	2115
<>	144:ef7eb2e8f9f7	2116	/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
<>	144:ef7eb2e8f9f7	2117	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2118	* @param __INTERRUPT__: ADC interrupt source to check
<>	144:ef7eb2e8f9f7	2119	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	2120	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
<>	144:ef7eb2e8f9f7	2121	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
<>	144:ef7eb2e8f9f7	2122	* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
<>	144:ef7eb2e8f9f7	2123	* @retval State of interruption (SET or RESET)
<>	144:ef7eb2e8f9f7	2124	*/
<>	144:ef7eb2e8f9f7	2125	#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
<>	144:ef7eb2e8f9f7	2126	(((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	2127
<>	144:ef7eb2e8f9f7	2128	/** @brief Get the selected ADC's flag status.
<>	144:ef7eb2e8f9f7	2129	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2130	* @param __FLAG__: ADC flag
<>	144:ef7eb2e8f9f7	2131	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	2132	* @arg ADC_FLAG_STRT: ADC Regular group start flag
<>	144:ef7eb2e8f9f7	2133	* @arg ADC_FLAG_JSTRT: ADC Injected group start flag
<>	144:ef7eb2e8f9f7	2134	* @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
<>	144:ef7eb2e8f9f7	2135	* @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
<>	144:ef7eb2e8f9f7	2136	* @arg ADC_FLAG_AWD: ADC Analog watchdog flag
<>	144:ef7eb2e8f9f7	2137	* @retval None
<>	144:ef7eb2e8f9f7	2138	*/
<>	144:ef7eb2e8f9f7	2139	#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
<>	144:ef7eb2e8f9f7	2140	((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<>	144:ef7eb2e8f9f7	2141
<>	144:ef7eb2e8f9f7	2142	/** @brief Clear the ADC's pending flags
<>	144:ef7eb2e8f9f7	2143	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2144	* @param __FLAG__: ADC flag
<>	144:ef7eb2e8f9f7	2145	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	2146	* @arg ADC_FLAG_STRT: ADC Regular group start flag
<>	144:ef7eb2e8f9f7	2147	* @arg ADC_FLAG_JSTRT: ADC Injected group start flag
<>	144:ef7eb2e8f9f7	2148	* @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
<>	144:ef7eb2e8f9f7	2149	* @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
<>	144:ef7eb2e8f9f7	2150	* @arg ADC_FLAG_AWD: ADC Analog watchdog flag
<>	144:ef7eb2e8f9f7	2151	* @retval None
<>	144:ef7eb2e8f9f7	2152	*/
<>	144:ef7eb2e8f9f7	2153	#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
<>	144:ef7eb2e8f9f7	2154	(WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
<>	144:ef7eb2e8f9f7	2155
<>	144:ef7eb2e8f9f7	2156	/** @brief Reset ADC handle state
<>	144:ef7eb2e8f9f7	2157	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2158	* @retval None
<>	144:ef7eb2e8f9f7	2159	*/
<>	144:ef7eb2e8f9f7	2160	#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2161	((__HANDLE__)->State = HAL_ADC_STATE_RESET)
<>	144:ef7eb2e8f9f7	2162	#endif /* STM32F373xC \|\| STM32F378xx */
<>	144:ef7eb2e8f9f7	2163
<>	144:ef7eb2e8f9f7	2164	/**
<>	144:ef7eb2e8f9f7	2165	* @}
<>	144:ef7eb2e8f9f7	2166	*/
<>	144:ef7eb2e8f9f7	2167
<>	144:ef7eb2e8f9f7	2168	/* Private macro ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	2169
<>	144:ef7eb2e8f9f7	2170	/** @addtogroup ADCEx_Private_Macro ADCEx Private Macros
<>	144:ef7eb2e8f9f7	2171	* @{
<>	144:ef7eb2e8f9f7	2172	*/
<>	144:ef7eb2e8f9f7	2173	/* Macro reserved for internal HAL driver usage, not intended to be used in */
<>	144:ef7eb2e8f9f7	2174	/* code of final user. */
<>	144:ef7eb2e8f9f7	2175
<>	144:ef7eb2e8f9f7	2176	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	2177	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	2178	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	2179	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	2180
<>	144:ef7eb2e8f9f7	2181	/**
<>	144:ef7eb2e8f9f7	2182	* @brief Verification of hardware constraints before ADC can be enabled
<>	144:ef7eb2e8f9f7	2183	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2184	* @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
<>	144:ef7eb2e8f9f7	2185	*/
<>	144:ef7eb2e8f9f7	2186	#define ADC_ENABLING_CONDITIONS(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2187	(( HAL_IS_BIT_CLR((__HANDLE__)->Instance->CR , \
<>	144:ef7eb2e8f9f7	2188	(ADC_CR_ADCAL \| ADC_CR_JADSTP \| ADC_CR_ADSTP \| \
<>	144:ef7eb2e8f9f7	2189	ADC_CR_JADSTART \|ADC_CR_ADSTART \| ADC_CR_ADDIS \| \
<>	144:ef7eb2e8f9f7	2190	ADC_CR_ADEN ) ) \
<>	144:ef7eb2e8f9f7	2191	) ? SET : RESET)
<>	144:ef7eb2e8f9f7	2192
<>	144:ef7eb2e8f9f7	2193	/**
<>	144:ef7eb2e8f9f7	2194	* @brief Verification of ADC state: enabled or disabled
<>	144:ef7eb2e8f9f7	2195	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2196	* @retval SET (ADC enabled) or RESET (ADC disabled)
<>	144:ef7eb2e8f9f7	2197	*/
<>	144:ef7eb2e8f9f7	2198	#define ADC_IS_ENABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2199	(( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN \| ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
<>	144:ef7eb2e8f9f7	2200	((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
<>	144:ef7eb2e8f9f7	2201	) ? SET : RESET)
<>	144:ef7eb2e8f9f7	2202
<>	144:ef7eb2e8f9f7	2203	/**
<>	144:ef7eb2e8f9f7	2204	* @brief Test if conversion trigger of regular group is software start
<>	144:ef7eb2e8f9f7	2205	* or external trigger.
<>	144:ef7eb2e8f9f7	2206	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2207	* @retval SET (software start) or RESET (external trigger)
<>	144:ef7eb2e8f9f7	2208	*/
<>	144:ef7eb2e8f9f7	2209	#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2210	(((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET)
<>	144:ef7eb2e8f9f7	2211
<>	144:ef7eb2e8f9f7	2212	/**
<>	144:ef7eb2e8f9f7	2213	* @brief Test if conversion trigger of injected group is software start
<>	144:ef7eb2e8f9f7	2214	* or external trigger.
<>	144:ef7eb2e8f9f7	2215	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2216	* @retval SET (software start) or RESET (external trigger)
<>	144:ef7eb2e8f9f7	2217	*/
<>	144:ef7eb2e8f9f7	2218	#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2219	(((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET)
<>	144:ef7eb2e8f9f7	2220
<>	144:ef7eb2e8f9f7	2221	/**
<>	144:ef7eb2e8f9f7	2222	* @brief Check if no conversion on going on regular and/or injected groups
<>	144:ef7eb2e8f9f7	2223	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2224	* @retval SET (conversion is on going) or RESET (no conversion is on going)
<>	144:ef7eb2e8f9f7	2225	*/
<>	144:ef7eb2e8f9f7	2226	#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2227	(( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART \| ADC_CR_JADSTART)) == RESET \
<>	144:ef7eb2e8f9f7	2228	) ? RESET : SET)
<>	144:ef7eb2e8f9f7	2229
<>	144:ef7eb2e8f9f7	2230	/**
<>	144:ef7eb2e8f9f7	2231	* @brief Check if no conversion on going on regular group
<>	144:ef7eb2e8f9f7	2232	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2233	* @retval SET (conversion is on going) or RESET (no conversion is on going)
<>	144:ef7eb2e8f9f7	2234	*/
<>	144:ef7eb2e8f9f7	2235	#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2236	(( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \
<>	144:ef7eb2e8f9f7	2237	) ? RESET : SET)
<>	144:ef7eb2e8f9f7	2238
<>	144:ef7eb2e8f9f7	2239	/**
<>	144:ef7eb2e8f9f7	2240	* @brief Check if no conversion on going on injected group
<>	144:ef7eb2e8f9f7	2241	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2242	* @retval SET (conversion is on going) or RESET (no conversion is on going)
<>	144:ef7eb2e8f9f7	2243	*/
<>	144:ef7eb2e8f9f7	2244	#define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2245	(( (((__HANDLE__)->Instance->CR) & ADC_CR_JADSTART) == RESET \
<>	144:ef7eb2e8f9f7	2246	) ? RESET : SET)
<>	144:ef7eb2e8f9f7	2247
<>	144:ef7eb2e8f9f7	2248	/**
<>	144:ef7eb2e8f9f7	2249	* @brief Returns resolution bits in CFGR1 register: RES[1:0].
<>	144:ef7eb2e8f9f7	2250	* Returned value is among parameters to @ref ADCEx_Resolution.
<>	144:ef7eb2e8f9f7	2251	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2252	* @retval None
<>	144:ef7eb2e8f9f7	2253	*/
<>	144:ef7eb2e8f9f7	2254	#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)
<>	144:ef7eb2e8f9f7	2255
<>	144:ef7eb2e8f9f7	2256	/**
<>	144:ef7eb2e8f9f7	2257	* @brief Simultaneously clears and sets specific bits of the handle State
<>	144:ef7eb2e8f9f7	2258	* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
<>	144:ef7eb2e8f9f7	2259	* the first parameter is the ADC handle State, the second parameter is the
<>	144:ef7eb2e8f9f7	2260	* bit field to clear, the third and last parameter is the bit field to set.
<>	144:ef7eb2e8f9f7	2261	* @retval None
<>	144:ef7eb2e8f9f7	2262	*/
<>	144:ef7eb2e8f9f7	2263	#define ADC_STATE_CLR_SET MODIFY_REG
<>	144:ef7eb2e8f9f7	2264
<>	144:ef7eb2e8f9f7	2265	/**
<>	144:ef7eb2e8f9f7	2266	* @brief Clear ADC error code (set it to error code: "no error")
<>	144:ef7eb2e8f9f7	2267	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2268	* @retval None
<>	144:ef7eb2e8f9f7	2269	*/
<>	144:ef7eb2e8f9f7	2270	#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
<>	144:ef7eb2e8f9f7	2271
<>	144:ef7eb2e8f9f7	2272	/**
<>	144:ef7eb2e8f9f7	2273	* @brief Set the ADC's sample time for Channels numbers between 0 and 9.
<>	144:ef7eb2e8f9f7	2274	* @param _SAMPLETIME_: Sample time parameter.
<>	144:ef7eb2e8f9f7	2275	* @param _CHANNELNB_: Channel number.
<>	144:ef7eb2e8f9f7	2276	* @retval None
<>	144:ef7eb2e8f9f7	2277	*/
<>	144:ef7eb2e8f9f7	2278	#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
<>	144:ef7eb2e8f9f7	2279
<>	144:ef7eb2e8f9f7	2280	/**
<>	144:ef7eb2e8f9f7	2281	* @brief Set the ADC's sample time for Channels numbers between 10 and 18.
<>	144:ef7eb2e8f9f7	2282	* @param _SAMPLETIME_: Sample time parameter.
<>	144:ef7eb2e8f9f7	2283	* @param _CHANNELNB_: Channel number.
<>	144:ef7eb2e8f9f7	2284	* @retval None
<>	144:ef7eb2e8f9f7	2285	*/
<>	144:ef7eb2e8f9f7	2286	#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
<>	144:ef7eb2e8f9f7	2287
<>	144:ef7eb2e8f9f7	2288	/**
<>	144:ef7eb2e8f9f7	2289	* @brief Set the selected regular Channel rank for rank between 1 and 4.
<>	144:ef7eb2e8f9f7	2290	* @param _CHANNELNB_: Channel number.
<>	144:ef7eb2e8f9f7	2291	* @param _RANKNB_: Rank number.
<>	144:ef7eb2e8f9f7	2292	* @retval None
<>	144:ef7eb2e8f9f7	2293	*/
<>	144:ef7eb2e8f9f7	2294	#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * (_RANKNB_)))
<>	144:ef7eb2e8f9f7	2295
<>	144:ef7eb2e8f9f7	2296	/**
<>	144:ef7eb2e8f9f7	2297	* @brief Set the selected regular Channel rank for rank between 5 and 9.
<>	144:ef7eb2e8f9f7	2298	* @param _CHANNELNB_: Channel number.
<>	144:ef7eb2e8f9f7	2299	* @param _RANKNB_: Rank number.
<>	144:ef7eb2e8f9f7	2300	* @retval None
<>	144:ef7eb2e8f9f7	2301	*/
<>	144:ef7eb2e8f9f7	2302	#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * ((_RANKNB_) - 5)))
<>	144:ef7eb2e8f9f7	2303
<>	144:ef7eb2e8f9f7	2304	/**
<>	144:ef7eb2e8f9f7	2305	* @brief Set the selected regular Channel rank for rank between 10 and 14.
<>	144:ef7eb2e8f9f7	2306	* @param _CHANNELNB_: Channel number.
<>	144:ef7eb2e8f9f7	2307	* @param _RANKNB_: Rank number.
<>	144:ef7eb2e8f9f7	2308	* @retval None
<>	144:ef7eb2e8f9f7	2309	*/
<>	144:ef7eb2e8f9f7	2310	#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * ((_RANKNB_) - 10)))
<>	144:ef7eb2e8f9f7	2311
<>	144:ef7eb2e8f9f7	2312	/**
<>	144:ef7eb2e8f9f7	2313	* @brief Set the selected regular Channel rank for rank between 15 and 16.
<>	144:ef7eb2e8f9f7	2314	* @param _CHANNELNB_: Channel number.
<>	144:ef7eb2e8f9f7	2315	* @param _RANKNB_: Rank number.
<>	144:ef7eb2e8f9f7	2316	* @retval None
<>	144:ef7eb2e8f9f7	2317	*/
<>	144:ef7eb2e8f9f7	2318	#define ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * ((_RANKNB_) - 15)))
<>	144:ef7eb2e8f9f7	2319
<>	144:ef7eb2e8f9f7	2320	/**
<>	144:ef7eb2e8f9f7	2321	* @brief Set the selected injected Channel rank.
<>	144:ef7eb2e8f9f7	2322	* @param _CHANNELNB_: Channel number.
<>	144:ef7eb2e8f9f7	2323	* @param _RANKNB_: Rank number.
<>	144:ef7eb2e8f9f7	2324	* @retval None
<>	144:ef7eb2e8f9f7	2325	*/
<>	144:ef7eb2e8f9f7	2326	#define ADC_JSQR_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6 * (_RANKNB_) +2))
<>	144:ef7eb2e8f9f7	2327
<>	144:ef7eb2e8f9f7	2328
<>	144:ef7eb2e8f9f7	2329	/**
<>	144:ef7eb2e8f9f7	2330	* @brief Set the Analog Watchdog 1 channel.
<>	144:ef7eb2e8f9f7	2331	* @param _CHANNEL_: channel to be monitored by Analog Watchdog 1.
<>	144:ef7eb2e8f9f7	2332	* @retval None
<>	144:ef7eb2e8f9f7	2333	*/
<>	144:ef7eb2e8f9f7	2334	#define ADC_CFGR_AWD1CH_SHIFT(_CHANNEL_) ((_CHANNEL_) << 26)
<>	144:ef7eb2e8f9f7	2335
<>	144:ef7eb2e8f9f7	2336	/**
<>	144:ef7eb2e8f9f7	2337	* @brief Configure the channel number into Analog Watchdog 2 or 3.
<>	144:ef7eb2e8f9f7	2338	* @param _CHANNEL_: ADC Channel
<>	144:ef7eb2e8f9f7	2339	* @retval None
<>	144:ef7eb2e8f9f7	2340	*/
<>	144:ef7eb2e8f9f7	2341	#define ADC_CFGR_AWD23CR(_CHANNEL_) (1U << (_CHANNEL_))
<>	144:ef7eb2e8f9f7	2342
<>	144:ef7eb2e8f9f7	2343	/**
<>	144:ef7eb2e8f9f7	2344	* @brief Enable automatic conversion of injected group
<>	144:ef7eb2e8f9f7	2345	* @param _INJECT_AUTO_CONVERSION_: Injected automatic conversion.
<>	144:ef7eb2e8f9f7	2346	* @retval None
<>	144:ef7eb2e8f9f7	2347	*/
<>	144:ef7eb2e8f9f7	2348	#define ADC_CFGR_INJECT_AUTO_CONVERSION(_INJECT_AUTO_CONVERSION_) ((_INJECT_AUTO_CONVERSION_) << 25)
<>	144:ef7eb2e8f9f7	2349
<>	144:ef7eb2e8f9f7	2350	/**
<>	144:ef7eb2e8f9f7	2351	* @brief Enable ADC injected context queue
<>	144:ef7eb2e8f9f7	2352	* @param _INJECT_CONTEXT_QUEUE_MODE_: Injected context queue mode.
<>	144:ef7eb2e8f9f7	2353	* @retval None
<>	144:ef7eb2e8f9f7	2354	*/
<>	144:ef7eb2e8f9f7	2355	#define ADC_CFGR_INJECT_CONTEXT_QUEUE(_INJECT_CONTEXT_QUEUE_MODE_) ((_INJECT_CONTEXT_QUEUE_MODE_) << 21)
<>	144:ef7eb2e8f9f7	2356
<>	144:ef7eb2e8f9f7	2357	/**
<>	144:ef7eb2e8f9f7	2358	* @brief Enable ADC discontinuous conversion mode for injected group
<>	144:ef7eb2e8f9f7	2359	* @param _INJECT_DISCONTINUOUS_MODE_: Injected discontinuous mode.
<>	144:ef7eb2e8f9f7	2360	* @retval None
<>	144:ef7eb2e8f9f7	2361	*/
<>	144:ef7eb2e8f9f7	2362	#define ADC_CFGR_INJECT_DISCCONTINUOUS(_INJECT_DISCONTINUOUS_MODE_) ((_INJECT_DISCONTINUOUS_MODE_) << 20)
<>	144:ef7eb2e8f9f7	2363
<>	144:ef7eb2e8f9f7	2364	/**
<>	144:ef7eb2e8f9f7	2365	* @brief Enable ADC discontinuous conversion mode for regular group
<>	144:ef7eb2e8f9f7	2366	* @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode.
<>	144:ef7eb2e8f9f7	2367	* @retval None
<>	144:ef7eb2e8f9f7	2368	*/
<>	144:ef7eb2e8f9f7	2369	#define ADC_CFGR_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) ((_REG_DISCONTINUOUS_MODE_) << 16)
<>	144:ef7eb2e8f9f7	2370
<>	144:ef7eb2e8f9f7	2371	/**
<>	144:ef7eb2e8f9f7	2372	* @brief Configures the number of discontinuous conversions for regular group.
<>	144:ef7eb2e8f9f7	2373	* @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
<>	144:ef7eb2e8f9f7	2374	* @retval None
<>	144:ef7eb2e8f9f7	2375	*/
<>	144:ef7eb2e8f9f7	2376	#define ADC_CFGR_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1) << 17)
<>	144:ef7eb2e8f9f7	2377
<>	144:ef7eb2e8f9f7	2378	/**
<>	144:ef7eb2e8f9f7	2379	* @brief Enable the ADC auto delay mode.
<>	144:ef7eb2e8f9f7	2380	* @param _AUTOWAIT_: Auto delay bit enable or disable.
<>	144:ef7eb2e8f9f7	2381	* @retval None
<>	144:ef7eb2e8f9f7	2382	*/
<>	144:ef7eb2e8f9f7	2383	#define ADC_CFGR_AUTOWAIT(_AUTOWAIT_) ((_AUTOWAIT_) << 14)
<>	144:ef7eb2e8f9f7	2384
<>	144:ef7eb2e8f9f7	2385	/**
<>	144:ef7eb2e8f9f7	2386	* @brief Enable ADC continuous conversion mode.
<>	144:ef7eb2e8f9f7	2387	* @param _CONTINUOUS_MODE_: Continuous mode.
<>	144:ef7eb2e8f9f7	2388	* @retval None
<>	144:ef7eb2e8f9f7	2389	*/
<>	144:ef7eb2e8f9f7	2390	#define ADC_CFGR_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13)
<>	144:ef7eb2e8f9f7	2391
<>	144:ef7eb2e8f9f7	2392	/**
<>	144:ef7eb2e8f9f7	2393	* @brief Enable ADC overrun mode.
<>	144:ef7eb2e8f9f7	2394	* @param _OVERRUN_MODE_: Overrun mode.
<>	144:ef7eb2e8f9f7	2395	* @retval Overrun bit setting to be programmed into CFGR register
<>	144:ef7eb2e8f9f7	2396	*/
<>	144:ef7eb2e8f9f7	2397	/* Note: Bit ADC_CFGR_OVRMOD not used directly in constant */
<>	144:ef7eb2e8f9f7	2398	/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */
<>	144:ef7eb2e8f9f7	2399	/* as the default case to be compliant with other STM32 devices. */
<>	144:ef7eb2e8f9f7	2400	#define ADC_CFGR_OVERRUN(_OVERRUN_MODE_) \
<>	144:ef7eb2e8f9f7	2401	( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \
<>	144:ef7eb2e8f9f7	2402	)? (ADC_CFGR_OVRMOD) : (0x00000000) \
<>	144:ef7eb2e8f9f7	2403	)
<>	144:ef7eb2e8f9f7	2404
<>	144:ef7eb2e8f9f7	2405	/**
<>	144:ef7eb2e8f9f7	2406	* @brief Enable the ADC DMA continuous request.
<>	144:ef7eb2e8f9f7	2407	* @param _DMACONTREQ_MODE_: DMA continuous request mode.
<>	144:ef7eb2e8f9f7	2408	* @retval None
<>	144:ef7eb2e8f9f7	2409	*/
<>	144:ef7eb2e8f9f7	2410	#define ADC_CFGR_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << 1)
<>	144:ef7eb2e8f9f7	2411
<>	144:ef7eb2e8f9f7	2412	/**
<>	144:ef7eb2e8f9f7	2413	* @brief For devices with 3 ADCs or more: Defines the external trigger source
<>	144:ef7eb2e8f9f7	2414	* for regular group according to ADC into common group ADC1&ADC2 or
<>	144:ef7eb2e8f9f7	2415	* ADC3&ADC4 (some triggers with same source have different value to
<>	144:ef7eb2e8f9f7	2416	* be programmed into ADC EXTSEL bits of CFGR register).
<>	144:ef7eb2e8f9f7	2417	* Note: No risk of trigger bits value of common group ADC1&ADC2
<>	144:ef7eb2e8f9f7	2418	* misleading to another trigger at same bits value, because the 3
<>	144:ef7eb2e8f9f7	2419	* exceptions below are circular and do not point to any other trigger
<>	144:ef7eb2e8f9f7	2420	* with direct treatment.
<>	144:ef7eb2e8f9f7	2421	* For devices with 2 ADCs or less: this macro makes no change.
<>	144:ef7eb2e8f9f7	2422	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2423	* @param __EXT_TRIG_CONV__: External trigger selected for regular group.
<>	144:ef7eb2e8f9f7	2424	* @retval External trigger to be programmed into EXTSEL bits of CFGR register
<>	144:ef7eb2e8f9f7	2425	*/
<>	144:ef7eb2e8f9f7	2426	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	2427	defined(STM32F303xC) \|\| defined(STM32F358xx)
<>	144:ef7eb2e8f9f7	2428
<>	144:ef7eb2e8f9f7	2429	#if defined(STM32F303xC) \|\| defined(STM32F358xx)
<>	144:ef7eb2e8f9f7	2430	#define ADC_CFGR_EXTSEL_SET(__HANDLE__, __EXT_TRIG_CONV__) \
<>	144:ef7eb2e8f9f7	2431	(( ((((__HANDLE__)->Instance) == ADC3) \|\| (((__HANDLE__)->Instance) == ADC4)) \
<>	144:ef7eb2e8f9f7	2432	)? \
<>	144:ef7eb2e8f9f7	2433	( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T2_TRGO \
<>	144:ef7eb2e8f9f7	2434	)? \
<>	144:ef7eb2e8f9f7	2435	(ADC3_4_EXTERNALTRIG_T2_TRGO) \
<>	144:ef7eb2e8f9f7	2436	: \
<>	144:ef7eb2e8f9f7	2437	( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T3_TRGO \
<>	144:ef7eb2e8f9f7	2438	)? \
<>	144:ef7eb2e8f9f7	2439	(ADC3_4_EXTERNALTRIG_T3_TRGO) \
<>	144:ef7eb2e8f9f7	2440	: \
<>	144:ef7eb2e8f9f7	2441	( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \
<>	144:ef7eb2e8f9f7	2442	)? \
<>	144:ef7eb2e8f9f7	2443	(ADC3_4_EXTERNALTRIG_T8_TRGO) \
<>	144:ef7eb2e8f9f7	2444	: \
<>	144:ef7eb2e8f9f7	2445	(__EXT_TRIG_CONV__) \
<>	144:ef7eb2e8f9f7	2446	) \
<>	144:ef7eb2e8f9f7	2447	) \
<>	144:ef7eb2e8f9f7	2448	) \
<>	144:ef7eb2e8f9f7	2449	: \
<>	144:ef7eb2e8f9f7	2450	(__EXT_TRIG_CONV__) \
<>	144:ef7eb2e8f9f7	2451	)
<>	144:ef7eb2e8f9f7	2452	#endif /* STM32F303xC \|\| STM32F358xx */
<>	144:ef7eb2e8f9f7	2453
<>	144:ef7eb2e8f9f7	2454	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
<>	144:ef7eb2e8f9f7	2455	/* Note: Macro including external triggers specific to device STM303xE: using */
<>	144:ef7eb2e8f9f7	2456	/* Timer20 with ADC trigger input remap. */
<>	144:ef7eb2e8f9f7	2457	#define ADC_CFGR_EXTSEL_SET(__HANDLE__, __EXT_TRIG_CONV__) \
<>	144:ef7eb2e8f9f7	2458	(( ((((__HANDLE__)->Instance) == ADC3) \|\| (((__HANDLE__)->Instance) == ADC4)) \
<>	144:ef7eb2e8f9f7	2459	)? \
<>	144:ef7eb2e8f9f7	2460	( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T2_TRGO \
<>	144:ef7eb2e8f9f7	2461	)? \
<>	144:ef7eb2e8f9f7	2462	(ADC3_4_EXTERNALTRIG_T2_TRGO) \
<>	144:ef7eb2e8f9f7	2463	: \
<>	144:ef7eb2e8f9f7	2464	( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T3_TRGO \
<>	144:ef7eb2e8f9f7	2465	)? \
<>	144:ef7eb2e8f9f7	2466	(ADC3_4_EXTERNALTRIG_T3_TRGO) \
<>	144:ef7eb2e8f9f7	2467	: \
<>	144:ef7eb2e8f9f7	2468	( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T8_TRGO \
<>	144:ef7eb2e8f9f7	2469	)? \
<>	144:ef7eb2e8f9f7	2470	(ADC3_4_EXTERNALTRIG_T8_TRGO) \
<>	144:ef7eb2e8f9f7	2471	: \
<>	144:ef7eb2e8f9f7	2472	( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T20_CC1 \
<>	144:ef7eb2e8f9f7	2473	)? \
<>	144:ef7eb2e8f9f7	2474	(ADC3_4_EXTERNALTRIG_T2_CC1) \
<>	144:ef7eb2e8f9f7	2475	: \
<>	144:ef7eb2e8f9f7	2476	( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T20_TRGO \
<>	144:ef7eb2e8f9f7	2477	)? \
<>	144:ef7eb2e8f9f7	2478	(ADC3_4_EXTERNALTRIG_EXT_IT2) \
<>	144:ef7eb2e8f9f7	2479	: \
<>	144:ef7eb2e8f9f7	2480	( ( (__EXT_TRIG_CONV__) == ADC_EXTERNALTRIGCONV_T20_TRGO2 \
<>	144:ef7eb2e8f9f7	2481	)? \
<>	144:ef7eb2e8f9f7	2482	(ADC3_4_EXTERNALTRIG_T4_CC1) \
<>	144:ef7eb2e8f9f7	2483	: \
<>	144:ef7eb2e8f9f7	2484	(__EXT_TRIG_CONV__) \
<>	144:ef7eb2e8f9f7	2485	) \
<>	144:ef7eb2e8f9f7	2486	) \
<>	144:ef7eb2e8f9f7	2487	) \
<>	144:ef7eb2e8f9f7	2488	) \
<>	144:ef7eb2e8f9f7	2489	) \
<>	144:ef7eb2e8f9f7	2490	) \
<>	144:ef7eb2e8f9f7	2491	: \
<>	144:ef7eb2e8f9f7	2492	(__EXT_TRIG_CONV__ & (~ADC_EXTERNALTRIGCONV_T20_MASK)) \
<>	144:ef7eb2e8f9f7	2493	)
<>	144:ef7eb2e8f9f7	2494	#endif /* STM32F303xE \|\| STM32F398xx */
<>	144:ef7eb2e8f9f7	2495	#else
<>	144:ef7eb2e8f9f7	2496	#define ADC_CFGR_EXTSEL_SET(__HANDLE__, __EXT_TRIG_CONV__) \
<>	144:ef7eb2e8f9f7	2497	(__EXT_TRIG_CONV__)
<>	144:ef7eb2e8f9f7	2498	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	2499	/* STM32F303xC \|\| STM32F358xx */
<>	144:ef7eb2e8f9f7	2500
<>	144:ef7eb2e8f9f7	2501	/**
<>	144:ef7eb2e8f9f7	2502	* @brief For devices with 3 ADCs or more: Defines the external trigger source
<>	144:ef7eb2e8f9f7	2503	* for injected group according to ADC into common group ADC1&ADC2 or
<>	144:ef7eb2e8f9f7	2504	* ADC3&ADC4 (some triggers with same source have different value to
<>	144:ef7eb2e8f9f7	2505	* be programmed into ADC JEXTSEL bits of JSQR register).
<>	144:ef7eb2e8f9f7	2506	* Note: No risk of trigger bits value of common group ADC1&ADC2
<>	144:ef7eb2e8f9f7	2507	* misleading to another trigger at same bits value, because the 3
<>	144:ef7eb2e8f9f7	2508	* exceptions below are circular and do not point to any other trigger
<>	144:ef7eb2e8f9f7	2509	* with direct treatment, except trigger
<>	144:ef7eb2e8f9f7	2510	* ADC_EXTERNALTRIGINJECCONV_T4_CC3 differentiated with SW offset.
<>	144:ef7eb2e8f9f7	2511	* For devices with 2 ADCs or less: this macro makes no change.
<>	144:ef7eb2e8f9f7	2512	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2513	* @param __EXT_TRIG_INJECTCONV__: External trigger selected for injected group
<>	144:ef7eb2e8f9f7	2514	* @retval External trigger to be programmed into JEXTSEL bits of JSQR register
<>	144:ef7eb2e8f9f7	2515	*/
<>	144:ef7eb2e8f9f7	2516	#if defined(STM32F303xC) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| defined(STM32F358xx)
<>	144:ef7eb2e8f9f7	2517	#if defined(STM32F303xC) \|\| defined(STM32F358xx)
<>	144:ef7eb2e8f9f7	2518	#define ADC_JSQR_JEXTSEL_SET(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
<>	144:ef7eb2e8f9f7	2519	(( ((((__HANDLE__)->Instance) == ADC3) \|\| (((__HANDLE__)->Instance) == ADC4)) \
<>	144:ef7eb2e8f9f7	2520	)? \
<>	144:ef7eb2e8f9f7	2521	( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO \
<>	144:ef7eb2e8f9f7	2522	)? \
<>	144:ef7eb2e8f9f7	2523	(ADC3_4_EXTERNALTRIGINJEC_T2_TRGO) \
<>	144:ef7eb2e8f9f7	2524	: \
<>	144:ef7eb2e8f9f7	2525	( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO \
<>	144:ef7eb2e8f9f7	2526	)? \
<>	144:ef7eb2e8f9f7	2527	(ADC3_4_EXTERNALTRIGINJEC_T4_TRGO) \
<>	144:ef7eb2e8f9f7	2528	: \
<>	144:ef7eb2e8f9f7	2529	( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \
<>	144:ef7eb2e8f9f7	2530	)? \
<>	144:ef7eb2e8f9f7	2531	(ADC3_4_EXTERNALTRIGINJEC_T8_CC4) \
<>	144:ef7eb2e8f9f7	2532	: \
<>	144:ef7eb2e8f9f7	2533	( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_CC3 \
<>	144:ef7eb2e8f9f7	2534	)? \
<>	144:ef7eb2e8f9f7	2535	(ADC3_4_EXTERNALTRIGINJEC_T4_CC3) \
<>	144:ef7eb2e8f9f7	2536	: \
<>	144:ef7eb2e8f9f7	2537	(__EXT_TRIG_INJECTCONV__) \
<>	144:ef7eb2e8f9f7	2538	) \
<>	144:ef7eb2e8f9f7	2539	) \
<>	144:ef7eb2e8f9f7	2540	) \
<>	144:ef7eb2e8f9f7	2541	) \
<>	144:ef7eb2e8f9f7	2542	: \
<>	144:ef7eb2e8f9f7	2543	(__EXT_TRIG_INJECTCONV__) \
<>	144:ef7eb2e8f9f7	2544	)
<>	144:ef7eb2e8f9f7	2545	#endif /* STM32F303xC \|\| STM32F358xx */
<>	144:ef7eb2e8f9f7	2546
<>	144:ef7eb2e8f9f7	2547	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
<>	144:ef7eb2e8f9f7	2548	/* Note: Macro including external triggers specific to device STM303xE: using */
<>	144:ef7eb2e8f9f7	2549	/* Timer20 with ADC trigger input remap. */
<>	144:ef7eb2e8f9f7	2550	#define ADC_JSQR_JEXTSEL_SET(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
<>	144:ef7eb2e8f9f7	2551	(( ((((__HANDLE__)->Instance) == ADC3) \|\| (((__HANDLE__)->Instance) == ADC4)) \
<>	144:ef7eb2e8f9f7	2552	)? \
<>	144:ef7eb2e8f9f7	2553	( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO \
<>	144:ef7eb2e8f9f7	2554	)? \
<>	144:ef7eb2e8f9f7	2555	(ADC3_4_EXTERNALTRIGINJEC_T2_TRGO) \
<>	144:ef7eb2e8f9f7	2556	: \
<>	144:ef7eb2e8f9f7	2557	( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO \
<>	144:ef7eb2e8f9f7	2558	)? \
<>	144:ef7eb2e8f9f7	2559	(ADC3_4_EXTERNALTRIGINJEC_T4_TRGO) \
<>	144:ef7eb2e8f9f7	2560	: \
<>	144:ef7eb2e8f9f7	2561	( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4 \
<>	144:ef7eb2e8f9f7	2562	)? \
<>	144:ef7eb2e8f9f7	2563	(ADC3_4_EXTERNALTRIGINJEC_T8_CC4) \
<>	144:ef7eb2e8f9f7	2564	: \
<>	144:ef7eb2e8f9f7	2565	( ( (__EXT_TRIG_INJECTCONV__) == ADC_EXTERNALTRIGINJECCONV_T4_CC3 \
<>	144:ef7eb2e8f9f7	2566	)? \
<>	144:ef7eb2e8f9f7	2567	(ADC3_4_EXTERNALTRIGINJEC_T4_CC3) \
<>	144:ef7eb2e8f9f7	2568	: \
<>	144:ef7eb2e8f9f7	2569	( ( (__EXT_TRIG_INJECTCONV__) \
<>	144:ef7eb2e8f9f7	2570	== ADC_EXTERNALTRIGINJECCONV_T20_TRGO \
<>	144:ef7eb2e8f9f7	2571	)? \
<>	144:ef7eb2e8f9f7	2572	(ADC3_4_EXTERNALTRIGINJEC_T20_TRGO) \
<>	144:ef7eb2e8f9f7	2573	: \
<>	144:ef7eb2e8f9f7	2574	( ( (__EXT_TRIG_INJECTCONV__) \
<>	144:ef7eb2e8f9f7	2575	== ADC_EXTERNALTRIGINJECCONV_T20_TRGO2 \
<>	144:ef7eb2e8f9f7	2576	)? \
<>	144:ef7eb2e8f9f7	2577	(ADC3_4_EXTERNALTRIGINJEC_T1_CC3) \
<>	144:ef7eb2e8f9f7	2578	: \
<>	144:ef7eb2e8f9f7	2579	(__EXT_TRIG_INJECTCONV__) \
<>	144:ef7eb2e8f9f7	2580	) \
<>	144:ef7eb2e8f9f7	2581	) \
<>	144:ef7eb2e8f9f7	2582	) \
<>	144:ef7eb2e8f9f7	2583	) \
<>	144:ef7eb2e8f9f7	2584	) \
<>	144:ef7eb2e8f9f7	2585	) \
<>	144:ef7eb2e8f9f7	2586	: \
<>	144:ef7eb2e8f9f7	2587	(__EXT_TRIG_INJECTCONV__ & (~ADC_EXTERNALTRIGCONV_T20_MASK)) \
<>	144:ef7eb2e8f9f7	2588	)
<>	144:ef7eb2e8f9f7	2589	#endif /* STM32F303xE \|\| STM32F398xx */
<>	144:ef7eb2e8f9f7	2590	#else
<>	144:ef7eb2e8f9f7	2591	#define ADC_JSQR_JEXTSEL_SET(__HANDLE__, __EXT_TRIG_INJECTCONV__) \
<>	144:ef7eb2e8f9f7	2592	(__EXT_TRIG_INJECTCONV__)
<>	144:ef7eb2e8f9f7	2593	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	2594	/* STM32F303xC \|\| STM32F358xx */
<>	144:ef7eb2e8f9f7	2595
<>	144:ef7eb2e8f9f7	2596	/**
<>	144:ef7eb2e8f9f7	2597	* @brief Configure the channel number into offset OFRx register
<>	144:ef7eb2e8f9f7	2598	* @param _CHANNEL_: ADC Channel
<>	144:ef7eb2e8f9f7	2599	* @retval None
<>	144:ef7eb2e8f9f7	2600	*/
<>	144:ef7eb2e8f9f7	2601	#define ADC_OFR_CHANNEL(_CHANNEL_) ((_CHANNEL_) << 26)
<>	144:ef7eb2e8f9f7	2602
<>	144:ef7eb2e8f9f7	2603	/**
<>	144:ef7eb2e8f9f7	2604	* @brief Configure the channel number into differential mode selection register
<>	144:ef7eb2e8f9f7	2605	* @param _CHANNEL_: ADC Channel
<>	144:ef7eb2e8f9f7	2606	* @retval None
<>	144:ef7eb2e8f9f7	2607	*/
<>	144:ef7eb2e8f9f7	2608	#define ADC_DIFSEL_CHANNEL(_CHANNEL_) (1U << (_CHANNEL_))
<>	144:ef7eb2e8f9f7	2609
<>	144:ef7eb2e8f9f7	2610	/**
<>	144:ef7eb2e8f9f7	2611	* @brief Calibration factor in differential mode to be set into calibration register
<>	144:ef7eb2e8f9f7	2612	* @param _Calibration_Factor_: Calibration factor value
<>	144:ef7eb2e8f9f7	2613	* @retval None
<>	144:ef7eb2e8f9f7	2614	*/
<>	144:ef7eb2e8f9f7	2615	#define ADC_CALFACT_DIFF_SET(_Calibration_Factor_) ((_Calibration_Factor_) << 16)
<>	144:ef7eb2e8f9f7	2616
<>	144:ef7eb2e8f9f7	2617	/**
<>	144:ef7eb2e8f9f7	2618	* @brief Calibration factor in differential mode to be retrieved from calibration register
<>	144:ef7eb2e8f9f7	2619	* @param _Calibration_Factor_: Calibration factor value
<>	144:ef7eb2e8f9f7	2620	* @retval None
<>	144:ef7eb2e8f9f7	2621	*/
<>	144:ef7eb2e8f9f7	2622	#define ADC_CALFACT_DIFF_GET(_Calibration_Factor_) ((_Calibration_Factor_) >> 16)
<>	144:ef7eb2e8f9f7	2623
<>	144:ef7eb2e8f9f7	2624	/**
<>	144:ef7eb2e8f9f7	2625	* @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
<>	144:ef7eb2e8f9f7	2626	* @param _Threshold_: Threshold value
<>	144:ef7eb2e8f9f7	2627	* @retval None
<>	144:ef7eb2e8f9f7	2628	*/
<>	144:ef7eb2e8f9f7	2629	#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16)
<>	144:ef7eb2e8f9f7	2630
<>	144:ef7eb2e8f9f7	2631	/**
<>	144:ef7eb2e8f9f7	2632	* @brief Enable the ADC DMA continuous request for ADC multimode.
<>	144:ef7eb2e8f9f7	2633	* @param _DMAContReq_MODE_: DMA continuous request mode.
<>	144:ef7eb2e8f9f7	2634	* @retval None
<>	144:ef7eb2e8f9f7	2635	*/
<>	144:ef7eb2e8f9f7	2636	#define ADC_CCR_MULTI_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 13)
<>	144:ef7eb2e8f9f7	2637
<>	144:ef7eb2e8f9f7	2638	/**
<>	144:ef7eb2e8f9f7	2639	* @brief Verification of hardware constraints before ADC can be disabled
<>	144:ef7eb2e8f9f7	2640	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2641	* @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
<>	144:ef7eb2e8f9f7	2642	*/
<>	144:ef7eb2e8f9f7	2643	#define ADC_DISABLING_CONDITIONS(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2644	(( ( ((__HANDLE__)->Instance->CR) & \
<>	144:ef7eb2e8f9f7	2645	(ADC_CR_JADSTART \| ADC_CR_ADSTART \| ADC_CR_ADEN)) == ADC_CR_ADEN \
<>	144:ef7eb2e8f9f7	2646	) ? SET : RESET)
<>	144:ef7eb2e8f9f7	2647
<>	144:ef7eb2e8f9f7	2648
<>	144:ef7eb2e8f9f7	2649	/**
<>	144:ef7eb2e8f9f7	2650	* @brief Shift the offset in function of the selected ADC resolution.
<>	144:ef7eb2e8f9f7	2651	* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0
<>	144:ef7eb2e8f9f7	2652	* If resolution 12 bits, no shift.
<>	144:ef7eb2e8f9f7	2653	* If resolution 10 bits, shift of 2 ranks on the left.
<>	144:ef7eb2e8f9f7	2654	* If resolution 8 bits, shift of 4 ranks on the left.
<>	144:ef7eb2e8f9f7	2655	* If resolution 6 bits, shift of 6 ranks on the left.
<>	144:ef7eb2e8f9f7	2656	* therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
<>	144:ef7eb2e8f9f7	2657	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2658	* @param _Offset_: Value to be shifted
<>	144:ef7eb2e8f9f7	2659	* @retval None
<>	144:ef7eb2e8f9f7	2660	*/
<>	144:ef7eb2e8f9f7	2661	#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \
<>	144:ef7eb2e8f9f7	2662	((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
<>	144:ef7eb2e8f9f7	2663
<>	144:ef7eb2e8f9f7	2664	/**
<>	144:ef7eb2e8f9f7	2665	* @brief Shift the AWD1 threshold in function of the selected ADC resolution.
<>	144:ef7eb2e8f9f7	2666	* Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
<>	144:ef7eb2e8f9f7	2667	* If resolution 12 bits, no shift.
<>	144:ef7eb2e8f9f7	2668	* If resolution 10 bits, shift of 2 ranks on the left.
<>	144:ef7eb2e8f9f7	2669	* If resolution 8 bits, shift of 4 ranks on the left.
<>	144:ef7eb2e8f9f7	2670	* If resolution 6 bits, shift of 6 ranks on the left.
<>	144:ef7eb2e8f9f7	2671	* therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
<>	144:ef7eb2e8f9f7	2672	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2673	* @param _Threshold_: Value to be shifted
<>	144:ef7eb2e8f9f7	2674	* @retval None
<>	144:ef7eb2e8f9f7	2675	*/
<>	144:ef7eb2e8f9f7	2676	#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
<>	144:ef7eb2e8f9f7	2677	((_Threshold_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
<>	144:ef7eb2e8f9f7	2678
<>	144:ef7eb2e8f9f7	2679	/**
<>	144:ef7eb2e8f9f7	2680	* @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.
<>	144:ef7eb2e8f9f7	2681	* Thresholds have to be left-aligned on bit 7.
<>	144:ef7eb2e8f9f7	2682	* If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded)
<>	144:ef7eb2e8f9f7	2683	* If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded)
<>	144:ef7eb2e8f9f7	2684	* If resolution 8 bits, no shift.
<>	144:ef7eb2e8f9f7	2685	* If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0)
<>	144:ef7eb2e8f9f7	2686	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2687	* @param _Threshold_: Value to be shifted
<>	144:ef7eb2e8f9f7	2688	* @retval None
<>	144:ef7eb2e8f9f7	2689	*/
<>	144:ef7eb2e8f9f7	2690	#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
<>	144:ef7eb2e8f9f7	2691	( ((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 \| ADC_CFGR_RES_0) ? \
<>	144:ef7eb2e8f9f7	2692	((_Threshold_) >> (4- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))) : \
<>	144:ef7eb2e8f9f7	2693	(_Threshold_) << 2 )
<>	144:ef7eb2e8f9f7	2694
<>	144:ef7eb2e8f9f7	2695	/**
<>	144:ef7eb2e8f9f7	2696	* @brief Defines if the selected ADC is within ADC common register ADC1_2 or ADC3_4
<>	144:ef7eb2e8f9f7	2697	* if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
<>	144:ef7eb2e8f9f7	2698	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2699	* @retval Common control register ADC1_2 or ADC3_4
<>	144:ef7eb2e8f9f7	2700	*/
<>	144:ef7eb2e8f9f7	2701	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	2702	defined(STM32F303xC) \|\| defined(STM32F358xx)
<>	144:ef7eb2e8f9f7	2703	#define ADC_MASTER_INSTANCE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2704	( ( ((((__HANDLE__)->Instance) == ADC1) \|\| (((__HANDLE__)->Instance) == ADC2)) \
<>	144:ef7eb2e8f9f7	2705	)? (ADC1) : (ADC3) \
<>	144:ef7eb2e8f9f7	2706	)
<>	144:ef7eb2e8f9f7	2707	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	2708	/* STM32F303xC \|\| STM32F358xx */
<>	144:ef7eb2e8f9f7	2709
<>	144:ef7eb2e8f9f7	2710	#if defined(STM32F302xE) \|\| \
<>	144:ef7eb2e8f9f7	2711	defined(STM32F302xC) \|\| \
<>	144:ef7eb2e8f9f7	2712	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
<>	144:ef7eb2e8f9f7	2713	#define ADC_MASTER_INSTANCE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2714	(ADC1)
<>	144:ef7eb2e8f9f7	2715	#endif /* STM32F302xE \|\| */
<>	144:ef7eb2e8f9f7	2716	/* STM32F302xC \|\| */
<>	144:ef7eb2e8f9f7	2717	/* STM32F303x8 \|\| STM32F328xx \|\| STM32F334x8 */
<>	144:ef7eb2e8f9f7	2718
<>	144:ef7eb2e8f9f7	2719	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	2720	#define ADC_MASTER_INSTANCE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2721	(ADC1)
<>	144:ef7eb2e8f9f7	2722	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	2723
<>	144:ef7eb2e8f9f7	2724	/**
<>	144:ef7eb2e8f9f7	2725	* @brief Defines if the selected ADC is within ADC common register ADC1_2 or ADC3_4
<>	144:ef7eb2e8f9f7	2726	* if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
<>	144:ef7eb2e8f9f7	2727	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2728	* @retval Common control register ADC1_2 or ADC3_4
<>	144:ef7eb2e8f9f7	2729	*/
<>	144:ef7eb2e8f9f7	2730	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	2731	defined(STM32F303xC) \|\| defined(STM32F358xx)
<>	144:ef7eb2e8f9f7	2732	#define ADC_COMMON_REGISTER(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2733	( ( ((((__HANDLE__)->Instance) == ADC1) \|\| (((__HANDLE__)->Instance) == ADC2)) \
<>	144:ef7eb2e8f9f7	2734	)? (ADC1_2_COMMON) : (ADC3_4_COMMON) \
<>	144:ef7eb2e8f9f7	2735	)
<>	144:ef7eb2e8f9f7	2736	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	2737	/* STM32F303xC \|\| STM32F358xx */
<>	144:ef7eb2e8f9f7	2738
<>	144:ef7eb2e8f9f7	2739	#if defined(STM32F302xE) \|\| \
<>	144:ef7eb2e8f9f7	2740	defined(STM32F302xC) \|\| \
<>	144:ef7eb2e8f9f7	2741	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
<>	144:ef7eb2e8f9f7	2742	#define ADC_COMMON_REGISTER(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2743	(ADC1_2_COMMON)
<>	144:ef7eb2e8f9f7	2744	#endif /* STM32F302xE \|\| */
<>	144:ef7eb2e8f9f7	2745	/* STM32F302xC \|\| */
<>	144:ef7eb2e8f9f7	2746	/* STM32F303x8 \|\| STM32F328xx \|\| STM32F334x8 */
<>	144:ef7eb2e8f9f7	2747
<>	144:ef7eb2e8f9f7	2748	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	2749	#define ADC_COMMON_REGISTER(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2750	(ADC1_COMMON)
<>	144:ef7eb2e8f9f7	2751	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	2752
<>	144:ef7eb2e8f9f7	2753	/**
<>	144:ef7eb2e8f9f7	2754	* @brief Selection of ADC common register CCR bits MULTI[4:0]corresponding to the selected ADC (applicable for devices with several ADCs)
<>	144:ef7eb2e8f9f7	2755	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2756	* @retval None
<>	144:ef7eb2e8f9f7	2757	*/
<>	144:ef7eb2e8f9f7	2758	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	2759	defined(STM32F303xC) \|\| defined(STM32F358xx)
<>	144:ef7eb2e8f9f7	2760	#define ADC_COMMON_CCR_MULTI(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2761	( ( ((((__HANDLE__)->Instance) == ADC1) \|\| (((__HANDLE__)->Instance) == ADC2)) \
<>	144:ef7eb2e8f9f7	2762	)? \
<>	144:ef7eb2e8f9f7	2763	(ADC1_2_COMMON->CCR & ADC12_CCR_MULTI) \
<>	144:ef7eb2e8f9f7	2764	: \
<>	144:ef7eb2e8f9f7	2765	(ADC3_4_COMMON->CCR & ADC34_CCR_MULTI) \
<>	144:ef7eb2e8f9f7	2766	)
<>	144:ef7eb2e8f9f7	2767	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	2768	/* STM32F303xC \|\| STM32F358xx */
<>	144:ef7eb2e8f9f7	2769
<>	144:ef7eb2e8f9f7	2770	#if defined(STM32F302xE) \|\| \
<>	144:ef7eb2e8f9f7	2771	defined(STM32F302xC) \|\| \
<>	144:ef7eb2e8f9f7	2772	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
<>	144:ef7eb2e8f9f7	2773	#define ADC_COMMON_CCR_MULTI(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2774	(ADC1_2_COMMON->CCR & ADC12_CCR_MULTI)
<>	144:ef7eb2e8f9f7	2775	#endif /* STM32F302xE \|\| */
<>	144:ef7eb2e8f9f7	2776	/* STM32F302xC \|\| */
<>	144:ef7eb2e8f9f7	2777	/* STM32F303x8 \|\| STM32F328xx \|\| STM32F334x8 */
<>	144:ef7eb2e8f9f7	2778
<>	144:ef7eb2e8f9f7	2779	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	2780	#define ADC_COMMON_CCR_MULTI(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2781	(RESET)
<>	144:ef7eb2e8f9f7	2782	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	2783
<>	144:ef7eb2e8f9f7	2784	/**
<>	144:ef7eb2e8f9f7	2785	* @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs)
<>	144:ef7eb2e8f9f7	2786	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2787	* @retval None
<>	144:ef7eb2e8f9f7	2788	*/
<>	144:ef7eb2e8f9f7	2789	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	2790	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	2791	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
<>	144:ef7eb2e8f9f7	2792	#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2793	((ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_MODE_INDEPENDENT) \|\| \
<>	144:ef7eb2e8f9f7	2794	(IS_ADC_MULTIMODE_MASTER_INSTANCE((__HANDLE__)->Instance)) )
<>	144:ef7eb2e8f9f7	2795	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	2796	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	2797	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
<>	144:ef7eb2e8f9f7	2798
<>	144:ef7eb2e8f9f7	2799	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	2800	#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2801	(!RESET)
<>	144:ef7eb2e8f9f7	2802	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	2803
<>	144:ef7eb2e8f9f7	2804	/**
<>	144:ef7eb2e8f9f7	2805	* @brief Verification of condition for ADC group regular start conversion: ADC must be in non-multimode or multimode on group injected only, or multimode with handle of ADC master (applicable for devices with several ADCs)
<>	144:ef7eb2e8f9f7	2806	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	2807	* @retval None
<>	144:ef7eb2e8f9f7	2808	*/
<>	144:ef7eb2e8f9f7	2809	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	2810	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	2811	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
<>	144:ef7eb2e8f9f7	2812	#define ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2813	((ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_MODE_INDEPENDENT) \|\| \
<>	144:ef7eb2e8f9f7	2814	(ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_INJECSIMULT) \|\| \
<>	144:ef7eb2e8f9f7	2815	(ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_ALTERTRIG) \|\| \
<>	144:ef7eb2e8f9f7	2816	(IS_ADC_MULTIMODE_MASTER_INSTANCE((__HANDLE__)->Instance)) )
<>	144:ef7eb2e8f9f7	2817	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	2818	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	2819	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
<>	144:ef7eb2e8f9f7	2820
<>	144:ef7eb2e8f9f7	2821	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	2822	#define ADC_NONMULTIMODE_REG_OR_MULTIMODEMASTER(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2823	(!RESET)
<>	144:ef7eb2e8f9f7	2824	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	2825
<>	144:ef7eb2e8f9f7	2826	/**
<>	144:ef7eb2e8f9f7	2827	* @brief Verification of condition for ADC group injected start conversion: ADC must be in non-multimode or multimode on group regular only, or multimode with handle of ADC master (applicable for devices with several ADCs)
<>	144:ef7eb2e8f9f7	2828	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	2829	* @retval None
<>	144:ef7eb2e8f9f7	2830	*/
<>	144:ef7eb2e8f9f7	2831	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	2832	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	2833	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
<>	144:ef7eb2e8f9f7	2834	#define ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2835	((ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_MODE_INDEPENDENT) \|\| \
<>	144:ef7eb2e8f9f7	2836	(ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_REGSIMULT) \|\| \
<>	144:ef7eb2e8f9f7	2837	(ADC_COMMON_CCR_MULTI(__HANDLE__) == ADC_DUALMODE_INTERL) \|\| \
<>	144:ef7eb2e8f9f7	2838	(IS_ADC_MULTIMODE_MASTER_INSTANCE((__HANDLE__)->Instance)) )
<>	144:ef7eb2e8f9f7	2839	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	2840	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	2841	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
<>	144:ef7eb2e8f9f7	2842
<>	144:ef7eb2e8f9f7	2843	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	2844	#define ADC_NONMULTIMODE_INJ_OR_MULTIMODEMASTER(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2845	(!RESET)
<>	144:ef7eb2e8f9f7	2846	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	2847
<>	144:ef7eb2e8f9f7	2848	/**
<>	144:ef7eb2e8f9f7	2849	* @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs)
<>	144:ef7eb2e8f9f7	2850	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2851	* @retval None
<>	144:ef7eb2e8f9f7	2852	*/
<>	144:ef7eb2e8f9f7	2853	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	2854	defined(STM32F303xC) \|\| defined(STM32F358xx)
<>	144:ef7eb2e8f9f7	2855	#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2856	(( (((__HANDLE__)->Instance) == ADC1) \|\| (((__HANDLE__)->Instance) == ADC2) \
<>	144:ef7eb2e8f9f7	2857	)? \
<>	144:ef7eb2e8f9f7	2858	(ADC1->CFGR & ADC_CFGR_JAUTO) \
<>	144:ef7eb2e8f9f7	2859	: \
<>	144:ef7eb2e8f9f7	2860	(ADC3->CFGR & ADC_CFGR_JAUTO) \
<>	144:ef7eb2e8f9f7	2861	)
<>	144:ef7eb2e8f9f7	2862	#elif defined(STM32F302xE) \|\| \
<>	144:ef7eb2e8f9f7	2863	defined(STM32F302xC) \|\| \
<>	144:ef7eb2e8f9f7	2864	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
<>	144:ef7eb2e8f9f7	2865	#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2866	(( (((__HANDLE__)->Instance) == ADC1) \|\| (((__HANDLE__)->Instance) == ADC2) \
<>	144:ef7eb2e8f9f7	2867	)? \
<>	144:ef7eb2e8f9f7	2868	(ADC1->CFGR & ADC_CFGR_JAUTO) \
<>	144:ef7eb2e8f9f7	2869	: \
<>	144:ef7eb2e8f9f7	2870	(RESET) \
<>	144:ef7eb2e8f9f7	2871	)
<>	144:ef7eb2e8f9f7	2872	#else
<>	144:ef7eb2e8f9f7	2873	#define ADC_MULTIMODE_AUTO_INJECTED(__HANDLE__) \
<>	144:ef7eb2e8f9f7	2874	(RESET)
<>	144:ef7eb2e8f9f7	2875	#endif /* STM32F101xG \|\| defined STM32F103x6 \|\| defined STM32F103xB \|\| defined STM32F105xC \|\| defined STM32F107xC \|\| defined STM32F103xE \|\| defined STM32F103xG */
<>	144:ef7eb2e8f9f7	2876
<>	144:ef7eb2e8f9f7	2877	/**
<>	144:ef7eb2e8f9f7	2878	* @brief Set handle of the other ADC sharing the same common register ADC1_2 or ADC3_4
<>	144:ef7eb2e8f9f7	2879	* if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
<>	144:ef7eb2e8f9f7	2880	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	2881	* @param __HANDLE_OTHER_ADC__: other ADC handle
<>	144:ef7eb2e8f9f7	2882	* @retval None
<>	144:ef7eb2e8f9f7	2883	*/
<>	144:ef7eb2e8f9f7	2884	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	2885	defined(STM32F303xC) \|\| defined(STM32F358xx)
<>	144:ef7eb2e8f9f7	2886	#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \
<>	144:ef7eb2e8f9f7	2887	( ( ((__HANDLE__)->Instance == ADC1) \
<>	144:ef7eb2e8f9f7	2888	)? \
<>	144:ef7eb2e8f9f7	2889	((__HANDLE_OTHER_ADC__)->Instance = ADC2) \
<>	144:ef7eb2e8f9f7	2890	: \
<>	144:ef7eb2e8f9f7	2891	( ( ((__HANDLE__)->Instance == ADC2) \
<>	144:ef7eb2e8f9f7	2892	)? \
<>	144:ef7eb2e8f9f7	2893	((__HANDLE_OTHER_ADC__)->Instance = ADC1) \
<>	144:ef7eb2e8f9f7	2894	: \
<>	144:ef7eb2e8f9f7	2895	( ( ((__HANDLE__)->Instance == ADC3) \
<>	144:ef7eb2e8f9f7	2896	)? \
<>	144:ef7eb2e8f9f7	2897	((__HANDLE_OTHER_ADC__)->Instance = ADC4) \
<>	144:ef7eb2e8f9f7	2898	: \
<>	144:ef7eb2e8f9f7	2899	( ( ((__HANDLE__)->Instance == ADC4) \
<>	144:ef7eb2e8f9f7	2900	)? \
<>	144:ef7eb2e8f9f7	2901	((__HANDLE_OTHER_ADC__)->Instance = ADC3) \
<>	144:ef7eb2e8f9f7	2902	: \
<>	144:ef7eb2e8f9f7	2903	((__HANDLE_OTHER_ADC__)->Instance = NULL) \
<>	144:ef7eb2e8f9f7	2904	) \
<>	144:ef7eb2e8f9f7	2905	) \
<>	144:ef7eb2e8f9f7	2906	) \
<>	144:ef7eb2e8f9f7	2907	)
<>	144:ef7eb2e8f9f7	2908	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	2909	/* STM32F303xC \|\| STM32F358xx */
<>	144:ef7eb2e8f9f7	2910
<>	144:ef7eb2e8f9f7	2911	#if defined(STM32F302xE) \|\| \
<>	144:ef7eb2e8f9f7	2912	defined(STM32F302xC) \|\| \
<>	144:ef7eb2e8f9f7	2913	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
<>	144:ef7eb2e8f9f7	2914	#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \
<>	144:ef7eb2e8f9f7	2915	( ( ((__HANDLE__)->Instance == ADC1) \
<>	144:ef7eb2e8f9f7	2916	)? \
<>	144:ef7eb2e8f9f7	2917	((__HANDLE_OTHER_ADC__)->Instance = ADC2) \
<>	144:ef7eb2e8f9f7	2918	: \
<>	144:ef7eb2e8f9f7	2919	((__HANDLE_OTHER_ADC__)->Instance = ADC1) \
<>	144:ef7eb2e8f9f7	2920	)
<>	144:ef7eb2e8f9f7	2921	#endif /* STM32F302xE \|\| */
<>	144:ef7eb2e8f9f7	2922	/* STM32F302xC \|\| */
<>	144:ef7eb2e8f9f7	2923	/* STM32F303x8 \|\| STM32F328xx \|\| STM32F334x8 */
<>	144:ef7eb2e8f9f7	2924
<>	144:ef7eb2e8f9f7	2925	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	2926	#define ADC_COMMON_ADC_OTHER(__HANDLE__, __HANDLE_OTHER_ADC__) \
<>	144:ef7eb2e8f9f7	2927	((__HANDLE_OTHER_ADC__)->Instance = NULL)
<>	144:ef7eb2e8f9f7	2928	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	2929
<>	144:ef7eb2e8f9f7	2930	/**
<>	144:ef7eb2e8f9f7	2931	* @brief Set handle of the ADC slave associated to the ADC master
<>	144:ef7eb2e8f9f7	2932	* if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
<>	144:ef7eb2e8f9f7	2933	* @param __HANDLE_MASTER__: ADC master handle
<>	144:ef7eb2e8f9f7	2934	* @param __HANDLE_SLAVE__: ADC slave handle
<>	144:ef7eb2e8f9f7	2935	* @retval None
<>	144:ef7eb2e8f9f7	2936	*/
<>	144:ef7eb2e8f9f7	2937	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	2938	defined(STM32F303xC) \|\| defined(STM32F358xx)
<>	144:ef7eb2e8f9f7	2939	#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
<>	144:ef7eb2e8f9f7	2940	( ( ((__HANDLE_MASTER__)->Instance == ADC1) \
<>	144:ef7eb2e8f9f7	2941	)? \
<>	144:ef7eb2e8f9f7	2942	((__HANDLE_SLAVE__)->Instance = ADC2) \
<>	144:ef7eb2e8f9f7	2943	: \
<>	144:ef7eb2e8f9f7	2944	( ( ((__HANDLE_MASTER__)->Instance == ADC3) \
<>	144:ef7eb2e8f9f7	2945	)? \
<>	144:ef7eb2e8f9f7	2946	((__HANDLE_SLAVE__)->Instance = ADC4) \
<>	144:ef7eb2e8f9f7	2947	: \
<>	144:ef7eb2e8f9f7	2948	((__HANDLE_SLAVE__)->Instance = NULL) \
<>	144:ef7eb2e8f9f7	2949	) \
<>	144:ef7eb2e8f9f7	2950	)
<>	144:ef7eb2e8f9f7	2951	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	2952	/* STM32F303xC \|\| STM32F358xx */
<>	144:ef7eb2e8f9f7	2953
<>	144:ef7eb2e8f9f7	2954	#if defined(STM32F302xE) \|\| \
<>	144:ef7eb2e8f9f7	2955	defined(STM32F302xC) \|\| \
<>	144:ef7eb2e8f9f7	2956	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
<>	144:ef7eb2e8f9f7	2957	#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
<>	144:ef7eb2e8f9f7	2958	( ( ((__HANDLE_MASTER__)->Instance == ADC1) \
<>	144:ef7eb2e8f9f7	2959	)? \
<>	144:ef7eb2e8f9f7	2960	((__HANDLE_SLAVE__)->Instance = ADC2) \
<>	144:ef7eb2e8f9f7	2961	: \
<>	144:ef7eb2e8f9f7	2962	( NULL ) \
<>	144:ef7eb2e8f9f7	2963	)
<>	144:ef7eb2e8f9f7	2964	#endif /* STM32F302xE \|\| */
<>	144:ef7eb2e8f9f7	2965	/* STM32F302xC \|\| */
<>	144:ef7eb2e8f9f7	2966	/* STM32F303x8 \|\| STM32F328xx \|\| STM32F334x8 */
<>	144:ef7eb2e8f9f7	2967
<>	144:ef7eb2e8f9f7	2968
<>	144:ef7eb2e8f9f7	2969	#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) \|\| \
<>	144:ef7eb2e8f9f7	2970	((RESOLUTION) == ADC_RESOLUTION_10B) \|\| \
<>	144:ef7eb2e8f9f7	2971	((RESOLUTION) == ADC_RESOLUTION_8B) \|\| \
<>	144:ef7eb2e8f9f7	2972	((RESOLUTION) == ADC_RESOLUTION_6B) )
<>	144:ef7eb2e8f9f7	2973
<>	144:ef7eb2e8f9f7	2974	#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) \|\| \
<>	144:ef7eb2e8f9f7	2975	((RESOLUTION) == ADC_RESOLUTION_6B) )
<>	144:ef7eb2e8f9f7	2976
<>	144:ef7eb2e8f9f7	2977
<>	144:ef7eb2e8f9f7	2978	#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) \|\| \
<>	144:ef7eb2e8f9f7	2979	((ALIGN) == ADC_DATAALIGN_LEFT) )
<>	144:ef7eb2e8f9f7	2980
<>	144:ef7eb2e8f9f7	2981	#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	2982	((SCAN_MODE) == ADC_SCAN_ENABLE) )
<>	144:ef7eb2e8f9f7	2983
<>	144:ef7eb2e8f9f7	2984	#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) \|\| \
<>	144:ef7eb2e8f9f7	2985	((EOC_SELECTION) == ADC_EOC_SEQ_CONV) \|\| \
<>	144:ef7eb2e8f9f7	2986	((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV) )
<>	144:ef7eb2e8f9f7	2987
<>	144:ef7eb2e8f9f7	2988	#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) \|\| \
<>	144:ef7eb2e8f9f7	2989	((OVR) == ADC_OVR_DATA_OVERWRITTEN) )
<>	144:ef7eb2e8f9f7	2990
<>	144:ef7eb2e8f9f7	2991	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	2992	((CHANNEL) == ADC_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	2993	((CHANNEL) == ADC_CHANNEL_3) \|\| \
<>	144:ef7eb2e8f9f7	2994	((CHANNEL) == ADC_CHANNEL_4) \|\| \
<>	144:ef7eb2e8f9f7	2995	((CHANNEL) == ADC_CHANNEL_5) \|\| \
<>	144:ef7eb2e8f9f7	2996	((CHANNEL) == ADC_CHANNEL_6) \|\| \
<>	144:ef7eb2e8f9f7	2997	((CHANNEL) == ADC_CHANNEL_7) \|\| \
<>	144:ef7eb2e8f9f7	2998	((CHANNEL) == ADC_CHANNEL_8) \|\| \
<>	144:ef7eb2e8f9f7	2999	((CHANNEL) == ADC_CHANNEL_9) \|\| \
<>	144:ef7eb2e8f9f7	3000	((CHANNEL) == ADC_CHANNEL_10) \|\| \
<>	144:ef7eb2e8f9f7	3001	((CHANNEL) == ADC_CHANNEL_11) \|\| \
<>	144:ef7eb2e8f9f7	3002	((CHANNEL) == ADC_CHANNEL_12) \|\| \
<>	144:ef7eb2e8f9f7	3003	((CHANNEL) == ADC_CHANNEL_13) \|\| \
<>	144:ef7eb2e8f9f7	3004	((CHANNEL) == ADC_CHANNEL_14) \|\| \
<>	144:ef7eb2e8f9f7	3005	((CHANNEL) == ADC_CHANNEL_15) \|\| \
<>	144:ef7eb2e8f9f7	3006	((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) \|\| \
<>	144:ef7eb2e8f9f7	3007	((CHANNEL) == ADC_CHANNEL_VBAT) \|\| \
<>	144:ef7eb2e8f9f7	3008	((CHANNEL) == ADC_CHANNEL_VREFINT) \|\| \
<>	144:ef7eb2e8f9f7	3009	((CHANNEL) == ADC_CHANNEL_VOPAMP1) \|\| \
<>	144:ef7eb2e8f9f7	3010	((CHANNEL) == ADC_CHANNEL_VOPAMP2) \|\| \
<>	144:ef7eb2e8f9f7	3011	((CHANNEL) == ADC_CHANNEL_VOPAMP3) \|\| \
<>	144:ef7eb2e8f9f7	3012	((CHANNEL) == ADC_CHANNEL_VOPAMP4) )
<>	144:ef7eb2e8f9f7	3013
<>	144:ef7eb2e8f9f7	3014	#define IS_ADC_DIFF_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	3015	((CHANNEL) == ADC_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	3016	((CHANNEL) == ADC_CHANNEL_3) \|\| \
<>	144:ef7eb2e8f9f7	3017	((CHANNEL) == ADC_CHANNEL_4) \|\| \
<>	144:ef7eb2e8f9f7	3018	((CHANNEL) == ADC_CHANNEL_5) \|\| \
<>	144:ef7eb2e8f9f7	3019	((CHANNEL) == ADC_CHANNEL_6) \|\| \
<>	144:ef7eb2e8f9f7	3020	((CHANNEL) == ADC_CHANNEL_7) \|\| \
<>	144:ef7eb2e8f9f7	3021	((CHANNEL) == ADC_CHANNEL_8) \|\| \
<>	144:ef7eb2e8f9f7	3022	((CHANNEL) == ADC_CHANNEL_9) \|\| \
<>	144:ef7eb2e8f9f7	3023	((CHANNEL) == ADC_CHANNEL_10) \|\| \
<>	144:ef7eb2e8f9f7	3024	((CHANNEL) == ADC_CHANNEL_11) \|\| \
<>	144:ef7eb2e8f9f7	3025	((CHANNEL) == ADC_CHANNEL_12) \|\| \
<>	144:ef7eb2e8f9f7	3026	((CHANNEL) == ADC_CHANNEL_13) \|\| \
<>	144:ef7eb2e8f9f7	3027	((CHANNEL) == ADC_CHANNEL_14) )
<>	144:ef7eb2e8f9f7	3028
<>	144:ef7eb2e8f9f7	3029	#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) \|\| \
<>	144:ef7eb2e8f9f7	3030	((TIME) == ADC_SAMPLETIME_2CYCLES_5) \|\| \
<>	144:ef7eb2e8f9f7	3031	((TIME) == ADC_SAMPLETIME_4CYCLES_5) \|\| \
<>	144:ef7eb2e8f9f7	3032	((TIME) == ADC_SAMPLETIME_7CYCLES_5) \|\| \
<>	144:ef7eb2e8f9f7	3033	((TIME) == ADC_SAMPLETIME_19CYCLES_5) \|\| \
<>	144:ef7eb2e8f9f7	3034	((TIME) == ADC_SAMPLETIME_61CYCLES_5) \|\| \
<>	144:ef7eb2e8f9f7	3035	((TIME) == ADC_SAMPLETIME_181CYCLES_5) \|\| \
<>	144:ef7eb2e8f9f7	3036	((TIME) == ADC_SAMPLETIME_601CYCLES_5) )
<>	144:ef7eb2e8f9f7	3037
<>	144:ef7eb2e8f9f7	3038	#define IS_ADC_SINGLE_DIFFERENTIAL(SING_DIFF) (((SING_DIFF) == ADC_SINGLE_ENDED) \|\| \
<>	144:ef7eb2e8f9f7	3039	((SING_DIFF) == ADC_DIFFERENTIAL_ENDED) )
<>	144:ef7eb2e8f9f7	3040
<>	144:ef7eb2e8f9f7	3041	#define IS_ADC_OFFSET_NUMBER(OFFSET_NUMBER) (((OFFSET_NUMBER) == ADC_OFFSET_NONE) \|\| \
<>	144:ef7eb2e8f9f7	3042	((OFFSET_NUMBER) == ADC_OFFSET_1) \|\| \
<>	144:ef7eb2e8f9f7	3043	((OFFSET_NUMBER) == ADC_OFFSET_2) \|\| \
<>	144:ef7eb2e8f9f7	3044	((OFFSET_NUMBER) == ADC_OFFSET_3) \|\| \
<>	144:ef7eb2e8f9f7	3045	((OFFSET_NUMBER) == ADC_OFFSET_4) )
<>	144:ef7eb2e8f9f7	3046
<>	144:ef7eb2e8f9f7	3047	#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) \|\| \
<>	144:ef7eb2e8f9f7	3048	((CHANNEL) == ADC_REGULAR_RANK_2 ) \|\| \
<>	144:ef7eb2e8f9f7	3049	((CHANNEL) == ADC_REGULAR_RANK_3 ) \|\| \
<>	144:ef7eb2e8f9f7	3050	((CHANNEL) == ADC_REGULAR_RANK_4 ) \|\| \
<>	144:ef7eb2e8f9f7	3051	((CHANNEL) == ADC_REGULAR_RANK_5 ) \|\| \
<>	144:ef7eb2e8f9f7	3052	((CHANNEL) == ADC_REGULAR_RANK_6 ) \|\| \
<>	144:ef7eb2e8f9f7	3053	((CHANNEL) == ADC_REGULAR_RANK_7 ) \|\| \
<>	144:ef7eb2e8f9f7	3054	((CHANNEL) == ADC_REGULAR_RANK_8 ) \|\| \
<>	144:ef7eb2e8f9f7	3055	((CHANNEL) == ADC_REGULAR_RANK_9 ) \|\| \
<>	144:ef7eb2e8f9f7	3056	((CHANNEL) == ADC_REGULAR_RANK_10) \|\| \
<>	144:ef7eb2e8f9f7	3057	((CHANNEL) == ADC_REGULAR_RANK_11) \|\| \
<>	144:ef7eb2e8f9f7	3058	((CHANNEL) == ADC_REGULAR_RANK_12) \|\| \
<>	144:ef7eb2e8f9f7	3059	((CHANNEL) == ADC_REGULAR_RANK_13) \|\| \
<>	144:ef7eb2e8f9f7	3060	((CHANNEL) == ADC_REGULAR_RANK_14) \|\| \
<>	144:ef7eb2e8f9f7	3061	((CHANNEL) == ADC_REGULAR_RANK_15) \|\| \
<>	144:ef7eb2e8f9f7	3062	((CHANNEL) == ADC_REGULAR_RANK_16) )
<>	144:ef7eb2e8f9f7	3063
<>	144:ef7eb2e8f9f7	3064	#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) \|\| \
<>	144:ef7eb2e8f9f7	3065	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) \|\| \
<>	144:ef7eb2e8f9f7	3066	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) \|\| \
<>	144:ef7eb2e8f9f7	3067	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
<>	144:ef7eb2e8f9f7	3068
<>	144:ef7eb2e8f9f7	3069	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	3070	defined(STM32F303xC) \|\| defined(STM32F358xx)
<>	144:ef7eb2e8f9f7	3071
<>	144:ef7eb2e8f9f7	3072	#if defined(STM32F303xC) \|\| defined(STM32F358xx)
<>	144:ef7eb2e8f9f7	3073	#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3074	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) \|\| \
<>	144:ef7eb2e8f9f7	3075	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) \|\| \
<>	144:ef7eb2e8f9f7	3076	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3077	((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3078	((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3079	((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) \|\| \
<>	144:ef7eb2e8f9f7	3080	\
<>	144:ef7eb2e8f9f7	3081	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3082	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) \|\| \
<>	144:ef7eb2e8f9f7	3083	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3084	((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3085	((REGTRIG) == ADC_EXTERNALTRIGCONV_T7_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3086	((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3087	((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT2) \|\| \
<>	144:ef7eb2e8f9f7	3088	\
<>	144:ef7eb2e8f9f7	3089	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) \|\| \
<>	144:ef7eb2e8f9f7	3090	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3091	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	3092	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3093	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3094	((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3095	((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3096	((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	3097	((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3098	\
<>	144:ef7eb2e8f9f7	3099	((REGTRIG) == ADC_SOFTWARE_START) )
<>	144:ef7eb2e8f9f7	3100	#endif /* STM32F303xC \|\| STM32F358xx */
<>	144:ef7eb2e8f9f7	3101
<>	144:ef7eb2e8f9f7	3102	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
<>	144:ef7eb2e8f9f7	3103	#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3104	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) \|\| \
<>	144:ef7eb2e8f9f7	3105	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) \|\| \
<>	144:ef7eb2e8f9f7	3106	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3107	((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3108	((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3109	((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) \|\| \
<>	144:ef7eb2e8f9f7	3110	\
<>	144:ef7eb2e8f9f7	3111	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3112	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) \|\| \
<>	144:ef7eb2e8f9f7	3113	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3114	((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3115	((REGTRIG) == ADC_EXTERNALTRIGCONV_T7_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3116	((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3117	((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT2) \|\| \
<>	144:ef7eb2e8f9f7	3118	\
<>	144:ef7eb2e8f9f7	3119	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) \|\| \
<>	144:ef7eb2e8f9f7	3120	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3121	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	3122	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3123	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3124	((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3125	((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3126	((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	3127	((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3128	\
<>	144:ef7eb2e8f9f7	3129	((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC2) \|\| \
<>	144:ef7eb2e8f9f7	3130	((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC3) \|\| \
<>	144:ef7eb2e8f9f7	3131	((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3132	((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3133	((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	3134	\
<>	144:ef7eb2e8f9f7	3135	((REGTRIG) == ADC_SOFTWARE_START) )
<>	144:ef7eb2e8f9f7	3136	#endif /* STM32F303xE \|\| STM32F398xx */
<>	144:ef7eb2e8f9f7	3137
<>	144:ef7eb2e8f9f7	3138	#endif /* STM32F303xC \|\| STM32F303xE \|\| STM32F398xx \|\| STM32F358xx */
<>	144:ef7eb2e8f9f7	3139
<>	144:ef7eb2e8f9f7	3140	#if defined(STM32F302xE) \|\| \
<>	144:ef7eb2e8f9f7	3141	defined(STM32F302xC)
<>	144:ef7eb2e8f9f7	3142
<>	144:ef7eb2e8f9f7	3143	#if defined(STM32F302xE)
<>	144:ef7eb2e8f9f7	3144	#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3145	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) \|\| \
<>	144:ef7eb2e8f9f7	3146	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) \|\| \
<>	144:ef7eb2e8f9f7	3147	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) \|\| \
<>	144:ef7eb2e8f9f7	3148	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3149	((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3150	((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) \|\| \
<>	144:ef7eb2e8f9f7	3151	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3152	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	3153	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3154	((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3155	((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3156	((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3157	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3158	\
<>	144:ef7eb2e8f9f7	3159	((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC2) \|\| \
<>	144:ef7eb2e8f9f7	3160	((REGTRIG) == ADC_EXTERNALTRIGCONV_T20_CC3) \|\| \
<>	144:ef7eb2e8f9f7	3161	\
<>	144:ef7eb2e8f9f7	3162	((REGTRIG) == ADC_SOFTWARE_START) )
<>	144:ef7eb2e8f9f7	3163	#endif /* STM32F302xE */
<>	144:ef7eb2e8f9f7	3164
<>	144:ef7eb2e8f9f7	3165	#if defined(STM32F302xC)
<>	144:ef7eb2e8f9f7	3166	#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3167	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) \|\| \
<>	144:ef7eb2e8f9f7	3168	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) \|\| \
<>	144:ef7eb2e8f9f7	3169	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) \|\| \
<>	144:ef7eb2e8f9f7	3170	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3171	((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3172	((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) \|\| \
<>	144:ef7eb2e8f9f7	3173	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3174	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	3175	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3176	((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3177	((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3178	((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3179	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3180	\
<>	144:ef7eb2e8f9f7	3181	((REGTRIG) == ADC_SOFTWARE_START) )
<>	144:ef7eb2e8f9f7	3182	#endif /* STM32F302xC */
<>	144:ef7eb2e8f9f7	3183
<>	144:ef7eb2e8f9f7	3184	#endif /* STM32F302xE \|\| */
<>	144:ef7eb2e8f9f7	3185	/* STM32F302xC */
<>	144:ef7eb2e8f9f7	3186
<>	144:ef7eb2e8f9f7	3187	#if defined(STM32F303x8) \|\| defined(STM32F328xx)
<>	144:ef7eb2e8f9f7	3188	#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3189	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) \|\| \
<>	144:ef7eb2e8f9f7	3190	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) \|\| \
<>	144:ef7eb2e8f9f7	3191	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) \|\| \
<>	144:ef7eb2e8f9f7	3192	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3193	((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3194	((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) \|\| \
<>	144:ef7eb2e8f9f7	3195	((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3196	((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	3197	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3198	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	3199	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3200	((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3201	((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3202	((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3203	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3204	\
<>	144:ef7eb2e8f9f7	3205	((REGTRIG) == ADC_SOFTWARE_START) )
<>	144:ef7eb2e8f9f7	3206	#endif /* STM32F303x8 \|\| STM32F328xx */
<>	144:ef7eb2e8f9f7	3207
<>	144:ef7eb2e8f9f7	3208	#if defined(STM32F334x8)
<>	144:ef7eb2e8f9f7	3209	#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3210	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) \|\| \
<>	144:ef7eb2e8f9f7	3211	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) \|\| \
<>	144:ef7eb2e8f9f7	3212	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) \|\| \
<>	144:ef7eb2e8f9f7	3213	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3214	((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) \|\| \
<>	144:ef7eb2e8f9f7	3215	((REGTRIG) == ADC_EXTERNALTRIGCONVHRTIM_TRG1) \|\| \
<>	144:ef7eb2e8f9f7	3216	((REGTRIG) == ADC_EXTERNALTRIGCONVHRTIM_TRG3) \|\| \
<>	144:ef7eb2e8f9f7	3217	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3218	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	3219	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3220	((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3221	((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3222	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3223	\
<>	144:ef7eb2e8f9f7	3224	((REGTRIG) == ADC_SOFTWARE_START) )
<>	144:ef7eb2e8f9f7	3225	#endif /* STM32F334x8 */
<>	144:ef7eb2e8f9f7	3226
<>	144:ef7eb2e8f9f7	3227	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	3228	#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3229	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) \|\| \
<>	144:ef7eb2e8f9f7	3230	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) \|\| \
<>	144:ef7eb2e8f9f7	3231	((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) \|\| \
<>	144:ef7eb2e8f9f7	3232	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3233	((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	3234	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3235	((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3236	((REGTRIG) == ADC_EXTERNALTRIGCONV_T15_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3237	((REGTRIG) == ADC_SOFTWARE_START) )
<>	144:ef7eb2e8f9f7	3238	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	3239
<>	144:ef7eb2e8f9f7	3240	#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) \|\| \
<>	144:ef7eb2e8f9f7	3241	((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) \|\| \
<>	144:ef7eb2e8f9f7	3242	((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) \|\| \
<>	144:ef7eb2e8f9f7	3243	((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
<>	144:ef7eb2e8f9f7	3244
<>	144:ef7eb2e8f9f7	3245
<>	144:ef7eb2e8f9f7	3246	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	3247	defined(STM32F303xC) \|\| defined(STM32F358xx)
<>	144:ef7eb2e8f9f7	3248
<>	144:ef7eb2e8f9f7	3249	#if defined(STM32F303xC) \|\| defined(STM32F358xx)
<>	144:ef7eb2e8f9f7	3250	#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3251	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3252	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3253	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3254	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) \|\| \
<>	144:ef7eb2e8f9f7	3255	\
<>	144:ef7eb2e8f9f7	3256	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) \|\| \
<>	144:ef7eb2e8f9f7	3257	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3258	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3259	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) \|\| \
<>	144:ef7eb2e8f9f7	3260	\
<>	144:ef7eb2e8f9f7	3261	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3262	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3263	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	3264	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3265	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) \|\| \
<>	144:ef7eb2e8f9f7	3266	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3267	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3268	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3269	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3270	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	3271	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3272	\
<>	144:ef7eb2e8f9f7	3273	((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
<>	144:ef7eb2e8f9f7	3274	#endif /* STM32F303xC \|\| STM32F358xx */
<>	144:ef7eb2e8f9f7	3275
<>	144:ef7eb2e8f9f7	3276	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
<>	144:ef7eb2e8f9f7	3277	#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3278	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3279	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3280	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3281	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) \|\| \
<>	144:ef7eb2e8f9f7	3282	\
<>	144:ef7eb2e8f9f7	3283	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) \|\| \
<>	144:ef7eb2e8f9f7	3284	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3285	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3286	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) \|\| \
<>	144:ef7eb2e8f9f7	3287	\
<>	144:ef7eb2e8f9f7	3288	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3289	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3290	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	3291	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3292	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) \|\| \
<>	144:ef7eb2e8f9f7	3293	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3294	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3295	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3296	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3297	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	3298	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3299	\
<>	144:ef7eb2e8f9f7	3300	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3301	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC2) \|\| \
<>	144:ef7eb2e8f9f7	3302	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3303	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	3304	\
<>	144:ef7eb2e8f9f7	3305	((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
<>	144:ef7eb2e8f9f7	3306	#endif /* STM32F303xE \|\| STM32F398xx */
<>	144:ef7eb2e8f9f7	3307
<>	144:ef7eb2e8f9f7	3308	#endif /* STM32F303xC \|\| STM32F303xE \|\| STM32F398xx \|\| STM32F358xx */
<>	144:ef7eb2e8f9f7	3309
<>	144:ef7eb2e8f9f7	3310	#if defined(STM32F302xE) \|\| \
<>	144:ef7eb2e8f9f7	3311	defined(STM32F302xC)
<>	144:ef7eb2e8f9f7	3312
<>	144:ef7eb2e8f9f7	3313	#if defined(STM32F302xE)
<>	144:ef7eb2e8f9f7	3314	#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3315	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3316	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	3317	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3318	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3319	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3320	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) \|\| \
<>	144:ef7eb2e8f9f7	3321	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3322	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3323	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3324	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3325	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3326	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) \|\| \
<>	144:ef7eb2e8f9f7	3327	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3328	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3329	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T20_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	3330	((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
<>	144:ef7eb2e8f9f7	3331	#endif /* STM32F302xE */
<>	144:ef7eb2e8f9f7	3332
<>	144:ef7eb2e8f9f7	3333	#if defined(STM32F302xC)
<>	144:ef7eb2e8f9f7	3334	#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3335	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3336	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	3337	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3338	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3339	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3340	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) \|\| \
<>	144:ef7eb2e8f9f7	3341	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3342	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3343	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3344	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3345	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3346	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) \|\| \
<>	144:ef7eb2e8f9f7	3347	((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
<>	144:ef7eb2e8f9f7	3348	#endif /* STM32F302xC */
<>	144:ef7eb2e8f9f7	3349
<>	144:ef7eb2e8f9f7	3350	#endif /* STM32F302xE \|\| */
<>	144:ef7eb2e8f9f7	3351	/* STM32F302xC */
<>	144:ef7eb2e8f9f7	3352
<>	144:ef7eb2e8f9f7	3353	#if defined(STM32F303x8) \|\| defined(STM32F328xx)
<>	144:ef7eb2e8f9f7	3354	#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3355	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3356	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3357	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3358	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3359	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3360	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) \|\| \
<>	144:ef7eb2e8f9f7	3361	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3362	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	3363	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3364	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	3365	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) \|\| \
<>	144:ef7eb2e8f9f7	3366	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3367	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3368	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3369	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3370	((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
<>	144:ef7eb2e8f9f7	3371	#endif /* STM32F303x8 \|\| STM32F328xx */
<>	144:ef7eb2e8f9f7	3372
<>	144:ef7eb2e8f9f7	3373	#if defined(STM32F334x8)
<>	144:ef7eb2e8f9f7	3374	#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3375	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3376	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3377	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3378	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3379	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) \|\| \
<>	144:ef7eb2e8f9f7	3380	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	3381	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG2) \|\| \
<>	144:ef7eb2e8f9f7	3382	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_HRTIM_TRG4) \|\| \
<>	144:ef7eb2e8f9f7	3383	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) \|\| \
<>	144:ef7eb2e8f9f7	3384	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3385	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3386	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3387	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3388	((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
<>	144:ef7eb2e8f9f7	3389	#endif /* STM32F334x8 */
<>	144:ef7eb2e8f9f7	3390
<>	144:ef7eb2e8f9f7	3391	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	3392	#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3393	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3394	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) \|\| \
<>	144:ef7eb2e8f9f7	3395	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	3396	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3397	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T15_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3398	((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
<>	144:ef7eb2e8f9f7	3399	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	3400
<>	144:ef7eb2e8f9f7	3401	#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) \|\| \
<>	144:ef7eb2e8f9f7	3402	((CHANNEL) == ADC_INJECTED_RANK_2) \|\| \
<>	144:ef7eb2e8f9f7	3403	((CHANNEL) == ADC_INJECTED_RANK_3) \|\| \
<>	144:ef7eb2e8f9f7	3404	((CHANNEL) == ADC_INJECTED_RANK_4) )
<>	144:ef7eb2e8f9f7	3405
<>	144:ef7eb2e8f9f7	3406	#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) \|\| \
<>	144:ef7eb2e8f9f7	3407	((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) \|\| \
<>	144:ef7eb2e8f9f7	3408	((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) \|\| \
<>	144:ef7eb2e8f9f7	3409	((MODE) == ADC_DUALMODE_REGINTERL_INJECSIMULT) \|\| \
<>	144:ef7eb2e8f9f7	3410	((MODE) == ADC_DUALMODE_INJECSIMULT) \|\| \
<>	144:ef7eb2e8f9f7	3411	((MODE) == ADC_DUALMODE_REGSIMULT) \|\| \
<>	144:ef7eb2e8f9f7	3412	((MODE) == ADC_DUALMODE_INTERL) \|\| \
<>	144:ef7eb2e8f9f7	3413	((MODE) == ADC_DUALMODE_ALTERTRIG) )
<>	144:ef7eb2e8f9f7	3414
<>	144:ef7eb2e8f9f7	3415	#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) \|\| \
<>	144:ef7eb2e8f9f7	3416	((MODE) == ADC_DMAACCESSMODE_12_10_BITS) \|\| \
<>	144:ef7eb2e8f9f7	3417	((MODE) == ADC_DMAACCESSMODE_8_6_BITS) )
<>	144:ef7eb2e8f9f7	3418
<>	144:ef7eb2e8f9f7	3419	#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_1CYCLE) \|\| \
<>	144:ef7eb2e8f9f7	3420	((DELAY) == ADC_TWOSAMPLINGDELAY_2CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	3421	((DELAY) == ADC_TWOSAMPLINGDELAY_3CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	3422	((DELAY) == ADC_TWOSAMPLINGDELAY_4CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	3423	((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	3424	((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	3425	((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	3426	((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	3427	((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	3428	((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	3429	((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	3430	((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) )
<>	144:ef7eb2e8f9f7	3431
<>	144:ef7eb2e8f9f7	3432	#define IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_1) \|\| \
<>	144:ef7eb2e8f9f7	3433	((WATCHDOG) == ADC_ANALOGWATCHDOG_2) \|\| \
<>	144:ef7eb2e8f9f7	3434	((WATCHDOG) == ADC_ANALOGWATCHDOG_3) )
<>	144:ef7eb2e8f9f7	3435
<>	144:ef7eb2e8f9f7	3436	#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) \|\| \
<>	144:ef7eb2e8f9f7	3437	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\| \
<>	144:ef7eb2e8f9f7	3438	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) \|\| \
<>	144:ef7eb2e8f9f7	3439	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) \|\| \
<>	144:ef7eb2e8f9f7	3440	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) \|\| \
<>	144:ef7eb2e8f9f7	3441	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) \|\| \
<>	144:ef7eb2e8f9f7	3442	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
<>	144:ef7eb2e8f9f7	3443
<>	144:ef7eb2e8f9f7	3444	#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) \|\| \
<>	144:ef7eb2e8f9f7	3445	((CONVERSION) == ADC_INJECTED_GROUP) \|\| \
<>	144:ef7eb2e8f9f7	3446	((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
<>	144:ef7eb2e8f9f7	3447
<>	144:ef7eb2e8f9f7	3448	#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) \|\| \
<>	144:ef7eb2e8f9f7	3449	((EVENT) == ADC_AWD2_EVENT) \|\| \
<>	144:ef7eb2e8f9f7	3450	((EVENT) == ADC_AWD3_EVENT) \|\| \
<>	144:ef7eb2e8f9f7	3451	((EVENT) == ADC_OVR_EVENT) \|\| \
<>	144:ef7eb2e8f9f7	3452	((EVENT) == ADC_JQOVF_EVENT) )
<>	144:ef7eb2e8f9f7	3453
<>	144:ef7eb2e8f9f7	3454	/** @defgroup ADCEx_range_verification ADC Extended Range Verification
<>	144:ef7eb2e8f9f7	3455	* in function of ADC resolution selected (12, 10, 8 or 6 bits)
<>	144:ef7eb2e8f9f7	3456	* @{
<>	144:ef7eb2e8f9f7	3457	*/
<>	144:ef7eb2e8f9f7	3458	#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
<>	144:ef7eb2e8f9f7	3459	((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) \|\| \
<>	144:ef7eb2e8f9f7	3460	(((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) \|\| \
<>	144:ef7eb2e8f9f7	3461	(((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) \|\| \
<>	144:ef7eb2e8f9f7	3462	(((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003F))) )
<>	144:ef7eb2e8f9f7	3463	/**
<>	144:ef7eb2e8f9f7	3464	* @}
<>	144:ef7eb2e8f9f7	3465	*/
<>	144:ef7eb2e8f9f7	3466
<>	144:ef7eb2e8f9f7	3467	/** @defgroup ADC_injected_nb_conv_verification ADC Injected Conversion Number Verification
<>	144:ef7eb2e8f9f7	3468	* @{
<>	144:ef7eb2e8f9f7	3469	*/
<>	144:ef7eb2e8f9f7	3470	#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
<>	144:ef7eb2e8f9f7	3471	/**
<>	144:ef7eb2e8f9f7	3472	* @}
<>	144:ef7eb2e8f9f7	3473	*/
<>	144:ef7eb2e8f9f7	3474
<>	144:ef7eb2e8f9f7	3475	/** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification
<>	144:ef7eb2e8f9f7	3476	* @{
<>	144:ef7eb2e8f9f7	3477	*/
<>	144:ef7eb2e8f9f7	3478	#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
<>	144:ef7eb2e8f9f7	3479	/**
<>	144:ef7eb2e8f9f7	3480	* @}
<>	144:ef7eb2e8f9f7	3481	*/
<>	144:ef7eb2e8f9f7	3482
<>	144:ef7eb2e8f9f7	3483	/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC Regular Discontinuous Mode NumberVerification
<>	144:ef7eb2e8f9f7	3484	* @{
<>	144:ef7eb2e8f9f7	3485	*/
<>	144:ef7eb2e8f9f7	3486	#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
<>	144:ef7eb2e8f9f7	3487	/**
<>	144:ef7eb2e8f9f7	3488	* @}
<>	144:ef7eb2e8f9f7	3489	*/
<>	144:ef7eb2e8f9f7	3490
<>	144:ef7eb2e8f9f7	3491	/** @defgroup ADC_calibration_factor_length_verification ADC Calibration Factor Length Verification
<>	144:ef7eb2e8f9f7	3492	* @{
<>	144:ef7eb2e8f9f7	3493	*/
<>	144:ef7eb2e8f9f7	3494	/**
<>	144:ef7eb2e8f9f7	3495	* @brief Calibration factor length verification (7 bits maximum)
<>	144:ef7eb2e8f9f7	3496	* @param _Calibration_Factor_: Calibration factor value
<>	144:ef7eb2e8f9f7	3497	* @retval None
<>	144:ef7eb2e8f9f7	3498	*/
<>	144:ef7eb2e8f9f7	3499	#define IS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= ((uint32_t)0x7F))
<>	144:ef7eb2e8f9f7	3500	/**
<>	144:ef7eb2e8f9f7	3501	* @}
<>	144:ef7eb2e8f9f7	3502	*/
<>	144:ef7eb2e8f9f7	3503
<>	144:ef7eb2e8f9f7	3504	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	3505	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	3506	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	3507	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	3508
<>	144:ef7eb2e8f9f7	3509
<>	144:ef7eb2e8f9f7	3510	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
<>	144:ef7eb2e8f9f7	3511
<>	144:ef7eb2e8f9f7	3512	/**
<>	144:ef7eb2e8f9f7	3513	* @brief Verification of ADC state: enabled or disabled
<>	144:ef7eb2e8f9f7	3514	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	3515	* @retval SET (ADC enabled) or RESET (ADC disabled)
<>	144:ef7eb2e8f9f7	3516	*/
<>	144:ef7eb2e8f9f7	3517	#define ADC_IS_ENABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	3518	((( ((__HANDLE__)->Instance->CR2 & ADC_CR2_ADON) == ADC_CR2_ADON ) \
<>	144:ef7eb2e8f9f7	3519	) ? SET : RESET)
<>	144:ef7eb2e8f9f7	3520
<>	144:ef7eb2e8f9f7	3521	/**
<>	144:ef7eb2e8f9f7	3522	* @brief Test if conversion trigger of regular group is software start
<>	144:ef7eb2e8f9f7	3523	* or external trigger.
<>	144:ef7eb2e8f9f7	3524	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	3525	* @retval SET (software start) or RESET (external trigger)
<>	144:ef7eb2e8f9f7	3526	*/
<>	144:ef7eb2e8f9f7	3527	#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
<>	144:ef7eb2e8f9f7	3528	(((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTSEL) == ADC_SOFTWARE_START)
<>	144:ef7eb2e8f9f7	3529
<>	144:ef7eb2e8f9f7	3530	/**
<>	144:ef7eb2e8f9f7	3531	* @brief Test if conversion trigger of injected group is software start
<>	144:ef7eb2e8f9f7	3532	* or external trigger.
<>	144:ef7eb2e8f9f7	3533	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	3534	* @retval SET (software start) or RESET (external trigger)
<>	144:ef7eb2e8f9f7	3535	*/
<>	144:ef7eb2e8f9f7	3536	#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
<>	144:ef7eb2e8f9f7	3537	(((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTSEL) == ADC_INJECTED_SOFTWARE_START)
<>	144:ef7eb2e8f9f7	3538
<>	144:ef7eb2e8f9f7	3539	/**
<>	144:ef7eb2e8f9f7	3540	* @brief Simultaneously clears and sets specific bits of the handle State
<>	144:ef7eb2e8f9f7	3541	* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
<>	144:ef7eb2e8f9f7	3542	* the first parameter is the ADC handle State, the second parameter is the
<>	144:ef7eb2e8f9f7	3543	* bit field to clear, the third and last parameter is the bit field to set.
<>	144:ef7eb2e8f9f7	3544	* @retval None
<>	144:ef7eb2e8f9f7	3545	*/
<>	144:ef7eb2e8f9f7	3546	#define ADC_STATE_CLR_SET MODIFY_REG
<>	144:ef7eb2e8f9f7	3547
<>	144:ef7eb2e8f9f7	3548	/**
<>	144:ef7eb2e8f9f7	3549	* @brief Clear ADC error code (set it to error code: "no error")
<>	144:ef7eb2e8f9f7	3550	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	3551	* @retval None
<>	144:ef7eb2e8f9f7	3552	*/
<>	144:ef7eb2e8f9f7	3553	#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	3554	((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
<>	144:ef7eb2e8f9f7	3555
<>	144:ef7eb2e8f9f7	3556	/**
<>	144:ef7eb2e8f9f7	3557	* @brief Set ADC number of conversions into regular channel sequence length.
<>	144:ef7eb2e8f9f7	3558	* @param _NbrOfConversion_: Regular channel sequence length
<>	144:ef7eb2e8f9f7	3559	* @retval None
<>	144:ef7eb2e8f9f7	3560	*/
<>	144:ef7eb2e8f9f7	3561	#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \
<>	144:ef7eb2e8f9f7	3562	(((_NbrOfConversion_) - (uint8_t)1) << 20)
<>	144:ef7eb2e8f9f7	3563
<>	144:ef7eb2e8f9f7	3564	/**
<>	144:ef7eb2e8f9f7	3565	* @brief Set the ADC's sample time for channel numbers between 10 and 18.
<>	144:ef7eb2e8f9f7	3566	* @param _SAMPLETIME_: Sample time parameter.
<>	144:ef7eb2e8f9f7	3567	* @param _CHANNELNB_: Channel number.
<>	144:ef7eb2e8f9f7	3568	* @retval None
<>	144:ef7eb2e8f9f7	3569	*/
<>	144:ef7eb2e8f9f7	3570	#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) \
<>	144:ef7eb2e8f9f7	3571	((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
<>	144:ef7eb2e8f9f7	3572
<>	144:ef7eb2e8f9f7	3573	/**
<>	144:ef7eb2e8f9f7	3574	* @brief Set the ADC's sample time for channel numbers between 0 and 9.
<>	144:ef7eb2e8f9f7	3575	* @param _SAMPLETIME_: Sample time parameter.
<>	144:ef7eb2e8f9f7	3576	* @param _CHANNELNB_: Channel number.
<>	144:ef7eb2e8f9f7	3577	* @retval None
<>	144:ef7eb2e8f9f7	3578	*/
<>	144:ef7eb2e8f9f7	3579	#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \
<>	144:ef7eb2e8f9f7	3580	((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
<>	144:ef7eb2e8f9f7	3581
<>	144:ef7eb2e8f9f7	3582	/**
<>	144:ef7eb2e8f9f7	3583	* @brief Set the selected regular channel rank for rank between 1 and 6.
<>	144:ef7eb2e8f9f7	3584	* @param _CHANNELNB_: Channel number.
<>	144:ef7eb2e8f9f7	3585	* @param _RANKNB_: Rank number.
<>	144:ef7eb2e8f9f7	3586	* @retval None
<>	144:ef7eb2e8f9f7	3587	*/
<>	144:ef7eb2e8f9f7	3588	#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \
<>	144:ef7eb2e8f9f7	3589	((_CHANNELNB_) << (5 * ((_RANKNB_) - 1)))
<>	144:ef7eb2e8f9f7	3590
<>	144:ef7eb2e8f9f7	3591	/**
<>	144:ef7eb2e8f9f7	3592	* @brief Set the selected regular channel rank for rank between 7 and 12.
<>	144:ef7eb2e8f9f7	3593	* @param _CHANNELNB_: Channel number.
<>	144:ef7eb2e8f9f7	3594	* @param _RANKNB_: Rank number.
<>	144:ef7eb2e8f9f7	3595	* @retval None
<>	144:ef7eb2e8f9f7	3596	*/
<>	144:ef7eb2e8f9f7	3597	#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \
<>	144:ef7eb2e8f9f7	3598	((_CHANNELNB_) << (5 * ((_RANKNB_) - 7)))
<>	144:ef7eb2e8f9f7	3599
<>	144:ef7eb2e8f9f7	3600	/**
<>	144:ef7eb2e8f9f7	3601	* @brief Set the selected regular channel rank for rank between 13 and 16.
<>	144:ef7eb2e8f9f7	3602	* @param _CHANNELNB_: Channel number.
<>	144:ef7eb2e8f9f7	3603	* @param _RANKNB_: Rank number.
<>	144:ef7eb2e8f9f7	3604	* @retval None
<>	144:ef7eb2e8f9f7	3605	*/
<>	144:ef7eb2e8f9f7	3606	#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \
<>	144:ef7eb2e8f9f7	3607	((_CHANNELNB_) << (5 * ((_RANKNB_) - 13)))
<>	144:ef7eb2e8f9f7	3608
<>	144:ef7eb2e8f9f7	3609	/**
<>	144:ef7eb2e8f9f7	3610	* @brief Set the injected sequence length.
<>	144:ef7eb2e8f9f7	3611	* @param _JSQR_JL_: Sequence length.
<>	144:ef7eb2e8f9f7	3612	* @retval None
<>	144:ef7eb2e8f9f7	3613	*/
<>	144:ef7eb2e8f9f7	3614	#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) \
<>	144:ef7eb2e8f9f7	3615	(((_JSQR_JL_) -1) << 20)
<>	144:ef7eb2e8f9f7	3616
<>	144:ef7eb2e8f9f7	3617	/**
<>	144:ef7eb2e8f9f7	3618	* @brief Set the selected injected channel rank
<>	144:ef7eb2e8f9f7	3619	* Note: on STM32F37x devices, channel rank position in JSQR register
<>	144:ef7eb2e8f9f7	3620	* is depending on total number of ranks selected into
<>	144:ef7eb2e8f9f7	3621	* injected sequencer (ranks sequence starting from 4-JL)
<>	144:ef7eb2e8f9f7	3622	* @param _CHANNELNB_: Channel number.
<>	144:ef7eb2e8f9f7	3623	* @param _RANKNB_: Rank number.
<>	144:ef7eb2e8f9f7	3624	* @param _JSQR_JL_: Sequence length.
<>	144:ef7eb2e8f9f7	3625	* @retval None
<>	144:ef7eb2e8f9f7	3626	*/
<>	144:ef7eb2e8f9f7	3627	#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \
<>	144:ef7eb2e8f9f7	3628	((_CHANNELNB_) << (5 * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
<>	144:ef7eb2e8f9f7	3629
<>	144:ef7eb2e8f9f7	3630	/**
<>	144:ef7eb2e8f9f7	3631	* @brief Enable ADC continuous conversion mode.
<>	144:ef7eb2e8f9f7	3632	* @param _CONTINUOUS_MODE_: Continuous mode.
<>	144:ef7eb2e8f9f7	3633	* @retval None
<>	144:ef7eb2e8f9f7	3634	*/
<>	144:ef7eb2e8f9f7	3635	#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \
<>	144:ef7eb2e8f9f7	3636	((_CONTINUOUS_MODE_) << 1)
<>	144:ef7eb2e8f9f7	3637
<>	144:ef7eb2e8f9f7	3638	/**
<>	144:ef7eb2e8f9f7	3639	* @brief Configures the number of discontinuous conversions for the regular group channels.
<>	144:ef7eb2e8f9f7	3640	* @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
<>	144:ef7eb2e8f9f7	3641	* @retval None
<>	144:ef7eb2e8f9f7	3642	*/
<>	144:ef7eb2e8f9f7	3643	#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \
<>	144:ef7eb2e8f9f7	3644	(((_NBR_DISCONTINUOUS_CONV_) - 1) << 13)
<>	144:ef7eb2e8f9f7	3645
<>	144:ef7eb2e8f9f7	3646	/**
<>	144:ef7eb2e8f9f7	3647	* @brief Enable ADC scan mode to convert multiple ranks with sequencer.
<>	144:ef7eb2e8f9f7	3648	* @param _SCAN_MODE_: Scan conversion mode.
<>	144:ef7eb2e8f9f7	3649	* @retval None
<>	144:ef7eb2e8f9f7	3650	*/
<>	144:ef7eb2e8f9f7	3651	/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */
<>	144:ef7eb2e8f9f7	3652	/* is equivalent to ADC_SCAN_ENABLE. */
<>	144:ef7eb2e8f9f7	3653	#define ADC_CR1_SCAN_SET(_SCAN_MODE_) \
<>	144:ef7eb2e8f9f7	3654	(( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) \|\| ((_SCAN_MODE_) == ENABLE) \
<>	144:ef7eb2e8f9f7	3655	)? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \
<>	144:ef7eb2e8f9f7	3656	)
<>	144:ef7eb2e8f9f7	3657
<>	144:ef7eb2e8f9f7	3658	/**
<>	144:ef7eb2e8f9f7	3659	* @brief Calibration factor in differential mode to be set into calibration register
<>	144:ef7eb2e8f9f7	3660	* @param _Calibration_Factor_: Calibration factor value
<>	144:ef7eb2e8f9f7	3661	* @retval None
<>	144:ef7eb2e8f9f7	3662	*/
<>	144:ef7eb2e8f9f7	3663	#define ADC_CALFACT_DIFF_SET(_Calibration_Factor_) \
<>	144:ef7eb2e8f9f7	3664	((_Calibration_Factor_) << 16)
<>	144:ef7eb2e8f9f7	3665
<>	144:ef7eb2e8f9f7	3666	/**
<>	144:ef7eb2e8f9f7	3667	* @brief Calibration factor in differential mode to be retrieved from calibration register
<>	144:ef7eb2e8f9f7	3668	* @param _Calibration_Factor_: Calibration factor value
<>	144:ef7eb2e8f9f7	3669	* @retval None
<>	144:ef7eb2e8f9f7	3670	*/
<>	144:ef7eb2e8f9f7	3671	#define ADC_CALFACT_DIFF_GET(_Calibration_Factor_) \
<>	144:ef7eb2e8f9f7	3672	((_Calibration_Factor_) >> 16)
<>	144:ef7eb2e8f9f7	3673
<>	144:ef7eb2e8f9f7	3674
<>	144:ef7eb2e8f9f7	3675	/**
<>	144:ef7eb2e8f9f7	3676	* @brief Get the maximum ADC conversion cycles on all channels.
<>	144:ef7eb2e8f9f7	3677	* Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
<>	144:ef7eb2e8f9f7	3678	* Approximation of sampling time within 4 ranges, returns the highest value:
<>	144:ef7eb2e8f9f7	3679	* below 7.5 cycles {1.5 cycle; 7.5 cycles},
<>	144:ef7eb2e8f9f7	3680	* between 13.5 cycles and 28.5 cycles {13.5 cycles; 28.5 cycles}
<>	144:ef7eb2e8f9f7	3681	* between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles}
<>	144:ef7eb2e8f9f7	3682	* equal to 239.5 cycles
<>	144:ef7eb2e8f9f7	3683	* Unit: ADC clock cycles
<>	144:ef7eb2e8f9f7	3684	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	3685	* @retval ADC conversion cycles on all channels
<>	144:ef7eb2e8f9f7	3686	*/
<>	144:ef7eb2e8f9f7	3687	#define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	3688	(( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET) && \
<>	144:ef7eb2e8f9f7	3689	(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ? \
<>	144:ef7eb2e8f9f7	3690	\
<>	144:ef7eb2e8f9f7	3691	(( (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
<>	144:ef7eb2e8f9f7	3692	(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET) ) ? \
<>	144:ef7eb2e8f9f7	3693	ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_7CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_28CYCLES5) \
<>	144:ef7eb2e8f9f7	3694	: \
<>	144:ef7eb2e8f9f7	3695	((((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1) == RESET) && \
<>	144:ef7eb2e8f9f7	3696	(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1) == RESET)) \|\| \
<>	144:ef7eb2e8f9f7	3697	((((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET) && \
<>	144:ef7eb2e8f9f7	3698	(((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0) == RESET))) ? \
<>	144:ef7eb2e8f9f7	3699	ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_71CYCLES5 : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_239CYCLES5) \
<>	144:ef7eb2e8f9f7	3700	)
<>	144:ef7eb2e8f9f7	3701
<>	144:ef7eb2e8f9f7	3702	/**
<>	144:ef7eb2e8f9f7	3703	* @brief Get the total ADC clock prescaler (APB2 prescaler x ADC prescaler)
<>	144:ef7eb2e8f9f7	3704	* from system clock configuration register.
<>	144:ef7eb2e8f9f7	3705	* Approximation within 3 ranges, returns the higher value:
<>	144:ef7eb2e8f9f7	3706	* total prescaler minimum: 2 (ADC presc 2, APB2 presc 0)
<>	144:ef7eb2e8f9f7	3707	* total prescaler 32 (ADC presc 0 and APB2 presc all, or
<>	144:ef7eb2e8f9f7	3708	* ADC presc {4, 6, 8} and APB2 presc {0, 2, 4})
<>	144:ef7eb2e8f9f7	3709	* total prescaler maximum: 128 (ADC presc {4, 6, 8} and APB2 presc {8, 16})
<>	144:ef7eb2e8f9f7	3710	* Unit: none (prescaler factor)
<>	144:ef7eb2e8f9f7	3711	* @retval ADC and APB2 prescaler factor
<>	144:ef7eb2e8f9f7	3712	*/
<>	144:ef7eb2e8f9f7	3713	#define ADC_CLOCK_PRESCALER_RANGE() \
<>	144:ef7eb2e8f9f7	3714	(( (RCC->CFGR & (RCC_CFGR_ADCPRE_1 \| RCC_CFGR_ADCPRE_0)) == RESET) ? \
<>	144:ef7eb2e8f9f7	3715	(( (RCC->CFGR & RCC_CFGR_PPRE2_2) == RESET) ? 2 : 32 ) \
<>	144:ef7eb2e8f9f7	3716	: \
<>	144:ef7eb2e8f9f7	3717	(( (RCC->CFGR & RCC_CFGR_PPRE2_1) == RESET) ? 32 : 128 ) \
<>	144:ef7eb2e8f9f7	3718	)
<>	144:ef7eb2e8f9f7	3719
<>	144:ef7eb2e8f9f7	3720	/**
<>	144:ef7eb2e8f9f7	3721	* @brief Get the ADC clock prescaler from system clock configuration register.
<>	144:ef7eb2e8f9f7	3722	* @retval None
<>	144:ef7eb2e8f9f7	3723	*/
<>	144:ef7eb2e8f9f7	3724	#define ADC_GET_CLOCK_PRESCALER() (((RCC->CFGR & RCC_CFGR_ADCPRE) >> 14) +1)
<>	144:ef7eb2e8f9f7	3725
<>	144:ef7eb2e8f9f7	3726	#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) \|\| \
<>	144:ef7eb2e8f9f7	3727	((ALIGN) == ADC_DATAALIGN_LEFT) )
<>	144:ef7eb2e8f9f7	3728
<>	144:ef7eb2e8f9f7	3729	#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	3730	((SCAN_MODE) == ADC_SCAN_ENABLE) )
<>	144:ef7eb2e8f9f7	3731
<>	144:ef7eb2e8f9f7	3732	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) \|\| \
<>	144:ef7eb2e8f9f7	3733	((CHANNEL) == ADC_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	3734	((CHANNEL) == ADC_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	3735	((CHANNEL) == ADC_CHANNEL_3) \|\| \
<>	144:ef7eb2e8f9f7	3736	((CHANNEL) == ADC_CHANNEL_4) \|\| \
<>	144:ef7eb2e8f9f7	3737	((CHANNEL) == ADC_CHANNEL_5) \|\| \
<>	144:ef7eb2e8f9f7	3738	((CHANNEL) == ADC_CHANNEL_6) \|\| \
<>	144:ef7eb2e8f9f7	3739	((CHANNEL) == ADC_CHANNEL_7) \|\| \
<>	144:ef7eb2e8f9f7	3740	((CHANNEL) == ADC_CHANNEL_8) \|\| \
<>	144:ef7eb2e8f9f7	3741	((CHANNEL) == ADC_CHANNEL_9) \|\| \
<>	144:ef7eb2e8f9f7	3742	((CHANNEL) == ADC_CHANNEL_10) \|\| \
<>	144:ef7eb2e8f9f7	3743	((CHANNEL) == ADC_CHANNEL_11) \|\| \
<>	144:ef7eb2e8f9f7	3744	((CHANNEL) == ADC_CHANNEL_12) \|\| \
<>	144:ef7eb2e8f9f7	3745	((CHANNEL) == ADC_CHANNEL_13) \|\| \
<>	144:ef7eb2e8f9f7	3746	((CHANNEL) == ADC_CHANNEL_14) \|\| \
<>	144:ef7eb2e8f9f7	3747	((CHANNEL) == ADC_CHANNEL_15) \|\| \
<>	144:ef7eb2e8f9f7	3748	((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) \|\| \
<>	144:ef7eb2e8f9f7	3749	((CHANNEL) == ADC_CHANNEL_VREFINT) \|\| \
<>	144:ef7eb2e8f9f7	3750	((CHANNEL) == ADC_CHANNEL_VBAT) )
<>	144:ef7eb2e8f9f7	3751
<>	144:ef7eb2e8f9f7	3752	#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) \|\| \
<>	144:ef7eb2e8f9f7	3753	((TIME) == ADC_SAMPLETIME_7CYCLES_5) \|\| \
<>	144:ef7eb2e8f9f7	3754	((TIME) == ADC_SAMPLETIME_13CYCLES_5) \|\| \
<>	144:ef7eb2e8f9f7	3755	((TIME) == ADC_SAMPLETIME_28CYCLES_5) \|\| \
<>	144:ef7eb2e8f9f7	3756	((TIME) == ADC_SAMPLETIME_41CYCLES_5) \|\| \
<>	144:ef7eb2e8f9f7	3757	((TIME) == ADC_SAMPLETIME_55CYCLES_5) \|\| \
<>	144:ef7eb2e8f9f7	3758	((TIME) == ADC_SAMPLETIME_71CYCLES_5) \|\| \
<>	144:ef7eb2e8f9f7	3759	((TIME) == ADC_SAMPLETIME_239CYCLES_5) )
<>	144:ef7eb2e8f9f7	3760
<>	144:ef7eb2e8f9f7	3761	#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) \|\| \
<>	144:ef7eb2e8f9f7	3762	((CHANNEL) == ADC_REGULAR_RANK_2 ) \|\| \
<>	144:ef7eb2e8f9f7	3763	((CHANNEL) == ADC_REGULAR_RANK_3 ) \|\| \
<>	144:ef7eb2e8f9f7	3764	((CHANNEL) == ADC_REGULAR_RANK_4 ) \|\| \
<>	144:ef7eb2e8f9f7	3765	((CHANNEL) == ADC_REGULAR_RANK_5 ) \|\| \
<>	144:ef7eb2e8f9f7	3766	((CHANNEL) == ADC_REGULAR_RANK_6 ) \|\| \
<>	144:ef7eb2e8f9f7	3767	((CHANNEL) == ADC_REGULAR_RANK_7 ) \|\| \
<>	144:ef7eb2e8f9f7	3768	((CHANNEL) == ADC_REGULAR_RANK_8 ) \|\| \
<>	144:ef7eb2e8f9f7	3769	((CHANNEL) == ADC_REGULAR_RANK_9 ) \|\| \
<>	144:ef7eb2e8f9f7	3770	((CHANNEL) == ADC_REGULAR_RANK_10) \|\| \
<>	144:ef7eb2e8f9f7	3771	((CHANNEL) == ADC_REGULAR_RANK_11) \|\| \
<>	144:ef7eb2e8f9f7	3772	((CHANNEL) == ADC_REGULAR_RANK_12) \|\| \
<>	144:ef7eb2e8f9f7	3773	((CHANNEL) == ADC_REGULAR_RANK_13) \|\| \
<>	144:ef7eb2e8f9f7	3774	((CHANNEL) == ADC_REGULAR_RANK_14) \|\| \
<>	144:ef7eb2e8f9f7	3775	((CHANNEL) == ADC_REGULAR_RANK_15) \|\| \
<>	144:ef7eb2e8f9f7	3776	((CHANNEL) == ADC_REGULAR_RANK_16) )
<>	144:ef7eb2e8f9f7	3777
<>	144:ef7eb2e8f9f7	3778	#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) \|\| \
<>	144:ef7eb2e8f9f7	3779	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) )
<>	144:ef7eb2e8f9f7	3780
<>	144:ef7eb2e8f9f7	3781	#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) \|\| \
<>	144:ef7eb2e8f9f7	3782	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3783	((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC2) \|\| \
<>	144:ef7eb2e8f9f7	3784	((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3785	((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_CC3) \|\| \
<>	144:ef7eb2e8f9f7	3786	((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3787	((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) \|\| \
<>	144:ef7eb2e8f9f7	3788	((REGTRIG) == ADC_SOFTWARE_START) )
<>	144:ef7eb2e8f9f7	3789
<>	144:ef7eb2e8f9f7	3790	#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) \|\| \
<>	144:ef7eb2e8f9f7	3791	((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) )
<>	144:ef7eb2e8f9f7	3792
<>	144:ef7eb2e8f9f7	3793	#define IS_ADC_EXTTRIGINJEC(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3794	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3795	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) \|\| \
<>	144:ef7eb2e8f9f7	3796	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	3797	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T19_CC1) \|\| \
<>	144:ef7eb2e8f9f7	3798	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T19_CC2) \|\| \
<>	144:ef7eb2e8f9f7	3799	((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) \|\| \
<>	144:ef7eb2e8f9f7	3800	((INJTRIG) == ADC_INJECTED_SOFTWARE_START) )
<>	144:ef7eb2e8f9f7	3801
<>	144:ef7eb2e8f9f7	3802	#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) \|\| \
<>	144:ef7eb2e8f9f7	3803	((CHANNEL) == ADC_INJECTED_RANK_2) \|\| \
<>	144:ef7eb2e8f9f7	3804	((CHANNEL) == ADC_INJECTED_RANK_3) \|\| \
<>	144:ef7eb2e8f9f7	3805	((CHANNEL) == ADC_INJECTED_RANK_4) )
<>	144:ef7eb2e8f9f7	3806
<>	144:ef7eb2e8f9f7	3807	#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) \|\| \
<>	144:ef7eb2e8f9f7	3808	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\| \
<>	144:ef7eb2e8f9f7	3809	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) \|\| \
<>	144:ef7eb2e8f9f7	3810	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) \|\| \
<>	144:ef7eb2e8f9f7	3811	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) \|\| \
<>	144:ef7eb2e8f9f7	3812	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) \|\| \
<>	144:ef7eb2e8f9f7	3813	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
<>	144:ef7eb2e8f9f7	3814
<>	144:ef7eb2e8f9f7	3815	#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) \|\| \
<>	144:ef7eb2e8f9f7	3816	((CONVERSION) == ADC_INJECTED_GROUP) \|\| \
<>	144:ef7eb2e8f9f7	3817	((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
<>	144:ef7eb2e8f9f7	3818
<>	144:ef7eb2e8f9f7	3819	#define IS_ADC_EVENT_TYPE(EVENT) ((EVENT) == ADC_AWD_EVENT)
<>	144:ef7eb2e8f9f7	3820
<>	144:ef7eb2e8f9f7	3821	/** @defgroup ADCEx_range_verification ADC Extended Range Verification
<>	144:ef7eb2e8f9f7	3822	* For a unique ADC resolution: 12 bits
<>	144:ef7eb2e8f9f7	3823	* @{
<>	144:ef7eb2e8f9f7	3824	*/
<>	144:ef7eb2e8f9f7	3825	#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= ((uint32_t)0x0FFF))
<>	144:ef7eb2e8f9f7	3826	/**
<>	144:ef7eb2e8f9f7	3827	* @}
<>	144:ef7eb2e8f9f7	3828	*/
<>	144:ef7eb2e8f9f7	3829
<>	144:ef7eb2e8f9f7	3830	/** @defgroup ADC_injected_nb_conv_verification ADC Injected Conversion Number Verification
<>	144:ef7eb2e8f9f7	3831	* @{
<>	144:ef7eb2e8f9f7	3832	*/
<>	144:ef7eb2e8f9f7	3833	#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
<>	144:ef7eb2e8f9f7	3834	/**
<>	144:ef7eb2e8f9f7	3835	* @}
<>	144:ef7eb2e8f9f7	3836	*/
<>	144:ef7eb2e8f9f7	3837
<>	144:ef7eb2e8f9f7	3838	/** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification
<>	144:ef7eb2e8f9f7	3839	* @{
<>	144:ef7eb2e8f9f7	3840	*/
<>	144:ef7eb2e8f9f7	3841	#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
<>	144:ef7eb2e8f9f7	3842	/**
<>	144:ef7eb2e8f9f7	3843	* @}
<>	144:ef7eb2e8f9f7	3844	*/
<>	144:ef7eb2e8f9f7	3845
<>	144:ef7eb2e8f9f7	3846	/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC Regular Discontinuous Mode NumberVerification
<>	144:ef7eb2e8f9f7	3847	* @{
<>	144:ef7eb2e8f9f7	3848	*/
<>	144:ef7eb2e8f9f7	3849	#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
<>	144:ef7eb2e8f9f7	3850	/**
<>	144:ef7eb2e8f9f7	3851	* @}
<>	144:ef7eb2e8f9f7	3852	*/
<>	144:ef7eb2e8f9f7	3853
<>	144:ef7eb2e8f9f7	3854	#endif /* STM32F373xC \|\| STM32F378xx */
<>	144:ef7eb2e8f9f7	3855	/**
<>	144:ef7eb2e8f9f7	3856	* @}
<>	144:ef7eb2e8f9f7	3857	*/
<>	144:ef7eb2e8f9f7	3858
<>	144:ef7eb2e8f9f7	3859
<>	144:ef7eb2e8f9f7	3860	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3861	/** @addtogroup ADCEx_Exported_Functions ADCEx Exported Functions
<>	144:ef7eb2e8f9f7	3862	* @{
<>	144:ef7eb2e8f9f7	3863	*/
<>	144:ef7eb2e8f9f7	3864
<>	144:ef7eb2e8f9f7	3865	/* Initialization/de-initialization functions *********************************/
<>	144:ef7eb2e8f9f7	3866
<>	144:ef7eb2e8f9f7	3867	/** @addtogroup ADCEx_Exported_Functions_Group2 ADCEx Input and Output operation functions
<>	144:ef7eb2e8f9f7	3868	* @{
<>	144:ef7eb2e8f9f7	3869	*/
<>	144:ef7eb2e8f9f7	3870	/* I/O operation functions ****************************************************/
<>	144:ef7eb2e8f9f7	3871
<>	144:ef7eb2e8f9f7	3872	/* ADC calibration */
<>	144:ef7eb2e8f9f7	3873	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	3874	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	3875	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	3876	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	3877	HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(struct __ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
<>	144:ef7eb2e8f9f7	3878	uint32_t HAL_ADCEx_Calibration_GetValue(struct __ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
<>	144:ef7eb2e8f9f7	3879	HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(struct __ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
<>	144:ef7eb2e8f9f7	3880	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	3881	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	3882	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	3883	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	3884
<>	144:ef7eb2e8f9f7	3885	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
<>	144:ef7eb2e8f9f7	3886	HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(struct __ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	3887	#endif /* STM32F373xC \|\| STM32F378xx */
<>	144:ef7eb2e8f9f7	3888
<>	144:ef7eb2e8f9f7	3889	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	3890	HAL_StatusTypeDef HAL_ADCEx_InjectedStart(struct __ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	3891	HAL_StatusTypeDef HAL_ADCEx_InjectedStop(struct __ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	3892	HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(struct __ADC_HandleTypeDef* hadc, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	3893
<>	144:ef7eb2e8f9f7	3894	/* Non-blocking mode: Interruption */
<>	144:ef7eb2e8f9f7	3895	HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(struct __ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	3896	HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(struct __ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	3897
<>	144:ef7eb2e8f9f7	3898	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	3899	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	3900	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	3901	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	3902	/* ADC multimode */
<>	144:ef7eb2e8f9f7	3903	HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(struct __ADC_HandleTypeDef hadc, uint32_t pData, uint32_t Length);
<>	144:ef7eb2e8f9f7	3904	HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(struct __ADC_HandleTypeDef *hadc);
<>	144:ef7eb2e8f9f7	3905	uint32_t HAL_ADCEx_MultiModeGetValue(struct __ADC_HandleTypeDef *hadc);
<>	144:ef7eb2e8f9f7	3906	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	3907	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	3908	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	3909	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	3910
<>	144:ef7eb2e8f9f7	3911	/* ADC group regular stop conversion without impacting group injected */
<>	144:ef7eb2e8f9f7	3912	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	3913	HAL_StatusTypeDef HAL_ADCEx_RegularStop(struct __ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	3914	/* Non-blocking mode: Interruption */
<>	144:ef7eb2e8f9f7	3915	HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(struct __ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	3916	/* Non-blocking mode: DMA */
<>	144:ef7eb2e8f9f7	3917	HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(struct __ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	3918	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	3919	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	3920	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	3921	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	3922	/* ADC multimode */
<>	144:ef7eb2e8f9f7	3923	HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(struct __ADC_HandleTypeDef *hadc);
<>	144:ef7eb2e8f9f7	3924	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	3925	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	3926	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	3927	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	3928
<>	144:ef7eb2e8f9f7	3929	/* ADC retrieve conversion value intended to be used with polling or interruption */
<>	144:ef7eb2e8f9f7	3930	uint32_t HAL_ADCEx_InjectedGetValue(struct __ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
<>	144:ef7eb2e8f9f7	3931
<>	144:ef7eb2e8f9f7	3932	/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
<>	144:ef7eb2e8f9f7	3933	void HAL_ADCEx_InjectedConvCpltCallback(struct __ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	3934
<>	144:ef7eb2e8f9f7	3935	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	3936	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	3937	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	3938	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	3939	void HAL_ADCEx_InjectedQueueOverflowCallback(struct __ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	3940	void HAL_ADCEx_LevelOutOfWindow2Callback(struct __ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	3941	void HAL_ADCEx_LevelOutOfWindow3Callback(struct __ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	3942	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	3943	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	3944	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	3945	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	3946	/**
<>	144:ef7eb2e8f9f7	3947	* @}
<>	144:ef7eb2e8f9f7	3948	*/
<>	144:ef7eb2e8f9f7	3949
<>	144:ef7eb2e8f9f7	3950	/** @addtogroup ADCEx_Exported_Functions_Group3 ADCEx Peripheral Control functions
<>	144:ef7eb2e8f9f7	3951	* @{
<>	144:ef7eb2e8f9f7	3952	*/
<>	144:ef7eb2e8f9f7	3953	/* Peripheral Control functions ***********************************************/
<>	144:ef7eb2e8f9f7	3954	HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(struct __ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
<>	144:ef7eb2e8f9f7	3955
<>	144:ef7eb2e8f9f7	3956	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	3957	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	3958	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	3959	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	3960	HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(struct __ADC_HandleTypeDef hadc, ADC_MultiModeTypeDef multimode);
<>	144:ef7eb2e8f9f7	3961	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	3962	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	3963	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	3964	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	3965	/**
<>	144:ef7eb2e8f9f7	3966	* @}
<>	144:ef7eb2e8f9f7	3967	*/
<>	144:ef7eb2e8f9f7	3968
<>	144:ef7eb2e8f9f7	3969	/**
<>	144:ef7eb2e8f9f7	3970	* @}
<>	144:ef7eb2e8f9f7	3971	*/
<>	144:ef7eb2e8f9f7	3972
<>	144:ef7eb2e8f9f7	3973	/**
<>	144:ef7eb2e8f9f7	3974	* @}
<>	144:ef7eb2e8f9f7	3975	*/
<>	144:ef7eb2e8f9f7	3976
<>	144:ef7eb2e8f9f7	3977	/**
<>	144:ef7eb2e8f9f7	3978	* @}
<>	144:ef7eb2e8f9f7	3979	*/
<>	144:ef7eb2e8f9f7	3980
<>	144:ef7eb2e8f9f7	3981	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	3982	}
<>	144:ef7eb2e8f9f7	3983	#endif
<>	144:ef7eb2e8f9f7	3984
<>	144:ef7eb2e8f9f7	3985	#endif /__STM32F3xx_ADC_H /
<>	144:ef7eb2e8f9f7	3986
<>	144:ef7eb2e8f9f7	3987
<>	144:ef7eb2e8f9f7	3988	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	08 Mar 2017
Imports:	12
Forks:	0
Commits:	165
Dependents:	3
Dependencies:	0
Followers:	5

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Greg Steiert

Jesse Marroquin

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targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc_ex.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

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targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_adc_ex.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

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