steven niu / Mbed 2 deprecated LP1768-lowpower_test

a test code to implement and test LP1768 power control mode

Dependencies:   mbed

This code implemented some LP1768 power mode : Sleep(), DeepSleep(), PowerDown(), DeepPowerDown(), BOGD_PowerDown(). It also has a test code to test these power modes and wakeup using watch dog. The wakeup part is based on Erik's code but add implementation for LP1768. As LP1768 has debug enabled in default, it cannot be waked up in DeepSleep mode. Therefore this code use WDC reset to wake up the chips from deep sleep. The test code also allow test the power under two clock frequency (96 MHz and 48MHz). Inspired by Paul and Michael Wang, I also tested the power reduction by power off PHY. The analysis could be found in http://mbed.org/users/steniu01/notebook/lp1768-power-mode-implementation-and-measurement-/#

ClockControl/ClockControl.cpp@2:15d9501bf5b3, 2014-08-02 (annotated)

Committer:
steniu01
Date:
Sat Aug 02 16:01:23 2014 +0000
Revision:
2:15d9501bf5b3
a test code to test LP1768 power mode.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
steniu01 2:15d9501bf5b3 1 #include "ClockControl.h"
steniu01 2:15d9501bf5b3 2
steniu01 2:15d9501bf5b3 3 void setPLL0Frequency(unsigned char clkSrc, unsigned short M, unsigned char N)
steniu01 2:15d9501bf5b3 4 {
steniu01 2:15d9501bf5b3 5 LPC_SC->CLKSRCSEL = clkSrc;
steniu01 2:15d9501bf5b3 6 LPC_SC->PLL0CFG = (((unsigned int)N-1) << 16) | M-1;
steniu01 2:15d9501bf5b3 7 LPC_SC->PLL0CON = 0x01;
steniu01 2:15d9501bf5b3 8 LPC_SC->PLL0FEED = 0xAA;
steniu01 2:15d9501bf5b3 9 LPC_SC->PLL0FEED = 0x55;
steniu01 2:15d9501bf5b3 10 while (!(LPC_SC->PLL0STAT & (1<<26)));
steniu01 2:15d9501bf5b3 11
steniu01 2:15d9501bf5b3 12 LPC_SC->PLL0CON = 0x03;
steniu01 2:15d9501bf5b3 13 LPC_SC->PLL0FEED = 0xAA;
steniu01 2:15d9501bf5b3 14 LPC_SC->PLL0FEED = 0x55;
steniu01 2:15d9501bf5b3 15 }
steniu01 2:15d9501bf5b3 16
steniu01 2:15d9501bf5b3 17 void setPLL1Frequency(unsigned char clkSrc, unsigned short M, unsigned char N)
steniu01 2:15d9501bf5b3 18 {
steniu01 2:15d9501bf5b3 19 LPC_SC->CLKSRCSEL = clkSrc;
steniu01 2:15d9501bf5b3 20 LPC_SC->PLL1CFG = (((unsigned int)N-1) << 16) | M-1;
steniu01 2:15d9501bf5b3 21 LPC_SC->PLL1CON = 0x01;
steniu01 2:15d9501bf5b3 22 LPC_SC->PLL1FEED = 0xAA;
steniu01 2:15d9501bf5b3 23 LPC_SC->PLL1FEED = 0x55;
steniu01 2:15d9501bf5b3 24 while (!(LPC_SC->PLL1STAT & (1<<26)));
steniu01 2:15d9501bf5b3 25
steniu01 2:15d9501bf5b3 26 LPC_SC->PLL1CON = 0x03;
steniu01 2:15d9501bf5b3 27 LPC_SC->PLL1FEED = 0xAA;
steniu01 2:15d9501bf5b3 28 LPC_SC->PLL1FEED = 0x55;
steniu01 2:15d9501bf5b3 29 }
steniu01 2:15d9501bf5b3 30
steniu01 2:15d9501bf5b3 31 unsigned int setSystemFrequency(unsigned char clkDivider, unsigned char clkSrc, unsigned short M, unsigned char N)
steniu01 2:15d9501bf5b3 32 {
steniu01 2:15d9501bf5b3 33 setPLL0Frequency(clkSrc, M, N);
steniu01 2:15d9501bf5b3 34 LPC_SC->CCLKCFG = clkDivider - 1;
steniu01 2:15d9501bf5b3 35 SystemCoreClockUpdate();
steniu01 2:15d9501bf5b3 36 return SystemCoreClock;
steniu01 2:15d9501bf5b3 37 }