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CHIP: LPC11u6x Clock Control block driver
Typedefs | Enumerations | Functions

CHIP: LPC11u6x Clock Control block driver

Typedefs

typedef enum CHIP_SYSCTL_PLLCLKSRC CHIP_SYSCTL_PLLCLKSRC_T
 Clock sources for system PLL.
typedef enum
CHIP_SYSCTL_USBPLLCLKSRC 		CHIP_SYSCTL_USBPLLCLKSRC_T
 Clock sources for USB PLL.
typedef enum CHIP_WDTLFO_OSC CHIP_WDTLFO_OSC_T
 Watchdog and low frequency oscillator frequencies plus or minus 40%.
typedef enum CHIP_SYSCTL_MAINCLKSRC CHIP_SYSCTL_MAINCLKSRC_T
 Clock sources for main system clock.
typedef enum CHIP_SYSCTL_CLOCK CHIP_SYSCTL_CLOCK_T
 System and peripheral clocks.
typedef enum CHIP_SYSCTL_USBCLKSRC CHIP_SYSCTL_USBCLKSRC_T
 Clock sources for USB.
typedef enum CHIP_SYSCTL_CLKOUTSRC CHIP_SYSCTL_CLKOUTSRC_T
 Clock sources for CLKOUT.

Enumerations

enum  CHIP_SYSCTL_PLLCLKSRC { SYSCTL_PLLCLKSRC_IRC = 0, SYSCTL_PLLCLKSRC_MAINOSC , SYSCTL_PLLCLKSRC_RESERVED1, SYSCTL_PLLCLKSRC_RTC32K }
 

Clock sources for system PLL.

More...
enum  CHIP_SYSCTL_USBPLLCLKSRC { SYSCTL_USBPLLCLKSRC_IRC = 0, SYSCTL_USBPLLCLKSRC_MAINOSC , SYSCTL_USBPLLCLKSRC_RESERVED1, SYSCTL_USBPLLCLKSRC_RESERVED2 }
 

Clock sources for USB PLL.

More...
enum  CHIP_WDTLFO_OSC { ,
  WDTLFO_OSC_0_60, WDTLFO_OSC_1_05, WDTLFO_OSC_1_40, WDTLFO_OSC_1_75,
  WDTLFO_OSC_2_10, WDTLFO_OSC_2_40, WDTLFO_OSC_2_70, WDTLFO_OSC_3_00,
  WDTLFO_OSC_3_25, WDTLFO_OSC_3_50, WDTLFO_OSC_3_75, WDTLFO_OSC_4_00,
  WDTLFO_OSC_4_20, WDTLFO_OSC_4_40, WDTLFO_OSC_4_60
}
 

Watchdog and low frequency oscillator frequencies plus or minus 40%.

More...
enum  CHIP_SYSCTL_MAINCLKSRC { SYSCTL_MAINCLKSRC_IRC = 0, SYSCTL_MAINCLKSRC_PLLIN, SYSCTL_MAINCLKSRC_WDTOSC, SYSCTL_MAINCLKSRC_PLLOUT }
 

Clock sources for main system clock.

More...
enum  CHIP_SYSCTL_CLOCK {
  SYSCTL_CLOCK_SYS = 0, SYSCTL_CLOCK_ROM, SYSCTL_CLOCK_RAM0, SYSCTL_CLOCK_FLASHREG,
  SYSCTL_CLOCK_FLASHARRAY, SYSCTL_CLOCK_I2C0, SYSCTL_CLOCK_GPIO, SYSCTL_CLOCK_CT16B0,
  SYSCTL_CLOCK_CT16B1, SYSCTL_CLOCK_CT32B0, SYSCTL_CLOCK_CT32B1, SYSCTL_CLOCK_SSP0,
  SYSCTL_CLOCK_UART0, SYSCTL_CLOCK_ADC, SYSCTL_CLOCK_USB, SYSCTL_CLOCK_WDT,
  SYSCTL_CLOCK_IOCON, SYSCTL_CLOCK_RESERVED17, SYSCTL_CLOCK_SSP1, SYSCTL_CLOCK_PINT,
  SYSCTL_CLOCK_USART1, SYSCTL_CLOCK_USART2, SYSCTL_CLOCK_USART3_4, SYSCTL_CLOCK_P0INT,
  SYSCTL_CLOCK_GROUP0INT = SYSCTL_CLOCK_P0INT, SYSCTL_CLOCK_P1INT, SYSCTL_CLOCK_GROUP1INT = SYSCTL_CLOCK_P1INT, SYSCTL_CLOCK_I2C1,
  SYSCTL_CLOCK_RAM1, SYSCTL_CLOCK_USBRAM, SYSCTL_CLOCK_CRC, SYSCTL_CLOCK_DMA,
  SYSCTL_CLOCK_RTC, SYSCTL_CLOCK_SCT0_1
}
 

System and peripheral clocks.

More...
enum  CHIP_SYSCTL_USBCLKSRC { SYSCTL_USBCLKSRC_PLLOUT = 0, SYSCTL_USBCLKSRC_MAINSYSCLK }
 

Clock sources for USB.

More...
enum  CHIP_SYSCTL_CLKOUTSRC { SYSCTL_CLKOUTSRC_IRC = 0, SYSCTL_CLKOUTSRC_MAINOSC , SYSCTL_CLKOUTSRC_WDTOSC, SYSCTL_CLKOUTSRC_MAINSYSCLK }
 

Clock sources for CLKOUT.

More...

Functions

STATIC INLINE void Chip_Clock_SetupSystemPLL (uint8_t msel, uint8_t psel)
 Set System PLL divider values.
STATIC INLINE bool Chip_Clock_IsSystemPLLLocked (void)
 Read System PLL lock status.
void Chip_Clock_SetSystemPLLSource (CHIP_SYSCTL_PLLCLKSRC_T src)
 Set System PLL clock source.
STATIC INLINE void Chip_Clock_SetupUSBPLL (uint8_t msel, uint8_t psel)
 Set USB PLL divider values.
STATIC INLINE bool Chip_Clock_IsUSBPLLLocked (void)
 Read USB PLL lock status.
void Chip_Clock_SetUSBPLLSource (CHIP_SYSCTL_USBPLLCLKSRC_T src)
 Set USB PLL clock source.
void Chip_Clock_SetPLLBypass (bool bypass, bool highfr)
 Bypass System Oscillator and set oscillator frequency range.
STATIC INLINE void Chip_Clock_EnableRTCOsc (void)
 Enable the RTC 32KHz output.
STATIC INLINE void Chip_Clock_DisableRTCOsc (void)
 Disable the RTC 32KHz output.
STATIC INLINE void Chip_Clock_SetWDTOSC (CHIP_WDTLFO_OSC_T wdtclk, uint8_t div)
 Setup Watchdog oscillator rate and divider.
void Chip_Clock_SetMainClockSource (CHIP_SYSCTL_MAINCLKSRC_T src)
 Set main system clock source.
STATIC INLINE
CHIP_SYSCTL_MAINCLKSRC_T 		Chip_Clock_GetMainClockSource (void)
 Returns the main clock source.
STATIC INLINE void Chip_Clock_SetSysClockDiv (uint32_t div)
 Set system clock divider.
STATIC INLINE void Chip_Clock_EnablePeriphClock (CHIP_SYSCTL_CLOCK_T clk)
 Enable a system or peripheral clock.
STATIC INLINE void Chip_Clock_DisablePeriphClock (CHIP_SYSCTL_CLOCK_T clk)
 Disable a system or peripheral clock.
STATIC INLINE void Chip_Clock_SetSSP0ClockDiv (uint32_t div)
 Set SSP0 divider.
STATIC INLINE uint32_t Chip_Clock_GetSSP0ClockDiv (void)
 Return SSP0 divider.
STATIC INLINE void Chip_Clock_SetUSART0ClockDiv (uint32_t div)
 Set USART0 divider clock.
STATIC INLINE uint32_t Chip_Clock_GetUASRT0ClockDiv (void)
 Return USART0 divider.
STATIC INLINE void Chip_Clock_SetSSP1ClockDiv (uint32_t div)
 Set SSP1 divider clock.
STATIC INLINE uint32_t Chip_Clock_GetSSP1ClockDiv (void)
 Return SSP1 divider.
uint32_t Chip_Clock_SetUSARTNBaseClockRate (uint32_t rate, bool fEnable)
 Set USART 1/2/3/4 UART base rate (up to main clock rate)
uint32_t Chip_Clock_GetUSARTNBaseClockRate (void)
 Get USART 1/2/3/4 UART base rate.
STATIC INLINE void Chip_Clock_SetUSARTNBaseClockDiv (uint8_t div)
 Set USART 1/2/3/4 fractional baud rate divider clock.
STATIC INLINE uint32_t Chip_Clock_GetUSARTNBaseClockDiv (void)
 Return USART 1/2/3/4 fractional baud rate divider.
STATIC INLINE void Chip_Clock_SetUSARTNFRGDivider (uint8_t div)
 Set The USART Fractional Generator Divider.
STATIC INLINE uint32_t Chip_Clock_GetUSARTNFRGDivider (void)
 Set The USART Fractional Generator Divider.
STATIC INLINE void Chip_Clock_SetUSARTNFRGMultiplier (uint8_t mult)
 Set The USART Fractional Generator Multiplier.
STATIC INLINE uint32_t Chip_Clock_GetUSARTNFRGMultiplier (void)
 Get The USART Fractional Generator Multiplier.
void Chip_Clock_SetUSBClockSource (CHIP_SYSCTL_USBCLKSRC_T src, uint32_t div)
 Set USB clock source and divider.
void Chip_Clock_SetCLKOUTSource (CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div)
 Set CLKOUT clock source and divider.
STATIC INLINE void Chip_Clock_SetIOCONFiltClockDiv (int index, uint32_t div)
 Set IOCON glitch filter clock divider value.
STATIC INLINE uint32_t Chip_Clock_GetIOCONFiltClockDiv (int index)
 Return IOCON glitch filter clock divider value.
STATIC INLINE uint32_t Chip_Clock_GetMainOscRate (void)
 Returns the main oscillator clock rate.
STATIC INLINE uint32_t Chip_Clock_GetIntOscRate (void)
 Returns the internal oscillator (IRC) clock rate.
STATIC INLINE uint32_t Chip_Clock_GetRTCOscRate (void)
 Returns the RTC clock rate.
uint32_t Chip_Clock_GetWDTOSCRate (void)
 Return estimated watchdog oscillator rate.
uint32_t Chip_Clock_GetSystemPLLInClockRate (void)
 Return System PLL input clock rate.
uint32_t Chip_Clock_GetSystemPLLOutClockRate (void)
 Return System PLL output clock rate.
uint32_t Chip_Clock_GetUSBPLLInClockRate (void)
 Return USB PLL input clock rate.
uint32_t Chip_Clock_GetUSBPLLOutClockRate (void)
 Return USB PLL output clock rate.
uint32_t Chip_Clock_GetMainClockRate (void)
 Return main clock rate.
uint32_t Chip_Clock_GetSystemClockRate (void)
 Return system clock rate.

Typedef Documentation

typedef enum CHIP_SYSCTL_CLKOUTSRC CHIP_SYSCTL_CLKOUTSRC_T

Clock sources for CLKOUT.

typedef enum CHIP_SYSCTL_CLOCK CHIP_SYSCTL_CLOCK_T

System and peripheral clocks.

typedef enum CHIP_SYSCTL_MAINCLKSRC CHIP_SYSCTL_MAINCLKSRC_T

Clock sources for main system clock.

typedef enum CHIP_SYSCTL_PLLCLKSRC CHIP_SYSCTL_PLLCLKSRC_T

Clock sources for system PLL.

typedef enum CHIP_SYSCTL_USBCLKSRC CHIP_SYSCTL_USBCLKSRC_T

Clock sources for USB.

typedef enum CHIP_SYSCTL_USBPLLCLKSRC CHIP_SYSCTL_USBPLLCLKSRC_T

Clock sources for USB PLL.

typedef enum CHIP_WDTLFO_OSC CHIP_WDTLFO_OSC_T

Watchdog and low frequency oscillator frequencies plus or minus 40%.

Enumeration Type Documentation

enum CHIP_SYSCTL_CLKOUTSRC

Clock sources for CLKOUT.

Enumerator:
SYSCTL_CLKOUTSRC_IRC 

Internal oscillator for CLKOUT

SYSCTL_CLKOUTSRC_MAINOSC 

Main oscillator for CLKOUT

SYSCTL_CLKOUTSRC_WDTOSC 

Watchdog oscillator for CLKOUT

SYSCTL_CLKOUTSRC_MAINSYSCLK 

Main system clock for CLKOUT

Definition at line 476 of file clock_11u6x.h.

enum CHIP_SYSCTL_CLOCK

System and peripheral clocks.

Enumerator:
SYSCTL_CLOCK_SYS 

0: System clock

SYSCTL_CLOCK_ROM 

1: ROM clock

SYSCTL_CLOCK_RAM0 

2: RAM0 clock

SYSCTL_CLOCK_FLASHREG 

3: FLASH register interface clock

SYSCTL_CLOCK_FLASHARRAY 

4: FLASH array access clock

SYSCTL_CLOCK_I2C0 

5: I2C0 clock

SYSCTL_CLOCK_GPIO 

6: GPIO clock

SYSCTL_CLOCK_CT16B0 

7: 16-bit Counter/timer 0 clock

SYSCTL_CLOCK_CT16B1 

8: 16-bit Counter/timer 1 clock

SYSCTL_CLOCK_CT32B0 

9: 32-bit Counter/timer 0 clock

SYSCTL_CLOCK_CT32B1 

10: 32-bit Counter/timer 1 clock

SYSCTL_CLOCK_SSP0 

11: SSP0 clock

SYSCTL_CLOCK_UART0 

12: UART0 clock

SYSCTL_CLOCK_ADC 

13: ADC clock

SYSCTL_CLOCK_USB 

14: USB clock

SYSCTL_CLOCK_WDT 

15: Watchdog timer clock

SYSCTL_CLOCK_IOCON 

16: IOCON block clock

SYSCTL_CLOCK_RESERVED17 

17: Reserved

SYSCTL_CLOCK_SSP1 

18: SSP1 clock

SYSCTL_CLOCK_PINT 

19: GPIO Pin int register interface clock

SYSCTL_CLOCK_USART1 

20: USART1 clock

SYSCTL_CLOCK_USART2 

21: USART2 clock

SYSCTL_CLOCK_USART3_4 

22: USART3_4 clock

SYSCTL_CLOCK_P0INT 

23: GPIO GROUP1 interrupt register clock

SYSCTL_CLOCK_GROUP0INT 

23: GPIO GROUP0 interrupt register interface clock

SYSCTL_CLOCK_P1INT 

24: GPIO GROUP1 interrupt register clock

SYSCTL_CLOCK_GROUP1INT 

24: GPIO GROUP1 interrupt register interface clock

SYSCTL_CLOCK_I2C1 

25: I2C1 clock

SYSCTL_CLOCK_RAM1 

26: SRAM block clock

SYSCTL_CLOCK_USBRAM 

27: USB SRAM block clock

SYSCTL_CLOCK_CRC 

25: CRC clock

SYSCTL_CLOCK_DMA 

25: DMA clock

SYSCTL_CLOCK_RTC 

25: RTC clock

SYSCTL_CLOCK_SCT0_1 

25: SCT 0/1 clock

Definition at line 244 of file clock_11u6x.h.

enum CHIP_SYSCTL_MAINCLKSRC

Clock sources for main system clock.

Enumerator:
SYSCTL_MAINCLKSRC_IRC 

Internal oscillator

SYSCTL_MAINCLKSRC_PLLIN 

System PLL input

SYSCTL_MAINCLKSRC_WDTOSC 

Watchdog oscillator rate

SYSCTL_MAINCLKSRC_PLLOUT 

System PLL output

Definition at line 204 of file clock_11u6x.h.

enum CHIP_SYSCTL_PLLCLKSRC

Clock sources for system PLL.

Enumerator:
SYSCTL_PLLCLKSRC_IRC 

Internal oscillator in

SYSCTL_PLLCLKSRC_MAINOSC 

Crystal (main) oscillator in

SYSCTL_PLLCLKSRC_RESERVED1 

Reserved

SYSCTL_PLLCLKSRC_RTC32K 

RTC 32KHz clock

Definition at line 78 of file clock_11u6x.h.

enum CHIP_SYSCTL_USBCLKSRC

Clock sources for USB.

Enumerator:
SYSCTL_USBCLKSRC_PLLOUT 

USB PLL out

SYSCTL_USBCLKSRC_MAINSYSCLK 

Main system clock

Definition at line 456 of file clock_11u6x.h.

enum CHIP_SYSCTL_USBPLLCLKSRC

Clock sources for USB PLL.

Enumerator:
SYSCTL_USBPLLCLKSRC_IRC 

Internal oscillator in

SYSCTL_USBPLLCLKSRC_MAINOSC 

Crystal (main) oscillator in

SYSCTL_USBPLLCLKSRC_RESERVED1 

Reserved

SYSCTL_USBPLLCLKSRC_RESERVED2 

Reserved

Definition at line 119 of file clock_11u6x.h.

enum CHIP_WDTLFO_OSC

Watchdog and low frequency oscillator frequencies plus or minus 40%.

Enumerator:
WDTLFO_OSC_0_60 

0.6 MHz watchdog/LFO rate

WDTLFO_OSC_1_05 

1.05 MHz watchdog/LFO rate

WDTLFO_OSC_1_40 

1.4 MHz watchdog/LFO rate

WDTLFO_OSC_1_75 

1.75 MHz watchdog/LFO rate

WDTLFO_OSC_2_10 

2.1 MHz watchdog/LFO rate

WDTLFO_OSC_2_40 

2.4 MHz watchdog/LFO rate

WDTLFO_OSC_2_70 

2.7 MHz watchdog/LFO rate

WDTLFO_OSC_3_00 

3.0 MHz watchdog/LFO rate

WDTLFO_OSC_3_25 

3.25 MHz watchdog/LFO rate

WDTLFO_OSC_3_50 

3.5 MHz watchdog/LFO rate

WDTLFO_OSC_3_75 

3.75 MHz watchdog/LFO rate

WDTLFO_OSC_4_00 

4.0 MHz watchdog/LFO rate

WDTLFO_OSC_4_20 

4.2 MHz watchdog/LFO rate

WDTLFO_OSC_4_40 

4.4 MHz watchdog/LFO rate

WDTLFO_OSC_4_60 

4.6 MHz watchdog/LFO rate

Definition at line 170 of file clock_11u6x.h.

Function Documentation

STATIC INLINE void Chip_Clock_DisablePeriphClock ( CHIP_SYSCTL_CLOCK_T  clk )

Disable a system or peripheral clock.

Parameters:
clk: Clock to disable
Returns:
Nothing

Definition at line 296 of file clock_11u6x.h.

STATIC INLINE void Chip_Clock_DisableRTCOsc ( void   )

Disable the RTC 32KHz output.

Returns:
Nothing

Definition at line 162 of file clock_11u6x.h.

STATIC INLINE void Chip_Clock_EnablePeriphClock ( CHIP_SYSCTL_CLOCK_T  clk )

Enable a system or peripheral clock.

Parameters:
clk: Clock to enable
Returns:
Nothing

Definition at line 286 of file clock_11u6x.h.

STATIC INLINE void Chip_Clock_EnableRTCOsc ( void   )

Enable the RTC 32KHz output.

Returns:
Nothing
Note:
This clock can be used for the main clock directly, but do not use this clock with the system PLL.

Definition at line 153 of file clock_11u6x.h.

STATIC INLINE uint32_t Chip_Clock_GetIntOscRate ( void   )

Returns the internal oscillator (IRC) clock rate.

Returns:
internal oscillator (IRC) clock rate in Hz

Definition at line 531 of file clock_11u6x.h.

STATIC INLINE uint32_t Chip_Clock_GetIOCONFiltClockDiv ( int  index )

Return IOCON glitch filter clock divider value.

Parameters:
index: IOCON divider index (0 - 6) to get
Returns:
IOCON glitch filter clock divider value

Definition at line 513 of file clock_11u6x.h.

uint32_t Chip_Clock_GetMainClockRate ( void   )

Return main clock rate.

Returns:
main clock rate

Definition at line 88 of file clock_11u6x.c.

STATIC INLINE CHIP_SYSCTL_MAINCLKSRC_T Chip_Clock_GetMainClockSource ( void   )

Returns the main clock source.

Returns:
Which clock is used for the core clock source?

Definition at line 224 of file clock_11u6x.h.

STATIC INLINE uint32_t Chip_Clock_GetMainOscRate ( void   )

Returns the main oscillator clock rate.

Returns:
main oscillator clock rate in Hz

Definition at line 522 of file clock_11u6x.h.

STATIC INLINE uint32_t Chip_Clock_GetRTCOscRate ( void   )

Returns the RTC clock rate.

Returns:
RTC oscillator clock rate in Hz

Definition at line 540 of file clock_11u6x.h.

STATIC INLINE uint32_t Chip_Clock_GetSSP0ClockDiv ( void   )

Return SSP0 divider.

Returns:
divider for SSP0 clock
Note:
A value of 0 means the clock is disabled.

Definition at line 318 of file clock_11u6x.h.

STATIC INLINE uint32_t Chip_Clock_GetSSP1ClockDiv ( void   )

Return SSP1 divider.

Returns:
divider for SSP1 clock
Note:
A value of 0 means the clock is disabled.

Definition at line 362 of file clock_11u6x.h.

uint32_t Chip_Clock_GetSystemClockRate ( void   )

Return system clock rate.

Returns:
system clock rate

Definition at line 114 of file clock_11u6x.c.

uint32_t Chip_Clock_GetSystemPLLInClockRate ( void   )

Return System PLL input clock rate.

Returns:
System PLL input clock rate

Definition at line 62 of file clock_11u6x.c.

uint32_t Chip_Clock_GetSystemPLLOutClockRate ( void   )

Return System PLL output clock rate.

Returns:
System PLL output clock rate

Definition at line 33 of file clock_11u6x.c.

STATIC INLINE uint32_t Chip_Clock_GetUASRT0ClockDiv ( void   )

Return USART0 divider.

Returns:
divider for UART clock
Note:
A value of 0 means the clock is disabled.

Definition at line 340 of file clock_11u6x.h.

STATIC INLINE uint32_t Chip_Clock_GetUSARTNBaseClockDiv ( void   )

Return USART 1/2/3/4 fractional baud rate divider.

Returns:
divider for USART 1/2/3/4 fractional baud rate clock
Note:
A value of 0 means the clock is disabled. This does not affect USART0.

Definition at line 410 of file clock_11u6x.h.

uint32_t Chip_Clock_GetUSARTNBaseClockRate ( void   )

Get USART 1/2/3/4 UART base rate.

Returns:
USART 1/2/3/4 UART base rate
STATIC INLINE uint32_t Chip_Clock_GetUSARTNFRGDivider ( void   )

Set The USART Fractional Generator Divider.

Returns:
Value of USART Fractional Generator Divider

Definition at line 429 of file clock_11u6x.h.

STATIC INLINE uint32_t Chip_Clock_GetUSARTNFRGMultiplier ( void   )

Get The USART Fractional Generator Multiplier.

Returns:
Value of USART Fractional Generator Multiplier

Definition at line 448 of file clock_11u6x.h.

uint32_t Chip_Clock_GetUSBPLLInClockRate ( void   )

Return USB PLL input clock rate.

Returns:
USB PLL input clock rate
uint32_t Chip_Clock_GetUSBPLLOutClockRate ( void   )

Return USB PLL output clock rate.

Returns:
USB PLL output clock rate
uint32_t Chip_Clock_GetWDTOSCRate ( void   )

Return estimated watchdog oscillator rate.

Returns:
Estimated watchdog oscillator rate
Note:
This rate is accurate to plus or minus 40%.

Definition at line 55 of file clock_11u6x.c.

STATIC INLINE bool Chip_Clock_IsSystemPLLLocked ( void   )

Read System PLL lock status.

Returns:
true of the PLL is locked. false if not locked

Definition at line 70 of file clock_11u6x.h.

STATIC INLINE bool Chip_Clock_IsUSBPLLLocked ( void   )

Read USB PLL lock status.

Returns:
true of the PLL is locked. false if not locked

Definition at line 111 of file clock_11u6x.h.

void Chip_Clock_SetCLKOUTSource ( CHIP_SYSCTL_CLKOUTSRC_T  src,
uint32_t  div 
)

Set CLKOUT clock source and divider.

Parameters:
src: Clock source for CLKOUT
div: divider for CLKOUT clock
Returns:
Nothing
Note:
Use 0 to disable, or a divider value of 1 to 255. The CLKOUT clock rate is the clock source divided by the divider. This function will also toggle the clock source update register to update the clock source.
STATIC INLINE void Chip_Clock_SetIOCONFiltClockDiv ( int  index,
uint32_t  div 
)

Set IOCON glitch filter clock divider value.

Parameters:
index: IOCON divider index (0 - 6) to set
div: value for IOCON filter divider value
Returns:
Nothing
Note:
Use 0 to disable, or a divider value of 1 to 255.

Definition at line 503 of file clock_11u6x.h.

void Chip_Clock_SetMainClockSource ( CHIP_SYSCTL_MAINCLKSRC_T  src )

Set main system clock source.

Parameters:
src: Clock source for main system
Returns:
Nothing
Note:
This function will also toggle the clock source update register to update the clock source.
void Chip_Clock_SetPLLBypass ( bool  bypass,
bool  highfr 
)

Bypass System Oscillator and set oscillator frequency range.

Parameters:
bypass: Flag to bypass oscillator
highfr: Flag to set oscillator range from 15-25 MHz
Returns:
Nothing
Note:
Sets the PLL input to bypass the oscillator. This would be used if an external clock that is not an oscillator is attached to the XTALIN pin.
STATIC INLINE void Chip_Clock_SetSSP0ClockDiv ( uint32_t  div )

Set SSP0 divider.

Parameters:
div: divider for SSP0 clock
Returns:
Nothing
Note:
Use 0 to disable, or a divider value of 1 to 255. The SSP0 clock rate is the main system clock divided by this value.

Definition at line 308 of file clock_11u6x.h.

STATIC INLINE void Chip_Clock_SetSSP1ClockDiv ( uint32_t  div )

Set SSP1 divider clock.

Parameters:
div: divider for SSP1 clock
Returns:
Nothing
Note:
Use 0 to disable, or a divider value of 1 to 255. The SSP1 clock rate is the main system clock divided by this value.

Definition at line 352 of file clock_11u6x.h.

STATIC INLINE void Chip_Clock_SetSysClockDiv ( uint32_t  div )

Set system clock divider.

Parameters:
div: divider for system clock
Returns:
Nothing
Note:
Use 0 to disable, or a divider value of 1 to 255. The system clock rate is the main system clock divided by this value.

Definition at line 236 of file clock_11u6x.h.

void Chip_Clock_SetSystemPLLSource ( CHIP_SYSCTL_PLLCLKSRC_T  src )

Set System PLL clock source.

Parameters:
src: Clock source for system PLL
Returns:
Nothing
Note:
This function will also toggle the clock source update register to update the clock source.
STATIC INLINE void Chip_Clock_SetupSystemPLL ( uint8_t  msel,
uint8_t  psel 
)

Set System PLL divider values.

Parameters:
msel: PLL feedback divider value. M = msel + 1.
psel: PLL post divider value. P = (1<<psel).
Returns:
Nothing
Note:
See the user manual for how to setup the PLL.

Definition at line 61 of file clock_11u6x.h.

STATIC INLINE void Chip_Clock_SetupUSBPLL ( uint8_t  msel,
uint8_t  psel 
)

Set USB PLL divider values.

Parameters:
msel: PLL feedback divider value. M = msel + 1.
psel: PLL post divider value. P = (1<<psel).
Returns:
Nothing
Note:
See the user manual for how to setup the PLL.

Definition at line 102 of file clock_11u6x.h.

STATIC INLINE void Chip_Clock_SetUSART0ClockDiv ( uint32_t  div )

Set USART0 divider clock.

Parameters:
div: divider for UART clock
Returns:
Nothing
Note:
Use 0 to disable, or a divider value of 1 to 255. The UART clock rate is the main system clock divided by this value.

Definition at line 330 of file clock_11u6x.h.

STATIC INLINE void Chip_Clock_SetUSARTNBaseClockDiv ( uint8_t  div )

Set USART 1/2/3/4 fractional baud rate divider clock.

Parameters:
div: divider for USART 1/2/3/4 fractional baud rate clock
Returns:
Nothing
Note:
Use 0 to disable, or a divider value of 1 to 255. This does not affect USART0.

Definition at line 399 of file clock_11u6x.h.

uint32_t Chip_Clock_SetUSARTNBaseClockRate ( uint32_t  rate,
bool  fEnable 
)

Set USART 1/2/3/4 UART base rate (up to main clock rate)

Parameters:
rate: Desired rate for fractional divider/multipler output
fEnable: true to use fractional clocking, false for integer clocking
Returns:
Actual rate generated
Note:
USARTs 1 - 4 use the same base clock for their baud rate basis. This function is used to generate that clock, while the UART driver's SetBaud functions will attempt to get the closest baud rate from this base clock without altering it. This needs to be setup prior to individual UART setup.
UARTs need a base clock 16x faster than the baud rate, so if you need a 115.2Kbps baud rate, you will need a clock rate of at least (115.2K * 16). The UART base clock is generated from the main system clock, so fractional clocking may be the only possible choice when using a low main system clock frequency. Do not alter the FRGCLKDIV register after this call.
STATIC INLINE void Chip_Clock_SetUSARTNFRGDivider ( uint8_t  div )

Set The USART Fractional Generator Divider.

Parameters:
div: Fractional Generator Divider value, should be 0xFF
Returns:
Nothing

Definition at line 420 of file clock_11u6x.h.

STATIC INLINE void Chip_Clock_SetUSARTNFRGMultiplier ( uint8_t  mult )

Set The USART Fractional Generator Multiplier.

Parameters:
mult: An 8-bit value (0-255) U_PCLK = UARTCLKDIV/(1 + MULT/256)
Returns:
Nothing

Definition at line 439 of file clock_11u6x.h.

void Chip_Clock_SetUSBClockSource ( CHIP_SYSCTL_USBCLKSRC_T  src,
uint32_t  div 
)

Set USB clock source and divider.

Parameters:
src: Clock source for USB
div: divider for USB clock
Returns:
Nothing
Note:
Use 0 to disable, or a divider value of 1 to 255. The USB clock rate is either the main system clock or USB PLL output clock divided by this value. This function will also toggle the clock source update register to update the clock source.
void Chip_Clock_SetUSBPLLSource ( CHIP_SYSCTL_USBPLLCLKSRC_T  src )

Set USB PLL clock source.

Parameters:
src: Clock source for USB PLL
Returns:
Nothing
Note:
This function will also toggle the clock source update register to update the clock source.
STATIC INLINE void Chip_Clock_SetWDTOSC ( CHIP_WDTLFO_OSC_T  wdtclk,
uint8_t  div 
)

Setup Watchdog oscillator rate and divider.

Parameters:
wdtclk: Selected watchdog clock rate
div: Watchdog divider value, even value between 2 and 64
Returns:
Nothing
Note:
Watchdog rate = selected rate divided by divider rate

Definition at line 196 of file clock_11u6x.h.

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