Diff: POKITTO_HW/lpc_defs.h

Revision:

58:5f58a2846a20

Parent:

30:796f9611d2ac

--- a/POKITTO_HW/lpc_defs.h	Tue Oct 02 20:38:50 2018 +0000
+++ b/POKITTO_HW/lpc_defs.h	Sun Oct 07 10:06:28 2018 +0000
@@ -12,34 +12,34 @@
 #define     __IO    volatile             /*!< Defines 'read / write' permissions              */
 
 
-#define LPC_PMU_BASE              0x40038000
-#define LPC_IOCON_BASE            0x40044000
+//#define LPC_PMU_BASE              0x40038000
+//#define LPC_IOCON_BASE            0x40044000
 #define LPC_SYSCTL_BASE           0x40048000
-#define LPC_GPIO_PORT_BASE        0xA0000000
+//#define LPC_GPIO_PORT_BASE        0xA0000000
 #define LPC_GPIO_GROUP_INT0_BASE  0x4005C000
 #define LPC_GPIO_GROUP_INT1_BASE  0x40060000
 #define LPC_PIN_INT_BASE          0xA0004000
-#define LPC_USART0_BASE           0x40008000
-#define LPC_USART1_BASE           0x4006C000
-#define LPC_USART2_BASE           0x40070000
-#define LPC_USART3_BASE           0x40074000
-#define LPC_USART4_BASE           0x4004C000
-#define LPC_I2C0_BASE             0x40000000
-#define LPC_I2C1_BASE             0x40020000
-#define LPC_SSP0_BASE             0x40040000
-#define LPC_SSP1_BASE             0x40058000
+//#define LPC_USART0_BASE           0x40008000
+//#define LPC_USART1_BASE           0x4006C000
+//#define LPC_USART2_BASE           0x40070000
+//#define LPC_USART3_BASE           0x40074000
+//#define LPC_USART4_BASE           0x4004C000
+//#define LPC_I2C0_BASE             0x40000000
+//#define LPC_I2C1_BASE             0x40020000
+//#define LPC_SSP0_BASE             0x40040000
+//#define LPC_SSP1_BASE             0x40058000
 #define LPC_USB0_BASE             0x40080000
-#define LPC_ADC_BASE              0x4001C000
-#define LPC_SCT0_BASE             0x5000C000
-#define LPC_SCT1_BASE             0x5000E000
+//#define LPC_ADC_BASE              0x4001C000
+//#define LPC_SCT0_BASE             0x5000C000
+//#define LPC_SCT1_BASE             0x5000E000
 #define LPC_TIMER16_0_BASE        0x4000C000
 #define LPC_TIMER16_1_BASE        0x40010000
 #define LPC_TIMER32_0_BASE        0x40014000
 #define LPC_TIMER32_1_BASE        0x40018000
-#define LPC_RTC_BASE              0x40024000
-#define LPC_WWDT_BASE             0x40004000
-#define LPC_DMA_BASE              0x50004000
-#define LPC_CRC_BASE              0x50000000
+//#define LPC_RTC_BASE              0x40024000
+//#define LPC_WWDT_BASE             0x40004000
+//#define LPC_DMA_BASE              0x50004000
+//#define LPC_CRC_BASE              0x50000000
 #define LPC_FLASH_BASE            0x4003C000
 #define LPC_DMATRIGMUX_BASE       0x40028000UL
 
@@ -118,7 +118,7 @@
 
 
 
-#define LPC_DMA                   ((LPC_DMA_T              *) LPC_DMA_BASE)
+//#define LPC_DMA                   ((LPC_DMA_T              *) LPC_DMA_BASE)
 
 /* DMA channel source/address/next descriptor */
 typedef struct {
@@ -206,8 +206,8 @@
 /* Number of elements in an array */
 #define NELEMENTS(array)  (sizeof(array) / sizeof(array[0]))
 
-#define LPC_SCT0                  ((LPC_SCT_T              *) LPC_SCT0_BASE)
-#define LPC_SCT1                  ((LPC_SCT_T              *) LPC_SCT1_BASE)
+//#define LPC_SCT0                  ((LPC_SCT_T              *) LPC_SCT0_BASE)
+//#define LPC_SCT1                  ((LPC_SCT_T              *) LPC_SCT1_BASE)
 #define LPC_TIMER16_0             ((LPC_TIMER_T            *) LPC_TIMER16_0_BASE)
 #define LPC_TIMER16_1             ((LPC_TIMER_T            *) LPC_TIMER16_1_BASE)
 #define LPC_TIMER32_0             ((LPC_TIMER_T            *) LPC_TIMER32_0_BASE)