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PokittoLib is the library needed for programming the Pokitto DIY game console (www.pokitto.com)

mbed-pokitto/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/LPC11U6x.h@64:6e6c6c2b664e, 2018-11-18 (annotated)

Committer:: spinal
Date:: Sun Nov 18 15:47:54 2018 +0000
Revision:: 64:6e6c6c2b664e
Parent:: 5:ea7377f3d1af

added fix for directrectangle()

Who changed what in which revision?

User	Revision	Line number	New contents of line
Pokitto	5:ea7377f3d1af	1
Pokitto	5:ea7377f3d1af	2	/**************************************************************************************************//
Pokitto	5:ea7377f3d1af	3	* @file LPC11U6x.h
Pokitto	5:ea7377f3d1af	4	*
Pokitto	5:ea7377f3d1af	5	* @brief CMSIS Cortex-M0PLUS Peripheral Access Layer Header File for
Pokitto	5:ea7377f3d1af	6	* LPC11U6x from .
Pokitto	5:ea7377f3d1af	7	*
Pokitto	5:ea7377f3d1af	8	* @version V0.4
Pokitto	5:ea7377f3d1af	9	* @date 22. October 2013
Pokitto	5:ea7377f3d1af	10	*
Pokitto	5:ea7377f3d1af	11	* @note Generated with SVDConv V2.81a
Pokitto	5:ea7377f3d1af	12	* from CMSIS SVD File 'LPC11U6x.svd' Version 0.4,
Pokitto	5:ea7377f3d1af	13	*
Pokitto	5:ea7377f3d1af	14	* modified by Keil
Pokitto	5:ea7377f3d1af	15	*******************************************************************************************************/
Pokitto	5:ea7377f3d1af	16
Pokitto	5:ea7377f3d1af	17
Pokitto	5:ea7377f3d1af	18
Pokitto	5:ea7377f3d1af	19	/** @addtogroup (null)
Pokitto	5:ea7377f3d1af	20	* @{
Pokitto	5:ea7377f3d1af	21	*/
Pokitto	5:ea7377f3d1af	22
Pokitto	5:ea7377f3d1af	23	/** @addtogroup LPC11U6x
Pokitto	5:ea7377f3d1af	24	* @{
Pokitto	5:ea7377f3d1af	25	*/
Pokitto	5:ea7377f3d1af	26
Pokitto	5:ea7377f3d1af	27	#ifndef LPC11U6X_H
Pokitto	5:ea7377f3d1af	28	#define LPC11U6X_H
Pokitto	5:ea7377f3d1af	29
Pokitto	5:ea7377f3d1af	30	#ifdef __cplusplus
Pokitto	5:ea7377f3d1af	31	extern "C" {
Pokitto	5:ea7377f3d1af	32	#endif
Pokitto	5:ea7377f3d1af	33
Pokitto	5:ea7377f3d1af	34
Pokitto	5:ea7377f3d1af	35	/* ------------------------- Interrupt Number Definition ------------------------ */
Pokitto	5:ea7377f3d1af	36
Pokitto	5:ea7377f3d1af	37	typedef enum {
Pokitto	5:ea7377f3d1af	38	/* ----------------- Cortex-M0PLUS Processor Exceptions Numbers ----------------- */
Pokitto	5:ea7377f3d1af	39	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
Pokitto	5:ea7377f3d1af	40	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
Pokitto	5:ea7377f3d1af	41	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
Pokitto	5:ea7377f3d1af	42
Pokitto	5:ea7377f3d1af	43
Pokitto	5:ea7377f3d1af	44
Pokitto	5:ea7377f3d1af	45	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
Pokitto	5:ea7377f3d1af	46
Pokitto	5:ea7377f3d1af	47
Pokitto	5:ea7377f3d1af	48	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
Pokitto	5:ea7377f3d1af	49	SysTick_IRQn = -1, /!< 15 System Tick Timer /
Pokitto	5:ea7377f3d1af	50	/* --------------------- LPC11U6x Specific Interrupt Numbers -------------------- */
Pokitto	5:ea7377f3d1af	51	PIN_INT0_IRQn = 0, /!< 0 PIN_INT0 /
Pokitto	5:ea7377f3d1af	52	PIN_INT1_IRQn = 1, /!< 1 PIN_INT1 /
Pokitto	5:ea7377f3d1af	53	PIN_INT2_IRQn = 2, /!< 2 PIN_INT2 /
Pokitto	5:ea7377f3d1af	54	PIN_INT3_IRQn = 3, /!< 3 PIN_INT3 /
Pokitto	5:ea7377f3d1af	55	PIN_INT4_IRQn = 4, /!< 4 PIN_INT4 /
Pokitto	5:ea7377f3d1af	56	PIN_INT5_IRQn = 5, /!< 5 PIN_INT5 /
Pokitto	5:ea7377f3d1af	57	PIN_INT6_IRQn = 6, /!< 6 PIN_INT6 /
Pokitto	5:ea7377f3d1af	58	PIN_INT7_IRQn = 7, /!< 7 PIN_INT7 /
Pokitto	5:ea7377f3d1af	59	GINT0_IRQn = 8, /!< 8 GINT0 /
Pokitto	5:ea7377f3d1af	60	GINT1_IRQn = 9, /!< 9 GINT1 /
Pokitto	5:ea7377f3d1af	61	I2C1_IRQn = 10, /!< 10 I2C1 /
Pokitto	5:ea7377f3d1af	62	USART1_4_IRQn = 11, /!< 11 USART1_4 /
Pokitto	5:ea7377f3d1af	63	USART2_3_IRQn = 12, /!< 12 USART2_3 /
Pokitto	5:ea7377f3d1af	64	SCT0_1_IRQn = 13, /!< 13 SCT0_1 /
Pokitto	5:ea7377f3d1af	65	SSP1_IRQn = 14, /!< 14 SSP1 /
Pokitto	5:ea7377f3d1af	66	I2C0_IRQn = 15, /!< 15 I2C0 /
Pokitto	5:ea7377f3d1af	67	CT16B0_IRQn = 16, /!< 16 CT16B0 /
Pokitto	5:ea7377f3d1af	68	CT16B1_IRQn = 17, /!< 17 CT16B1 /
Pokitto	5:ea7377f3d1af	69	CT32B0_IRQn = 18, /!< 18 CT32B0 /
Pokitto	5:ea7377f3d1af	70	CT32B1_IRQn = 19, /!< 19 CT32B1 /
Pokitto	5:ea7377f3d1af	71	SSP0_IRQn = 20, /!< 20 SSP0 /
Pokitto	5:ea7377f3d1af	72	USART0_IRQn = 21, /!< 21 USART0 /
Pokitto	5:ea7377f3d1af	73	USB_IRQn = 22, /!< 22 USB /
Pokitto	5:ea7377f3d1af	74	USB_FIQ_IRQn = 23, /!< 23 USB_FIQ /
Pokitto	5:ea7377f3d1af	75	ADC_A_IRQn = 24, /!< 24 ADC_A /
Pokitto	5:ea7377f3d1af	76	RTC_IRQn = 25, /!< 25 RTC /
Pokitto	5:ea7377f3d1af	77	BOD_WDT_IRQn = 26, /!< 26 BOD_WDT /
Pokitto	5:ea7377f3d1af	78	FLASH_IRQn = 27, /!< 27 FLASH /
Pokitto	5:ea7377f3d1af	79	DMA_IRQn = 28, /!< 28 DMA /
Pokitto	5:ea7377f3d1af	80	ADC_B_IRQn = 29, /!< 29 ADC_B /
Pokitto	5:ea7377f3d1af	81	USBWAKEUP_IRQn = 30 /!< 30 USBWAKEUP /
Pokitto	5:ea7377f3d1af	82	} IRQn_Type;
Pokitto	5:ea7377f3d1af	83
Pokitto	5:ea7377f3d1af	84
Pokitto	5:ea7377f3d1af	85	/** @addtogroup Configuration_of_CMSIS
Pokitto	5:ea7377f3d1af	86	* @{
Pokitto	5:ea7377f3d1af	87	*/
Pokitto	5:ea7377f3d1af	88
Pokitto	5:ea7377f3d1af	89
Pokitto	5:ea7377f3d1af	90	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	91	/* ================ Processor and Core Peripheral Section ================ */
Pokitto	5:ea7377f3d1af	92	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	93
Pokitto	5:ea7377f3d1af	94	/* ----------------Configuration of the Cortex-M0PLUS Processor and Core Peripherals---------------- */
Pokitto	5:ea7377f3d1af	95	#define __CM0PLUS_REV 0x0000 /!< Cortex-M0PLUS Core Revision /
Pokitto	5:ea7377f3d1af	96	#define __MPU_PRESENT 0 /!< MPU present or not /
Pokitto	5:ea7377f3d1af	97	#define __NVIC_PRIO_BITS 2 /!< Number of Bits used for Priority Levels /
Pokitto	5:ea7377f3d1af	98	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
Pokitto	5:ea7377f3d1af	99	#define __VTOR_PRESENT 1 /!< Set to 1 if CPU supports Vector Table Offset Register /
Pokitto	5:ea7377f3d1af	100	/** @} / / End of group Configuration_of_CMSIS */
Pokitto	5:ea7377f3d1af	101
Pokitto	5:ea7377f3d1af	102	#include "core_cm0plus.h" /!< Cortex-M0PLUS processor and core peripherals /
Pokitto	5:ea7377f3d1af	103	#include "system_LPC11U6x.h" /!< LPC11U6x System /
Pokitto	5:ea7377f3d1af	104
Pokitto	5:ea7377f3d1af	105
Pokitto	5:ea7377f3d1af	106	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	107	/* ================ Device Specific Peripheral Section ================ */
Pokitto	5:ea7377f3d1af	108	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	109
Pokitto	5:ea7377f3d1af	110
Pokitto	5:ea7377f3d1af	111	/** @addtogroup Device_Peripheral_Registers
Pokitto	5:ea7377f3d1af	112	* @{
Pokitto	5:ea7377f3d1af	113	*/
Pokitto	5:ea7377f3d1af	114
Pokitto	5:ea7377f3d1af	115
Pokitto	5:ea7377f3d1af	116	/* ------------------- Start of section using anonymous unions ------------------ */
Pokitto	5:ea7377f3d1af	117	#if defined(__CC_ARM)
Pokitto	5:ea7377f3d1af	118	#pragma push
Pokitto	5:ea7377f3d1af	119	#pragma anon_unions
Pokitto	5:ea7377f3d1af	120	#elif defined(__ICCARM__)
Pokitto	5:ea7377f3d1af	121	#pragma language=extended
Pokitto	5:ea7377f3d1af	122	#elif defined(__GNUC__)
Pokitto	5:ea7377f3d1af	123	/* anonymous unions are enabled by default */
Pokitto	5:ea7377f3d1af	124	#elif defined(__TMS470__)
Pokitto	5:ea7377f3d1af	125	/* anonymous unions are enabled by default */
Pokitto	5:ea7377f3d1af	126	#elif defined(__TASKING__)
Pokitto	5:ea7377f3d1af	127	#pragma warning 586
Pokitto	5:ea7377f3d1af	128	#else
Pokitto	5:ea7377f3d1af	129	#warning Not supported compiler type
Pokitto	5:ea7377f3d1af	130	#endif
Pokitto	5:ea7377f3d1af	131
Pokitto	5:ea7377f3d1af	132
Pokitto	5:ea7377f3d1af	133
Pokitto	5:ea7377f3d1af	134	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	135	/* ================ I2C0 ================ */
Pokitto	5:ea7377f3d1af	136	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	137
Pokitto	5:ea7377f3d1af	138
Pokitto	5:ea7377f3d1af	139	/**
Pokitto	5:ea7377f3d1af	140	* @brief I2C-bus controller (I2C0)
Pokitto	5:ea7377f3d1af	141	*/
Pokitto	5:ea7377f3d1af	142
Pokitto	5:ea7377f3d1af	143	typedef struct { /!< I2C0 Structure /
Pokitto	5:ea7377f3d1af	144	__IO uint32_t CONSET; /*!< I2C Control Set Register. When a one is written to a bit of
Pokitto	5:ea7377f3d1af	145	this register, the corresponding bit in the I2C control register
Pokitto	5:ea7377f3d1af	146	is set. Writing a zero has no effect on the corresponding bit
Pokitto	5:ea7377f3d1af	147	in the I2C control register. */
Pokitto	5:ea7377f3d1af	148	__I uint32_t STAT; /*!< I2C Status Register. During I2C operation, this register provides
Pokitto	5:ea7377f3d1af	149	detailed status codes that allow software to determine the next
Pokitto	5:ea7377f3d1af	150	action needed. */
Pokitto	5:ea7377f3d1af	151	__IO uint32_t DAT; /*!< I2C Data Register. During master or slave transmit mode, data
Pokitto	5:ea7377f3d1af	152	to be transmitted is written to this register. During master
Pokitto	5:ea7377f3d1af	153	or slave receive mode, data that has been received may be read
Pokitto	5:ea7377f3d1af	154	from this register. */
Pokitto	5:ea7377f3d1af	155	__IO uint32_t ADR0; /*!< I2C Slave Address Register 0. Contains the 7-bit slave address
Pokitto	5:ea7377f3d1af	156	for operation of the I2C interface in slave mode, and is not
Pokitto	5:ea7377f3d1af	157	used in master mode. The least significant bit determines whether
Pokitto	5:ea7377f3d1af	158	a slave responds to the General Call address. */
Pokitto	5:ea7377f3d1af	159	__IO uint32_t SCLH; /*!< SCH Duty Cycle Register High Half Word. Determines the high
Pokitto	5:ea7377f3d1af	160	time of the I2C clock. */
Pokitto	5:ea7377f3d1af	161	__IO uint32_t SCLL; /*!< SCL Duty Cycle Register Low Half Word. Determines the low time
Pokitto	5:ea7377f3d1af	162	of the I2C clock. I2nSCLL and I2nSCLH together determine the
Pokitto	5:ea7377f3d1af	163	clock frequency generated by an I2C master and certain times
Pokitto	5:ea7377f3d1af	164	used in slave mode. */
Pokitto	5:ea7377f3d1af	165	__O uint32_t CONCLR; /*!< I2C Control Clear Register. When a one is written to a bit of
Pokitto	5:ea7377f3d1af	166	this register, the corresponding bit in the I2C control register
Pokitto	5:ea7377f3d1af	167	is cleared. Writing a zero has no effect on the corresponding
Pokitto	5:ea7377f3d1af	168	bit in the I2C control register. */
Pokitto	5:ea7377f3d1af	169	__IO uint32_t MMCTRL; /!< Monitor mode control register. /
Pokitto	5:ea7377f3d1af	170	__IO uint32_t ADR1; /*!< I2C Slave Address Register. Contains the 7-bit slave address
Pokitto	5:ea7377f3d1af	171	for operation of the I2C interface in slave mode, and is not
Pokitto	5:ea7377f3d1af	172	used in master mode. The least significant bit determines whether
Pokitto	5:ea7377f3d1af	173	a slave responds to the General Call address. */
Pokitto	5:ea7377f3d1af	174	__IO uint32_t ADR2; /*!< I2C Slave Address Register. Contains the 7-bit slave address
Pokitto	5:ea7377f3d1af	175	for operation of the I2C interface in slave mode, and is not
Pokitto	5:ea7377f3d1af	176	used in master mode. The least significant bit determines whether
Pokitto	5:ea7377f3d1af	177	a slave responds to the General Call address. */
Pokitto	5:ea7377f3d1af	178	__IO uint32_t ADR3; /*!< I2C Slave Address Register. Contains the 7-bit slave address
Pokitto	5:ea7377f3d1af	179	for operation of the I2C interface in slave mode, and is not
Pokitto	5:ea7377f3d1af	180	used in master mode. The least significant bit determines whether
Pokitto	5:ea7377f3d1af	181	a slave responds to the General Call address. */
Pokitto	5:ea7377f3d1af	182	__I uint32_t DATA_BUFFER; /*!< Data buffer register. The contents of the 8 MSBs of the I2DAT
Pokitto	5:ea7377f3d1af	183	shift register will be transferred to the DATA_BUFFER automatically
Pokitto	5:ea7377f3d1af	184	after every nine bits (8 bits of data plus ACK or NACK) has
Pokitto	5:ea7377f3d1af	185	been received on the bus. */
Pokitto	5:ea7377f3d1af	186	__IO uint32_t MASK0; /*!< I2C Slave address mask register. This mask register is associated
Pokitto	5:ea7377f3d1af	187	with I2ADR0 to determine an address match. The mask register
Pokitto	5:ea7377f3d1af	188	has no effect when comparing to the General Call address (0000000). */
Pokitto	5:ea7377f3d1af	189	__IO uint32_t MASK1; /*!< I2C Slave address mask register. This mask register is associated
Pokitto	5:ea7377f3d1af	190	with I2ADR0 to determine an address match. The mask register
Pokitto	5:ea7377f3d1af	191	has no effect when comparing to the General Call address (0000000). */
Pokitto	5:ea7377f3d1af	192	__IO uint32_t MASK2; /*!< I2C Slave address mask register. This mask register is associated
Pokitto	5:ea7377f3d1af	193	with I2ADR0 to determine an address match. The mask register
Pokitto	5:ea7377f3d1af	194	has no effect when comparing to the General Call address (0000000). */
Pokitto	5:ea7377f3d1af	195	__IO uint32_t MASK3; /*!< I2C Slave address mask register. This mask register is associated
Pokitto	5:ea7377f3d1af	196	with I2ADR0 to determine an address match. The mask register
Pokitto	5:ea7377f3d1af	197	has no effect when comparing to the General Call address (0000000). */
Pokitto	5:ea7377f3d1af	198	} LPC_I2C0_Type;
Pokitto	5:ea7377f3d1af	199
Pokitto	5:ea7377f3d1af	200
Pokitto	5:ea7377f3d1af	201	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	202	/* ================ WWDT ================ */
Pokitto	5:ea7377f3d1af	203	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	204
Pokitto	5:ea7377f3d1af	205
Pokitto	5:ea7377f3d1af	206	/**
Pokitto	5:ea7377f3d1af	207	* @brief Windowed Watchdog Timer (WWDT) (WWDT)
Pokitto	5:ea7377f3d1af	208	*/
Pokitto	5:ea7377f3d1af	209
Pokitto	5:ea7377f3d1af	210	typedef struct { /!< WWDT Structure /
Pokitto	5:ea7377f3d1af	211	__IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
Pokitto	5:ea7377f3d1af	212	and status of the Watchdog Timer. */
Pokitto	5:ea7377f3d1af	213	__IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
Pokitto	5:ea7377f3d1af	214	the time-out value. */
Pokitto	5:ea7377f3d1af	215	__O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
Pokitto	5:ea7377f3d1af	216	to this register reloads the Watchdog timer with the value contained
Pokitto	5:ea7377f3d1af	217	in WDTC. */
Pokitto	5:ea7377f3d1af	218	__I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
Pokitto	5:ea7377f3d1af	219	the current value of the Watchdog timer. */
Pokitto	5:ea7377f3d1af	220	__IO uint32_t CLKSEL; /!< Watchdog clock select register. /
Pokitto	5:ea7377f3d1af	221	__IO uint32_t WARNINT; /!< Watchdog Warning Interrupt compare value. /
Pokitto	5:ea7377f3d1af	222	__IO uint32_t WINDOW; /!< Watchdog Window compare value. /
Pokitto	5:ea7377f3d1af	223	} LPC_WWDT_Type;
Pokitto	5:ea7377f3d1af	224
Pokitto	5:ea7377f3d1af	225
Pokitto	5:ea7377f3d1af	226	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	227	/* ================ USART0 ================ */
Pokitto	5:ea7377f3d1af	228	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	229
Pokitto	5:ea7377f3d1af	230
Pokitto	5:ea7377f3d1af	231	/**
Pokitto	5:ea7377f3d1af	232	* @brief USART0 (USART0)
Pokitto	5:ea7377f3d1af	233	*/
Pokitto	5:ea7377f3d1af	234
Pokitto	5:ea7377f3d1af	235	typedef struct { /!< USART0 Structure /
Pokitto	5:ea7377f3d1af	236
Pokitto	5:ea7377f3d1af	237	union {
Pokitto	5:ea7377f3d1af	238	__IO uint32_t DLL; /*!< Divisor Latch LSB. Least significant byte of the baud rate divisor
Pokitto	5:ea7377f3d1af	239	value. The full divisor is used to generate a baud rate from
Pokitto	5:ea7377f3d1af	240	the fractional rate divider. (DLAB=1) */
Pokitto	5:ea7377f3d1af	241	__O uint32_t THR; /*!< Transmit Holding Register. The next character to be transmitted
Pokitto	5:ea7377f3d1af	242	is written here. (DLAB=0) */
Pokitto	5:ea7377f3d1af	243	__I uint32_t RBR; /*!< Receiver Buffer Register. Contains the next received character
Pokitto	5:ea7377f3d1af	244	to be read. (DLAB=0) */
Pokitto	5:ea7377f3d1af	245	};
Pokitto	5:ea7377f3d1af	246
Pokitto	5:ea7377f3d1af	247	union {
Pokitto	5:ea7377f3d1af	248	__IO uint32_t IER; /*!< Interrupt Enable Register. Contains individual interrupt enable
Pokitto	5:ea7377f3d1af	249	bits for the 7 potential USART interrupts. (DLAB=0) */
Pokitto	5:ea7377f3d1af	250	__IO uint32_t DLM; /*!< Divisor Latch MSB. Most significant byte of the baud rate divisor
Pokitto	5:ea7377f3d1af	251	value. The full divisor is used to generate a baud rate from
Pokitto	5:ea7377f3d1af	252	the fractional rate divider. (DLAB=1) */
Pokitto	5:ea7377f3d1af	253	};
Pokitto	5:ea7377f3d1af	254
Pokitto	5:ea7377f3d1af	255	union {
Pokitto	5:ea7377f3d1af	256	__O uint32_t FCR; /!< FIFO Control Register. Controls USART FIFO usage and modes. /
Pokitto	5:ea7377f3d1af	257	__I uint32_t IIR; /!< Interrupt ID Register. Identifies which interrupt(s) are pending. /
Pokitto	5:ea7377f3d1af	258	};
Pokitto	5:ea7377f3d1af	259	__IO uint32_t LCR; /*!< Line Control Register. Contains controls for frame formatting
Pokitto	5:ea7377f3d1af	260	and break generation. */
Pokitto	5:ea7377f3d1af	261	__IO uint32_t MCR; /!< Modem Control Register. /
Pokitto	5:ea7377f3d1af	262	__I uint32_t LSR; /*!< Line Status Register. Contains flags for transmit and receive
Pokitto	5:ea7377f3d1af	263	status, including line errors. */
Pokitto	5:ea7377f3d1af	264	__I uint32_t MSR; /!< Modem Status Register. /
Pokitto	5:ea7377f3d1af	265	__IO uint32_t SCR; /!< Scratch Pad Register. Eight-bit temporary storage for software. /
Pokitto	5:ea7377f3d1af	266	__IO uint32_t ACR; /*!< Auto-baud Control Register. Contains controls for the auto-baud
Pokitto	5:ea7377f3d1af	267	feature. */
Pokitto	5:ea7377f3d1af	268	__IO uint32_t ICR; /*!< IrDA Control Register. Enables and configures the IrDA (remote
Pokitto	5:ea7377f3d1af	269	control) mode. */
Pokitto	5:ea7377f3d1af	270	__IO uint32_t FDR; /*!< Fractional Divider Register. Generates a clock input for the
Pokitto	5:ea7377f3d1af	271	baud rate divider. */
Pokitto	5:ea7377f3d1af	272	__IO uint32_t OSR; /*!< Oversampling Register. Controls the degree of oversampling during
Pokitto	5:ea7377f3d1af	273	each bit time. */
Pokitto	5:ea7377f3d1af	274	__IO uint32_t TER; /*!< Transmit Enable Register. Turns off USART transmitter for use
Pokitto	5:ea7377f3d1af	275	with software flow control. */
Pokitto	5:ea7377f3d1af	276	__I uint32_t RESERVED0[3];
Pokitto	5:ea7377f3d1af	277	__IO uint32_t HDEN; /!< Half duplex enable register. /
Pokitto	5:ea7377f3d1af	278	__I uint32_t RESERVED1;
Pokitto	5:ea7377f3d1af	279	__IO uint32_t SCICTRL; /*!< Smart Card Interface Control register. Enables and configures
Pokitto	5:ea7377f3d1af	280	the Smart Card Interface feature. */
Pokitto	5:ea7377f3d1af	281	__IO uint32_t RS485CTRL; /*!< RS-485/EIA-485 Control. Contains controls to configure various
Pokitto	5:ea7377f3d1af	282	aspects of RS-485/EIA-485 modes. */
Pokitto	5:ea7377f3d1af	283	__IO uint32_t RS485ADRMATCH; /*!< RS-485/EIA-485 address match. Contains the address match value
Pokitto	5:ea7377f3d1af	284	for RS-485/EIA-485 mode. */
Pokitto	5:ea7377f3d1af	285	__IO uint32_t RS485DLY; /!< RS-485/EIA-485 direction control delay. /
Pokitto	5:ea7377f3d1af	286	__IO uint32_t SYNCCTRL; /!< Synchronous mode control register. /
Pokitto	5:ea7377f3d1af	287	} LPC_USART0_Type;
Pokitto	5:ea7377f3d1af	288
Pokitto	5:ea7377f3d1af	289
Pokitto	5:ea7377f3d1af	290	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	291	/* ================ CT16B0 ================ */
Pokitto	5:ea7377f3d1af	292	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	293
Pokitto	5:ea7377f3d1af	294
Pokitto	5:ea7377f3d1af	295	/**
Pokitto	5:ea7377f3d1af	296	* @brief 16-bit counter/timers CT16B0 (CT16B0)
Pokitto	5:ea7377f3d1af	297	*/
Pokitto	5:ea7377f3d1af	298
Pokitto	5:ea7377f3d1af	299	typedef struct { /!< CT16B0 Structure /
Pokitto	5:ea7377f3d1af	300	__IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
Pokitto	5:ea7377f3d1af	301	The IR can be read to identify which of eight possible interrupt
Pokitto	5:ea7377f3d1af	302	sources are pending. */
Pokitto	5:ea7377f3d1af	303	__IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
Pokitto	5:ea7377f3d1af	304	Counter functions. The Timer Counter can be disabled or reset
Pokitto	5:ea7377f3d1af	305	through the TCR. */
Pokitto	5:ea7377f3d1af	306	__IO uint32_t TC; /*!< Timer Counter. The 16-bit TC is incremented every PR+1 cycles
Pokitto	5:ea7377f3d1af	307	of PCLK. The TC is controlled through the TCR. */
Pokitto	5:ea7377f3d1af	308	__IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (below) is equal
Pokitto	5:ea7377f3d1af	309	to this value, the next clock increments the TC and clears the
Pokitto	5:ea7377f3d1af	310	PC. */
Pokitto	5:ea7377f3d1af	311	__IO uint32_t PC; /*!< Prescale Counter. The 16-bit PC is a counter which is incremented
Pokitto	5:ea7377f3d1af	312	to the value stored in PR. When the value in PR is reached,
Pokitto	5:ea7377f3d1af	313	the TC is incremented and the PC is cleared. The PC is observable
Pokitto	5:ea7377f3d1af	314	and controllable through the bus interface. */
Pokitto	5:ea7377f3d1af	315	__IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
Pokitto	5:ea7377f3d1af	316	is generated and if the TC is reset when a Match occurs. */
Pokitto	5:ea7377f3d1af	317	__IO uint32_t MR0; /*!< Match Register. MR can be enabled through the MCR to reset the
Pokitto	5:ea7377f3d1af	318	TC, stop both the TC and PC, and/or generate an interrupt every
Pokitto	5:ea7377f3d1af	319	time MR0 matches the TC. */
Pokitto	5:ea7377f3d1af	320	__IO uint32_t MR1; /*!< Match Register. MR can be enabled through the MCR to reset the
Pokitto	5:ea7377f3d1af	321	TC, stop both the TC and PC, and/or generate an interrupt every
Pokitto	5:ea7377f3d1af	322	time MR0 matches the TC. */
Pokitto	5:ea7377f3d1af	323	__IO uint32_t MR2; /*!< Match Register. MR can be enabled through the MCR to reset the
Pokitto	5:ea7377f3d1af	324	TC, stop both the TC and PC, and/or generate an interrupt every
Pokitto	5:ea7377f3d1af	325	time MR0 matches the TC. */
Pokitto	5:ea7377f3d1af	326	__IO uint32_t MR3; /*!< Match Register. MR can be enabled through the MCR to reset the
Pokitto	5:ea7377f3d1af	327	TC, stop both the TC and PC, and/or generate an interrupt every
Pokitto	5:ea7377f3d1af	328	time MR0 matches the TC. */
Pokitto	5:ea7377f3d1af	329	__IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
Pokitto	5:ea7377f3d1af	330	capture inputs are used to load the Capture Registers and whether
Pokitto	5:ea7377f3d1af	331	or not an interrupt is generated when a capture takes place. */
Pokitto	5:ea7377f3d1af	332	__I uint32_t CR0; /*!< Capture Register. CR is loaded with the value of TC when there
Pokitto	5:ea7377f3d1af	333	is an event on the CAP input. */
Pokitto	5:ea7377f3d1af	334	__I uint32_t CR1; /*!< Capture Register. CR is loaded with the value of TC when there
Pokitto	5:ea7377f3d1af	335	is an event on the CAP input. */
Pokitto	5:ea7377f3d1af	336	__I uint32_t CR2; /*!< Capture Register. CR is loaded with the value of TC when there
Pokitto	5:ea7377f3d1af	337	is an event on the CAP input. */
Pokitto	5:ea7377f3d1af	338	__I uint32_t RESERVED0;
Pokitto	5:ea7377f3d1af	339	__IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
Pokitto	5:ea7377f3d1af	340	and the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
Pokitto	5:ea7377f3d1af	341	__I uint32_t RESERVED1[12];
Pokitto	5:ea7377f3d1af	342	__IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
Pokitto	5:ea7377f3d1af	343	mode, and in Counter mode selects the signal and edge(s) for
Pokitto	5:ea7377f3d1af	344	counting. */
Pokitto	5:ea7377f3d1af	345	__IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
Pokitto	5:ea7377f3d1af	346	match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
Pokitto	5:ea7377f3d1af	347	} LPC_CT16B0_Type;
Pokitto	5:ea7377f3d1af	348
Pokitto	5:ea7377f3d1af	349
Pokitto	5:ea7377f3d1af	350	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	351	/* ================ CT32B0 ================ */
Pokitto	5:ea7377f3d1af	352	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	353
Pokitto	5:ea7377f3d1af	354
Pokitto	5:ea7377f3d1af	355	/**
Pokitto	5:ea7377f3d1af	356	* @brief 32-bit counter/timers CT32B0 (CT32B0)
Pokitto	5:ea7377f3d1af	357	*/
Pokitto	5:ea7377f3d1af	358
Pokitto	5:ea7377f3d1af	359	typedef struct { /!< CT32B0 Structure /
Pokitto	5:ea7377f3d1af	360	__IO uint32_t IR; /*!< Interrupt Register. The IR can be written to clear interrupts.
Pokitto	5:ea7377f3d1af	361	The IR can be read to identify which of eight possible interrupt
Pokitto	5:ea7377f3d1af	362	sources are pending. */
Pokitto	5:ea7377f3d1af	363	__IO uint32_t TCR; /*!< Timer Control Register. The TCR is used to control the Timer
Pokitto	5:ea7377f3d1af	364	Counter functions. The Timer Counter can be disabled or reset
Pokitto	5:ea7377f3d1af	365	through the TCR. */
Pokitto	5:ea7377f3d1af	366	__IO uint32_t TC; /*!< Timer Counter. The 32-bit TC is incremented every PR+1 cycles
Pokitto	5:ea7377f3d1af	367	of PCLK. The TC is controlled through the TCR. */
Pokitto	5:ea7377f3d1af	368	__IO uint32_t PR; /*!< Prescale Register. When the Prescale Counter (below) is equal
Pokitto	5:ea7377f3d1af	369	to this value, the next clock increments the TC and clears the
Pokitto	5:ea7377f3d1af	370	PC. */
Pokitto	5:ea7377f3d1af	371	__IO uint32_t PC; /*!< Prescale Counter. The 32-bit PC is a counter which is incremented
Pokitto	5:ea7377f3d1af	372	to the value stored in PR. When the value in PR is reached,
Pokitto	5:ea7377f3d1af	373	the TC is incremented and the PC is cleared. The PC is observable
Pokitto	5:ea7377f3d1af	374	and controllable through the bus interface. */
Pokitto	5:ea7377f3d1af	375	__IO uint32_t MCR; /*!< Match Control Register. The MCR is used to control if an interrupt
Pokitto	5:ea7377f3d1af	376	is generated and if the TC is reset when a Match occurs. */
Pokitto	5:ea7377f3d1af	377	__IO uint32_t MR0; /*!< Match Register. MR can be enabled through the MCR to reset the
Pokitto	5:ea7377f3d1af	378	TC, stop both the TC and PC, and/or generate an interrupt every
Pokitto	5:ea7377f3d1af	379	time MR0 matches the TC. */
Pokitto	5:ea7377f3d1af	380	__IO uint32_t MR1; /*!< Match Register. MR can be enabled through the MCR to reset the
Pokitto	5:ea7377f3d1af	381	TC, stop both the TC and PC, and/or generate an interrupt every
Pokitto	5:ea7377f3d1af	382	time MR0 matches the TC. */
Pokitto	5:ea7377f3d1af	383	__IO uint32_t MR2; /*!< Match Register. MR can be enabled through the MCR to reset the
Pokitto	5:ea7377f3d1af	384	TC, stop both the TC and PC, and/or generate an interrupt every
Pokitto	5:ea7377f3d1af	385	time MR0 matches the TC. */
Pokitto	5:ea7377f3d1af	386	__IO uint32_t MR3; /*!< Match Register. MR can be enabled through the MCR to reset the
Pokitto	5:ea7377f3d1af	387	TC, stop both the TC and PC, and/or generate an interrupt every
Pokitto	5:ea7377f3d1af	388	time MR0 matches the TC. */
Pokitto	5:ea7377f3d1af	389	__IO uint32_t CCR; /*!< Capture Control Register. The CCR controls which edges of the
Pokitto	5:ea7377f3d1af	390	capture inputs are used to load the Capture Registers and whether
Pokitto	5:ea7377f3d1af	391	or not an interrupt is generated when a capture takes place. */
Pokitto	5:ea7377f3d1af	392	__I uint32_t CR0; /*!< Capture Register. CR is loaded with the value of TC when there
Pokitto	5:ea7377f3d1af	393	is an event on the CAP input. */
Pokitto	5:ea7377f3d1af	394	__I uint32_t CR1; /*!< Capture Register. CR is loaded with the value of TC when there
Pokitto	5:ea7377f3d1af	395	is an event on the CAP input. */
Pokitto	5:ea7377f3d1af	396	__I uint32_t CR2; /*!< Capture Register. CR is loaded with the value of TC when there
Pokitto	5:ea7377f3d1af	397	is an event on the CAP input. */
Pokitto	5:ea7377f3d1af	398	__I uint32_t RESERVED0;
Pokitto	5:ea7377f3d1af	399	__IO uint32_t EMR; /*!< External Match Register. The EMR controls the match function
Pokitto	5:ea7377f3d1af	400	and the external match pins CT32Bn_MAT[3:0]. */
Pokitto	5:ea7377f3d1af	401	__I uint32_t RESERVED1[12];
Pokitto	5:ea7377f3d1af	402	__IO uint32_t CTCR; /*!< Count Control Register. The CTCR selects between Timer and Counter
Pokitto	5:ea7377f3d1af	403	mode, and in Counter mode selects the signal and edge(s) for
Pokitto	5:ea7377f3d1af	404	counting. */
Pokitto	5:ea7377f3d1af	405	__IO uint32_t PWMC; /*!< PWM Control Register. The PWMCON enables PWM mode for the external
Pokitto	5:ea7377f3d1af	406	match pins CT32Bn_MAT[3:0]. */
Pokitto	5:ea7377f3d1af	407	} LPC_CT32B0_Type;
Pokitto	5:ea7377f3d1af	408
Pokitto	5:ea7377f3d1af	409
Pokitto	5:ea7377f3d1af	410	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	411	/* ================ ADC ================ */
Pokitto	5:ea7377f3d1af	412	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	413
Pokitto	5:ea7377f3d1af	414
Pokitto	5:ea7377f3d1af	415	/**
Pokitto	5:ea7377f3d1af	416	* @brief Product name title=Kylin UM Chapter title=Kylin12-bit Analog-to-Digital Converter (ADC) Modification date=5/13/2013 Major revision=0 Minor revision=1 (ADC)
Pokitto	5:ea7377f3d1af	417	*/
Pokitto	5:ea7377f3d1af	418
Pokitto	5:ea7377f3d1af	419	typedef struct { /!< ADC Structure /
Pokitto	5:ea7377f3d1af	420	__IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
Pokitto	5:ea7377f3d1af	421	bits for each sequence and the A/D power-down bit. */
Pokitto	5:ea7377f3d1af	422	__I uint32_t RESERVED0;
Pokitto	5:ea7377f3d1af	423	__IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
Pokitto	5:ea7377f3d1af	424	and channel selection for conversion sequence-A. Also specifies
Pokitto	5:ea7377f3d1af	425	interrupt mode for sequence-A. */
Pokitto	5:ea7377f3d1af	426	__IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
Pokitto	5:ea7377f3d1af	427	and channel selection for conversion sequence-B. Also specifies
Pokitto	5:ea7377f3d1af	428	interrupt mode for sequence-B. */
Pokitto	5:ea7377f3d1af	429	__IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
Pokitto	5:ea7377f3d1af	430	the result of the most recent A/D conversion performed under
Pokitto	5:ea7377f3d1af	431	sequence-A */
Pokitto	5:ea7377f3d1af	432	__IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
Pokitto	5:ea7377f3d1af	433	the result of the most recent A/D conversion performed under
Pokitto	5:ea7377f3d1af	434	sequence-B */
Pokitto	5:ea7377f3d1af	435	__I uint32_t RESERVED1[2];
Pokitto	5:ea7377f3d1af	436	__I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
Pokitto	5:ea7377f3d1af	437	of the most recent conversion completed on channel 0. */
Pokitto	5:ea7377f3d1af	438	__IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
Pokitto	5:ea7377f3d1af	439	level for automatic threshold comparison for any channels linked
Pokitto	5:ea7377f3d1af	440	to threshold pair 0. */
Pokitto	5:ea7377f3d1af	441	__IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
Pokitto	5:ea7377f3d1af	442	level for automatic threshold comparison for any channels linked
Pokitto	5:ea7377f3d1af	443	to threshold pair 1. */
Pokitto	5:ea7377f3d1af	444	__IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
Pokitto	5:ea7377f3d1af	445	level for automatic threshold comparison for any channels linked
Pokitto	5:ea7377f3d1af	446	to threshold pair 0. */
Pokitto	5:ea7377f3d1af	447	__IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
Pokitto	5:ea7377f3d1af	448	level for automatic threshold comparison for any channels linked
Pokitto	5:ea7377f3d1af	449	to threshold pair 1. */
Pokitto	5:ea7377f3d1af	450	__I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
Pokitto	5:ea7377f3d1af	451	threshold compare registers are to be used for each channel */
Pokitto	5:ea7377f3d1af	452	__IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
Pokitto	5:ea7377f3d1af	453	bits that enable the sequence-A, sequence-B, threshold compare
Pokitto	5:ea7377f3d1af	454	and data overrun interrupts to be generated. */
Pokitto	5:ea7377f3d1af	455	__I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
Pokitto	5:ea7377f3d1af	456	and the individual component overrun and threshold-compare flags.
Pokitto	5:ea7377f3d1af	457	(The overrun bits replicate information stored in the result
Pokitto	5:ea7377f3d1af	458	registers). */
Pokitto	5:ea7377f3d1af	459	__IO uint32_t TRM; /!< ADC trim register. /
Pokitto	5:ea7377f3d1af	460	} LPC_ADC_Type;
Pokitto	5:ea7377f3d1af	461
Pokitto	5:ea7377f3d1af	462
Pokitto	5:ea7377f3d1af	463	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	464	/* ================ RTC ================ */
Pokitto	5:ea7377f3d1af	465	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	466
Pokitto	5:ea7377f3d1af	467
Pokitto	5:ea7377f3d1af	468	/**
Pokitto	5:ea7377f3d1af	469	* @brief Real-Time Clock (RTC) (RTC)
Pokitto	5:ea7377f3d1af	470	*/
Pokitto	5:ea7377f3d1af	471
Pokitto	5:ea7377f3d1af	472	typedef struct { /!< RTC Structure /
Pokitto	5:ea7377f3d1af	473	__IO uint32_t CTRL; /!< RTC control register /
Pokitto	5:ea7377f3d1af	474	__IO uint32_t MATCH; /!< RTC match register /
Pokitto	5:ea7377f3d1af	475	__IO uint32_t COUNT; /!< RTC counter register /
Pokitto	5:ea7377f3d1af	476	__IO uint32_t WAKE; /!< RTC high-resolution/wake-up timer control register /
Pokitto	5:ea7377f3d1af	477	} LPC_RTC_Type;
Pokitto	5:ea7377f3d1af	478
Pokitto	5:ea7377f3d1af	479
Pokitto	5:ea7377f3d1af	480	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	481	/* ================ DMATRIGMUX ================ */
Pokitto	5:ea7377f3d1af	482	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	483
Pokitto	5:ea7377f3d1af	484
Pokitto	5:ea7377f3d1af	485	/**
Pokitto	5:ea7377f3d1af	486	* @brief Product name title=Kylin UM Chapter title=KylinDMA controller Modification date=5/13/2013 Major revision=0 Minor revision=1 (DMATRIGMUX)
Pokitto	5:ea7377f3d1af	487	*/
Pokitto	5:ea7377f3d1af	488
Pokitto	5:ea7377f3d1af	489	typedef struct { /!< DMATRIGMUX Structure /
Pokitto	5:ea7377f3d1af	490	__IO uint32_t DMA_ITRIG_PINMUX[16]; /!< Trigger input select register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	491	} LPC_DMATRIGMUX_Type;
Pokitto	5:ea7377f3d1af	492
Pokitto	5:ea7377f3d1af	493
Pokitto	5:ea7377f3d1af	494	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	495	/* ================ PMU ================ */
Pokitto	5:ea7377f3d1af	496	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	497
Pokitto	5:ea7377f3d1af	498
Pokitto	5:ea7377f3d1af	499	/**
Pokitto	5:ea7377f3d1af	500	* @brief Product name title=Kylin UM Chapter title=KylinPower Management Unit (PMU) Modification date=5/13/2013 Major revision=0 Minor revision=1 (PMU)
Pokitto	5:ea7377f3d1af	501	*/
Pokitto	5:ea7377f3d1af	502
Pokitto	5:ea7377f3d1af	503	typedef struct { /!< PMU Structure /
Pokitto	5:ea7377f3d1af	504	__IO uint32_t PCON; /!< Power control register /
Pokitto	5:ea7377f3d1af	505	__IO uint32_t GPREG0; /!< General purpose register 0 /
Pokitto	5:ea7377f3d1af	506	__IO uint32_t GPREG1; /!< General purpose register 0 /
Pokitto	5:ea7377f3d1af	507	__IO uint32_t GPREG2; /!< General purpose register 0 /
Pokitto	5:ea7377f3d1af	508	__IO uint32_t GPREG3; /!< General purpose register 0 /
Pokitto	5:ea7377f3d1af	509	__IO uint32_t DPDCTRL; /!< Deep power down control register /
Pokitto	5:ea7377f3d1af	510	} LPC_PMU_Type;
Pokitto	5:ea7377f3d1af	511
Pokitto	5:ea7377f3d1af	512
Pokitto	5:ea7377f3d1af	513	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	514	/* ================ FLASHCTRL ================ */
Pokitto	5:ea7377f3d1af	515	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	516
Pokitto	5:ea7377f3d1af	517
Pokitto	5:ea7377f3d1af	518	/**
Pokitto	5:ea7377f3d1af	519	* @brief Flash controller (FLASHCTRL)
Pokitto	5:ea7377f3d1af	520	*/
Pokitto	5:ea7377f3d1af	521
Pokitto	5:ea7377f3d1af	522	typedef struct { /!< FLASHCTRL Structure /
Pokitto	5:ea7377f3d1af	523	__I uint32_t RESERVED0[4];
Pokitto	5:ea7377f3d1af	524	__IO uint32_t FLASHCFG; /!< Flash configuration register /
Pokitto	5:ea7377f3d1af	525	__I uint32_t RESERVED1[3];
Pokitto	5:ea7377f3d1af	526	__IO uint32_t FMSSTART; /!< Signature start address register /
Pokitto	5:ea7377f3d1af	527	__IO uint32_t FMSSTOP; /!< Signature stop-address register /
Pokitto	5:ea7377f3d1af	528	__I uint32_t RESERVED2;
Pokitto	5:ea7377f3d1af	529	__I uint32_t FMSW0; /!< Signature Word /
Pokitto	5:ea7377f3d1af	530	} LPC_FLASHCTRL_Type;
Pokitto	5:ea7377f3d1af	531
Pokitto	5:ea7377f3d1af	532
Pokitto	5:ea7377f3d1af	533	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	534	/* ================ SSP0 ================ */
Pokitto	5:ea7377f3d1af	535	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	536
Pokitto	5:ea7377f3d1af	537
Pokitto	5:ea7377f3d1af	538	/**
Pokitto	5:ea7377f3d1af	539	* @brief SSP/SPI (SSP0)
Pokitto	5:ea7377f3d1af	540	*/
Pokitto	5:ea7377f3d1af	541
Pokitto	5:ea7377f3d1af	542	typedef struct { /!< SSP0 Structure /
Pokitto	5:ea7377f3d1af	543	__IO uint32_t CR0; /*!< Control Register 0. Selects the serial clock rate, bus type,
Pokitto	5:ea7377f3d1af	544	and data size. */
Pokitto	5:ea7377f3d1af	545	__IO uint32_t CR1; /!< Control Register 1. Selects master/slave and other modes. /
Pokitto	5:ea7377f3d1af	546	__IO uint32_t DR; /*!< Data Register. Writes fill the transmit FIFO, and reads empty
Pokitto	5:ea7377f3d1af	547	the receive FIFO. */
Pokitto	5:ea7377f3d1af	548	__I uint32_t SR; /!< Status Register /
Pokitto	5:ea7377f3d1af	549	__IO uint32_t CPSR; /!< Clock Prescale Register /
Pokitto	5:ea7377f3d1af	550	__IO uint32_t IMSC; /!< Interrupt Mask Set and Clear Register /
Pokitto	5:ea7377f3d1af	551	__I uint32_t RIS; /!< Raw Interrupt Status Register /
Pokitto	5:ea7377f3d1af	552	__I uint32_t MIS; /!< Masked Interrupt Status Register /
Pokitto	5:ea7377f3d1af	553	__O uint32_t ICR; /!< SSPICR Interrupt Clear Register /
Pokitto	5:ea7377f3d1af	554	} LPC_SSP0_Type;
Pokitto	5:ea7377f3d1af	555
Pokitto	5:ea7377f3d1af	556
Pokitto	5:ea7377f3d1af	557	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	558	/* ================ IOCON ================ */
Pokitto	5:ea7377f3d1af	559	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	560
Pokitto	5:ea7377f3d1af	561
Pokitto	5:ea7377f3d1af	562	/**
Pokitto	5:ea7377f3d1af	563	* @brief Product name title=Kylin UM Chapter title=KylinI/O control (IOCON) Modification date=5/13/2013 Major revision=0 Minor revision=1 (IOCON)
Pokitto	5:ea7377f3d1af	564	*/
Pokitto	5:ea7377f3d1af	565
Pokitto	5:ea7377f3d1af	566	typedef struct { /!< IOCON Structure /
Pokitto	5:ea7377f3d1af	567	__IO uint32_t PIO0_0; /!< I/O configuration for port PIO0 /
Pokitto	5:ea7377f3d1af	568	__IO uint32_t PIO0_1; /!< I/O configuration for port PIO0 /
Pokitto	5:ea7377f3d1af	569	__IO uint32_t PIO0_2; /!< I/O configuration for port PIO0 /
Pokitto	5:ea7377f3d1af	570	__IO uint32_t PIO0_3; /!< I/O configuration for port PIO0 /
Pokitto	5:ea7377f3d1af	571	__IO uint32_t PIO0_4; /!< I/O configuration for port PIO0 /
Pokitto	5:ea7377f3d1af	572	__IO uint32_t PIO0_5; /!< I/O configuration for port PIO0 /
Pokitto	5:ea7377f3d1af	573	__IO uint32_t PIO0_6; /!< I/O configuration for port PIO0 /
Pokitto	5:ea7377f3d1af	574	__IO uint32_t PIO0_7; /!< I/O configuration for port PIO0 /
Pokitto	5:ea7377f3d1af	575	__IO uint32_t PIO0_8; /!< I/O configuration for port PIO0 /
Pokitto	5:ea7377f3d1af	576	__IO uint32_t PIO0_9; /!< I/O configuration for port PIO0 /
Pokitto	5:ea7377f3d1af	577	__IO uint32_t PIO0_10; /!< I/O configuration for port PIO0 /
Pokitto	5:ea7377f3d1af	578	__IO uint32_t PIO0_11; /!< I/O configuration for port PIO0 /
Pokitto	5:ea7377f3d1af	579	__IO uint32_t PIO0_12; /!< I/O configuration for port PIO0 /
Pokitto	5:ea7377f3d1af	580	__IO uint32_t PIO0_13; /!< I/O configuration for port PIO0 /
Pokitto	5:ea7377f3d1af	581	__IO uint32_t PIO0_14; /!< I/O configuration for port PIO0 /
Pokitto	5:ea7377f3d1af	582	__IO uint32_t PIO0_15; /!< I/O configuration for port PIO0 /
Pokitto	5:ea7377f3d1af	583	__IO uint32_t PIO0_16; /!< I/O configuration for port PIO0 /
Pokitto	5:ea7377f3d1af	584	__IO uint32_t PIO0_17; /!< I/O configuration for port PIO0 /
Pokitto	5:ea7377f3d1af	585	__IO uint32_t PIO0_18; /!< I/O configuration for port PIO0 /
Pokitto	5:ea7377f3d1af	586	__IO uint32_t PIO0_19; /!< I/O configuration for port PIO0 /
Pokitto	5:ea7377f3d1af	587	__IO uint32_t PIO0_20; /!< I/O configuration for port PIO0 /
Pokitto	5:ea7377f3d1af	588	__IO uint32_t PIO0_21; /!< I/O configuration for port PIO0 /
Pokitto	5:ea7377f3d1af	589	__IO uint32_t PIO0_22; /!< I/O configuration for port PIO0 /
Pokitto	5:ea7377f3d1af	590	__IO uint32_t PIO0_23; /!< I/O configuration for port PIO0 /
Pokitto	5:ea7377f3d1af	591	__IO uint32_t PIO1_0; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	592	__IO uint32_t PIO1_1; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	593	__IO uint32_t PIO1_2; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	594	__IO uint32_t PIO1_3; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	595	__IO uint32_t PIO1_4; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	596	__IO uint32_t PIO1_5; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	597	__IO uint32_t PIO1_6; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	598	__IO uint32_t PIO1_7; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	599	__IO uint32_t PIO1_8; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	600	__IO uint32_t PIO1_9; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	601	__IO uint32_t PIO1_10; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	602	__IO uint32_t PIO1_11; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	603	__IO uint32_t PIO1_12; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	604	__IO uint32_t PIO1_13; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	605	__IO uint32_t PIO1_14; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	606	__IO uint32_t PIO1_15; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	607	__IO uint32_t PIO1_16; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	608	__IO uint32_t PIO1_17; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	609	__IO uint32_t PIO1_18; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	610	__IO uint32_t PIO1_19; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	611	__IO uint32_t PIO1_20; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	612	__IO uint32_t PIO1_21; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	613	__IO uint32_t PIO1_22; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	614	__IO uint32_t PIO1_23; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	615	__IO uint32_t PIO1_24; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	616	__IO uint32_t PIO1_25; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	617	__IO uint32_t PIO1_26; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	618	__IO uint32_t PIO1_27; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	619	__IO uint32_t PIO1_28; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	620	__IO uint32_t PIO1_29; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	621	__IO uint32_t PIO1_30; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	622	__IO uint32_t PIO1_31; /!< I/O configuration for port PIO1 /
Pokitto	5:ea7377f3d1af	623	__I uint32_t RESERVED0[4];
Pokitto	5:ea7377f3d1af	624	__IO uint32_t PIO2_0; /!< I/O configuration for port PIO2 /
Pokitto	5:ea7377f3d1af	625	__IO uint32_t PIO2_1; /!< I/O configuration for port PIO2 /
Pokitto	5:ea7377f3d1af	626	__I uint32_t RESERVED1;
Pokitto	5:ea7377f3d1af	627	__IO uint32_t PIO2_2; /!< I/O configuration for port PIO2 /
Pokitto	5:ea7377f3d1af	628	__IO uint32_t PIO2_3; /!< I/O configuration for port PIO2 /
Pokitto	5:ea7377f3d1af	629	__IO uint32_t PIO2_4; /!< I/O configuration for port PIO2 /
Pokitto	5:ea7377f3d1af	630	__IO uint32_t PIO2_5; /!< I/O configuration for port PIO2 /
Pokitto	5:ea7377f3d1af	631	__IO uint32_t PIO2_6; /!< I/O configuration for port PIO2 /
Pokitto	5:ea7377f3d1af	632	__IO uint32_t PIO2_7; /!< I/O configuration for port PIO2 /
Pokitto	5:ea7377f3d1af	633	__IO uint32_t PIO2_8; /!< I/O configuration for port PIO2 /
Pokitto	5:ea7377f3d1af	634	__IO uint32_t PIO2_9; /!< I/O configuration for port PIO2 /
Pokitto	5:ea7377f3d1af	635	__IO uint32_t PIO2_10; /!< I/O configuration for port PIO2 /
Pokitto	5:ea7377f3d1af	636	__IO uint32_t PIO2_11; /!< I/O configuration for port PIO2 /
Pokitto	5:ea7377f3d1af	637	__IO uint32_t PIO2_12; /!< I/O configuration for port PIO2 /
Pokitto	5:ea7377f3d1af	638	__IO uint32_t PIO2_13; /!< I/O configuration for port PIO2 /
Pokitto	5:ea7377f3d1af	639	__IO uint32_t PIO2_14; /!< I/O configuration for port PIO2 /
Pokitto	5:ea7377f3d1af	640	__IO uint32_t PIO2_15; /!< I/O configuration for port PIO2 /
Pokitto	5:ea7377f3d1af	641	__IO uint32_t PIO2_16; /!< I/O configuration for port PIO2 /
Pokitto	5:ea7377f3d1af	642	__IO uint32_t PIO2_17; /!< I/O configuration for port PIO2 /
Pokitto	5:ea7377f3d1af	643	__IO uint32_t PIO2_18; /!< I/O configuration for port PIO2 /
Pokitto	5:ea7377f3d1af	644	__IO uint32_t PIO2_19; /!< I/O configuration for port PIO2 /
Pokitto	5:ea7377f3d1af	645	__IO uint32_t PIO2_20; /!< I/O configuration for port PIO2 /
Pokitto	5:ea7377f3d1af	646	__IO uint32_t PIO2_21; /!< I/O configuration for port PIO2 /
Pokitto	5:ea7377f3d1af	647	__IO uint32_t PIO2_22; /!< I/O configuration for port PIO2 /
Pokitto	5:ea7377f3d1af	648	__IO uint32_t PIO2_23; /!< I/O configuration for port PIO2 /
Pokitto	5:ea7377f3d1af	649	} LPC_IOCON_Type;
Pokitto	5:ea7377f3d1af	650
Pokitto	5:ea7377f3d1af	651
Pokitto	5:ea7377f3d1af	652	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	653	/* ================ SYSCON ================ */
Pokitto	5:ea7377f3d1af	654	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	655
Pokitto	5:ea7377f3d1af	656
Pokitto	5:ea7377f3d1af	657	/**
Pokitto	5:ea7377f3d1af	658	* @brief Product name title=Kylin UM Chapter title=KylinSystem configuration (SYSCON) Modification date=5/13/2013 Major revision=0 Minor revision=1 (SYSCON)
Pokitto	5:ea7377f3d1af	659	*/
Pokitto	5:ea7377f3d1af	660
Pokitto	5:ea7377f3d1af	661	typedef struct { /!< SYSCON Structure /
Pokitto	5:ea7377f3d1af	662	__IO uint32_t SYSMEMREMAP; /!< System memory remap /
Pokitto	5:ea7377f3d1af	663	__IO uint32_t PRESETCTRL; /!< Peripheral reset control /
Pokitto	5:ea7377f3d1af	664	__IO uint32_t SYSPLLCTRL; /!< System PLL control /
Pokitto	5:ea7377f3d1af	665	__I uint32_t SYSPLLSTAT; /!< System PLL status /
Pokitto	5:ea7377f3d1af	666	__IO uint32_t USBPLLCTRL; /!< USB PLL control /
Pokitto	5:ea7377f3d1af	667	__I uint32_t USBPLLSTAT; /!< USB PLL status /
Pokitto	5:ea7377f3d1af	668	__I uint32_t RESERVED0;
Pokitto	5:ea7377f3d1af	669	__IO uint32_t RTCOSCCTRL; /!< RTC oscillator 32 kHz output control /
Pokitto	5:ea7377f3d1af	670	__IO uint32_t SYSOSCCTRL; /!< System oscillator control /
Pokitto	5:ea7377f3d1af	671	__IO uint32_t WDTOSCCTRL; /!< Watchdog oscillator control /
Pokitto	5:ea7377f3d1af	672	__I uint32_t RESERVED1[2];
Pokitto	5:ea7377f3d1af	673	__IO uint32_t SYSRSTSTAT; /!< System reset status register /
Pokitto	5:ea7377f3d1af	674	__I uint32_t RESERVED2[3];
Pokitto	5:ea7377f3d1af	675	__IO uint32_t SYSPLLCLKSEL; /!< System PLL clock source select /
Pokitto	5:ea7377f3d1af	676	__IO uint32_t SYSPLLCLKUEN; /!< System PLL clock source update enable /
Pokitto	5:ea7377f3d1af	677	__IO uint32_t USBPLLCLKSEL; /!< USB PLL clock source select /
Pokitto	5:ea7377f3d1af	678	__IO uint32_t USBPLLCLKUEN; /!< USB PLL clock source update enable /
Pokitto	5:ea7377f3d1af	679	__I uint32_t RESERVED3[8];
Pokitto	5:ea7377f3d1af	680	__IO uint32_t MAINCLKSEL; /!< Main clock source select /
Pokitto	5:ea7377f3d1af	681	__IO uint32_t MAINCLKUEN; /!< Main clock source update enable /
Pokitto	5:ea7377f3d1af	682	__IO uint32_t SYSAHBCLKDIV; /!< System clock divider /
Pokitto	5:ea7377f3d1af	683	__I uint32_t RESERVED4;
Pokitto	5:ea7377f3d1af	684	__IO uint32_t SYSAHBCLKCTRL; /!< System clock control /
Pokitto	5:ea7377f3d1af	685	__I uint32_t RESERVED5[4];
Pokitto	5:ea7377f3d1af	686	__IO uint32_t SSP0CLKDIV; /!< SSP0 clock divider /
Pokitto	5:ea7377f3d1af	687	__IO uint32_t USART0CLKDIV; /!< USART0 clock divider /
Pokitto	5:ea7377f3d1af	688	__IO uint32_t SSP1CLKDIV; /!< SSP1 clock divider /
Pokitto	5:ea7377f3d1af	689	__IO uint32_t FRGCLKDIV; /*!< Clock divider for the common fractional baud rate generator
Pokitto	5:ea7377f3d1af	690	of USART1 to USART4 */
Pokitto	5:ea7377f3d1af	691	__I uint32_t RESERVED6[7];
Pokitto	5:ea7377f3d1af	692	__IO uint32_t USBCLKSEL; /!< USB clock source select /
Pokitto	5:ea7377f3d1af	693	__IO uint32_t USBCLKUEN; /!< USB clock source update enable /
Pokitto	5:ea7377f3d1af	694	__IO uint32_t USBCLKDIV; /!< USB clock source divider /
Pokitto	5:ea7377f3d1af	695	__I uint32_t RESERVED7[5];
Pokitto	5:ea7377f3d1af	696	__IO uint32_t CLKOUTSEL; /!< CLKOUT clock source select /
Pokitto	5:ea7377f3d1af	697	__IO uint32_t CLKOUTUEN; /!< CLKOUT clock source update enable /
Pokitto	5:ea7377f3d1af	698	__IO uint32_t CLKOUTDIV; /!< CLKOUT clock divider /
Pokitto	5:ea7377f3d1af	699	__I uint32_t RESERVED8;
Pokitto	5:ea7377f3d1af	700	__IO uint32_t UARTFRGDIV; /!< USART fractional generator divider value /
Pokitto	5:ea7377f3d1af	701	__IO uint32_t UARTFRGMULT; /!< USART fractional generator multiplier value /
Pokitto	5:ea7377f3d1af	702	__I uint32_t RESERVED9;
Pokitto	5:ea7377f3d1af	703	__IO uint32_t EXTTRACECMD; /!< External trace buffer command register /
Pokitto	5:ea7377f3d1af	704	__I uint32_t PIOPORCAP0; /!< POR captured PIO status 0 /
Pokitto	5:ea7377f3d1af	705	__I uint32_t PIOPORCAP1; /!< POR captured PIO status 1 /
Pokitto	5:ea7377f3d1af	706	__I uint32_t PIOPORCAP2; /!< POR captured PIO status 1 /
Pokitto	5:ea7377f3d1af	707	__I uint32_t RESERVED10[10];
Pokitto	5:ea7377f3d1af	708	__IO uint32_t IOCONCLKDIV6; /*!< Peripheral clock 6 to the IOCON block for programmable glitch
Pokitto	5:ea7377f3d1af	709	filter */
Pokitto	5:ea7377f3d1af	710	__IO uint32_t IOCONCLKDIV5; /*!< Peripheral clock 5 to the IOCON block for programmable glitch
Pokitto	5:ea7377f3d1af	711	filter */
Pokitto	5:ea7377f3d1af	712	__IO uint32_t IOCONCLKDIV4; /*!< Peripheral clock 4 to the IOCON block for programmable glitch
Pokitto	5:ea7377f3d1af	713	filter */
Pokitto	5:ea7377f3d1af	714	__IO uint32_t IOCONCLKDIV3; /*!< Peripheral clock 3 to the IOCON block for programmable glitch
Pokitto	5:ea7377f3d1af	715	filter */
Pokitto	5:ea7377f3d1af	716	__IO uint32_t IOCONCLKDIV2; /*!< Peripheral clock 2 to the IOCON block for programmable glitch
Pokitto	5:ea7377f3d1af	717	filter */
Pokitto	5:ea7377f3d1af	718	__IO uint32_t IOCONCLKDIV1; /*!< Peripheral clock 1 to the IOCON block for programmable glitch
Pokitto	5:ea7377f3d1af	719	filter */
Pokitto	5:ea7377f3d1af	720	__IO uint32_t IOCONCLKDIV0; /*!< Peripheral clock 0 to the IOCON block for programmable glitch
Pokitto	5:ea7377f3d1af	721	filter */
Pokitto	5:ea7377f3d1af	722	__IO uint32_t BODCTRL; /!< Brown-Out Detect /
Pokitto	5:ea7377f3d1af	723	__IO uint32_t SYSTCKCAL; /!< System tick counter calibration /
Pokitto	5:ea7377f3d1af	724	__IO uint32_t AHBMATRIXPRIO; /!< AHB matrix priority configuration /
Pokitto	5:ea7377f3d1af	725	__I uint32_t RESERVED11[5];
Pokitto	5:ea7377f3d1af	726	__IO uint32_t IRQLATENCY; /!< IRQ delay. Allows trade-off between interrupt latency and determinism. /
Pokitto	5:ea7377f3d1af	727	__IO uint32_t NMISRC; /!< NMI Source Control /
Pokitto	5:ea7377f3d1af	728	union {
Pokitto	5:ea7377f3d1af	729	__IO uint32_t PINTSEL[8];
Pokitto	5:ea7377f3d1af	730	struct {
Pokitto	5:ea7377f3d1af	731	__IO uint32_t PINTSEL0; /!< GPIO Pin Interrupt Select register 0 /
Pokitto	5:ea7377f3d1af	732	__IO uint32_t PINTSEL1; /!< GPIO Pin Interrupt Select register 0 /
Pokitto	5:ea7377f3d1af	733	__IO uint32_t PINTSEL2; /!< GPIO Pin Interrupt Select register 0 /
Pokitto	5:ea7377f3d1af	734	__IO uint32_t PINTSEL3; /!< GPIO Pin Interrupt Select register 0 /
Pokitto	5:ea7377f3d1af	735	__IO uint32_t PINTSEL4; /!< GPIO Pin Interrupt Select register 0 /
Pokitto	5:ea7377f3d1af	736	__IO uint32_t PINTSEL5; /!< GPIO Pin Interrupt Select register 0 /
Pokitto	5:ea7377f3d1af	737	__IO uint32_t PINTSEL6; /!< GPIO Pin Interrupt Select register 0 /
Pokitto	5:ea7377f3d1af	738	__IO uint32_t PINTSEL7; /!< GPIO Pin Interrupt Select register 0 /
Pokitto	5:ea7377f3d1af	739	};
Pokitto	5:ea7377f3d1af	740	};
Pokitto	5:ea7377f3d1af	741	__IO uint32_t USBCLKCTRL; /!< USB clock control /
Pokitto	5:ea7377f3d1af	742	__I uint32_t USBCLKST; /!< USB clock status /
Pokitto	5:ea7377f3d1af	743	__I uint32_t RESERVED12[25];
Pokitto	5:ea7377f3d1af	744	__IO uint32_t STARTERP0; /!< Start logic 0 interrupt wake-up enable register 0 /
Pokitto	5:ea7377f3d1af	745	__I uint32_t RESERVED13[3];
Pokitto	5:ea7377f3d1af	746	__IO uint32_t STARTERP1; /!< Start logic 1 interrupt wake-up enable register 1 /
Pokitto	5:ea7377f3d1af	747	__I uint32_t RESERVED14[6];
Pokitto	5:ea7377f3d1af	748	__IO uint32_t PDSLEEPCFG; /!< Power-down states in deep-sleep mode /
Pokitto	5:ea7377f3d1af	749	__IO uint32_t PDAWAKECFG; /!< Power-down states for wake-up from deep-sleep /
Pokitto	5:ea7377f3d1af	750	__IO uint32_t PDRUNCFG; /!< Power configuration register /
Pokitto	5:ea7377f3d1af	751	__I uint32_t RESERVED15[110];
Pokitto	5:ea7377f3d1af	752	__I uint32_t DEVICE_ID; /!< Device ID /
Pokitto	5:ea7377f3d1af	753	} LPC_SYSCON_Type;
Pokitto	5:ea7377f3d1af	754
Pokitto	5:ea7377f3d1af	755
Pokitto	5:ea7377f3d1af	756	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	757	/* ================ USART4 ================ */
Pokitto	5:ea7377f3d1af	758	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	759
Pokitto	5:ea7377f3d1af	760
Pokitto	5:ea7377f3d1af	761	/**
Pokitto	5:ea7377f3d1af	762	* @brief USART4 (USART4)
Pokitto	5:ea7377f3d1af	763	*/
Pokitto	5:ea7377f3d1af	764
Pokitto	5:ea7377f3d1af	765	typedef struct { /!< USART4 Structure /
Pokitto	5:ea7377f3d1af	766	__IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
Pokitto	5:ea7377f3d1af	767	that typically are not changed during operation. */
Pokitto	5:ea7377f3d1af	768	__IO uint32_t CTL; /*!< USART Control register. USART control settings that are more
Pokitto	5:ea7377f3d1af	769	likely to change during operation. */
Pokitto	5:ea7377f3d1af	770	__IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
Pokitto	5:ea7377f3d1af	771	here. Writing ones clears some bits in the register. Some bits
Pokitto	5:ea7377f3d1af	772	can be cleared by writing a 1 to them. */
Pokitto	5:ea7377f3d1af	773	__IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
Pokitto	5:ea7377f3d1af	774	interrupt enable bit for each potential USART interrupt. A complete
Pokitto	5:ea7377f3d1af	775	value may be read from this register. Writing a 1 to any implemented
Pokitto	5:ea7377f3d1af	776	bit position causes that bit to be set. */
Pokitto	5:ea7377f3d1af	777	__O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
Pokitto	5:ea7377f3d1af	778	of bits in the INTENSET register. Writing a 1 to any implemented
Pokitto	5:ea7377f3d1af	779	bit position causes the corresponding bit to be cleared. */
Pokitto	5:ea7377f3d1af	780	__I uint32_t RXDAT; /!< Receiver Data register. Contains the last character received. /
Pokitto	5:ea7377f3d1af	781	__I uint32_t RXDATSTAT; /*!< Receiver Data with Status register. Combines the last character
Pokitto	5:ea7377f3d1af	782	received with the current USART receive status. Allows DMA or
Pokitto	5:ea7377f3d1af	783	software to recover incoming data and status together. */
Pokitto	5:ea7377f3d1af	784	__IO uint32_t TXDAT; /!< Transmit Data register. Data to be transmitted is written here. /
Pokitto	5:ea7377f3d1af	785	__IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
Pokitto	5:ea7377f3d1af	786	value. */
Pokitto	5:ea7377f3d1af	787	__I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
Pokitto	5:ea7377f3d1af	788	enabled. */
Pokitto	5:ea7377f3d1af	789	__IO uint32_t OSR; /!< Oversample selection register for asynchronous communication. /
Pokitto	5:ea7377f3d1af	790	__IO uint32_t ADDR; /!< Address register for automatic address matching. /
Pokitto	5:ea7377f3d1af	791	} LPC_USART4_Type;
Pokitto	5:ea7377f3d1af	792
Pokitto	5:ea7377f3d1af	793
Pokitto	5:ea7377f3d1af	794	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	795	/* ================ GINT0 ================ */
Pokitto	5:ea7377f3d1af	796	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	797
Pokitto	5:ea7377f3d1af	798
Pokitto	5:ea7377f3d1af	799	/**
Pokitto	5:ea7377f3d1af	800	* @brief GPIO group interrupt 0 (GINT0)
Pokitto	5:ea7377f3d1af	801	*/
Pokitto	5:ea7377f3d1af	802
Pokitto	5:ea7377f3d1af	803	typedef struct { /!< GINT0 Structure /
Pokitto	5:ea7377f3d1af	804	__IO uint32_t CTRL; /!< GPIO grouped interrupt control register /
Pokitto	5:ea7377f3d1af	805	__I uint32_t RESERVED0[7];
Pokitto	5:ea7377f3d1af	806	__IO uint32_t PORT_POL[3]; /!< GPIO grouped interrupt port 0 polarity register /
Pokitto	5:ea7377f3d1af	807	__I uint32_t RESERVED1[5];
Pokitto	5:ea7377f3d1af	808	__IO uint32_t PORT_ENA[3]; /!< GPIO grouped interrupt port enable register /
Pokitto	5:ea7377f3d1af	809	} LPC_GINT0_Type;
Pokitto	5:ea7377f3d1af	810
Pokitto	5:ea7377f3d1af	811
Pokitto	5:ea7377f3d1af	812	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	813	/* ================ USB ================ */
Pokitto	5:ea7377f3d1af	814	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	815
Pokitto	5:ea7377f3d1af	816
Pokitto	5:ea7377f3d1af	817	/**
Pokitto	5:ea7377f3d1af	818	* @brief USB device controller (USB)
Pokitto	5:ea7377f3d1af	819	*/
Pokitto	5:ea7377f3d1af	820
Pokitto	5:ea7377f3d1af	821	typedef struct { /!< USB Structure /
Pokitto	5:ea7377f3d1af	822	__IO uint32_t DEVCMDSTAT; /!< USB Device Command/Status register /
Pokitto	5:ea7377f3d1af	823	__IO uint32_t INFO; /!< USB Info register /
Pokitto	5:ea7377f3d1af	824	__IO uint32_t EPLISTSTART; /!< USB EP Command/Status List start address /
Pokitto	5:ea7377f3d1af	825	__IO uint32_t DATABUFSTART; /!< USB Data buffer start address /
Pokitto	5:ea7377f3d1af	826	__IO uint32_t LPM; /!< Link Power Management register /
Pokitto	5:ea7377f3d1af	827	__IO uint32_t EPSKIP; /!< USB Endpoint skip /
Pokitto	5:ea7377f3d1af	828	__IO uint32_t EPINUSE; /!< USB Endpoint Buffer in use /
Pokitto	5:ea7377f3d1af	829	__IO uint32_t EPBUFCFG; /!< USB Endpoint Buffer Configuration register /
Pokitto	5:ea7377f3d1af	830	__IO uint32_t INTSTAT; /!< USB interrupt status register /
Pokitto	5:ea7377f3d1af	831	__IO uint32_t INTEN; /!< USB interrupt enable register /
Pokitto	5:ea7377f3d1af	832	__IO uint32_t INTSETSTAT; /!< USB set interrupt status register /
Pokitto	5:ea7377f3d1af	833	__IO uint32_t INTROUTING; /!< USB interrupt routing register /
Pokitto	5:ea7377f3d1af	834	__I uint32_t RESERVED0;
Pokitto	5:ea7377f3d1af	835	__I uint32_t EPTOGGLE; /!< USB Endpoint toggle register /
Pokitto	5:ea7377f3d1af	836	} LPC_USB_Type;
Pokitto	5:ea7377f3d1af	837
Pokitto	5:ea7377f3d1af	838
Pokitto	5:ea7377f3d1af	839	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	840	/* ================ CRC ================ */
Pokitto	5:ea7377f3d1af	841	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	842
Pokitto	5:ea7377f3d1af	843
Pokitto	5:ea7377f3d1af	844	/**
Pokitto	5:ea7377f3d1af	845	* @brief Cyclic Redundancy Check (CRC) engine (CRC)
Pokitto	5:ea7377f3d1af	846	*/
Pokitto	5:ea7377f3d1af	847
Pokitto	5:ea7377f3d1af	848	typedef struct { /!< CRC Structure /
Pokitto	5:ea7377f3d1af	849	__IO uint32_t MODE; /!< CRC mode register /
Pokitto	5:ea7377f3d1af	850	__IO uint32_t SEED; /!< CRC seed register /
Pokitto	5:ea7377f3d1af	851
Pokitto	5:ea7377f3d1af	852	union {
Pokitto	5:ea7377f3d1af	853	__O uint32_t WR_DATA; /!< CRC data register /
Pokitto	5:ea7377f3d1af	854	__I uint32_t SUM; /!< CRC checksum register /
Pokitto	5:ea7377f3d1af	855	};
Pokitto	5:ea7377f3d1af	856	} LPC_CRC_Type;
Pokitto	5:ea7377f3d1af	857
Pokitto	5:ea7377f3d1af	858
Pokitto	5:ea7377f3d1af	859	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	860	/* ================ DMA ================ */
Pokitto	5:ea7377f3d1af	861	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	862
Pokitto	5:ea7377f3d1af	863
Pokitto	5:ea7377f3d1af	864	/**
Pokitto	5:ea7377f3d1af	865	* @brief Product name title=Kylin UM Chapter title=KylinDMA controller Modification date=5/13/2013 Major revision=0 Minor revision=1 (DMA)
Pokitto	5:ea7377f3d1af	866	*/
Pokitto	5:ea7377f3d1af	867
Pokitto	5:ea7377f3d1af	868	typedef struct { /!< DMA Structure /
Pokitto	5:ea7377f3d1af	869	__IO uint32_t CTRL; /!< DMA control. /
Pokitto	5:ea7377f3d1af	870	__I uint32_t INTSTAT; /!< Interrupt status. /
Pokitto	5:ea7377f3d1af	871	__IO uint32_t SRAMBASE; /!< SRAM address of the channel configuration table. /
Pokitto	5:ea7377f3d1af	872	__I uint32_t RESERVED0[5];
Pokitto	5:ea7377f3d1af	873	__IO uint32_t ENABLESET0; /!< Channel Enable read and Set for all DMA channels. /
Pokitto	5:ea7377f3d1af	874	__I uint32_t RESERVED1;
Pokitto	5:ea7377f3d1af	875	__O uint32_t ENABLECLR0; /!< Channel Enable Clear for all DMA channels. /
Pokitto	5:ea7377f3d1af	876	__I uint32_t RESERVED2;
Pokitto	5:ea7377f3d1af	877	__I uint32_t ACTIVE0; /!< Channel Active status for all DMA channels. /
Pokitto	5:ea7377f3d1af	878	__I uint32_t RESERVED3;
Pokitto	5:ea7377f3d1af	879	__I uint32_t BUSY0; /!< Channel Busy status for all DMA channels. /
Pokitto	5:ea7377f3d1af	880	__I uint32_t RESERVED4;
Pokitto	5:ea7377f3d1af	881	__IO uint32_t ERRINT0; /!< Error Interrupt status for all DMA channels. /
Pokitto	5:ea7377f3d1af	882	__I uint32_t RESERVED5;
Pokitto	5:ea7377f3d1af	883	__IO uint32_t INTENSET0; /!< Interrupt Enable read and Set for all DMA channels. /
Pokitto	5:ea7377f3d1af	884	__I uint32_t RESERVED6;
Pokitto	5:ea7377f3d1af	885	__O uint32_t INTENCLR0; /!< Interrupt Enable Clear for all DMA channels. /
Pokitto	5:ea7377f3d1af	886	__I uint32_t RESERVED7;
Pokitto	5:ea7377f3d1af	887	__IO uint32_t INTA0; /!< Interrupt A status for all DMA channels. /
Pokitto	5:ea7377f3d1af	888	__I uint32_t RESERVED8;
Pokitto	5:ea7377f3d1af	889	__IO uint32_t INTB0; /!< Interrupt B status for all DMA channels. /
Pokitto	5:ea7377f3d1af	890	__I uint32_t RESERVED9;
Pokitto	5:ea7377f3d1af	891	__O uint32_t SETVALID0; /!< Set ValidPending control bits for all DMA channels. /
Pokitto	5:ea7377f3d1af	892	__I uint32_t RESERVED10;
Pokitto	5:ea7377f3d1af	893	__O uint32_t SETTRIG0; /!< Set Trigger control bits for all DMA channels. /
Pokitto	5:ea7377f3d1af	894	__I uint32_t RESERVED11;
Pokitto	5:ea7377f3d1af	895	__O uint32_t ABORT0; /!< Channel Abort control for all DMA channels. /
Pokitto	5:ea7377f3d1af	896	__I uint32_t RESERVED12[225];
Pokitto	5:ea7377f3d1af	897	__IO uint32_t CFG0; /!< Configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	898	__I uint32_t CTLSTAT0; /!< Control and status register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	899	__IO uint32_t XFERCFG0; /!< Transfer configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	900	__I uint32_t RESERVED13;
Pokitto	5:ea7377f3d1af	901	__IO uint32_t CFG1; /!< Configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	902	__I uint32_t CTLSTAT1; /!< Control and status register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	903	__IO uint32_t XFERCFG1; /!< Transfer configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	904	__I uint32_t RESERVED14;
Pokitto	5:ea7377f3d1af	905	__IO uint32_t CFG2; /!< Configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	906	__I uint32_t CTLSTAT2; /!< Control and status register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	907	__IO uint32_t XFERCFG2; /!< Transfer configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	908	__I uint32_t RESERVED15;
Pokitto	5:ea7377f3d1af	909	__IO uint32_t CFG3; /!< Configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	910	__I uint32_t CTLSTAT3; /!< Control and status register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	911	__IO uint32_t XFERCFG3; /!< Transfer configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	912	__I uint32_t RESERVED16;
Pokitto	5:ea7377f3d1af	913	__IO uint32_t CFG4; /!< Configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	914	__I uint32_t CTLSTAT4; /!< Control and status register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	915	__IO uint32_t XFERCFG4; /!< Transfer configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	916	__I uint32_t RESERVED17;
Pokitto	5:ea7377f3d1af	917	__IO uint32_t CFG5; /!< Configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	918	__I uint32_t CTLSTAT5; /!< Control and status register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	919	__IO uint32_t XFERCFG5; /!< Transfer configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	920	__I uint32_t RESERVED18;
Pokitto	5:ea7377f3d1af	921	__IO uint32_t CFG6; /!< Configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	922	__I uint32_t CTLSTAT6; /!< Control and status register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	923	__IO uint32_t XFERCFG6; /!< Transfer configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	924	__I uint32_t RESERVED19;
Pokitto	5:ea7377f3d1af	925	__IO uint32_t CFG7; /!< Configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	926	__I uint32_t CTLSTAT7; /!< Control and status register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	927	__IO uint32_t XFERCFG7; /!< Transfer configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	928	__I uint32_t RESERVED20;
Pokitto	5:ea7377f3d1af	929	__IO uint32_t CFG8; /!< Configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	930	__I uint32_t CTLSTAT8; /!< Control and status register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	931	__IO uint32_t XFERCFG8; /!< Transfer configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	932	__I uint32_t RESERVED21;
Pokitto	5:ea7377f3d1af	933	__IO uint32_t CFG9; /!< Configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	934	__I uint32_t CTLSTAT9; /!< Control and status register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	935	__IO uint32_t XFERCFG9; /!< Transfer configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	936	__I uint32_t RESERVED22;
Pokitto	5:ea7377f3d1af	937	__IO uint32_t CFG10; /!< Configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	938	__I uint32_t CTLSTAT10; /!< Control and status register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	939	__IO uint32_t XFERCFG10; /!< Transfer configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	940	__I uint32_t RESERVED23;
Pokitto	5:ea7377f3d1af	941	__IO uint32_t CFG11; /!< Configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	942	__I uint32_t CTLSTAT11; /!< Control and status register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	943	__IO uint32_t XFERCFG11; /!< Transfer configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	944	__I uint32_t RESERVED24;
Pokitto	5:ea7377f3d1af	945	__IO uint32_t CFG12; /!< Configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	946	__I uint32_t CTLSTAT12; /!< Control and status register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	947	__IO uint32_t XFERCFG12; /!< Transfer configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	948	__I uint32_t RESERVED25;
Pokitto	5:ea7377f3d1af	949	__IO uint32_t CFG13; /!< Configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	950	__I uint32_t CTLSTAT13; /!< Control and status register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	951	__IO uint32_t XFERCFG13; /!< Transfer configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	952	__I uint32_t RESERVED26;
Pokitto	5:ea7377f3d1af	953	__IO uint32_t CFG14; /!< Configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	954	__I uint32_t CTLSTAT14; /!< Control and status register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	955	__IO uint32_t XFERCFG14; /!< Transfer configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	956	__I uint32_t RESERVED27;
Pokitto	5:ea7377f3d1af	957	__IO uint32_t CFG15; /!< Configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	958	__I uint32_t CTLSTAT15; /!< Control and status register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	959	__IO uint32_t XFERCFG15; /!< Transfer configuration register for DMA channel 0. /
Pokitto	5:ea7377f3d1af	960	} LPC_DMA_Type;
Pokitto	5:ea7377f3d1af	961
Pokitto	5:ea7377f3d1af	962
Pokitto	5:ea7377f3d1af	963	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	964	/* ================ SCT0 ================ */
Pokitto	5:ea7377f3d1af	965	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	966
Pokitto	5:ea7377f3d1af	967
Pokitto	5:ea7377f3d1af	968	/**
Pokitto	5:ea7377f3d1af	969	* @brief Product name title=Kylin UM Chapter title=KylinState Configurable Timers (SCT0/1) Modification date=5/14/2013 Major revision=0 Minor revision=1 (SCT0)
Pokitto	5:ea7377f3d1af	970	*/
Pokitto	5:ea7377f3d1af	971
Pokitto	5:ea7377f3d1af	972	typedef struct { /!< SCT0 Structure /
Pokitto	5:ea7377f3d1af	973	__IO uint32_t CONFIG; /!< SCT configuration register /
Pokitto	5:ea7377f3d1af	974	__IO uint32_t CTRL; /!< SCT control register /
Pokitto	5:ea7377f3d1af	975	__IO uint32_t LIMIT; /!< SCT limit register /
Pokitto	5:ea7377f3d1af	976	__IO uint32_t HALT; /!< SCT halt condition register /
Pokitto	5:ea7377f3d1af	977	__IO uint32_t STOP; /!< SCT stop condition register /
Pokitto	5:ea7377f3d1af	978	__IO uint32_t START; /!< SCT start condition register /
Pokitto	5:ea7377f3d1af	979	__I uint32_t RESERVED0[10];
Pokitto	5:ea7377f3d1af	980	__IO uint32_t COUNT; /!< SCT counter register /
Pokitto	5:ea7377f3d1af	981	__IO uint32_t STATE; /!< SCT state register /
Pokitto	5:ea7377f3d1af	982	__I uint32_t INPUT; /!< SCT input register /
Pokitto	5:ea7377f3d1af	983	__IO uint32_t REGMODE; /!< SCT match/capture registers mode register /
Pokitto	5:ea7377f3d1af	984	__IO uint32_t OUTPUT; /!< SCT output register /
Pokitto	5:ea7377f3d1af	985	__IO uint32_t OUTPUTDIRCTRL; /!< SCT output counter direction control register /
Pokitto	5:ea7377f3d1af	986	__IO uint32_t RES; /!< SCT conflict resolution register /
Pokitto	5:ea7377f3d1af	987	__IO uint32_t DMAREQ0; /!< SCT DMA request 0 register /
Pokitto	5:ea7377f3d1af	988	__IO uint32_t DMAREQ1; /!< SCT DMA request 1 register /
Pokitto	5:ea7377f3d1af	989	__I uint32_t RESERVED1[35];
Pokitto	5:ea7377f3d1af	990	__IO uint32_t EVEN; /!< SCT event enable register /
Pokitto	5:ea7377f3d1af	991	__IO uint32_t EVFLAG; /!< SCT event flag register /
Pokitto	5:ea7377f3d1af	992	__IO uint32_t CONEN; /!< SCT conflict enable register /
Pokitto	5:ea7377f3d1af	993	__IO uint32_t CONFLAG; /!< SCT conflict flag register /
Pokitto	5:ea7377f3d1af	994
Pokitto	5:ea7377f3d1af	995	union {
Pokitto	5:ea7377f3d1af	996	__IO uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
Pokitto	5:ea7377f3d1af	997	= 1 */
Pokitto	5:ea7377f3d1af	998	__IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
Pokitto	5:ea7377f3d1af	999	REGMODE4 = 0 */
Pokitto	5:ea7377f3d1af	1000	};
Pokitto	5:ea7377f3d1af	1001
Pokitto	5:ea7377f3d1af	1002	union {
Pokitto	5:ea7377f3d1af	1003	__IO uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
Pokitto	5:ea7377f3d1af	1004	= 1 */
Pokitto	5:ea7377f3d1af	1005	__IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
Pokitto	5:ea7377f3d1af	1006	REGMODE4 = 0 */
Pokitto	5:ea7377f3d1af	1007	};
Pokitto	5:ea7377f3d1af	1008
Pokitto	5:ea7377f3d1af	1009	union {
Pokitto	5:ea7377f3d1af	1010	__IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
Pokitto	5:ea7377f3d1af	1011	REGMODE4 = 0 */
Pokitto	5:ea7377f3d1af	1012	__IO uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
Pokitto	5:ea7377f3d1af	1013	= 1 */
Pokitto	5:ea7377f3d1af	1014	};
Pokitto	5:ea7377f3d1af	1015
Pokitto	5:ea7377f3d1af	1016	union {
Pokitto	5:ea7377f3d1af	1017	__IO uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
Pokitto	5:ea7377f3d1af	1018	= 1 */
Pokitto	5:ea7377f3d1af	1019	__IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
Pokitto	5:ea7377f3d1af	1020	REGMODE4 = 0 */
Pokitto	5:ea7377f3d1af	1021	};
Pokitto	5:ea7377f3d1af	1022
Pokitto	5:ea7377f3d1af	1023	union {
Pokitto	5:ea7377f3d1af	1024	__IO uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 4; REGMOD0 to REGMODE4
Pokitto	5:ea7377f3d1af	1025	= 1 */
Pokitto	5:ea7377f3d1af	1026	__IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 4; REGMOD0 to
Pokitto	5:ea7377f3d1af	1027	REGMODE4 = 0 */
Pokitto	5:ea7377f3d1af	1028	};
Pokitto	5:ea7377f3d1af	1029	__I uint32_t RESERVED2[59];
Pokitto	5:ea7377f3d1af	1030
Pokitto	5:ea7377f3d1af	1031	union {
Pokitto	5:ea7377f3d1af	1032	__IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
Pokitto	5:ea7377f3d1af	1033	= 1 */
Pokitto	5:ea7377f3d1af	1034	__IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
Pokitto	5:ea7377f3d1af	1035	= 0 */
Pokitto	5:ea7377f3d1af	1036	};
Pokitto	5:ea7377f3d1af	1037
Pokitto	5:ea7377f3d1af	1038	union {
Pokitto	5:ea7377f3d1af	1039	__IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
Pokitto	5:ea7377f3d1af	1040	= 0 */
Pokitto	5:ea7377f3d1af	1041	__IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
Pokitto	5:ea7377f3d1af	1042	= 1 */
Pokitto	5:ea7377f3d1af	1043	};
Pokitto	5:ea7377f3d1af	1044
Pokitto	5:ea7377f3d1af	1045	union {
Pokitto	5:ea7377f3d1af	1046	__IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
Pokitto	5:ea7377f3d1af	1047	= 0 */
Pokitto	5:ea7377f3d1af	1048	__IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
Pokitto	5:ea7377f3d1af	1049	= 1 */
Pokitto	5:ea7377f3d1af	1050	};
Pokitto	5:ea7377f3d1af	1051
Pokitto	5:ea7377f3d1af	1052	union {
Pokitto	5:ea7377f3d1af	1053	__IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
Pokitto	5:ea7377f3d1af	1054	= 1 */
Pokitto	5:ea7377f3d1af	1055	__IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
Pokitto	5:ea7377f3d1af	1056	= 0 */
Pokitto	5:ea7377f3d1af	1057	};
Pokitto	5:ea7377f3d1af	1058
Pokitto	5:ea7377f3d1af	1059	union {
Pokitto	5:ea7377f3d1af	1060	__IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 4; REGMOD0 = 1 to REGMODE4
Pokitto	5:ea7377f3d1af	1061	= 1 */
Pokitto	5:ea7377f3d1af	1062	__IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 4; REGMOD0 = 0 to REGMODE4
Pokitto	5:ea7377f3d1af	1063	= 0 */
Pokitto	5:ea7377f3d1af	1064	};
Pokitto	5:ea7377f3d1af	1065	__I uint32_t RESERVED3[59];
Pokitto	5:ea7377f3d1af	1066	__IO uint32_t EV0_STATE; /!< SCT event state register 0 /
Pokitto	5:ea7377f3d1af	1067	__IO uint32_t EV0_CTRL; /!< SCT event control register 0 /
Pokitto	5:ea7377f3d1af	1068	__IO uint32_t EV1_STATE; /!< SCT event state register 0 /
Pokitto	5:ea7377f3d1af	1069	__IO uint32_t EV1_CTRL; /!< SCT event control register 0 /
Pokitto	5:ea7377f3d1af	1070	__IO uint32_t EV2_STATE; /!< SCT event state register 0 /
Pokitto	5:ea7377f3d1af	1071	__IO uint32_t EV2_CTRL; /!< SCT event control register 0 /
Pokitto	5:ea7377f3d1af	1072	__IO uint32_t EV3_STATE; /!< SCT event state register 0 /
Pokitto	5:ea7377f3d1af	1073	__IO uint32_t EV3_CTRL; /!< SCT event control register 0 /
Pokitto	5:ea7377f3d1af	1074	__IO uint32_t EV4_STATE; /!< SCT event state register 0 /
Pokitto	5:ea7377f3d1af	1075	__IO uint32_t EV4_CTRL; /!< SCT event control register 0 /
Pokitto	5:ea7377f3d1af	1076	__IO uint32_t EV5_STATE; /!< SCT event state register 0 /
Pokitto	5:ea7377f3d1af	1077	__IO uint32_t EV5_CTRL; /!< SCT event control register 0 /
Pokitto	5:ea7377f3d1af	1078	__I uint32_t RESERVED4[116];
Pokitto	5:ea7377f3d1af	1079	__IO uint32_t OUT0_SET; /!< SCT output 0 set register /
Pokitto	5:ea7377f3d1af	1080	__IO uint32_t OUT0_CLR; /!< SCT output 0 clear register /
Pokitto	5:ea7377f3d1af	1081	__IO uint32_t OUT1_SET; /!< SCT output 0 set register /
Pokitto	5:ea7377f3d1af	1082	__IO uint32_t OUT1_CLR; /!< SCT output 0 clear register /
Pokitto	5:ea7377f3d1af	1083	__IO uint32_t OUT2_SET; /!< SCT output 0 set register /
Pokitto	5:ea7377f3d1af	1084	__IO uint32_t OUT2_CLR; /!< SCT output 0 clear register /
Pokitto	5:ea7377f3d1af	1085	__IO uint32_t OUT3_SET; /!< SCT output 0 set register /
Pokitto	5:ea7377f3d1af	1086	__IO uint32_t OUT3_CLR; /!< SCT output 0 clear register /
Pokitto	5:ea7377f3d1af	1087	} LPC_SCT0_Type;
Pokitto	5:ea7377f3d1af	1088
Pokitto	5:ea7377f3d1af	1089
Pokitto	5:ea7377f3d1af	1090	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	1091	/* ================ GPIO_PORT ================ */
Pokitto	5:ea7377f3d1af	1092	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	1093
Pokitto	5:ea7377f3d1af	1094
Pokitto	5:ea7377f3d1af	1095	/**
Pokitto	5:ea7377f3d1af	1096	* @brief General Purpose I/O (GPIO) (GPIO_PORT)
Pokitto	5:ea7377f3d1af	1097	*/
Pokitto	5:ea7377f3d1af	1098
Pokitto	5:ea7377f3d1af	1099	typedef struct { /!< GPIO_PORT Structure /
Pokitto	5:ea7377f3d1af	1100	__IO uint8_t B[88]; /!< Byte pin registers /
Pokitto	5:ea7377f3d1af	1101	__I uint32_t RESERVED0[42];
Pokitto	5:ea7377f3d1af	1102	__IO uint32_t W[88]; /!< Word pin registers /
Pokitto	5:ea7377f3d1af	1103	__I uint32_t RESERVED1[1896];
Pokitto	5:ea7377f3d1af	1104	__IO uint32_t DIR[3]; /!< Port Direction registers /
Pokitto	5:ea7377f3d1af	1105	__I uint32_t RESERVED2[29];
Pokitto	5:ea7377f3d1af	1106	__IO uint32_t MASK[3]; /!< Port Mask register /
Pokitto	5:ea7377f3d1af	1107	__I uint32_t RESERVED3[29];
Pokitto	5:ea7377f3d1af	1108	__IO uint32_t PIN[3]; /!< Port pin register /
Pokitto	5:ea7377f3d1af	1109	__I uint32_t RESERVED4[29];
Pokitto	5:ea7377f3d1af	1110	__IO uint32_t MPIN[3]; /!< Masked port register /
Pokitto	5:ea7377f3d1af	1111	__I uint32_t RESERVED5[29];
Pokitto	5:ea7377f3d1af	1112	__IO uint32_t SET[3]; /!< Write: Set port register Read: port output bits /
Pokitto	5:ea7377f3d1af	1113	__I uint32_t RESERVED6[29];
Pokitto	5:ea7377f3d1af	1114	__O uint32_t CLR[3]; /!< Clear port /
Pokitto	5:ea7377f3d1af	1115	__I uint32_t RESERVED7[29];
Pokitto	5:ea7377f3d1af	1116	__O uint32_t NOT[3]; /!< Toggle port /
Pokitto	5:ea7377f3d1af	1117	} LPC_GPIO_PORT_Type;
Pokitto	5:ea7377f3d1af	1118
Pokitto	5:ea7377f3d1af	1119
Pokitto	5:ea7377f3d1af	1120	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	1121	/* ================ PINT ================ */
Pokitto	5:ea7377f3d1af	1122	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	1123
Pokitto	5:ea7377f3d1af	1124
Pokitto	5:ea7377f3d1af	1125	/**
Pokitto	5:ea7377f3d1af	1126	* @brief Pin interruptand pattern match (PINT) (PINT)
Pokitto	5:ea7377f3d1af	1127	*/
Pokitto	5:ea7377f3d1af	1128
Pokitto	5:ea7377f3d1af	1129	typedef struct { /!< PINT Structure /
Pokitto	5:ea7377f3d1af	1130	__IO uint32_t ISEL; /!< Pin Interrupt Mode register /
Pokitto	5:ea7377f3d1af	1131	__IO uint32_t IENR; /!< Pin interrupt level or rising edge interrupt enable register /
Pokitto	5:ea7377f3d1af	1132	__O uint32_t SIENR; /!< Pin interrupt level or rising edge interrupt set register /
Pokitto	5:ea7377f3d1af	1133	__O uint32_t CIENR; /!< Pin interrupt level (rising edge interrupt) clear register /
Pokitto	5:ea7377f3d1af	1134	__IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
Pokitto	5:ea7377f3d1af	1135	register */
Pokitto	5:ea7377f3d1af	1136	__O uint32_t SIENF; /!< Pin interrupt active level or falling edge interrupt set register /
Pokitto	5:ea7377f3d1af	1137	__O uint32_t CIENF; /!< Pin interrupt active level or falling edge interrupt clear register /
Pokitto	5:ea7377f3d1af	1138	__IO uint32_t RISE; /!< Pin interrupt rising edge register /
Pokitto	5:ea7377f3d1af	1139	__IO uint32_t FALL; /!< Pin interrupt falling edge register /
Pokitto	5:ea7377f3d1af	1140	__IO uint32_t IST; /!< Pin interrupt status register /
Pokitto	5:ea7377f3d1af	1141	__IO uint32_t PMCTRL; /!< Pattern match interrupt control register /
Pokitto	5:ea7377f3d1af	1142	__IO uint32_t PMSRC; /!< Pattern match interrupt bit-slice source register /
Pokitto	5:ea7377f3d1af	1143	__IO uint32_t PMCFG; /!< Pattern match interrupt bit slice configuration register /
Pokitto	5:ea7377f3d1af	1144	} LPC_PINT_Type;
Pokitto	5:ea7377f3d1af	1145
Pokitto	5:ea7377f3d1af	1146
Pokitto	5:ea7377f3d1af	1147	/* -------------------- End of section using anonymous unions ------------------- */
Pokitto	5:ea7377f3d1af	1148	#if defined(__CC_ARM)
Pokitto	5:ea7377f3d1af	1149	#pragma pop
Pokitto	5:ea7377f3d1af	1150	#elif defined(__ICCARM__)
Pokitto	5:ea7377f3d1af	1151	/* leave anonymous unions enabled */
Pokitto	5:ea7377f3d1af	1152	#elif defined(__GNUC__)
Pokitto	5:ea7377f3d1af	1153	/* anonymous unions are enabled by default */
Pokitto	5:ea7377f3d1af	1154	#elif defined(__TMS470__)
Pokitto	5:ea7377f3d1af	1155	/* anonymous unions are enabled by default */
Pokitto	5:ea7377f3d1af	1156	#elif defined(__TASKING__)
Pokitto	5:ea7377f3d1af	1157	#pragma warning restore
Pokitto	5:ea7377f3d1af	1158	#else
Pokitto	5:ea7377f3d1af	1159	#warning Not supported compiler type
Pokitto	5:ea7377f3d1af	1160	#endif
Pokitto	5:ea7377f3d1af	1161
Pokitto	5:ea7377f3d1af	1162
Pokitto	5:ea7377f3d1af	1163
Pokitto	5:ea7377f3d1af	1164
Pokitto	5:ea7377f3d1af	1165	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	1166	/* ================ Peripheral memory map ================ */
Pokitto	5:ea7377f3d1af	1167	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	1168
Pokitto	5:ea7377f3d1af	1169	#define LPC_I2C0_BASE 0x40000000UL
Pokitto	5:ea7377f3d1af	1170	#define LPC_WWDT_BASE 0x40004000UL
Pokitto	5:ea7377f3d1af	1171	#define LPC_USART0_BASE 0x40008000UL
Pokitto	5:ea7377f3d1af	1172	#define LPC_CT16B0_BASE 0x4000C000UL
Pokitto	5:ea7377f3d1af	1173	#define LPC_CT16B1_BASE 0x40010000UL
Pokitto	5:ea7377f3d1af	1174	#define LPC_CT32B0_BASE 0x40014000UL
Pokitto	5:ea7377f3d1af	1175	#define LPC_CT32B1_BASE 0x40018000UL
Pokitto	5:ea7377f3d1af	1176	#define LPC_ADC_BASE 0x4001C000UL
Pokitto	5:ea7377f3d1af	1177	#define LPC_I2C1_BASE 0x40020000UL
Pokitto	5:ea7377f3d1af	1178	#define LPC_RTC_BASE 0x40024000UL
Pokitto	5:ea7377f3d1af	1179	#define LPC_DMATRIGMUX_BASE 0x40028000UL
Pokitto	5:ea7377f3d1af	1180	#define LPC_PMU_BASE 0x40038000UL
Pokitto	5:ea7377f3d1af	1181	#define LPC_FLASHCTRL_BASE 0x4003C000UL
Pokitto	5:ea7377f3d1af	1182	#define LPC_SSP0_BASE 0x40040000UL
Pokitto	5:ea7377f3d1af	1183	#define LPC_IOCON_BASE 0x40044000UL
Pokitto	5:ea7377f3d1af	1184	#define LPC_SYSCON_BASE 0x40048000UL
Pokitto	5:ea7377f3d1af	1185	#define LPC_USART4_BASE 0x4004C000UL
Pokitto	5:ea7377f3d1af	1186	#define LPC_SSP1_BASE 0x40058000UL
Pokitto	5:ea7377f3d1af	1187	#define LPC_GINT0_BASE 0x4005C000UL
Pokitto	5:ea7377f3d1af	1188	#define LPC_GINT1_BASE 0x40060000UL
Pokitto	5:ea7377f3d1af	1189	#define LPC_USART1_BASE 0x4006C000UL
Pokitto	5:ea7377f3d1af	1190	#define LPC_USART2_BASE 0x40070000UL
Pokitto	5:ea7377f3d1af	1191	#define LPC_USART3_BASE 0x40074000UL
Pokitto	5:ea7377f3d1af	1192	#define LPC_USB_BASE 0x40080000UL
Pokitto	5:ea7377f3d1af	1193	#define LPC_CRC_BASE 0x50000000UL
Pokitto	5:ea7377f3d1af	1194	#define LPC_DMA_BASE 0x50004000UL
Pokitto	5:ea7377f3d1af	1195	#define LPC_SCT0_BASE 0x5000C000UL
Pokitto	5:ea7377f3d1af	1196	#define LPC_SCT1_BASE 0x5000E000UL
Pokitto	5:ea7377f3d1af	1197	#define LPC_GPIO_PORT_BASE 0xA0000000UL
Pokitto	5:ea7377f3d1af	1198	#define LPC_PINT_BASE 0xA0004000UL
Pokitto	5:ea7377f3d1af	1199
Pokitto	5:ea7377f3d1af	1200
Pokitto	5:ea7377f3d1af	1201	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	1202	/* ================ Peripheral declaration ================ */
Pokitto	5:ea7377f3d1af	1203	/* ================================================================================ */
Pokitto	5:ea7377f3d1af	1204
Pokitto	5:ea7377f3d1af	1205	#define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
Pokitto	5:ea7377f3d1af	1206	#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
Pokitto	5:ea7377f3d1af	1207	#define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
Pokitto	5:ea7377f3d1af	1208	#define LPC_CT16B0 ((LPC_CT16B0_Type *) LPC_CT16B0_BASE)
Pokitto	5:ea7377f3d1af	1209	#define LPC_CT16B1 ((LPC_CT16B0_Type *) LPC_CT16B1_BASE)
Pokitto	5:ea7377f3d1af	1210	#define LPC_CT32B0 ((LPC_CT32B0_Type *) LPC_CT32B0_BASE)
Pokitto	5:ea7377f3d1af	1211	#define LPC_CT32B1 ((LPC_CT32B0_Type *) LPC_CT32B1_BASE)
Pokitto	5:ea7377f3d1af	1212	#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
Pokitto	5:ea7377f3d1af	1213	#define LPC_I2C1 ((LPC_I2C0_Type *) LPC_I2C1_BASE)
Pokitto	5:ea7377f3d1af	1214	#define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
Pokitto	5:ea7377f3d1af	1215	#define LPC_DMATRIGMUX ((LPC_DMATRIGMUX_Type *) LPC_DMATRIGMUX_BASE)
Pokitto	5:ea7377f3d1af	1216	#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
Pokitto	5:ea7377f3d1af	1217	#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
Pokitto	5:ea7377f3d1af	1218	#define LPC_SSP0 ((LPC_SSP0_Type *) LPC_SSP0_BASE)
Pokitto	5:ea7377f3d1af	1219	#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
Pokitto	5:ea7377f3d1af	1220	#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
Pokitto	5:ea7377f3d1af	1221	#define LPC_USART4 ((LPC_USART4_Type *) LPC_USART4_BASE)
Pokitto	5:ea7377f3d1af	1222	#define LPC_SSP1 ((LPC_SSP0_Type *) LPC_SSP1_BASE)
Pokitto	5:ea7377f3d1af	1223	#define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
Pokitto	5:ea7377f3d1af	1224	#define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
Pokitto	5:ea7377f3d1af	1225	#define LPC_USART1 ((LPC_USART4_Type *) LPC_USART1_BASE)
Pokitto	5:ea7377f3d1af	1226	#define LPC_USART2 ((LPC_USART4_Type *) LPC_USART2_BASE)
Pokitto	5:ea7377f3d1af	1227	#define LPC_USART3 ((LPC_USART4_Type *) LPC_USART3_BASE)
Pokitto	5:ea7377f3d1af	1228	#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
Pokitto	5:ea7377f3d1af	1229	#define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
Pokitto	5:ea7377f3d1af	1230	#define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
Pokitto	5:ea7377f3d1af	1231	#define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
Pokitto	5:ea7377f3d1af	1232	#define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
Pokitto	5:ea7377f3d1af	1233	#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
Pokitto	5:ea7377f3d1af	1234	#define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
Pokitto	5:ea7377f3d1af	1235
Pokitto	5:ea7377f3d1af	1236
Pokitto	5:ea7377f3d1af	1237	/** @} / / End of group Device_Peripheral_Registers */
Pokitto	5:ea7377f3d1af	1238	/** @} / / End of group LPC11U6x */
Pokitto	5:ea7377f3d1af	1239	/** @} / / End of group (null) */
Pokitto	5:ea7377f3d1af	1240
Pokitto	5:ea7377f3d1af	1241	#ifdef __cplusplus
Pokitto	5:ea7377f3d1af	1242	}
Pokitto	5:ea7377f3d1af	1243	#endif
Pokitto	5:ea7377f3d1af	1244
Pokitto	5:ea7377f3d1af	1245
Pokitto	5:ea7377f3d1af	1246	#endif /* LPC11U6x_H */
Pokitto	5:ea7377f3d1af	1247

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Type:	Library
Created:	20 Nov 2018
Imports:	5
Forks:	0
Commits:	65
Dependents:	0
Dependencies:	0
Followers:	1

mbed-pokitto/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/LPC11U6x.h@64:6e6c6c2b664e, 2018-11-18 (annotated)

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