spinal cord / PokittoLib_

PokittoLib is the library needed for programming the Pokitto DIY game console (www.pokitto.com)

POKITTO_HW/lpc_defs.h@64:6e6c6c2b664e, 2018-11-18 (annotated)

Committer:
spinal
Date:
Sun Nov 18 15:47:54 2018 +0000
Revision:
64:6e6c6c2b664e
Parent:
58:5f58a2846a20 
added fix for directrectangle()

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Pokitto 30:796f9611d2ac 1 #ifndef LPCDEFS_H
Pokitto 30:796f9611d2ac 2 #define LPCDEFS_H
Pokitto 30:796f9611d2ac 3
Pokitto 30:796f9611d2ac 4 #include <stdint.h>
Pokitto 30:796f9611d2ac 5
Pokitto 30:796f9611d2ac 6 #ifdef __cplusplus
Pokitto 30:796f9611d2ac 7 #define __I volatile /*!< Defines 'read only' permissions */
Pokitto 30:796f9611d2ac 8 #else
Pokitto 30:796f9611d2ac 9 #define __I volatile const /*!< Defines 'read only' permissions */
Pokitto 30:796f9611d2ac 10 #endif
Pokitto 30:796f9611d2ac 11 #define __O volatile /*!< Defines 'write only' permissions */
Pokitto 30:796f9611d2ac 12 #define __IO volatile /*!< Defines 'read / write' permissions */
Pokitto 30:796f9611d2ac 13
Pokitto 30:796f9611d2ac 14
Pokitto 58:5f58a2846a20 15 //#define LPC_PMU_BASE 0x40038000
Pokitto 58:5f58a2846a20 16 //#define LPC_IOCON_BASE 0x40044000
Pokitto 30:796f9611d2ac 17 #define LPC_SYSCTL_BASE 0x40048000
Pokitto 58:5f58a2846a20 18 //#define LPC_GPIO_PORT_BASE 0xA0000000
Pokitto 30:796f9611d2ac 19 #define LPC_GPIO_GROUP_INT0_BASE 0x4005C000
Pokitto 30:796f9611d2ac 20 #define LPC_GPIO_GROUP_INT1_BASE 0x40060000
Pokitto 30:796f9611d2ac 21 #define LPC_PIN_INT_BASE 0xA0004000
Pokitto 58:5f58a2846a20 22 //#define LPC_USART0_BASE 0x40008000
Pokitto 58:5f58a2846a20 23 //#define LPC_USART1_BASE 0x4006C000
Pokitto 58:5f58a2846a20 24 //#define LPC_USART2_BASE 0x40070000
Pokitto 58:5f58a2846a20 25 //#define LPC_USART3_BASE 0x40074000
Pokitto 58:5f58a2846a20 26 //#define LPC_USART4_BASE 0x4004C000
Pokitto 58:5f58a2846a20 27 //#define LPC_I2C0_BASE 0x40000000
Pokitto 58:5f58a2846a20 28 //#define LPC_I2C1_BASE 0x40020000
Pokitto 58:5f58a2846a20 29 //#define LPC_SSP0_BASE 0x40040000
Pokitto 58:5f58a2846a20 30 //#define LPC_SSP1_BASE 0x40058000
Pokitto 30:796f9611d2ac 31 #define LPC_USB0_BASE 0x40080000
Pokitto 58:5f58a2846a20 32 //#define LPC_ADC_BASE 0x4001C000
Pokitto 58:5f58a2846a20 33 //#define LPC_SCT0_BASE 0x5000C000
Pokitto 58:5f58a2846a20 34 //#define LPC_SCT1_BASE 0x5000E000
Pokitto 30:796f9611d2ac 35 #define LPC_TIMER16_0_BASE 0x4000C000
Pokitto 30:796f9611d2ac 36 #define LPC_TIMER16_1_BASE 0x40010000
Pokitto 30:796f9611d2ac 37 #define LPC_TIMER32_0_BASE 0x40014000
Pokitto 30:796f9611d2ac 38 #define LPC_TIMER32_1_BASE 0x40018000
Pokitto 58:5f58a2846a20 39 //#define LPC_RTC_BASE 0x40024000
Pokitto 58:5f58a2846a20 40 //#define LPC_WWDT_BASE 0x40004000
Pokitto 58:5f58a2846a20 41 //#define LPC_DMA_BASE 0x50004000
Pokitto 58:5f58a2846a20 42 //#define LPC_CRC_BASE 0x50000000
Pokitto 30:796f9611d2ac 43 #define LPC_FLASH_BASE 0x4003C000
Pokitto 30:796f9611d2ac 44 #define LPC_DMATRIGMUX_BASE 0x40028000UL
Pokitto 30:796f9611d2ac 45
Pokitto 30:796f9611d2ac 46 /**
Pokitto 30:796f9611d2ac 47 * @brief LPC11U6X System Control block structure
Pokitto 30:796f9611d2ac 48 */
Pokitto 30:796f9611d2ac 49 typedef struct { /*!< SYSCTL Structure */
Pokitto 30:796f9611d2ac 50 __IO uint32_t SYSMEMREMAP; /*!< System Memory remap register */
Pokitto 30:796f9611d2ac 51 __IO uint32_t PRESETCTRL; /*!< Peripheral reset Control register */
Pokitto 30:796f9611d2ac 52 __IO uint32_t SYSPLLCTRL; /*!< System PLL control register */
Pokitto 30:796f9611d2ac 53 __I uint32_t SYSPLLSTAT; /*!< System PLL status register */
Pokitto 30:796f9611d2ac 54 __IO uint32_t USBPLLCTRL; /*!< USB PLL control register */
Pokitto 30:796f9611d2ac 55 __I uint32_t USBPLLSTAT; /*!< USB PLL status register */
Pokitto 30:796f9611d2ac 56 __I uint32_t RESERVED1[1];
Pokitto 30:796f9611d2ac 57 __IO uint32_t RTCOSCCTRL; /*!< RTC Oscillator control register */
Pokitto 30:796f9611d2ac 58 __IO uint32_t SYSOSCCTRL; /*!< System Oscillator control register */
Pokitto 30:796f9611d2ac 59 __IO uint32_t WDTOSCCTRL; /*!< Watchdog Oscillator control register */
Pokitto 30:796f9611d2ac 60 __I uint32_t RESERVED2[2];
Pokitto 30:796f9611d2ac 61 __IO uint32_t SYSRSTSTAT; /*!< System Reset Status register */
Pokitto 30:796f9611d2ac 62 __I uint32_t RESERVED3[3];
Pokitto 30:796f9611d2ac 63 __IO uint32_t SYSPLLCLKSEL; /*!< System PLL clock source select register */
Pokitto 30:796f9611d2ac 64 __IO uint32_t SYSPLLCLKUEN; /*!< System PLL clock source update enable register*/
Pokitto 30:796f9611d2ac 65 __IO uint32_t USBPLLCLKSEL; /*!< USB PLL clock source select register */
Pokitto 30:796f9611d2ac 66 __IO uint32_t USBPLLCLKUEN; /*!< USB PLL clock source update enable register */
Pokitto 30:796f9611d2ac 67 __I uint32_t RESERVED4[8];
Pokitto 30:796f9611d2ac 68 __IO uint32_t MAINCLKSEL; /*!< Main clock source select register */
Pokitto 30:796f9611d2ac 69 __IO uint32_t MAINCLKUEN; /*!< Main clock source update enable register */
Pokitto 30:796f9611d2ac 70 __IO uint32_t SYSAHBCLKDIV; /*!< System Clock divider register */
Pokitto 30:796f9611d2ac 71 __I uint32_t RESERVED5;
Pokitto 30:796f9611d2ac 72 __IO uint32_t SYSAHBCLKCTRL; /*!< System clock control register */
Pokitto 30:796f9611d2ac 73 __I uint32_t RESERVED6[4];
Pokitto 30:796f9611d2ac 74 __IO uint32_t SSP0CLKDIV; /*!< SSP0 clock divider register */
Pokitto 30:796f9611d2ac 75 __IO uint32_t USART0CLKDIV; /*!< UART clock divider register */
Pokitto 30:796f9611d2ac 76 __IO uint32_t SSP1CLKDIV; /*!< SSP1 clock divider register */
Pokitto 30:796f9611d2ac 77 __IO uint32_t FRGCLKDIV; /*!< FRG clock divider (USARTS 1 - 4) register */
Pokitto 30:796f9611d2ac 78 __I uint32_t RESERVED7[7];
Pokitto 30:796f9611d2ac 79 __IO uint32_t USBCLKSEL; /*!< USB clock source select register */
Pokitto 30:796f9611d2ac 80 __IO uint32_t USBCLKUEN; /*!< USB clock source update enable register */
Pokitto 30:796f9611d2ac 81 __IO uint32_t USBCLKDIV; /*!< USB clock source divider register */
Pokitto 30:796f9611d2ac 82 __I uint32_t RESERVED8[5];
Pokitto 30:796f9611d2ac 83 __IO uint32_t CLKOUTSEL; /*!< Clock out source select register */
Pokitto 30:796f9611d2ac 84 __IO uint32_t CLKOUTUEN; /*!< Clock out source update enable register */
Pokitto 30:796f9611d2ac 85 __IO uint32_t CLKOUTDIV; /*!< Clock out divider register */
Pokitto 30:796f9611d2ac 86 __I uint32_t RESERVED9;
Pokitto 30:796f9611d2ac 87 __IO uint32_t UARTFRGDIV; /*!< USART fractional generator divider (USARTS 1 - 4) register */
Pokitto 30:796f9611d2ac 88 __IO uint32_t UARTFRGMULT; /*!< USART fractional generator multiplier (USARTS 1 - 4) register */
Pokitto 30:796f9611d2ac 89 __I uint32_t RESERVED10;
Pokitto 30:796f9611d2ac 90 __IO uint32_t EXTTRACECMD; /*!< External trace buffer command register */
Pokitto 30:796f9611d2ac 91 __I uint32_t PIOPORCAP[3]; /*!< POR captured PIO status registers */
Pokitto 30:796f9611d2ac 92 __I uint32_t RESERVED11[10];
Pokitto 30:796f9611d2ac 93 __IO uint32_t IOCONCLKDIV[7]; /*!< IOCON block for programmable glitch filter divider registers */
Pokitto 30:796f9611d2ac 94 __IO uint32_t BODCTRL; /*!< Brown Out Detect register */
Pokitto 30:796f9611d2ac 95 __IO uint32_t SYSTCKCAL; /*!< System tick counter calibration register */
Pokitto 30:796f9611d2ac 96 __I uint32_t RESERVED12[6];
Pokitto 30:796f9611d2ac 97 __IO uint32_t IRQLATENCY; /*!< IRQ delay register */
Pokitto 30:796f9611d2ac 98 __IO uint32_t NMISRC; /*!< NMI source control register */
Pokitto 30:796f9611d2ac 99 __IO uint32_t PINTSEL[8]; /*!< GPIO pin interrupt select register 0-7 */
Pokitto 30:796f9611d2ac 100 __IO uint32_t USBCLKCTRL; /*!< USB clock control register */
Pokitto 30:796f9611d2ac 101 __I uint32_t USBCLKST; /*!< USB clock status register */
Pokitto 30:796f9611d2ac 102 __I uint32_t RESERVED13[25];
Pokitto 30:796f9611d2ac 103 __IO uint32_t STARTERP0; /*!< Start logic 0 interrupt wake-up enable register */
Pokitto 30:796f9611d2ac 104 __I uint32_t RESERVED14[3];
Pokitto 30:796f9611d2ac 105 __IO uint32_t STARTERP1; /*!< Start logic 1 interrupt wake-up enable register */
Pokitto 30:796f9611d2ac 106 __I uint32_t RESERVED15[6];
Pokitto 30:796f9611d2ac 107 __IO uint32_t PDSLEEPCFG; /*!< Power down states in deep sleep mode register */
Pokitto 30:796f9611d2ac 108 __IO uint32_t PDWAKECFG; /*!< Power down states in wake up from deep sleep register */
Pokitto 30:796f9611d2ac 109 __IO uint32_t PDRUNCFG; /*!< Power configuration register*/
Pokitto 30:796f9611d2ac 110 __I uint32_t RESERVED16[110];
Pokitto 30:796f9611d2ac 111 __I uint32_t DEVICEID; /*!< Device ID register */
Pokitto 30:796f9611d2ac 112 } LPC_SYSCTL_T;
Pokitto 30:796f9611d2ac 113
Pokitto 30:796f9611d2ac 114
Pokitto 30:796f9611d2ac 115 #define LPC_SYSCTL_BASE 0x40048000
Pokitto 30:796f9611d2ac 116
Pokitto 30:796f9611d2ac 117 #define LPC_SYSCTL ((LPC_SYSCTL_T *) LPC_SYSCTL_BASE)
Pokitto 30:796f9611d2ac 118
Pokitto 30:796f9611d2ac 119
Pokitto 30:796f9611d2ac 120
Pokitto 58:5f58a2846a20 121 //#define LPC_DMA ((LPC_DMA_T *) LPC_DMA_BASE)
Pokitto 30:796f9611d2ac 122
Pokitto 30:796f9611d2ac 123 /* DMA channel source/address/next descriptor */
Pokitto 30:796f9611d2ac 124 typedef struct {
Pokitto 30:796f9611d2ac 125 uint32_t xfercfg; /*!< Transfer configuration (only used in linked lists and ping-pong configs) */
Pokitto 30:796f9611d2ac 126 uint32_t source; /*!< DMA transfer source end address */
Pokitto 30:796f9611d2ac 127 uint32_t dest; /*!< DMA transfer desintation end address */
Pokitto 30:796f9611d2ac 128 uint32_t next; /*!< Link to next DMA descriptor, must be 16 byte aligned */
Pokitto 30:796f9611d2ac 129 } DMA_CHDESC_T;
Pokitto 30:796f9611d2ac 130
Pokitto 30:796f9611d2ac 131
Pokitto 30:796f9611d2ac 132 /* DMA channel mapping - each channel is mapped to an individual peripheral
Pokitto 30:796f9611d2ac 133 and direction or a DMA imput mux trigger */
Pokitto 30:796f9611d2ac 134 typedef enum {
Pokitto 30:796f9611d2ac 135 SSP0_RX_DMA = 0, /*!< SSP0 receive DMA channel */
Pokitto 30:796f9611d2ac 136 DMA_CH0 = SSP0_RX_DMA,
Pokitto 30:796f9611d2ac 137 DMAREQ_SSP0_TX, /*!< SSP0 transmit DMA channel */
Pokitto 30:796f9611d2ac 138 DMA_CH1 = DMAREQ_SSP0_TX,
Pokitto 30:796f9611d2ac 139 DMAREQ_SSP1_RX, /*!< SSP1 receive DMA channel */
Pokitto 30:796f9611d2ac 140 DMA_CH2 = DMAREQ_SSP1_RX,
Pokitto 30:796f9611d2ac 141 DMAREQ_SSP1_TX, /*!< SSP1 transmit DMA channel */
Pokitto 30:796f9611d2ac 142 DMA_CH3 = DMAREQ_SSP1_TX,
Pokitto 30:796f9611d2ac 143 DMAREQ_USART0_RX, /*!< USART0 receive DMA channel */
Pokitto 30:796f9611d2ac 144 DMA_CH4 = DMAREQ_USART0_RX,
Pokitto 30:796f9611d2ac 145 DMAREQ_USART0_TX, /*!< USART0 transmit DMA channel */
Pokitto 30:796f9611d2ac 146 DMA_CH5 = DMAREQ_USART0_TX,
Pokitto 30:796f9611d2ac 147 DMAREQ_USART1_RX, /*!< USART1 transmit DMA channel */
Pokitto 30:796f9611d2ac 148 DMA_CH6 = DMAREQ_USART1_RX,
Pokitto 30:796f9611d2ac 149 DMAREQ_USART1_TX, /*!< USART1 transmit DMA channel */
Pokitto 30:796f9611d2ac 150 DMA_CH7 = DMAREQ_USART1_TX,
Pokitto 30:796f9611d2ac 151 DMAREQ_USART2_RX, /*!< USART2 transmit DMA channel */
Pokitto 30:796f9611d2ac 152 DMA_CH8 = DMAREQ_USART2_RX,
Pokitto 30:796f9611d2ac 153 DMAREQ_USART2_TX, /*!< USART2 transmit DMA channel */
Pokitto 30:796f9611d2ac 154 DMA_CH9 = DMAREQ_USART2_TX,
Pokitto 30:796f9611d2ac 155 DMAREQ_USART3_RX, /*!< USART3 transmit DMA channel */
Pokitto 30:796f9611d2ac 156 DMA_CH10 = DMAREQ_USART3_RX,
Pokitto 30:796f9611d2ac 157 DMAREQ_USART3_TX, /*!< USART3 transmit DMA channel */
Pokitto 30:796f9611d2ac 158 DMA_CH11 = DMAREQ_USART3_TX,
Pokitto 30:796f9611d2ac 159 DMAREQ_USART4_RX, /*!< USART4 transmit DMA channel */
Pokitto 30:796f9611d2ac 160 DMA_CH12 = DMAREQ_USART4_RX,
Pokitto 30:796f9611d2ac 161 DMAREQ_USART4_TX, /*!< USART4 transmit DMA channel */
Pokitto 30:796f9611d2ac 162 DMA_CH13 = DMAREQ_USART4_TX,
Pokitto 30:796f9611d2ac 163 DMAREQ_RESERVED_14,
Pokitto 30:796f9611d2ac 164 DMA_CH14 = DMAREQ_RESERVED_14,
Pokitto 30:796f9611d2ac 165 DMAREQ_RESERVED_15,
Pokitto 30:796f9611d2ac 166 DMA_CH15 = DMAREQ_RESERVED_15
Pokitto 30:796f9611d2ac 167 } DMA_CHID_T;
Pokitto 30:796f9611d2ac 168
Pokitto 30:796f9611d2ac 169 /* On LPC412x, Max DMA channel is 22 */
Pokitto 30:796f9611d2ac 170 #define MAX_DMA_CHANNEL (DMA_CH15 + 1)
Pokitto 30:796f9611d2ac 171
Pokitto 30:796f9611d2ac 172 #undef _BIT
Pokitto 30:796f9611d2ac 173 /* Set bit macro */
Pokitto 30:796f9611d2ac 174 #define _BIT(n) (1 << (n))
Pokitto 30:796f9611d2ac 175
Pokitto 30:796f9611d2ac 176 /* _SBF(f,v) sets the bit field starting at position "f" to value "v".
Pokitto 30:796f9611d2ac 177 * _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
Pokitto 30:796f9611d2ac 178 * e.g., "((_SBF(5,7) | _SBF(12,0xF)) & 0xFFFF)"
Pokitto 30:796f9611d2ac 179 */
Pokitto 30:796f9611d2ac 180 #undef _SBF
Pokitto 30:796f9611d2ac 181 /* Set bit field macro */
Pokitto 30:796f9611d2ac 182 #define _SBF(f, v) ((v) << (f))
Pokitto 30:796f9611d2ac 183
Pokitto 30:796f9611d2ac 184 /* _BITMASK constructs a symbol with 'field_width' least significant
Pokitto 30:796f9611d2ac 185 * bits set.
Pokitto 30:796f9611d2ac 186 * e.g., _BITMASK(5) constructs '0x1F', _BITMASK(16) == 0xFFFF
Pokitto 30:796f9611d2ac 187 * The symbol is intended to be used to limit the bit field width
Pokitto 30:796f9611d2ac 188 * thusly:
Pokitto 30:796f9611d2ac 189 * <a_register> = (any_expression) & _BITMASK(x), where 0 < x <= 32.
Pokitto 30:796f9611d2ac 190 * If "any_expression" results in a value that is larger than can be
Pokitto 30:796f9611d2ac 191 * contained in 'x' bits, the bits above 'x - 1' are masked off. When
Pokitto 30:796f9611d2ac 192 * used with the _SBF example above, the example would be written:
Pokitto 30:796f9611d2ac 193 * a_reg = ((_SBF(5,7) | _SBF(12,0xF)) & _BITMASK(16))
Pokitto 30:796f9611d2ac 194 * This ensures that the value written to a_reg is no wider than
Pokitto 30:796f9611d2ac 195 * 16 bits, and makes the code easier to read and understand.
Pokitto 30:796f9611d2ac 196 */
Pokitto 30:796f9611d2ac 197 #undef _BITMASK
Pokitto 30:796f9611d2ac 198 /* Bitmask creation macro */
Pokitto 30:796f9611d2ac 199 #define _BITMASK(field_width) ( _BIT(field_width) - 1)
Pokitto 30:796f9611d2ac 200
Pokitto 30:796f9611d2ac 201 /* NULL pointer */
Pokitto 30:796f9611d2ac 202 #ifndef NULL
Pokitto 30:796f9611d2ac 203 #define NULL ((void *) 0)
Pokitto 30:796f9611d2ac 204 #endif
Pokitto 30:796f9611d2ac 205
Pokitto 30:796f9611d2ac 206 /* Number of elements in an array */
Pokitto 30:796f9611d2ac 207 #define NELEMENTS(array) (sizeof(array) / sizeof(array[0]))
Pokitto 30:796f9611d2ac 208
Pokitto 58:5f58a2846a20 209 //#define LPC_SCT0 ((LPC_SCT_T *) LPC_SCT0_BASE)
Pokitto 58:5f58a2846a20 210 //#define LPC_SCT1 ((LPC_SCT_T *) LPC_SCT1_BASE)
Pokitto 30:796f9611d2ac 211 #define LPC_TIMER16_0 ((LPC_TIMER_T *) LPC_TIMER16_0_BASE)
Pokitto 30:796f9611d2ac 212 #define LPC_TIMER16_1 ((LPC_TIMER_T *) LPC_TIMER16_1_BASE)
Pokitto 30:796f9611d2ac 213 #define LPC_TIMER32_0 ((LPC_TIMER_T *) LPC_TIMER32_0_BASE)
Pokitto 30:796f9611d2ac 214 #define LPC_TIMER32_1 ((LPC_TIMER_T *) LPC_TIMER32_1_BASE)
Pokitto 30:796f9611d2ac 215
Pokitto 30:796f9611d2ac 216 #endif
Pokitto 30:796f9611d2ac 217