this is a first compilation of a library for IQS5xx. For now, it work with the iqs572ev02 devellopment board. The code is inspired with the sample code provide by Azotech. I have some issu with the interrupt pin RDY, which seem to be high even I don't touch de board.
IQS5xx/IQS5xx_addresses.h@2:bd4b620316aa, 2020-01-01 (annotated)
- Committer:
- skydarc
- Date:
- Wed Jan 01 16:39:19 2020 +0000
- Revision:
- 2:bd4b620316aa
- Parent:
- 0:4907da2299a4
done ! the rdy pin is functionnal. the "system config 1" register need to be properly configured.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
skydarc | 0:4907da2299a4 | 1 | /****************************************************************************** |
skydarc | 0:4907da2299a4 | 2 | * * |
skydarc | 0:4907da2299a4 | 3 | Module specification |
skydarc | 0:4907da2299a4 | 4 | * * |
skydarc | 0:4907da2299a4 | 5 | Copyright by |
skydarc | 0:4907da2299a4 | 6 | * * |
skydarc | 0:4907da2299a4 | 7 | Azoteq (Pty) Ltd |
skydarc | 0:4907da2299a4 | 8 | Republic of South Africa |
skydarc | 0:4907da2299a4 | 9 | * * |
skydarc | 0:4907da2299a4 | 10 | Tel: +27(0)21 863 0033 |
skydarc | 0:4907da2299a4 | 11 | www.azoteq.com |
skydarc | 0:4907da2299a4 | 12 | * * |
skydarc | 0:4907da2299a4 | 13 | ******************************************************************************* |
skydarc | 0:4907da2299a4 | 14 | Refer to IQS5xx datasheet for more information, available here: |
skydarc | 0:4907da2299a4 | 15 | -insert datasheet link |
skydarc | 0:4907da2299a4 | 16 | ******************************************************************************* |
skydarc | 0:4907da2299a4 | 17 | IQS5xx - Registers & Memory Map |
skydarc | 0:4907da2299a4 | 18 | *******************************************************************************/ |
skydarc | 0:4907da2299a4 | 19 | |
skydarc | 0:4907da2299a4 | 20 | #ifndef __IQS5XX_H |
skydarc | 0:4907da2299a4 | 21 | #define __IQS5XX_H |
skydarc | 0:4907da2299a4 | 22 | |
skydarc | 0:4907da2299a4 | 23 | |
skydarc | 0:4907da2299a4 | 24 | #define IQS5xx_ADDR 0x74 |
skydarc | 0:4907da2299a4 | 25 | #define END_WINDOW (uint16_t)0xEEEE |
skydarc | 0:4907da2299a4 | 26 | |
skydarc | 0:4907da2299a4 | 27 | #define BitIsSet(VAR,Index) (VAR & (1<<Index)) != 0 |
skydarc | 0:4907da2299a4 | 28 | |
skydarc | 0:4907da2299a4 | 29 | //***************************************************************************** |
skydarc | 0:4907da2299a4 | 30 | // |
skydarc | 0:4907da2299a4 | 31 | //! ---------------------- IQS5xx-B000 BIT DEFINITIONS ----------------- |
skydarc | 0:4907da2299a4 | 32 | // |
skydarc | 0:4907da2299a4 | 33 | //***************************************************************************** |
skydarc | 0:4907da2299a4 | 34 | |
skydarc | 0:4907da2299a4 | 35 | // |
skydarc | 0:4907da2299a4 | 36 | //! GestureEvents0 bit definitions |
skydarc | 0:4907da2299a4 | 37 | // |
skydarc | 0:4907da2299a4 | 38 | #define SWIPE_Y_NEG 0x20 |
skydarc | 0:4907da2299a4 | 39 | #define SWIPE_Y_POS 0x10 |
skydarc | 0:4907da2299a4 | 40 | #define SWIPE_X_POS 0x08 |
skydarc | 0:4907da2299a4 | 41 | #define SWIPE_X_NEG 0x04 |
skydarc | 0:4907da2299a4 | 42 | #define TAP_AND_HOLD 0x02 |
skydarc | 0:4907da2299a4 | 43 | #define SINGLE_TAP 0x01 |
skydarc | 0:4907da2299a4 | 44 | // |
skydarc | 0:4907da2299a4 | 45 | //! GesturesEvents1 bit definitions |
skydarc | 0:4907da2299a4 | 46 | // |
skydarc | 0:4907da2299a4 | 47 | #define ZOOM 0x04 |
skydarc | 0:4907da2299a4 | 48 | #define SCROLL 0x02 |
skydarc | 0:4907da2299a4 | 49 | #define TWO_FINGER_TAP 0x01 |
skydarc | 0:4907da2299a4 | 50 | // |
skydarc | 0:4907da2299a4 | 51 | //! SystemInfo0 bit definitions |
skydarc | 0:4907da2299a4 | 52 | // |
skydarc | 0:4907da2299a4 | 53 | #define SHOW_RESET 0x80 |
skydarc | 0:4907da2299a4 | 54 | #define ALP_REATI_OCCURRED 0x40 |
skydarc | 0:4907da2299a4 | 55 | #define ALP_ATI_ERROR 0x20 |
skydarc | 0:4907da2299a4 | 56 | #define REATI_OCCURRED 0x10 |
skydarc | 0:4907da2299a4 | 57 | #define ATI_ERROR 0x08 |
skydarc | 0:4907da2299a4 | 58 | #define CHARGING_MODE_2 0x04 |
skydarc | 0:4907da2299a4 | 59 | #define CHARGING_MODE_1 0x02 |
skydarc | 0:4907da2299a4 | 60 | #define CHARGING_MODE_0 0x01 |
skydarc | 0:4907da2299a4 | 61 | // |
skydarc | 0:4907da2299a4 | 62 | //! SystemInfo1 bit definitions |
skydarc | 0:4907da2299a4 | 63 | // |
skydarc | 0:4907da2299a4 | 64 | #define SNAP_TOGGLE 0x10 |
skydarc | 0:4907da2299a4 | 65 | #define RR_MISSED 0x08 |
skydarc | 0:4907da2299a4 | 66 | #define TOO_MANY_FINGERS 0x04 |
skydarc | 0:4907da2299a4 | 67 | #define PALM_DETECT 0x02 |
skydarc | 0:4907da2299a4 | 68 | #define TP_MOVEMENT 0x01 |
skydarc | 0:4907da2299a4 | 69 | // |
skydarc | 0:4907da2299a4 | 70 | //! SystemControl0 bit definitions |
skydarc | 0:4907da2299a4 | 71 | // |
skydarc | 0:4907da2299a4 | 72 | #define ACK_RESET 0x80 |
skydarc | 0:4907da2299a4 | 73 | #define AUTO_ATI 0x20 |
skydarc | 0:4907da2299a4 | 74 | #define ALP_RESEED 0x10 |
skydarc | 0:4907da2299a4 | 75 | #define RESEED 0x08 |
skydarc | 0:4907da2299a4 | 76 | #define MODE_SELECT_2 0x04 |
skydarc | 0:4907da2299a4 | 77 | #define MODE_SELECT_1 0x02 |
skydarc | 0:4907da2299a4 | 78 | #define MODE_SELECT_0 0x01 |
skydarc | 0:4907da2299a4 | 79 | // |
skydarc | 0:4907da2299a4 | 80 | //! SystemControl1 bit definitions |
skydarc | 0:4907da2299a4 | 81 | // |
skydarc | 0:4907da2299a4 | 82 | #define RESET 0x02 |
skydarc | 0:4907da2299a4 | 83 | #define SUSPEND 0x01 |
skydarc | 0:4907da2299a4 | 84 | // |
skydarc | 0:4907da2299a4 | 85 | //! SystemConfig0 bit definitions |
skydarc | 0:4907da2299a4 | 86 | // |
skydarc | 0:4907da2299a4 | 87 | #define MANUAL_CONTROL 0x80 |
skydarc | 0:4907da2299a4 | 88 | #define SETUP_COMPLETE 0x40 |
skydarc | 0:4907da2299a4 | 89 | #define WDT_ENABLE 0x20 |
skydarc | 0:4907da2299a4 | 90 | #define ALP_REATI 0x08 |
skydarc | 0:4907da2299a4 | 91 | #define REATI 0x04 |
skydarc | 0:4907da2299a4 | 92 | #define IO_WAKEUP_SELECT 0x02 |
skydarc | 0:4907da2299a4 | 93 | #define IO_WAKE 0x01 |
skydarc | 0:4907da2299a4 | 94 | // |
skydarc | 0:4907da2299a4 | 95 | //! SystemConfig1 bit definitions |
skydarc | 0:4907da2299a4 | 96 | // |
skydarc | 0:4907da2299a4 | 97 | #define PROX_EVENT 0x80 |
skydarc | 0:4907da2299a4 | 98 | #define TOUCH_EVENT 0x40 |
skydarc | 0:4907da2299a4 | 99 | #define SNAP_EVENT 0x20 |
skydarc | 0:4907da2299a4 | 100 | #define ALP_PROX_EVENT 0x10 |
skydarc | 0:4907da2299a4 | 101 | #define REATI_EVENT 0x08 |
skydarc | 0:4907da2299a4 | 102 | #define TP_EVENT 0x04 |
skydarc | 0:4907da2299a4 | 103 | #define GESTURE_EVENT 0x02 |
skydarc | 0:4907da2299a4 | 104 | #define EVENT_MODE 0x01 |
skydarc | 0:4907da2299a4 | 105 | // |
skydarc | 0:4907da2299a4 | 106 | //! FilterSettings0 bit definitions |
skydarc | 0:4907da2299a4 | 107 | // |
skydarc | 0:4907da2299a4 | 108 | #define ALP_COUNT_FILTER 0x08 |
skydarc | 0:4907da2299a4 | 109 | #define IIR_SELECT 0x04 |
skydarc | 0:4907da2299a4 | 110 | #define MAV_FILTER 0x02 |
skydarc | 0:4907da2299a4 | 111 | #define IIR_FILTER 0x01 |
skydarc | 0:4907da2299a4 | 112 | // |
skydarc | 0:4907da2299a4 | 113 | //! ALPChannelSetup0 bit definitions |
skydarc | 0:4907da2299a4 | 114 | // |
skydarc | 0:4907da2299a4 | 115 | #define CHARGE_TYPE 0x80 |
skydarc | 0:4907da2299a4 | 116 | #define RX_GROUP 0x40 |
skydarc | 0:4907da2299a4 | 117 | #define PROX_REV 0x20 |
skydarc | 0:4907da2299a4 | 118 | #define ALP_ENABLE 0x10 |
skydarc | 0:4907da2299a4 | 119 | // |
skydarc | 0:4907da2299a4 | 120 | //! IQS525RxToTx bit definitions |
skydarc | 0:4907da2299a4 | 121 | // |
skydarc | 0:4907da2299a4 | 122 | #define RX7_TX2 0x80 |
skydarc | 0:4907da2299a4 | 123 | #define RX6_TX3 0x40 |
skydarc | 0:4907da2299a4 | 124 | #define RX5_TX4 0x20 |
skydarc | 0:4907da2299a4 | 125 | #define RX4_TX5 0x10 |
skydarc | 0:4907da2299a4 | 126 | #define RX3_TX6 0x08 |
skydarc | 0:4907da2299a4 | 127 | #define RX2_TX7 0x04 |
skydarc | 0:4907da2299a4 | 128 | #define RX1_TX8 0x02 |
skydarc | 0:4907da2299a4 | 129 | #define RX0_TX9 0x01 |
skydarc | 0:4907da2299a4 | 130 | // |
skydarc | 0:4907da2299a4 | 131 | //! HardwareSettingsA bit definitions |
skydarc | 0:4907da2299a4 | 132 | // |
skydarc | 0:4907da2299a4 | 133 | #define ND_ENABLE 0x20 |
skydarc | 0:4907da2299a4 | 134 | #define RX_FLOAT 0x04 |
skydarc | 0:4907da2299a4 | 135 | // |
skydarc | 0:4907da2299a4 | 136 | //! HardwareSettingsB bit definitions |
skydarc | 0:4907da2299a4 | 137 | // |
skydarc | 0:4907da2299a4 | 138 | #define CK_FREQ_2 0x40 |
skydarc | 0:4907da2299a4 | 139 | #define CK_FREQ_1 0x20 |
skydarc | 0:4907da2299a4 | 140 | #define CK_FREQ_0 0x10 |
skydarc | 0:4907da2299a4 | 141 | #define ANA_DEAD_TIME 0x02 |
skydarc | 0:4907da2299a4 | 142 | #define INCR_PHASE 0x01 |
skydarc | 0:4907da2299a4 | 143 | // |
skydarc | 0:4907da2299a4 | 144 | //! HardwareSettingsC bit definitions |
skydarc | 0:4907da2299a4 | 145 | // |
skydarc | 0:4907da2299a4 | 146 | #define STAB_TIME_1 0x80 |
skydarc | 0:4907da2299a4 | 147 | #define STAB_TIME_0 0x40 |
skydarc | 0:4907da2299a4 | 148 | #define OPAMP_BIAS_1 0x20 |
skydarc | 0:4907da2299a4 | 149 | #define OPAMP_BIAS_0 0x10 |
skydarc | 0:4907da2299a4 | 150 | #define VTRIP_3 0x08 |
skydarc | 0:4907da2299a4 | 151 | #define VTRIP_2 0x04 |
skydarc | 0:4907da2299a4 | 152 | #define VTRIP_1 0x02 |
skydarc | 0:4907da2299a4 | 153 | #define VTRIP_0 0x01 |
skydarc | 0:4907da2299a4 | 154 | // |
skydarc | 0:4907da2299a4 | 155 | //! HardwareSettingsD bit definitions |
skydarc | 0:4907da2299a4 | 156 | // |
skydarc | 0:4907da2299a4 | 157 | #define UPLEN_2 0x40 |
skydarc | 0:4907da2299a4 | 158 | #define UPLEN_1 0x20 |
skydarc | 0:4907da2299a4 | 159 | #define UPLEN_0 0x10 |
skydarc | 0:4907da2299a4 | 160 | #define PASSLEN_2 0x04 |
skydarc | 0:4907da2299a4 | 161 | #define PASSLEN_1 0x02 |
skydarc | 0:4907da2299a4 | 162 | #define PASSLEN_0 0x01 |
skydarc | 0:4907da2299a4 | 163 | // |
skydarc | 0:4907da2299a4 | 164 | //! XYConfig0 bit definitions |
skydarc | 0:4907da2299a4 | 165 | // |
skydarc | 0:4907da2299a4 | 166 | #define PALM_REJECT 0x08 |
skydarc | 0:4907da2299a4 | 167 | #define SWITCH_XY_AXIS 0x04 |
skydarc | 0:4907da2299a4 | 168 | #define FLIP_Y 0x02 |
skydarc | 0:4907da2299a4 | 169 | #define FLIP_X 0x01 |
skydarc | 0:4907da2299a4 | 170 | // |
skydarc | 0:4907da2299a4 | 171 | //! SFGestureEnable bit definitions |
skydarc | 0:4907da2299a4 | 172 | // |
skydarc | 0:4907da2299a4 | 173 | #define SWIPE_Y_MINUS_EN 0x20 |
skydarc | 0:4907da2299a4 | 174 | #define SWIPE_Y_PLUS_EN 0x10 |
skydarc | 0:4907da2299a4 | 175 | #define SWIPE_X_PLUS_EN 0x08 |
skydarc | 0:4907da2299a4 | 176 | #define SWIPE_X_MINUS_EN 0x04 |
skydarc | 0:4907da2299a4 | 177 | #define TAP_AND_HOLD_EN 0x02 |
skydarc | 0:4907da2299a4 | 178 | #define SINGLE_TAP_EN 0x01 |
skydarc | 0:4907da2299a4 | 179 | // |
skydarc | 0:4907da2299a4 | 180 | //! MFGestureEnable bit definitions |
skydarc | 0:4907da2299a4 | 181 | // |
skydarc | 0:4907da2299a4 | 182 | #define ZOOM_EN 0x04 |
skydarc | 0:4907da2299a4 | 183 | #define SCROLL_EN 0x02 |
skydarc | 0:4907da2299a4 | 184 | #define TWO_FINGER_TAP_EN 0x01 |
skydarc | 0:4907da2299a4 | 185 | |
skydarc | 0:4907da2299a4 | 186 | //***************************************************************************** |
skydarc | 0:4907da2299a4 | 187 | // |
skydarc | 0:4907da2299a4 | 188 | //! ------------------ IQS5xx-B00 MEMORY MAP REGISTERS ------------------ |
skydarc | 0:4907da2299a4 | 189 | // |
skydarc | 0:4907da2299a4 | 190 | //***************************************************************************** |
skydarc | 0:4907da2299a4 | 191 | |
skydarc | 0:4907da2299a4 | 192 | /******************** DEVICE INFO REGISTERS ***************************/ |
skydarc | 0:4907da2299a4 | 193 | #define ProductNumber_adr 0x0000 //(READ) //2 BYTES; |
skydarc | 0:4907da2299a4 | 194 | #define ProjectNumber_adr 0x0002 //(READ) //2 BYTES; |
skydarc | 0:4907da2299a4 | 195 | #define MajorVersion_adr 0x0004 //(READ) |
skydarc | 0:4907da2299a4 | 196 | #define MinorVersion_adr 0x0005 //(READ) |
skydarc | 0:4907da2299a4 | 197 | #define BLStatus_adr 0x0006 //(READ) |
skydarc | 0:4907da2299a4 | 198 | /******************** ************************* ***************************/ |
skydarc | 0:4907da2299a4 | 199 | #define MaxTouch_adr 0x000B //(READ) |
skydarc | 0:4907da2299a4 | 200 | #define PrevCycleTime_adr 0x000C //(READ) |
skydarc | 0:4907da2299a4 | 201 | /******************** GESTURES AND EVENT STATUS REGISTERS ***************************/ |
skydarc | 0:4907da2299a4 | 202 | #define GestureEvents0_adr 0x000D //(READ) |
skydarc | 0:4907da2299a4 | 203 | #define GestureEvents1_adr 0x000E //(READ) |
skydarc | 0:4907da2299a4 | 204 | #define SystemInfo0_adr 0x000F //(READ) |
skydarc | 0:4907da2299a4 | 205 | #define SystemInfo1_adr 0x0010 //(READ) |
skydarc | 0:4907da2299a4 | 206 | /******************** XY DATA REGISTERS ***************************/ |
skydarc | 0:4907da2299a4 | 207 | #define NoOfFingers_adr 0x0011 //(READ) |
skydarc | 0:4907da2299a4 | 208 | #define RelativeX_adr 0x0012 //(READ) //2 BYTES; |
skydarc | 0:4907da2299a4 | 209 | #define RelativeY_adr 0x0014 //(READ) //2 BYTES; |
skydarc | 0:4907da2299a4 | 210 | /******************** INDIVIDUAL FINGER DATA ***************************/ |
skydarc | 0:4907da2299a4 | 211 | #define AbsoluteX_adr 0x0016 //(READ) 2 BYTES //ADD 0x0007 FOR FINGER 2; 0x000E FOR FINGER 3; 0x0015 FOR FINGER 4 AND 0x001C FOR FINGER 5 |
skydarc | 0:4907da2299a4 | 212 | #define AbsoluteY_adr 0x0018 //(READ) 2 BYTES //ADD 0x0007 FOR FINGER 2; 0x000E FOR FINGER 3; 0x0015 FOR FINGER 4 AND 0x001C FOR FINGER 5 |
skydarc | 0:4907da2299a4 | 213 | #define TouchStrength_adr 0x001A //(READ) 2 BYTES //ADD 0x0007 FOR FINGER 2; 0x000E FOR FINGER 3; 0x0015 FOR FINGER 4 AND 0x001C FOR FINGER 5 |
skydarc | 0:4907da2299a4 | 214 | #define Area_adr 0x001C //(READ) //ADD 0x0007 FOR FINGER 2; 0x000E FOR FINGER 3; 0x0015 FOR FINGER 4 AND 0x001C FOR FINGER 5 |
skydarc | 0:4907da2299a4 | 215 | /******************** CHANNEL STATUS REGISTERS ***************************/ |
skydarc | 0:4907da2299a4 | 216 | #define ProxStatus_adr 0x0039 //(READ) //32 BYTES; |
skydarc | 0:4907da2299a4 | 217 | #define TouchStatus_adr 0x0059 //(READ) //30 BYTES; |
skydarc | 0:4907da2299a4 | 218 | #define SnapStatus_adr 0x0077 //(READ) //30 BYTES; |
skydarc | 0:4907da2299a4 | 219 | /******************** DATA STREAMING REGISTERS ***************************/ |
skydarc | 0:4907da2299a4 | 220 | #define Counts_adr 0x0095 //(READ) //300 BYTES; |
skydarc | 0:4907da2299a4 | 221 | #define Delta_adr 0x01C1 //(READ) //300 BYTES; |
skydarc | 0:4907da2299a4 | 222 | #define ALPCount_adr 0x02ED //(READ) //2 BYTES; |
skydarc | 0:4907da2299a4 | 223 | #define ALPIndivCounts_adr 0x02EF //(READ) //20 BYTES; |
skydarc | 0:4907da2299a4 | 224 | #define References_adr 0x0303 //(READ/WRITE) //300 BYTES; |
skydarc | 0:4907da2299a4 | 225 | #define ALPLTA_adr 0x042F //(READ/WRITE) //2 BYTES; |
skydarc | 0:4907da2299a4 | 226 | /******************** SYSTEM CONTROL REGISTERS ***************************/ |
skydarc | 0:4907da2299a4 | 227 | #define SystemControl0_adr 0x0431 //(READ/WRITE) |
skydarc | 0:4907da2299a4 | 228 | #define SystemControl1_adr 0x0432 //(READ/WRITE) |
skydarc | 0:4907da2299a4 | 229 | /******************** ATI SETTINGS REGISTERS ***************************/ |
skydarc | 0:4907da2299a4 | 230 | #define ALPATIComp_adr 0x0435 //(READ/WRITE) //10 BYTES; |
skydarc | 0:4907da2299a4 | 231 | #define ATICompensation_adr 0x043F //(READ/WRITE) //150 BYTES; |
skydarc | 0:4907da2299a4 | 232 | #define ATICAdjust_adr 0x04D5 //(READ/WRITE/E2) //150 BYTES; |
skydarc | 0:4907da2299a4 | 233 | #define GlobalATIC_adr 0x056B //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 234 | #define ALPATIC_adr 0x056C //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 235 | #define ATITarget_adr 0x056D //(READ/WRITE/E2) //2 BYTES; |
skydarc | 0:4907da2299a4 | 236 | #define ALPATITarget_adr 0x056F //(READ/WRITE/E2) //2 BYTES; |
skydarc | 0:4907da2299a4 | 237 | #define RefDriftLimit_adr 0x0571 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 238 | #define ALPLTADriftLimit_adr 0x0572 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 239 | #define ReATILowerLimit_adr 0x0573 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 240 | #define ReATIUpperLimit_adr 0x0574 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 241 | #define MaxCountLimit_adr 0x0575 //(READ/WRITE/E2) //2 BYTES; |
skydarc | 0:4907da2299a4 | 242 | #define ReATIRetryTime_adr 0x0577 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 243 | /******************** TIMING SETTINGS REGISTERS ***************************/ |
skydarc | 0:4907da2299a4 | 244 | #define ActiveRR_adr 0x057A //(READ/WRITE/E2) //2 BYTES; |
skydarc | 0:4907da2299a4 | 245 | #define IdleTouchRR_adr 0x057C //(READ/WRITE/E2) //2 BYTES; |
skydarc | 0:4907da2299a4 | 246 | #define IdleRR_adr 0x057E //(READ/WRITE/E2) //2 BYTES; |
skydarc | 0:4907da2299a4 | 247 | #define LP1RR_adr 0x0580 //(READ/WRITE/E2) //2 BYTES; |
skydarc | 0:4907da2299a4 | 248 | #define LP2RR_adr 0x0582 //(READ/WRITE/E2) //2 BYTES; |
skydarc | 0:4907da2299a4 | 249 | #define ActiveTimeout_adr 0x0584 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 250 | #define IdleTouchTimeout_adr 0x0585 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 251 | #define IdleTimeout_adr 0x0586 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 252 | #define LP1Timeout_adr 0x0587 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 253 | #define RefUpdateTime_adr 0x0588 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 254 | #define SnapTimeout_adr 0x0589 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 255 | #define I2CTimeout_adr 0x058A //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 256 | /******************** SYSTEM CONFIG REGISTERS ***************************/ |
skydarc | 0:4907da2299a4 | 257 | #define SystemConfig0_adr 0x058E //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 258 | #define SystemConfig1_adr 0x058F //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 259 | /******************** THRESHOLD SETTINGS REGISTERS ***************************/ |
skydarc | 0:4907da2299a4 | 260 | #define SnapThreshold_adr 0x0592 //(READ/WRITE/E2) //2 BYTES; |
skydarc | 0:4907da2299a4 | 261 | #define ProxThreshold_adr 0x0594 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 262 | #define ALPProxThreshold_adr 0x0595 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 263 | #define GlobalTouchSet_adr 0x0596 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 264 | #define GlobalTouchClear_adr 0x0597 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 265 | #define IndivTouchAdjust_adr 0x0598 //(READ/WRITE/E2) //150 BYTES; |
skydarc | 0:4907da2299a4 | 266 | /******************** FILTER SETTINGS REGISTERS ***************************/ |
skydarc | 0:4907da2299a4 | 267 | #define FilterSettings0_adr 0x0632 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 268 | #define XYStaticBeta_adr 0x0633 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 269 | #define ALPCountBeta_adr 0x0634 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 270 | #define ALP1LTABeta_adr 0x0635 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 271 | #define ALP2LTABeta_adr 0x0636 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 272 | #define DynamicBottomBeta_adr 0x0637 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 273 | #define DynamicLowerSpeed_adr 0x0638 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 274 | #define DynamicUpperSpeed_adr 0x0639 //(READ/WRITE/E2) //2 BYTES; |
skydarc | 0:4907da2299a4 | 275 | /******************** CHANNEL SET UP (RX-TX MAPPING) REGISTERS ***************************/ |
skydarc | 0:4907da2299a4 | 276 | #define TotalRx_adr 0x063D //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 277 | #define TotalTx_adr 0x063E //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 278 | #define RxMapping_adr 0x063F //(READ/WRITE/E2) //10 BYTES; |
skydarc | 0:4907da2299a4 | 279 | #define TxMapping_adr 0x0649 //(READ/WRITE/E2) //15 BYTES; |
skydarc | 0:4907da2299a4 | 280 | #define ALPChannelSetup0_adr 0x0658 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 281 | #define ALPRxSelect_adr 0x0659 //(READ/WRITE/E2) //2 BYTES; |
skydarc | 0:4907da2299a4 | 282 | #define ALPTxSelect_adr 0x065B //(READ/WRITE/E2) //2 BYTES; |
skydarc | 0:4907da2299a4 | 283 | #define IQS525RxToTx_adr 0x065D //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 284 | /******************** HARDWARE SETTINGS REGISTERS ***************************/ |
skydarc | 0:4907da2299a4 | 285 | #define HardwareSettingsA_adr 0x065F //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 286 | #define HardwareSettingsB1_adr 0x0660 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 287 | #define HardwareSettingsB2_adr 0x0661 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 288 | #define HardwareSettingsC1_adr 0x0662 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 289 | #define HardwareSettingsC2_adr 0x0663 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 290 | #define HardwareSettingsD1_adr 0x0664 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 291 | #define HardwareSettingsD2_adr 0x0665 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 292 | /******************** XY CONFIG REGISTERS ***************************/ |
skydarc | 0:4907da2299a4 | 293 | #define XYConfig0_adr 0x0669 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 294 | #define MaxMultitouches_adr 0x066A //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 295 | #define FingerSplitFactor_adr 0x066B //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 296 | #define PalmRejectThreshold_adr 0x066C //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 297 | #define PalmRejectTimeout_adr 0x066D //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 298 | #define XResolution_adr 0x066E //(READ/WRITE/E2) //2 BYTES; |
skydarc | 0:4907da2299a4 | 299 | #define YResolution_adr 0x0670 //(READ/WRITE/E2) //2 BYTES; |
skydarc | 0:4907da2299a4 | 300 | #define StationaryTouchThr_adr 0x0672 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 301 | /*********************************************************************/ |
skydarc | 0:4907da2299a4 | 302 | #define DefaultReadAdr_adr 0x0675 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 303 | /******************** DEBOUNCE SETTING REGISTERS ***************************/ |
skydarc | 0:4907da2299a4 | 304 | #define ProxDb_adr 0x0679 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 305 | #define TouchSnapDb_adr 0x067A //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 306 | /******************** CHANNEL CONFIG REGISTERS ***************************/ |
skydarc | 0:4907da2299a4 | 307 | #define ActiveChannels_adr 0x067B //(READ/WRITE/E2) //30 BYTES; |
skydarc | 0:4907da2299a4 | 308 | #define SnapChannels_adr 0x0699 //(READ/WRITE/E2) //30 BYTES; |
skydarc | 0:4907da2299a4 | 309 | /******************** GESTURE SETTING REGISTERS ***************************/ |
skydarc | 0:4907da2299a4 | 310 | #define SFGestureEnable_adr 0x06B7 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 311 | #define MFGestureEnable_adr 0x06B8 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 312 | #define TapTime_adr 0x06B9 //(READ/WRITE/E2) //2 BYTES; |
skydarc | 0:4907da2299a4 | 313 | #define TapDistance_adr 0x06BB //(READ/WRITE/E2) //2 BYTES; |
skydarc | 0:4907da2299a4 | 314 | #define HoldTime_adr 0x06BD //(READ/WRITE/E2) //2 BYTES; |
skydarc | 0:4907da2299a4 | 315 | #define SwipeInitTime_adr 0x06BF //(READ/WRITE/E2) //2 BYTES; |
skydarc | 0:4907da2299a4 | 316 | #define SwipeInitDistance_adr 0x06C1 //(READ/WRITE/E2) //2 BYTES; |
skydarc | 0:4907da2299a4 | 317 | #define SwipeConsTime_adr 0x06C2 //(READ/WRITE/E2) //2 BYTES; |
skydarc | 0:4907da2299a4 | 318 | #define SwipeConsDistance_adr 0x06C5 //(READ/WRITE/E2) //2 BYTES; |
skydarc | 0:4907da2299a4 | 319 | #define SwipeAngle_adr 0x06C7 //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 320 | #define ScrollInitDistance_adr 0x06C8 //(READ/WRITE/E2) //2 BYTES; |
skydarc | 0:4907da2299a4 | 321 | #define ScrollAngle_adr 0x06CA //(READ/WRITE/E2) |
skydarc | 0:4907da2299a4 | 322 | #define ZoomInitDistance_adr 0x06CB //(READ/WRITE/E2) //2 BYTES; |
skydarc | 0:4907da2299a4 | 323 | #define ZoomConsDistance_adr 0x06CD //(READ/WRITE/E2) //2 BYTES; |
skydarc | 0:4907da2299a4 | 324 | |
skydarc | 0:4907da2299a4 | 325 | #endif |