/ Nucleo_BLE_BlueNRG

BLE UART example

Fork of Nucleo_BLE_BlueNRG by ST Americas mbed Team

hci/src/bluenrg_shield_bsp.c@0:a948f5f3904c, 2014-12-19 (annotated)

Committer:
sjallouli
Date:
Fri Dec 19 18:56:07 2014 +0000
Revision:
0:a948f5f3904c
Child:
1:be1cb4be316f
BLE_BlueNRG for Nucleo board

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sjallouli 0:a948f5f3904c 1 /**
sjallouli 0:a948f5f3904c 2 ******************************************************************************
sjallouli 0:a948f5f3904c 3 * File Name : bluenrg_shield_bsp.c
sjallouli 0:a948f5f3904c 4 * Date : 01/10/2014
sjallouli 0:a948f5f3904c 5 * Description : This file provides code for the BlueNRG Shield driver
sjallouli 0:a948f5f3904c 6 * based on mbed HAL.
sjallouli 0:a948f5f3904c 7 ******************************************************************************
sjallouli 0:a948f5f3904c 8 *
sjallouli 0:a948f5f3904c 9 * COPYRIGHT(c) 2014 STMicroelectronics
sjallouli 0:a948f5f3904c 10 *
sjallouli 0:a948f5f3904c 11 * Redistribution and use in source and binary forms, with or without modification,
sjallouli 0:a948f5f3904c 12 * are permitted provided that the following conditions are met:
sjallouli 0:a948f5f3904c 13 * 1. Redistributions of source code must retain the above copyright notice,
sjallouli 0:a948f5f3904c 14 * this list of conditions and the following disclaimer.
sjallouli 0:a948f5f3904c 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
sjallouli 0:a948f5f3904c 16 * this list of conditions and the following disclaimer in the documentation
sjallouli 0:a948f5f3904c 17 * and/or other materials provided with the distribution.
sjallouli 0:a948f5f3904c 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
sjallouli 0:a948f5f3904c 19 * may be used to endorse or promote products derived from this software
sjallouli 0:a948f5f3904c 20 * without specific prior written permission.
sjallouli 0:a948f5f3904c 21 *
sjallouli 0:a948f5f3904c 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
sjallouli 0:a948f5f3904c 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
sjallouli 0:a948f5f3904c 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
sjallouli 0:a948f5f3904c 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
sjallouli 0:a948f5f3904c 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
sjallouli 0:a948f5f3904c 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
sjallouli 0:a948f5f3904c 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
sjallouli 0:a948f5f3904c 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
sjallouli 0:a948f5f3904c 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
sjallouli 0:a948f5f3904c 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
sjallouli 0:a948f5f3904c 32 *
sjallouli 0:a948f5f3904c 33 ******************************************************************************
sjallouli 0:a948f5f3904c 34 */
sjallouli 0:a948f5f3904c 35 /* Includes ------------------------------------------------------------------*/
sjallouli 0:a948f5f3904c 36
sjallouli 0:a948f5f3904c 37 #include "hci.h"
sjallouli 0:a948f5f3904c 38 #include "spi_api.h"
sjallouli 0:a948f5f3904c 39 #include "gpio_irq_api.h"
sjallouli 0:a948f5f3904c 40 #include "gpio_api.h"
sjallouli 0:a948f5f3904c 41 #include "wait_api.h"
sjallouli 0:a948f5f3904c 42 #include "pinmap.h"
sjallouli 0:a948f5f3904c 43 #include "bluenrg_shield_bsp.h"
sjallouli 0:a948f5f3904c 44
sjallouli 0:a948f5f3904c 45 spi_t __spi;
sjallouli 0:a948f5f3904c 46 gpio_irq_t irq_exti;
sjallouli 0:a948f5f3904c 47 gpio_t gpio_pin_A0, gpio_pin_CS, gpio_pin_MOSI, gpio_pin_MISO, gpio_pin_SCLK, gpio_pin_RESET;
sjallouli 0:a948f5f3904c 48 void EXTI_irq_handler(uint32_t id, gpio_irq_event event);
sjallouli 0:a948f5f3904c 49
sjallouli 0:a948f5f3904c 50 /** @addtogroup BlueNRG_Shield
sjallouli 0:a948f5f3904c 51 * @{
sjallouli 0:a948f5f3904c 52 */
sjallouli 0:a948f5f3904c 53
sjallouli 0:a948f5f3904c 54 /** @defgroup BlueNRG_Shield_Driver
sjallouli 0:a948f5f3904c 55 * @brief BlueNRG Shield driver based on mbed HAL
sjallouli 0:a948f5f3904c 56 * @{
sjallouli 0:a948f5f3904c 57 */
sjallouli 0:a948f5f3904c 58
sjallouli 0:a948f5f3904c 59
sjallouli 0:a948f5f3904c 60 /*
sjallouli 0:a948f5f3904c 61 * mbed EXTI IRQ Handler
sjallouli 0:a948f5f3904c 62 *
sjallouli 0:a948f5f3904c 63 */
sjallouli 0:a948f5f3904c 64 void EXTI_irq_handler(uint32_t id, gpio_irq_event event)
sjallouli 0:a948f5f3904c 65 {
sjallouli 0:a948f5f3904c 66 tHciDataPacket * hciReadPacket = NULL;
sjallouli 0:a948f5f3904c 67 uint8_t data_len;
sjallouli 0:a948f5f3904c 68
sjallouli 0:a948f5f3904c 69 //Check id of the IRQ
sjallouli 0:a948f5f3904c 70 if(id == (uint32_t)BNRG_SPI_INSTANCE) {
sjallouli 0:a948f5f3904c 71
sjallouli 0:a948f5f3904c 72 while (gpio_read(&gpio_pin_A0) == 1) {
sjallouli 0:a948f5f3904c 73 if (list_is_empty (&hciReadPktPool) == FALSE){
sjallouli 0:a948f5f3904c 74 /* enqueueing a packet for read */
sjallouli 0:a948f5f3904c 75 list_remove_head (&hciReadPktPool, (tListNode **)&hciReadPacket);
sjallouli 0:a948f5f3904c 76 data_len = BlueNRG_SPI_Read_All(hciReadPacket->dataBuff, HCI_PACKET_SIZE);
sjallouli 0:a948f5f3904c 77
sjallouli 0:a948f5f3904c 78 if(data_len > 0){
sjallouli 0:a948f5f3904c 79 /* Packet will be inserted to the correct queue */
sjallouli 0:a948f5f3904c 80 HCI_Input(hciReadPacket);
sjallouli 0:a948f5f3904c 81 } else {
sjallouli 0:a948f5f3904c 82 /* Insert the packet back into the pool */
sjallouli 0:a948f5f3904c 83 list_insert_head(&hciReadPktPool, (tListNode *)hciReadPacket);
sjallouli 0:a948f5f3904c 84 }
sjallouli 0:a948f5f3904c 85
sjallouli 0:a948f5f3904c 86 } else{
sjallouli 0:a948f5f3904c 87 /* TODO: HCI Read Packet Pool is empty, wait for a free packet */
sjallouli 0:a948f5f3904c 88 }
sjallouli 0:a948f5f3904c 89
sjallouli 0:a948f5f3904c 90 }
sjallouli 0:a948f5f3904c 91 }
sjallouli 0:a948f5f3904c 92 }
sjallouli 0:a948f5f3904c 93
sjallouli 0:a948f5f3904c 94 /**
sjallouli 0:a948f5f3904c 95 * @brief This function is used to initialize the SPI communication with
sjallouli 0:a948f5f3904c 96 * the BlueNRG Shield. All params should come from the User
sjallouli 0:a948f5f3904c 97 * @param SPI_MOSI : PA_7 (Nucleo), D11 (Generic Arduino Pin)
sjallouli 0:a948f5f3904c 98 * @param SPI_MISO : PA_6, D12
sjallouli 0:a948f5f3904c 99 * @param SPI_SCLK : PB_3, D3
sjallouli 0:a948f5f3904c 100 * @param SPI_CS : PA_1, A1
sjallouli 0:a948f5f3904c 101 * @param EXTI_IRQ : PA_0, A0
sjallouli 0:a948f5f3904c 102 * @param BlueNRG_RESET : PA_8, D7
sjallouli 0:a948f5f3904c 103 * @retval None
sjallouli 0:a948f5f3904c 104 */
sjallouli 0:a948f5f3904c 105 void BNRG_SPI_Init(void)
sjallouli 0:a948f5f3904c 106 {
sjallouli 0:a948f5f3904c 107 int ret;
sjallouli 0:a948f5f3904c 108 spi_init(&__spi, D11, D12, D3, NC);
sjallouli 0:a948f5f3904c 109 //spi_format(&__spi, 8, 0, 0);
sjallouli 0:a948f5f3904c 110 //spi_frequency(&__spi, 1000000);
sjallouli 0:a948f5f3904c 111
sjallouli 0:a948f5f3904c 112 /*Init IRQ for EXTI Interrupt*/
sjallouli 0:a948f5f3904c 113 //gpio_init(&gpio_pin_A0, A0);//PA_0 in Nucleo
sjallouli 0:a948f5f3904c 114 ret = gpio_irq_init(&irq_exti, A0, EXTI_irq_handler,(uint32_t)BNRG_SPI_INSTANCE);
sjallouli 0:a948f5f3904c 115 gpio_irq_set(&irq_exti, IRQ_RISE, 1);//Set mode to IRQ_RISE
sjallouli 0:a948f5f3904c 116 gpio_init_in(&gpio_pin_A0, A0);//PA_0 in Nucleo//Configure the GPIO Pin as Input pin and PullDefault
sjallouli 0:a948f5f3904c 117 //gpio_irq_enable(&irq_exti);//IRQ already enabled in IRQ init call above.
sjallouli 0:a948f5f3904c 118
sjallouli 0:a948f5f3904c 119 /* Reset Pin Config */
sjallouli 0:a948f5f3904c 120 gpio_init(&gpio_pin_RESET, D7);//PA_8 in Nucleo
sjallouli 0:a948f5f3904c 121 gpio_mode(&gpio_pin_RESET, PullNone);
sjallouli 0:a948f5f3904c 122 gpio_dir(&gpio_pin_RESET, PIN_OUTPUT);
sjallouli 0:a948f5f3904c 123 gpio_write(&gpio_pin_RESET, 1);
sjallouli 0:a948f5f3904c 124
sjallouli 0:a948f5f3904c 125 /* SCLK - PA_5 - Not needed to configure if correct PinName is given to spi_init, in this case PB_3 for L0*/
sjallouli 0:a948f5f3904c 126 /*gpio_init(&gpio_pin_SCLK, PB_3); //PA_5 is not USED????!!!! Since configuring PA_5 does not work!
sjallouli 0:a948f5f3904c 127 gpio_mode(&gpio_pin_SCLK, PullUp);
sjallouli 0:a948f5f3904c 128 //gpio_dir(&gpio_pin_SCLK, PIN_INPUT); //just 2 options of PIN_INPUT and PIN_OUTPUT does not suffice to configure Pin.
sjallouli 0:a948f5f3904c 129 pin_function(PB_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, 0));*/
sjallouli 0:a948f5f3904c 130
sjallouli 0:a948f5f3904c 131 /* NSS/CSN/CS - PA_1*/
sjallouli 0:a948f5f3904c 132 gpio_init(&gpio_pin_CS, A1);//PA_1 in Nucleo
sjallouli 0:a948f5f3904c 133 gpio_mode(&gpio_pin_CS, PullNone);
sjallouli 0:a948f5f3904c 134 gpio_dir(&gpio_pin_CS, PIN_OUTPUT);
sjallouli 0:a948f5f3904c 135 gpio_write(&gpio_pin_CS, 1);
sjallouli 0:a948f5f3904c 136
sjallouli 0:a948f5f3904c 137 }
sjallouli 0:a948f5f3904c 138
sjallouli 0:a948f5f3904c 139 /**
sjallouli 0:a948f5f3904c 140 * @brief Read from BlueNRG SPI buffer and store data into local buffer
sjallouli 0:a948f5f3904c 141 * @param buffer: buffer where data from SPI are stored
sjallouli 0:a948f5f3904c 142 * @param buff_size: buffer size
sjallouli 0:a948f5f3904c 143 * @retval number of read bytes
sjallouli 0:a948f5f3904c 144 */
sjallouli 0:a948f5f3904c 145 int32_t BlueNRG_SPI_Read_All(uint8_t *buffer, uint8_t buff_size)
sjallouli 0:a948f5f3904c 146 {
sjallouli 0:a948f5f3904c 147 uint16_t byte_count;
sjallouli 0:a948f5f3904c 148 uint8_t len = 0;
sjallouli 0:a948f5f3904c 149 uint8_t i = 0;
sjallouli 0:a948f5f3904c 150 uint8_t char_ff = 0xff;
sjallouli 0:a948f5f3904c 151 volatile uint8_t read_char, tmpreg;
sjallouli 0:a948f5f3904c 152
sjallouli 0:a948f5f3904c 153 uint8_t header_master[5] = {0x0b, 0x00, 0x00, 0x00, 0x00};
sjallouli 0:a948f5f3904c 154 uint8_t header_slave[5];
sjallouli 0:a948f5f3904c 155
sjallouli 0:a948f5f3904c 156 /* CS reset */
sjallouli 0:a948f5f3904c 157 gpio_write(&gpio_pin_CS, 0);
sjallouli 0:a948f5f3904c 158
sjallouli 0:a948f5f3904c 159 /* Read the header */
sjallouli 0:a948f5f3904c 160 for (i = 0; i < 5; i++)
sjallouli 0:a948f5f3904c 161 {
sjallouli 0:a948f5f3904c 162 tmpreg = spi_master_write(&__spi, header_master[i]);
sjallouli 0:a948f5f3904c 163 header_slave[i] = (uint8_t)(tmpreg);
sjallouli 0:a948f5f3904c 164 }
sjallouli 0:a948f5f3904c 165
sjallouli 0:a948f5f3904c 166
sjallouli 0:a948f5f3904c 167 if (header_slave[0] == 0x02) {
sjallouli 0:a948f5f3904c 168 /* device is ready */
sjallouli 0:a948f5f3904c 169 byte_count = (header_slave[4]<<8)|header_slave[3];
sjallouli 0:a948f5f3904c 170
sjallouli 0:a948f5f3904c 171 if (byte_count > 0) {
sjallouli 0:a948f5f3904c 172 /* avoid to read more data that size of the buffer */
sjallouli 0:a948f5f3904c 173 if (byte_count > buff_size){
sjallouli 0:a948f5f3904c 174 byte_count = buff_size;
sjallouli 0:a948f5f3904c 175 }
sjallouli 0:a948f5f3904c 176
sjallouli 0:a948f5f3904c 177 for (len = 0; len < byte_count; len++){
sjallouli 0:a948f5f3904c 178 read_char = spi_master_write(&__spi, char_ff);
sjallouli 0:a948f5f3904c 179 buffer[len] = read_char;
sjallouli 0:a948f5f3904c 180 }
sjallouli 0:a948f5f3904c 181 }
sjallouli 0:a948f5f3904c 182 }
sjallouli 0:a948f5f3904c 183 /* Release CS line */
sjallouli 0:a948f5f3904c 184 gpio_write(&gpio_pin_CS, 1);
sjallouli 0:a948f5f3904c 185
sjallouli 0:a948f5f3904c 186 return len;
sjallouli 0:a948f5f3904c 187 }
sjallouli 0:a948f5f3904c 188
sjallouli 0:a948f5f3904c 189 /**
sjallouli 0:a948f5f3904c 190 * @brief Write data from local buffer to SPI
sjallouli 0:a948f5f3904c 191 * @param data1: first data buffer to be written
sjallouli 0:a948f5f3904c 192 * @param data2: second data buffer to be written
sjallouli 0:a948f5f3904c 193 * @param Nb_bytes1: size of first data buffer to be written
sjallouli 0:a948f5f3904c 194 * @param Nb_bytes2: size of second data buffer to be written
sjallouli 0:a948f5f3904c 195 * @retval number of read bytes
sjallouli 0:a948f5f3904c 196 */
sjallouli 0:a948f5f3904c 197 int32_t BlueNRG_SPI_Write(uint8_t* data1, uint8_t* data2, uint8_t Nb_bytes1, uint8_t Nb_bytes2)
sjallouli 0:a948f5f3904c 198 {
sjallouli 0:a948f5f3904c 199 uint32_t i;
sjallouli 0:a948f5f3904c 200 volatile uint8_t read_char;
sjallouli 0:a948f5f3904c 201 int32_t result = 0;
sjallouli 0:a948f5f3904c 202 volatile uint8_t tmpreg;
sjallouli 0:a948f5f3904c 203
sjallouli 0:a948f5f3904c 204 unsigned char header_master[5] = {0x0a, 0x00, 0x00, 0x00, 0x00};
sjallouli 0:a948f5f3904c 205 unsigned char header_slave[5] = {0xaa, 0x00, 0x00, 0x00, 0x00};
sjallouli 0:a948f5f3904c 206
sjallouli 0:a948f5f3904c 207 Disable_SPI_IRQ();
sjallouli 0:a948f5f3904c 208
sjallouli 0:a948f5f3904c 209 /* CS reset */
sjallouli 0:a948f5f3904c 210 gpio_write(&gpio_pin_CS, 0);
sjallouli 0:a948f5f3904c 211
sjallouli 0:a948f5f3904c 212 /* Exchange header */
sjallouli 0:a948f5f3904c 213 for (i = 0; i < 5; i++)
sjallouli 0:a948f5f3904c 214 {
sjallouli 0:a948f5f3904c 215 tmpreg = spi_master_write(&__spi, header_master[i]);
sjallouli 0:a948f5f3904c 216 header_slave[i] = tmpreg;
sjallouli 0:a948f5f3904c 217 }
sjallouli 0:a948f5f3904c 218
sjallouli 0:a948f5f3904c 219 if (header_slave[0] == 0x02) {
sjallouli 0:a948f5f3904c 220 /* SPI is ready */
sjallouli 0:a948f5f3904c 221 if (header_slave[1] >= (Nb_bytes1+Nb_bytes2)) {
sjallouli 0:a948f5f3904c 222 /* Buffer is big enough */
sjallouli 0:a948f5f3904c 223 for (i = 0; i < Nb_bytes1; i++) {
sjallouli 0:a948f5f3904c 224 read_char = spi_master_write(&__spi, *(data1 + i));
sjallouli 0:a948f5f3904c 225 }
sjallouli 0:a948f5f3904c 226 for (i = 0; i < Nb_bytes2; i++) {
sjallouli 0:a948f5f3904c 227 read_char = spi_master_write(&__spi, *(data2 + i));
sjallouli 0:a948f5f3904c 228 }
sjallouli 0:a948f5f3904c 229 } else {
sjallouli 0:a948f5f3904c 230 /* Buffer is too small */
sjallouli 0:a948f5f3904c 231 result = -2;
sjallouli 0:a948f5f3904c 232 }
sjallouli 0:a948f5f3904c 233 } else {
sjallouli 0:a948f5f3904c 234 /* SPI is not ready */
sjallouli 0:a948f5f3904c 235 result = -1;
sjallouli 0:a948f5f3904c 236 }
sjallouli 0:a948f5f3904c 237
sjallouli 0:a948f5f3904c 238 /* Release CS line */
sjallouli 0:a948f5f3904c 239 gpio_write(&gpio_pin_CS, 1);
sjallouli 0:a948f5f3904c 240
sjallouli 0:a948f5f3904c 241 Enable_SPI_IRQ();
sjallouli 0:a948f5f3904c 242
sjallouli 0:a948f5f3904c 243 return result;
sjallouli 0:a948f5f3904c 244 }
sjallouli 0:a948f5f3904c 245
sjallouli 0:a948f5f3904c 246 /**
sjallouli 0:a948f5f3904c 247 * Writes data to a serial interface. *
sjallouli 0:a948f5f3904c 248 * @param data1 1st buffer
sjallouli 0:a948f5f3904c 249 * @param data2 2nd buffer
sjallouli 0:a948f5f3904c 250 * @param n_bytes1 number of bytes in 1st buffer
sjallouli 0:a948f5f3904c 251 * @param n_bytes2 number of bytes in 2nd buffer
sjallouli 0:a948f5f3904c 252 */
sjallouli 0:a948f5f3904c 253 void Hal_Write_Serial(const void* data1, const void* data2, int32_t n_bytes1, int32_t n_bytes2)
sjallouli 0:a948f5f3904c 254 {
sjallouli 0:a948f5f3904c 255 struct timer t;
sjallouli 0:a948f5f3904c 256
sjallouli 0:a948f5f3904c 257 Timer_Set(&t, CLOCK_SECOND/10);
sjallouli 0:a948f5f3904c 258
sjallouli 0:a948f5f3904c 259 while(1){
sjallouli 0:a948f5f3904c 260 if(BlueNRG_SPI_Write((uint8_t *)data1,(uint8_t *)data2, n_bytes1, n_bytes2)==0) break;
sjallouli 0:a948f5f3904c 261 if(Timer_Expired(&t)){
sjallouli 0:a948f5f3904c 262 break;
sjallouli 0:a948f5f3904c 263 }
sjallouli 0:a948f5f3904c 264 }
sjallouli 0:a948f5f3904c 265 }
sjallouli 0:a948f5f3904c 266
sjallouli 0:a948f5f3904c 267 /**
sjallouli 0:a948f5f3904c 268 * @brief Disable SPI IRQ
sjallouli 0:a948f5f3904c 269 * @param None
sjallouli 0:a948f5f3904c 270 * @retval None
sjallouli 0:a948f5f3904c 271 */
sjallouli 0:a948f5f3904c 272 void Disable_SPI_IRQ(void)
sjallouli 0:a948f5f3904c 273 {
sjallouli 0:a948f5f3904c 274 gpio_irq_disable(&irq_exti);
sjallouli 0:a948f5f3904c 275 }
sjallouli 0:a948f5f3904c 276
sjallouli 0:a948f5f3904c 277 /**
sjallouli 0:a948f5f3904c 278 * @brief Enable SPI IRQ
sjallouli 0:a948f5f3904c 279 * @param None
sjallouli 0:a948f5f3904c 280 * @retval None
sjallouli 0:a948f5f3904c 281 */
sjallouli 0:a948f5f3904c 282 void Enable_SPI_IRQ(void)
sjallouli 0:a948f5f3904c 283 {
sjallouli 0:a948f5f3904c 284 gpio_irq_enable(&irq_exti);
sjallouli 0:a948f5f3904c 285 }
sjallouli 0:a948f5f3904c 286
sjallouli 0:a948f5f3904c 287 /**
sjallouli 0:a948f5f3904c 288 * @brief Clear Pending SPI IRQ
sjallouli 0:a948f5f3904c 289 * @param None
sjallouli 0:a948f5f3904c 290 * @retval None
sjallouli 0:a948f5f3904c 291 */
sjallouli 0:a948f5f3904c 292 void Clear_SPI_IRQ(void)
sjallouli 0:a948f5f3904c 293 {
sjallouli 0:a948f5f3904c 294 //Not Used
sjallouli 0:a948f5f3904c 295 }
sjallouli 0:a948f5f3904c 296
sjallouli 0:a948f5f3904c 297 /**
sjallouli 0:a948f5f3904c 298 * @brief Clear EXTI (External Interrupt) line for SPI IRQ
sjallouli 0:a948f5f3904c 299 * @param None
sjallouli 0:a948f5f3904c 300 * @retval None
sjallouli 0:a948f5f3904c 301 */
sjallouli 0:a948f5f3904c 302 void Clear_SPI_EXTI_Flag(void)
sjallouli 0:a948f5f3904c 303 {
sjallouli 0:a948f5f3904c 304 //Not Used
sjallouli 0:a948f5f3904c 305 }
sjallouli 0:a948f5f3904c 306
sjallouli 0:a948f5f3904c 307 /**
sjallouli 0:a948f5f3904c 308 * @brief Reset the BlueNRG
sjallouli 0:a948f5f3904c 309 * @param None
sjallouli 0:a948f5f3904c 310 * @retval None
sjallouli 0:a948f5f3904c 311 */
sjallouli 0:a948f5f3904c 312 void BlueNRG_RST(void)
sjallouli 0:a948f5f3904c 313 {
sjallouli 0:a948f5f3904c 314 gpio_write(&gpio_pin_RESET, 0);
sjallouli 0:a948f5f3904c 315 wait_us(5);
sjallouli 0:a948f5f3904c 316 gpio_write(&gpio_pin_RESET, 1);
sjallouli 0:a948f5f3904c 317 wait_us(5);
sjallouli 0:a948f5f3904c 318 }
sjallouli 0:a948f5f3904c 319
sjallouli 0:a948f5f3904c 320 /**
sjallouli 0:a948f5f3904c 321 * @}
sjallouli 0:a948f5f3904c 322 */
sjallouli 0:a948f5f3904c 323
sjallouli 0:a948f5f3904c 324 /**
sjallouli 0:a948f5f3904c 325 * @}
sjallouli 0:a948f5f3904c 326 */
sjallouli 0:a948f5f3904c 327
sjallouli 0:a948f5f3904c 328 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/