siva surendar / mbed-dev

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targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/TOOLCHAIN_ARM_STD/startup_stm32l011xx.S@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/TOOLCHAIN_ARM_STD/startup_stm32l011xx.S@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
<> 144:ef7eb2e8f9f7 2 ;* File Name : startup_stm32l011xx.s
<> 144:ef7eb2e8f9f7 3 ;* Author : MCD Application Team
<> 144:ef7eb2e8f9f7 4 ;* Version : V1.5.0
<> 144:ef7eb2e8f9f7 5 ;* Date : 8-January-2016
<> 144:ef7eb2e8f9f7 6 ;* Description : STM32l011xx Devices vector table for MDK-ARM toolchain.
<> 144:ef7eb2e8f9f7 7 ;* This module performs:
<> 144:ef7eb2e8f9f7 8 ;* - Set the initial SP
<> 144:ef7eb2e8f9f7 9 ;* - Set the initial PC == Reset_Handler
<> 144:ef7eb2e8f9f7 10 ;* - Set the vector table entries with the exceptions ISR address
<> 144:ef7eb2e8f9f7 11 ;* - Branches to __main in the C library (which eventually
<> 144:ef7eb2e8f9f7 12 ;* calls main()).
<> 144:ef7eb2e8f9f7 13 ;* After Reset the Cortex-M0+ processor is in Thread mode,
<> 144:ef7eb2e8f9f7 14 ;* priority is Privileged, and the Stack is set to Main.
<> 144:ef7eb2e8f9f7 15 ;* <<< Use Configuration Wizard in Context Menu >>>
<> 144:ef7eb2e8f9f7 16 ;*******************************************************************************
<> 144:ef7eb2e8f9f7 17 ;*
<> 144:ef7eb2e8f9f7 18 ;* Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 19 ;* are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 20 ;* 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 21 ;* this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 22 ;* 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 23 ;* this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 24 ;* and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 25 ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 26 ;* may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 27 ;* without specific prior written permission.
<> 144:ef7eb2e8f9f7 28 ;*
<> 144:ef7eb2e8f9f7 29 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 30 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 31 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 32 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 33 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 34 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 35 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 36 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 37 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 38 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 39 ;*
<> 144:ef7eb2e8f9f7 40 ;*******************************************************************************
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 __initial_sp EQU 0x20000800 ; Top of RAM
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 PRESERVE8
<> 144:ef7eb2e8f9f7 45 THUMB
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 ; Vector Table Mapped to Address 0 at Reset
<> 144:ef7eb2e8f9f7 49 AREA RESET, DATA, READONLY
<> 144:ef7eb2e8f9f7 50 EXPORT __Vectors
<> 144:ef7eb2e8f9f7 51 EXPORT __Vectors_End
<> 144:ef7eb2e8f9f7 52 EXPORT __Vectors_Size
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 __Vectors DCD __initial_sp ; Top of Stack
<> 144:ef7eb2e8f9f7 55 DCD Reset_Handler ; Reset Handler
<> 144:ef7eb2e8f9f7 56 DCD NMI_Handler ; NMI Handler
<> 144:ef7eb2e8f9f7 57 DCD HardFault_Handler ; Hard Fault Handler
<> 144:ef7eb2e8f9f7 58 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 59 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 60 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 61 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 62 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 63 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 64 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 65 DCD SVC_Handler ; SVCall Handler
<> 144:ef7eb2e8f9f7 66 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 67 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 68 DCD PendSV_Handler ; PendSV Handler
<> 144:ef7eb2e8f9f7 69 DCD SysTick_Handler ; SysTick Handler
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 ; External Interrupts
<> 144:ef7eb2e8f9f7 72 DCD WWDG_IRQHandler ; Window Watchdog
<> 144:ef7eb2e8f9f7 73 DCD PVD_IRQHandler ; PVD through EXTI Line detect
<> 144:ef7eb2e8f9f7 74 DCD RTC_IRQHandler ; RTC through EXTI Line
<> 144:ef7eb2e8f9f7 75 DCD FLASH_IRQHandler ; FLASH
<> 144:ef7eb2e8f9f7 76 DCD RCC_IRQHandler ; RCC
<> 144:ef7eb2e8f9f7 77 DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
<> 144:ef7eb2e8f9f7 78 DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
<> 144:ef7eb2e8f9f7 79 DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
<> 144:ef7eb2e8f9f7 80 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 81 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
<> 144:ef7eb2e8f9f7 82 DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
<> 144:ef7eb2e8f9f7 83 DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
<> 144:ef7eb2e8f9f7 84 DCD ADC1_COMP_IRQHandler ; ADC1, COMP1
<> 144:ef7eb2e8f9f7 85 DCD LPTIM1_IRQHandler ; LPTIM1
<> 144:ef7eb2e8f9f7 86 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 87 DCD TIM2_IRQHandler ; TIM2
<> 144:ef7eb2e8f9f7 88 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 89 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 90 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 91 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 92 DCD TIM21_IRQHandler ; TIM21
<> 144:ef7eb2e8f9f7 93 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 94 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 95 DCD I2C1_IRQHandler ; I2C1
<> 144:ef7eb2e8f9f7 96 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 97 DCD SPI1_IRQHandler ; SPI1
<> 144:ef7eb2e8f9f7 98 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 99 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 100 DCD USART2_IRQHandler ; USART2
<> 144:ef7eb2e8f9f7 101 DCD LPUART1_IRQHandler ; LPUART1
<> 144:ef7eb2e8f9f7 102 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 103 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 __Vectors_End
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 __Vectors_Size EQU __Vectors_End - __Vectors
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 AREA |.text|, CODE, READONLY
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 ; Reset handler routine
<> 144:ef7eb2e8f9f7 112 Reset_Handler PROC
<> 144:ef7eb2e8f9f7 113 EXPORT Reset_Handler [WEAK]
<> 144:ef7eb2e8f9f7 114 IMPORT __main
<> 144:ef7eb2e8f9f7 115 IMPORT SystemInit
<> 144:ef7eb2e8f9f7 116 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 117 BLX R0
<> 144:ef7eb2e8f9f7 118 LDR R0, =__main
<> 144:ef7eb2e8f9f7 119 BX R0
<> 144:ef7eb2e8f9f7 120 ENDP
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 ; Dummy Exception Handlers (infinite loops which can be modified)
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 NMI_Handler PROC
<> 144:ef7eb2e8f9f7 125 EXPORT NMI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 126 B .
<> 144:ef7eb2e8f9f7 127 ENDP
<> 144:ef7eb2e8f9f7 128 HardFault_Handler\
<> 144:ef7eb2e8f9f7 129 PROC
<> 144:ef7eb2e8f9f7 130 EXPORT HardFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 131 B .
<> 144:ef7eb2e8f9f7 132 ENDP
<> 144:ef7eb2e8f9f7 133 SVC_Handler PROC
<> 144:ef7eb2e8f9f7 134 EXPORT SVC_Handler [WEAK]
<> 144:ef7eb2e8f9f7 135 B .
<> 144:ef7eb2e8f9f7 136 ENDP
<> 144:ef7eb2e8f9f7 137 PendSV_Handler PROC
<> 144:ef7eb2e8f9f7 138 EXPORT PendSV_Handler [WEAK]
<> 144:ef7eb2e8f9f7 139 B .
<> 144:ef7eb2e8f9f7 140 ENDP
<> 144:ef7eb2e8f9f7 141 SysTick_Handler PROC
<> 144:ef7eb2e8f9f7 142 EXPORT SysTick_Handler [WEAK]
<> 144:ef7eb2e8f9f7 143 B .
<> 144:ef7eb2e8f9f7 144 ENDP
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 Default_Handler PROC
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 EXPORT WWDG_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 149 EXPORT PVD_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 150 EXPORT RTC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 151 EXPORT FLASH_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 152 EXPORT RCC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 153 EXPORT EXTI0_1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 154 EXPORT EXTI2_3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 155 EXPORT EXTI4_15_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 156 EXPORT DMA1_Channel1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 157 EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 158 EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 159 EXPORT ADC1_COMP_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 160 EXPORT LPTIM1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 161 EXPORT TIM2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 162 EXPORT TIM21_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 163 EXPORT I2C1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 164 EXPORT SPI1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 165 EXPORT USART2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 166 EXPORT LPUART1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 WWDG_IRQHandler
<> 144:ef7eb2e8f9f7 169 PVD_IRQHandler
<> 144:ef7eb2e8f9f7 170 RTC_IRQHandler
<> 144:ef7eb2e8f9f7 171 FLASH_IRQHandler
<> 144:ef7eb2e8f9f7 172 RCC_IRQHandler
<> 144:ef7eb2e8f9f7 173 EXTI0_1_IRQHandler
<> 144:ef7eb2e8f9f7 174 EXTI2_3_IRQHandler
<> 144:ef7eb2e8f9f7 175 EXTI4_15_IRQHandler
<> 144:ef7eb2e8f9f7 176 DMA1_Channel1_IRQHandler
<> 144:ef7eb2e8f9f7 177 DMA1_Channel2_3_IRQHandler
<> 144:ef7eb2e8f9f7 178 DMA1_Channel4_5_6_7_IRQHandler
<> 144:ef7eb2e8f9f7 179 ADC1_COMP_IRQHandler
<> 144:ef7eb2e8f9f7 180 LPTIM1_IRQHandler
<> 144:ef7eb2e8f9f7 181 TIM2_IRQHandler
<> 144:ef7eb2e8f9f7 182 TIM21_IRQHandler
<> 144:ef7eb2e8f9f7 183 I2C1_IRQHandler
<> 144:ef7eb2e8f9f7 184 SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 185 USART2_IRQHandler
<> 144:ef7eb2e8f9f7 186 LPUART1_IRQHandler
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 B .
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 ENDP
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 ALIGN
<> 144:ef7eb2e8f9f7 193 END
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****