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targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_pwr_ex.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_hal_pwr_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.1
<> 144:ef7eb2e8f9f7 6 * @date 31-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief Extended PWR HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Power Controller (PWR) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Extended Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 ******************************************************************************
<> 144:ef7eb2e8f9f7 14 * @attention
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 17 *
<> 144:ef7eb2e8f9f7 18 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 19 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 20 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 21 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 22 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 23 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 24 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 26 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 27 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 28 *
<> 144:ef7eb2e8f9f7 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 32 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 39 *
<> 144:ef7eb2e8f9f7 40 ******************************************************************************
<> 144:ef7eb2e8f9f7 41 */
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 44 #include "stm32l4xx_hal.h"
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /** @addtogroup STM32L4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 47 * @{
<> 144:ef7eb2e8f9f7 48 */
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /** @defgroup PWREx PWREx
<> 144:ef7eb2e8f9f7 51 * @brief PWR Extended HAL module driver
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 #ifdef HAL_PWR_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
<> 144:ef7eb2e8f9f7 61 #define PWR_PORTH_AVAILABLE_PINS (PWR_GPIO_BIT_0|PWR_GPIO_BIT_1)
<> 144:ef7eb2e8f9f7 62 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx)
<> 144:ef7eb2e8f9f7 63 #define PWR_PORTH_AVAILABLE_PINS (PWR_GPIO_BIT_0|PWR_GPIO_BIT_1|PWR_GPIO_BIT_3)
<> 144:ef7eb2e8f9f7 64 #endif
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines
<> 144:ef7eb2e8f9f7 67 * @{
<> 144:ef7eb2e8f9f7 68 */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 /** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask
<> 144:ef7eb2e8f9f7 71 * @{
<> 144:ef7eb2e8f9f7 72 */
<> 144:ef7eb2e8f9f7 73 #define PVM_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVM threshold crossing */
<> 144:ef7eb2e8f9f7 74 #define PVM_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVM threshold crossing */
<> 144:ef7eb2e8f9f7 75 #define PVM_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVM trigger */
<> 144:ef7eb2e8f9f7 76 #define PVM_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVM trigger */
<> 144:ef7eb2e8f9f7 77 /**
<> 144:ef7eb2e8f9f7 78 * @}
<> 144:ef7eb2e8f9f7 79 */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value
<> 144:ef7eb2e8f9f7 82 * @{
<> 144:ef7eb2e8f9f7 83 */
<> 144:ef7eb2e8f9f7 84 #define PWR_FLAG_SETTING_DELAY_US 50 /*!< Time out value for REGLPF and VOSF flags setting */
<> 144:ef7eb2e8f9f7 85 /**
<> 144:ef7eb2e8f9f7 86 * @}
<> 144:ef7eb2e8f9f7 87 */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /**
<> 144:ef7eb2e8f9f7 92 * @}
<> 144:ef7eb2e8f9f7 93 */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 98 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 99 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 100 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions
<> 144:ef7eb2e8f9f7 103 * @{
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 107 * @brief Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 108 *
<> 144:ef7eb2e8f9f7 109 @verbatim
<> 144:ef7eb2e8f9f7 110 ===============================================================================
<> 144:ef7eb2e8f9f7 111 ##### Extended Peripheral Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 112 ===============================================================================
<> 144:ef7eb2e8f9f7 113 [..]
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 @endverbatim
<> 144:ef7eb2e8f9f7 116 * @{
<> 144:ef7eb2e8f9f7 117 */
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /**
<> 144:ef7eb2e8f9f7 121 * @brief Return Voltage Scaling Range.
<> 144:ef7eb2e8f9f7 122 * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2)
<> 144:ef7eb2e8f9f7 123 */
<> 144:ef7eb2e8f9f7 124 uint32_t HAL_PWREx_GetVoltageRange(void)
<> 144:ef7eb2e8f9f7 125 {
<> 144:ef7eb2e8f9f7 126 return (PWR->CR1 & PWR_CR1_VOS);
<> 144:ef7eb2e8f9f7 127 }
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /**
<> 144:ef7eb2e8f9f7 132 * @brief Configure the main internal regulator output voltage.
<> 144:ef7eb2e8f9f7 133 * @param VoltageScaling: specifies the regulator output voltage to achieve
<> 144:ef7eb2e8f9f7 134 * a tradeoff between performance and power consumption.
<> 144:ef7eb2e8f9f7 135 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 136 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode,
<> 144:ef7eb2e8f9f7 137 * typical output voltage at 1.2 V,
<> 144:ef7eb2e8f9f7 138 * system frequency up to 80 MHz.
<> 144:ef7eb2e8f9f7 139 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode,
<> 144:ef7eb2e8f9f7 140 * typical output voltage at 1.0 V,
<> 144:ef7eb2e8f9f7 141 * system frequency up to 26 MHz.
<> 144:ef7eb2e8f9f7 142 * @note When moving from Range 1 to Range 2, the system frequency must be decreased to
<> 144:ef7eb2e8f9f7 143 * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API.
<> 144:ef7eb2e8f9f7 144 * When moving from Range 2 to Range 1, the system frequency can be increased to
<> 144:ef7eb2e8f9f7 145 * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API.
<> 144:ef7eb2e8f9f7 146 * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be
<> 144:ef7eb2e8f9f7 147 * cleared before returning the status. If the flag is not cleared within
<> 144:ef7eb2e8f9f7 148 * 50 microseconds, HAL_TIMEOUT status is reported.
<> 144:ef7eb2e8f9f7 149 * @retval HAL Status
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
<> 144:ef7eb2e8f9f7 152 {
<> 144:ef7eb2e8f9f7 153 uint32_t wait_loop_index = 0;
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /* If Set Range 1 */
<> 144:ef7eb2e8f9f7 158 if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
<> 144:ef7eb2e8f9f7 159 {
<> 144:ef7eb2e8f9f7 160 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
<> 144:ef7eb2e8f9f7 161 {
<> 144:ef7eb2e8f9f7 162 /* Set Range 1 */
<> 144:ef7eb2e8f9f7 163 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /* Wait until VOSF is cleared */
<> 144:ef7eb2e8f9f7 166 wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000));
<> 144:ef7eb2e8f9f7 167 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)))
<> 144:ef7eb2e8f9f7 168 {
<> 144:ef7eb2e8f9f7 169 wait_loop_index--;
<> 144:ef7eb2e8f9f7 170 }
<> 144:ef7eb2e8f9f7 171 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
<> 144:ef7eb2e8f9f7 172 {
<> 144:ef7eb2e8f9f7 173 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 174 }
<> 144:ef7eb2e8f9f7 175 }
<> 144:ef7eb2e8f9f7 176 }
<> 144:ef7eb2e8f9f7 177 else
<> 144:ef7eb2e8f9f7 178 {
<> 144:ef7eb2e8f9f7 179 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
<> 144:ef7eb2e8f9f7 180 {
<> 144:ef7eb2e8f9f7 181 /* Set Range 2 */
<> 144:ef7eb2e8f9f7 182 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
<> 144:ef7eb2e8f9f7 183 /* No need to wait for VOSF to be cleared for this transition */
<> 144:ef7eb2e8f9f7 184 }
<> 144:ef7eb2e8f9f7 185 }
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 return HAL_OK;
<> 144:ef7eb2e8f9f7 188 }
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /**
<> 144:ef7eb2e8f9f7 192 * @brief Enable battery charging.
<> 144:ef7eb2e8f9f7 193 * When VDD is present, charge the external battery on VBAT thru an internal resistor.
<> 144:ef7eb2e8f9f7 194 * @param ResistorSelection: specifies the resistor impedance.
<> 144:ef7eb2e8f9f7 195 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 196 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor
<> 144:ef7eb2e8f9f7 197 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor
<> 144:ef7eb2e8f9f7 198 * @retval None
<> 144:ef7eb2e8f9f7 199 */
<> 144:ef7eb2e8f9f7 200 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection)
<> 144:ef7eb2e8f9f7 201 {
<> 144:ef7eb2e8f9f7 202 assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection));
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /* Specify resistor selection */
<> 144:ef7eb2e8f9f7 205 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection);
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /* Enable battery charging */
<> 144:ef7eb2e8f9f7 208 SET_BIT(PWR->CR4, PWR_CR4_VBE);
<> 144:ef7eb2e8f9f7 209 }
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /**
<> 144:ef7eb2e8f9f7 213 * @brief Disable battery charging.
<> 144:ef7eb2e8f9f7 214 * @retval None
<> 144:ef7eb2e8f9f7 215 */
<> 144:ef7eb2e8f9f7 216 void HAL_PWREx_DisableBatteryCharging(void)
<> 144:ef7eb2e8f9f7 217 {
<> 144:ef7eb2e8f9f7 218 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
<> 144:ef7eb2e8f9f7 219 }
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
<> 144:ef7eb2e8f9f7 223 /**
<> 144:ef7eb2e8f9f7 224 * @brief Enable VDDUSB supply.
<> 144:ef7eb2e8f9f7 225 * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
<> 144:ef7eb2e8f9f7 226 * @retval None
<> 144:ef7eb2e8f9f7 227 */
<> 144:ef7eb2e8f9f7 228 void HAL_PWREx_EnableVddUSB(void)
<> 144:ef7eb2e8f9f7 229 {
<> 144:ef7eb2e8f9f7 230 SET_BIT(PWR->CR2, PWR_CR2_USV);
<> 144:ef7eb2e8f9f7 231 }
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /**
<> 144:ef7eb2e8f9f7 235 * @brief Disable VDDUSB supply.
<> 144:ef7eb2e8f9f7 236 * @retval None
<> 144:ef7eb2e8f9f7 237 */
<> 144:ef7eb2e8f9f7 238 void HAL_PWREx_DisableVddUSB(void)
<> 144:ef7eb2e8f9f7 239 {
<> 144:ef7eb2e8f9f7 240 CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
<> 144:ef7eb2e8f9f7 241 }
<> 144:ef7eb2e8f9f7 242 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
<> 144:ef7eb2e8f9f7 245 /**
<> 144:ef7eb2e8f9f7 246 * @brief Enable VDDIO2 supply.
<> 144:ef7eb2e8f9f7 247 * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present.
<> 144:ef7eb2e8f9f7 248 * @retval None
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250 void HAL_PWREx_EnableVddIO2(void)
<> 144:ef7eb2e8f9f7 251 {
<> 144:ef7eb2e8f9f7 252 SET_BIT(PWR->CR2, PWR_CR2_IOSV);
<> 144:ef7eb2e8f9f7 253 }
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /**
<> 144:ef7eb2e8f9f7 257 * @brief Disable VDDIO2 supply.
<> 144:ef7eb2e8f9f7 258 * @retval None
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260 void HAL_PWREx_DisableVddIO2(void)
<> 144:ef7eb2e8f9f7 261 {
<> 144:ef7eb2e8f9f7 262 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
<> 144:ef7eb2e8f9f7 263 }
<> 144:ef7eb2e8f9f7 264 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /**
<> 144:ef7eb2e8f9f7 268 * @brief Enable Internal Wake-up Line.
<> 144:ef7eb2e8f9f7 269 * @retval None
<> 144:ef7eb2e8f9f7 270 */
<> 144:ef7eb2e8f9f7 271 void HAL_PWREx_EnableInternalWakeUpLine(void)
<> 144:ef7eb2e8f9f7 272 {
<> 144:ef7eb2e8f9f7 273 SET_BIT(PWR->CR3, PWR_CR3_EIWF);
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /**
<> 144:ef7eb2e8f9f7 278 * @brief Disable Internal Wake-up Line.
<> 144:ef7eb2e8f9f7 279 * @retval None
<> 144:ef7eb2e8f9f7 280 */
<> 144:ef7eb2e8f9f7 281 void HAL_PWREx_DisableInternalWakeUpLine(void)
<> 144:ef7eb2e8f9f7 282 {
<> 144:ef7eb2e8f9f7 283 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
<> 144:ef7eb2e8f9f7 284 }
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /**
<> 144:ef7eb2e8f9f7 289 * @brief Enable GPIO pull-up state in Standby and Shutdown modes.
<> 144:ef7eb2e8f9f7 290 * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in
<> 144:ef7eb2e8f9f7 291 * pull-up state in Standby and Shutdown modes.
<> 144:ef7eb2e8f9f7 292 * @note This state is effective in Standby and Shutdown modes only if APC bit
<> 144:ef7eb2e8f9f7 293 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
<> 144:ef7eb2e8f9f7 294 * @note The configuration is lost when exiting the Shutdown mode due to the
<> 144:ef7eb2e8f9f7 295 * power-on reset, maintained when exiting the Standby mode.
<> 144:ef7eb2e8f9f7 296 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
<> 144:ef7eb2e8f9f7 297 * PDy bit of PWR_PDCRx register is cleared unless it is reserved.
<> 144:ef7eb2e8f9f7 298 * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input
<> 144:ef7eb2e8f9f7 299 * parameter at the same time are set.
<> 144:ef7eb2e8f9f7 300 * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
<> 144:ef7eb2e8f9f7 301 * to select the GPIO peripheral.
<> 144:ef7eb2e8f9f7 302 * @param GPIONumber: Specify the I/O pins numbers.
<> 144:ef7eb2e8f9f7 303 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 304 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
<> 144:ef7eb2e8f9f7 305 * I/O pins are available) or the logical OR of several of them to set
<> 144:ef7eb2e8f9f7 306 * several bits for a given port in a single API call.
<> 144:ef7eb2e8f9f7 307 * @retval HAL Status
<> 144:ef7eb2e8f9f7 308 */
<> 144:ef7eb2e8f9f7 309 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
<> 144:ef7eb2e8f9f7 310 {
<> 144:ef7eb2e8f9f7 311 assert_param(IS_PWR_GPIO(GPIO));
<> 144:ef7eb2e8f9f7 312 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 switch (GPIO)
<> 144:ef7eb2e8f9f7 315 {
<> 144:ef7eb2e8f9f7 316 case PWR_GPIO_A:
<> 144:ef7eb2e8f9f7 317 SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
<> 144:ef7eb2e8f9f7 318 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
<> 144:ef7eb2e8f9f7 319 break;
<> 144:ef7eb2e8f9f7 320 case PWR_GPIO_B:
<> 144:ef7eb2e8f9f7 321 SET_BIT(PWR->PUCRB, GPIONumber);
<> 144:ef7eb2e8f9f7 322 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
<> 144:ef7eb2e8f9f7 323 break;
<> 144:ef7eb2e8f9f7 324 case PWR_GPIO_C:
<> 144:ef7eb2e8f9f7 325 SET_BIT(PWR->PUCRC, GPIONumber);
<> 144:ef7eb2e8f9f7 326 CLEAR_BIT(PWR->PDCRC, GPIONumber);
<> 144:ef7eb2e8f9f7 327 break;
<> 144:ef7eb2e8f9f7 328 #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
<> 144:ef7eb2e8f9f7 329 case PWR_GPIO_D:
<> 144:ef7eb2e8f9f7 330 SET_BIT(PWR->PUCRD, GPIONumber);
<> 144:ef7eb2e8f9f7 331 CLEAR_BIT(PWR->PDCRD, GPIONumber);
<> 144:ef7eb2e8f9f7 332 break;
<> 144:ef7eb2e8f9f7 333 case PWR_GPIO_E:
<> 144:ef7eb2e8f9f7 334 SET_BIT(PWR->PUCRE, GPIONumber);
<> 144:ef7eb2e8f9f7 335 CLEAR_BIT(PWR->PDCRE, GPIONumber);
<> 144:ef7eb2e8f9f7 336 break;
<> 144:ef7eb2e8f9f7 337 #endif
<> 144:ef7eb2e8f9f7 338 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
<> 144:ef7eb2e8f9f7 339 case PWR_GPIO_F:
<> 144:ef7eb2e8f9f7 340 SET_BIT(PWR->PUCRF, GPIONumber);
<> 144:ef7eb2e8f9f7 341 CLEAR_BIT(PWR->PDCRF, GPIONumber);
<> 144:ef7eb2e8f9f7 342 break;
<> 144:ef7eb2e8f9f7 343 case PWR_GPIO_G:
<> 144:ef7eb2e8f9f7 344 SET_BIT(PWR->PUCRG, GPIONumber);
<> 144:ef7eb2e8f9f7 345 CLEAR_BIT(PWR->PDCRG, GPIONumber);
<> 144:ef7eb2e8f9f7 346 break;
<> 144:ef7eb2e8f9f7 347 #endif
<> 144:ef7eb2e8f9f7 348 case PWR_GPIO_H:
<> 144:ef7eb2e8f9f7 349 SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
<> 144:ef7eb2e8f9f7 350 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
<> 144:ef7eb2e8f9f7 351 break;
<> 144:ef7eb2e8f9f7 352 default:
<> 144:ef7eb2e8f9f7 353 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 354 }
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 return HAL_OK;
<> 144:ef7eb2e8f9f7 357 }
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /**
<> 144:ef7eb2e8f9f7 361 * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes.
<> 144:ef7eb2e8f9f7 362 * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O
<> 144:ef7eb2e8f9f7 363 * in pull-up state in Standby and Shutdown modes.
<> 144:ef7eb2e8f9f7 364 * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input
<> 144:ef7eb2e8f9f7 365 * parameter at the same time are reset.
<> 144:ef7eb2e8f9f7 366 * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H
<> 144:ef7eb2e8f9f7 367 * to select the GPIO peripheral.
<> 144:ef7eb2e8f9f7 368 * @param GPIONumber: Specify the I/O pins numbers.
<> 144:ef7eb2e8f9f7 369 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 370 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
<> 144:ef7eb2e8f9f7 371 * I/O pins are available) or the logical OR of several of them to reset
<> 144:ef7eb2e8f9f7 372 * several bits for a given port in a single API call.
<> 144:ef7eb2e8f9f7 373 * @retval HAL Status
<> 144:ef7eb2e8f9f7 374 */
<> 144:ef7eb2e8f9f7 375 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
<> 144:ef7eb2e8f9f7 376 {
<> 144:ef7eb2e8f9f7 377 assert_param(IS_PWR_GPIO(GPIO));
<> 144:ef7eb2e8f9f7 378 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 switch (GPIO)
<> 144:ef7eb2e8f9f7 381 {
<> 144:ef7eb2e8f9f7 382 case PWR_GPIO_A:
<> 144:ef7eb2e8f9f7 383 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
<> 144:ef7eb2e8f9f7 384 break;
<> 144:ef7eb2e8f9f7 385 case PWR_GPIO_B:
<> 144:ef7eb2e8f9f7 386 CLEAR_BIT(PWR->PUCRB, GPIONumber);
<> 144:ef7eb2e8f9f7 387 break;
<> 144:ef7eb2e8f9f7 388 case PWR_GPIO_C:
<> 144:ef7eb2e8f9f7 389 CLEAR_BIT(PWR->PUCRC, GPIONumber);
<> 144:ef7eb2e8f9f7 390 break;
<> 144:ef7eb2e8f9f7 391 #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
<> 144:ef7eb2e8f9f7 392 case PWR_GPIO_D:
<> 144:ef7eb2e8f9f7 393 CLEAR_BIT(PWR->PUCRD, GPIONumber);
<> 144:ef7eb2e8f9f7 394 break;
<> 144:ef7eb2e8f9f7 395 case PWR_GPIO_E:
<> 144:ef7eb2e8f9f7 396 CLEAR_BIT(PWR->PUCRE, GPIONumber);
<> 144:ef7eb2e8f9f7 397 break;
<> 144:ef7eb2e8f9f7 398 #endif
<> 144:ef7eb2e8f9f7 399 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
<> 144:ef7eb2e8f9f7 400 case PWR_GPIO_F:
<> 144:ef7eb2e8f9f7 401 CLEAR_BIT(PWR->PUCRF, GPIONumber);
<> 144:ef7eb2e8f9f7 402 break;
<> 144:ef7eb2e8f9f7 403 case PWR_GPIO_G:
<> 144:ef7eb2e8f9f7 404 CLEAR_BIT(PWR->PUCRG, GPIONumber);
<> 144:ef7eb2e8f9f7 405 break;
<> 144:ef7eb2e8f9f7 406 #endif
<> 144:ef7eb2e8f9f7 407 case PWR_GPIO_H:
<> 144:ef7eb2e8f9f7 408 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
<> 144:ef7eb2e8f9f7 409 break;
<> 144:ef7eb2e8f9f7 410 default:
<> 144:ef7eb2e8f9f7 411 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 412 }
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 return HAL_OK;
<> 144:ef7eb2e8f9f7 415 }
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /**
<> 144:ef7eb2e8f9f7 420 * @brief Enable GPIO pull-down state in Standby and Shutdown modes.
<> 144:ef7eb2e8f9f7 421 * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in
<> 144:ef7eb2e8f9f7 422 * pull-down state in Standby and Shutdown modes.
<> 144:ef7eb2e8f9f7 423 * @note This state is effective in Standby and Shutdown modes only if APC bit
<> 144:ef7eb2e8f9f7 424 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
<> 144:ef7eb2e8f9f7 425 * @note The configuration is lost when exiting the Shutdown mode due to the
<> 144:ef7eb2e8f9f7 426 * power-on reset, maintained when exiting the Standby mode.
<> 144:ef7eb2e8f9f7 427 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding
<> 144:ef7eb2e8f9f7 428 * PUy bit of PWR_PUCRx register is cleared unless it is reserved.
<> 144:ef7eb2e8f9f7 429 * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input
<> 144:ef7eb2e8f9f7 430 * parameter at the same time are set.
<> 144:ef7eb2e8f9f7 431 * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
<> 144:ef7eb2e8f9f7 432 * to select the GPIO peripheral.
<> 144:ef7eb2e8f9f7 433 * @param GPIONumber: Specify the I/O pins numbers.
<> 144:ef7eb2e8f9f7 434 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 435 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
<> 144:ef7eb2e8f9f7 436 * I/O pins are available) or the logical OR of several of them to set
<> 144:ef7eb2e8f9f7 437 * several bits for a given port in a single API call.
<> 144:ef7eb2e8f9f7 438 * @retval HAL Status
<> 144:ef7eb2e8f9f7 439 */
<> 144:ef7eb2e8f9f7 440 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
<> 144:ef7eb2e8f9f7 441 {
<> 144:ef7eb2e8f9f7 442 assert_param(IS_PWR_GPIO(GPIO));
<> 144:ef7eb2e8f9f7 443 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 switch (GPIO)
<> 144:ef7eb2e8f9f7 446 {
<> 144:ef7eb2e8f9f7 447 case PWR_GPIO_A:
<> 144:ef7eb2e8f9f7 448 SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
<> 144:ef7eb2e8f9f7 449 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14))));
<> 144:ef7eb2e8f9f7 450 break;
<> 144:ef7eb2e8f9f7 451 case PWR_GPIO_B:
<> 144:ef7eb2e8f9f7 452 SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
<> 144:ef7eb2e8f9f7 453 CLEAR_BIT(PWR->PUCRB, GPIONumber);
<> 144:ef7eb2e8f9f7 454 break;
<> 144:ef7eb2e8f9f7 455 case PWR_GPIO_C:
<> 144:ef7eb2e8f9f7 456 SET_BIT(PWR->PDCRC, GPIONumber);
<> 144:ef7eb2e8f9f7 457 CLEAR_BIT(PWR->PUCRC, GPIONumber);
<> 144:ef7eb2e8f9f7 458 break;
<> 144:ef7eb2e8f9f7 459 #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
<> 144:ef7eb2e8f9f7 460 case PWR_GPIO_D:
<> 144:ef7eb2e8f9f7 461 SET_BIT(PWR->PDCRD, GPIONumber);
<> 144:ef7eb2e8f9f7 462 CLEAR_BIT(PWR->PUCRD, GPIONumber);
<> 144:ef7eb2e8f9f7 463 break;
<> 144:ef7eb2e8f9f7 464 case PWR_GPIO_E:
<> 144:ef7eb2e8f9f7 465 SET_BIT(PWR->PDCRE, GPIONumber);
<> 144:ef7eb2e8f9f7 466 CLEAR_BIT(PWR->PUCRE, GPIONumber);
<> 144:ef7eb2e8f9f7 467 break;
<> 144:ef7eb2e8f9f7 468 #endif
<> 144:ef7eb2e8f9f7 469 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
<> 144:ef7eb2e8f9f7 470 case PWR_GPIO_F:
<> 144:ef7eb2e8f9f7 471 SET_BIT(PWR->PDCRF, GPIONumber);
<> 144:ef7eb2e8f9f7 472 CLEAR_BIT(PWR->PUCRF, GPIONumber);
<> 144:ef7eb2e8f9f7 473 break;
<> 144:ef7eb2e8f9f7 474 case PWR_GPIO_G:
<> 144:ef7eb2e8f9f7 475 SET_BIT(PWR->PDCRG, GPIONumber);
<> 144:ef7eb2e8f9f7 476 CLEAR_BIT(PWR->PUCRG, GPIONumber);
<> 144:ef7eb2e8f9f7 477 break;
<> 144:ef7eb2e8f9f7 478 #endif
<> 144:ef7eb2e8f9f7 479 case PWR_GPIO_H:
<> 144:ef7eb2e8f9f7 480 SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
<> 144:ef7eb2e8f9f7 481 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
<> 144:ef7eb2e8f9f7 482 break;
<> 144:ef7eb2e8f9f7 483 default:
<> 144:ef7eb2e8f9f7 484 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 485 }
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 return HAL_OK;
<> 144:ef7eb2e8f9f7 488 }
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /**
<> 144:ef7eb2e8f9f7 492 * @brief Disable GPIO pull-down state in Standby and Shutdown modes.
<> 144:ef7eb2e8f9f7 493 * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O
<> 144:ef7eb2e8f9f7 494 * in pull-down state in Standby and Shutdown modes.
<> 144:ef7eb2e8f9f7 495 * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input
<> 144:ef7eb2e8f9f7 496 * parameter at the same time are reset.
<> 144:ef7eb2e8f9f7 497 * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H
<> 144:ef7eb2e8f9f7 498 * to select the GPIO peripheral.
<> 144:ef7eb2e8f9f7 499 * @param GPIONumber: Specify the I/O pins numbers.
<> 144:ef7eb2e8f9f7 500 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 501 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for PORTH where less
<> 144:ef7eb2e8f9f7 502 * I/O pins are available) or the logical OR of several of them to reset
<> 144:ef7eb2e8f9f7 503 * several bits for a given port in a single API call.
<> 144:ef7eb2e8f9f7 504 * @retval HAL Status
<> 144:ef7eb2e8f9f7 505 */
<> 144:ef7eb2e8f9f7 506 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
<> 144:ef7eb2e8f9f7 507 {
<> 144:ef7eb2e8f9f7 508 assert_param(IS_PWR_GPIO(GPIO));
<> 144:ef7eb2e8f9f7 509 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber));
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 switch (GPIO)
<> 144:ef7eb2e8f9f7 512 {
<> 144:ef7eb2e8f9f7 513 case PWR_GPIO_A:
<> 144:ef7eb2e8f9f7 514 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15))));
<> 144:ef7eb2e8f9f7 515 break;
<> 144:ef7eb2e8f9f7 516 case PWR_GPIO_B:
<> 144:ef7eb2e8f9f7 517 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4))));
<> 144:ef7eb2e8f9f7 518 break;
<> 144:ef7eb2e8f9f7 519 case PWR_GPIO_C:
<> 144:ef7eb2e8f9f7 520 CLEAR_BIT(PWR->PDCRC, GPIONumber);
<> 144:ef7eb2e8f9f7 521 break;
<> 144:ef7eb2e8f9f7 522 #if defined (STM32L431xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
<> 144:ef7eb2e8f9f7 523 case PWR_GPIO_D:
<> 144:ef7eb2e8f9f7 524 CLEAR_BIT(PWR->PDCRD, GPIONumber);
<> 144:ef7eb2e8f9f7 525 break;
<> 144:ef7eb2e8f9f7 526 case PWR_GPIO_E:
<> 144:ef7eb2e8f9f7 527 CLEAR_BIT(PWR->PDCRE, GPIONumber);
<> 144:ef7eb2e8f9f7 528 break;
<> 144:ef7eb2e8f9f7 529 #endif
<> 144:ef7eb2e8f9f7 530 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
<> 144:ef7eb2e8f9f7 531 case PWR_GPIO_F:
<> 144:ef7eb2e8f9f7 532 CLEAR_BIT(PWR->PDCRF, GPIONumber);
<> 144:ef7eb2e8f9f7 533 break;
<> 144:ef7eb2e8f9f7 534 case PWR_GPIO_G:
<> 144:ef7eb2e8f9f7 535 CLEAR_BIT(PWR->PDCRG, GPIONumber);
<> 144:ef7eb2e8f9f7 536 break;
<> 144:ef7eb2e8f9f7 537 #endif
<> 144:ef7eb2e8f9f7 538 case PWR_GPIO_H:
<> 144:ef7eb2e8f9f7 539 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS));
<> 144:ef7eb2e8f9f7 540 break;
<> 144:ef7eb2e8f9f7 541 default:
<> 144:ef7eb2e8f9f7 542 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 543 }
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 return HAL_OK;
<> 144:ef7eb2e8f9f7 546 }
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 /**
<> 144:ef7eb2e8f9f7 551 * @brief Enable pull-up and pull-down configuration.
<> 144:ef7eb2e8f9f7 552 * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in
<> 144:ef7eb2e8f9f7 553 * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes.
<> 144:ef7eb2e8f9f7 554 * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding
<> 144:ef7eb2e8f9f7 555 * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher).
<> 144:ef7eb2e8f9f7 556 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there
<> 144:ef7eb2e8f9f7 557 * is no conflict when setting PUy or PDy bit.
<> 144:ef7eb2e8f9f7 558 * @retval None
<> 144:ef7eb2e8f9f7 559 */
<> 144:ef7eb2e8f9f7 560 void HAL_PWREx_EnablePullUpPullDownConfig(void)
<> 144:ef7eb2e8f9f7 561 {
<> 144:ef7eb2e8f9f7 562 SET_BIT(PWR->CR3, PWR_CR3_APC);
<> 144:ef7eb2e8f9f7 563 }
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 /**
<> 144:ef7eb2e8f9f7 567 * @brief Disable pull-up and pull-down configuration.
<> 144:ef7eb2e8f9f7 568 * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in
<> 144:ef7eb2e8f9f7 569 * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes.
<> 144:ef7eb2e8f9f7 570 * @retval None
<> 144:ef7eb2e8f9f7 571 */
<> 144:ef7eb2e8f9f7 572 void HAL_PWREx_DisablePullUpPullDownConfig(void)
<> 144:ef7eb2e8f9f7 573 {
<> 144:ef7eb2e8f9f7 574 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
<> 144:ef7eb2e8f9f7 575 }
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 /**
<> 144:ef7eb2e8f9f7 580 * @brief Enable SRAM2 content retention in Standby mode.
<> 144:ef7eb2e8f9f7 581 * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in
<> 144:ef7eb2e8f9f7 582 * Standby mode and its content is kept.
<> 144:ef7eb2e8f9f7 583 * @retval None
<> 144:ef7eb2e8f9f7 584 */
<> 144:ef7eb2e8f9f7 585 void HAL_PWREx_EnableSRAM2ContentRetention(void)
<> 144:ef7eb2e8f9f7 586 {
<> 144:ef7eb2e8f9f7 587 SET_BIT(PWR->CR3, PWR_CR3_RRS);
<> 144:ef7eb2e8f9f7 588 }
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /**
<> 144:ef7eb2e8f9f7 592 * @brief Disable SRAM2 content retention in Standby mode.
<> 144:ef7eb2e8f9f7 593 * @note When RRS bit is reset, SRAM2 is powered off in Standby mode
<> 144:ef7eb2e8f9f7 594 * and its content is lost.
<> 144:ef7eb2e8f9f7 595 * @retval None
<> 144:ef7eb2e8f9f7 596 */
<> 144:ef7eb2e8f9f7 597 void HAL_PWREx_DisableSRAM2ContentRetention(void)
<> 144:ef7eb2e8f9f7 598 {
<> 144:ef7eb2e8f9f7 599 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
<> 144:ef7eb2e8f9f7 600 }
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
<> 144:ef7eb2e8f9f7 606 /**
<> 144:ef7eb2e8f9f7 607 * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
<> 144:ef7eb2e8f9f7 608 * @retval None
<> 144:ef7eb2e8f9f7 609 */
<> 144:ef7eb2e8f9f7 610 void HAL_PWREx_EnablePVM1(void)
<> 144:ef7eb2e8f9f7 611 {
<> 144:ef7eb2e8f9f7 612 SET_BIT(PWR->CR2, PWR_PVM_1);
<> 144:ef7eb2e8f9f7 613 }
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 /**
<> 144:ef7eb2e8f9f7 616 * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
<> 144:ef7eb2e8f9f7 617 * @retval None
<> 144:ef7eb2e8f9f7 618 */
<> 144:ef7eb2e8f9f7 619 void HAL_PWREx_DisablePVM1(void)
<> 144:ef7eb2e8f9f7 620 {
<> 144:ef7eb2e8f9f7 621 CLEAR_BIT(PWR->CR2, PWR_PVM_1);
<> 144:ef7eb2e8f9f7 622 }
<> 144:ef7eb2e8f9f7 623 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
<> 144:ef7eb2e8f9f7 627 /**
<> 144:ef7eb2e8f9f7 628 * @brief Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
<> 144:ef7eb2e8f9f7 629 * @retval None
<> 144:ef7eb2e8f9f7 630 */
<> 144:ef7eb2e8f9f7 631 void HAL_PWREx_EnablePVM2(void)
<> 144:ef7eb2e8f9f7 632 {
<> 144:ef7eb2e8f9f7 633 SET_BIT(PWR->CR2, PWR_PVM_2);
<> 144:ef7eb2e8f9f7 634 }
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /**
<> 144:ef7eb2e8f9f7 637 * @brief Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V.
<> 144:ef7eb2e8f9f7 638 * @retval None
<> 144:ef7eb2e8f9f7 639 */
<> 144:ef7eb2e8f9f7 640 void HAL_PWREx_DisablePVM2(void)
<> 144:ef7eb2e8f9f7 641 {
<> 144:ef7eb2e8f9f7 642 CLEAR_BIT(PWR->CR2, PWR_PVM_2);
<> 144:ef7eb2e8f9f7 643 }
<> 144:ef7eb2e8f9f7 644 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 /**
<> 144:ef7eb2e8f9f7 648 * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.
<> 144:ef7eb2e8f9f7 649 * @retval None
<> 144:ef7eb2e8f9f7 650 */
<> 144:ef7eb2e8f9f7 651 void HAL_PWREx_EnablePVM3(void)
<> 144:ef7eb2e8f9f7 652 {
<> 144:ef7eb2e8f9f7 653 SET_BIT(PWR->CR2, PWR_PVM_3);
<> 144:ef7eb2e8f9f7 654 }
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 /**
<> 144:ef7eb2e8f9f7 657 * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62V.
<> 144:ef7eb2e8f9f7 658 * @retval None
<> 144:ef7eb2e8f9f7 659 */
<> 144:ef7eb2e8f9f7 660 void HAL_PWREx_DisablePVM3(void)
<> 144:ef7eb2e8f9f7 661 {
<> 144:ef7eb2e8f9f7 662 CLEAR_BIT(PWR->CR2, PWR_PVM_3);
<> 144:ef7eb2e8f9f7 663 }
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 /**
<> 144:ef7eb2e8f9f7 667 * @brief Enable the Power Voltage Monitoring 4: VDDA versus 2.2V.
<> 144:ef7eb2e8f9f7 668 * @retval None
<> 144:ef7eb2e8f9f7 669 */
<> 144:ef7eb2e8f9f7 670 void HAL_PWREx_EnablePVM4(void)
<> 144:ef7eb2e8f9f7 671 {
<> 144:ef7eb2e8f9f7 672 SET_BIT(PWR->CR2, PWR_PVM_4);
<> 144:ef7eb2e8f9f7 673 }
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 /**
<> 144:ef7eb2e8f9f7 676 * @brief Disable the Power Voltage Monitoring 4: VDDA versus 2.2V.
<> 144:ef7eb2e8f9f7 677 * @retval None
<> 144:ef7eb2e8f9f7 678 */
<> 144:ef7eb2e8f9f7 679 void HAL_PWREx_DisablePVM4(void)
<> 144:ef7eb2e8f9f7 680 {
<> 144:ef7eb2e8f9f7 681 CLEAR_BIT(PWR->CR2, PWR_PVM_4);
<> 144:ef7eb2e8f9f7 682 }
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687 /**
<> 144:ef7eb2e8f9f7 688 * @brief Configure the Peripheral Voltage Monitoring (PVM).
<> 144:ef7eb2e8f9f7 689 * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the
<> 144:ef7eb2e8f9f7 690 * PVM configuration information.
<> 144:ef7eb2e8f9f7 691 * @note The API configures a single PVM according to the information contained
<> 144:ef7eb2e8f9f7 692 * in the input structure. To configure several PVMs, the API must be singly
<> 144:ef7eb2e8f9f7 693 * called for each PVM used.
<> 144:ef7eb2e8f9f7 694 * @note Refer to the electrical characteristics of your device datasheet for
<> 144:ef7eb2e8f9f7 695 * more details about the voltage thresholds corresponding to each
<> 144:ef7eb2e8f9f7 696 * detection level and to each monitored supply.
<> 144:ef7eb2e8f9f7 697 * @retval HAL status
<> 144:ef7eb2e8f9f7 698 */
<> 144:ef7eb2e8f9f7 699 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
<> 144:ef7eb2e8f9f7 700 {
<> 144:ef7eb2e8f9f7 701 /* Check the parameters */
<> 144:ef7eb2e8f9f7 702 assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType));
<> 144:ef7eb2e8f9f7 703 assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode));
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 /* Configure EXTI 35 to 38 interrupts if so required:
<> 144:ef7eb2e8f9f7 707 scan thru PVMType to detect which PVMx is set and
<> 144:ef7eb2e8f9f7 708 configure the corresponding EXTI line accordingly. */
<> 144:ef7eb2e8f9f7 709 switch (sConfigPVM->PVMType)
<> 144:ef7eb2e8f9f7 710 {
<> 144:ef7eb2e8f9f7 711 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
<> 144:ef7eb2e8f9f7 712 case PWR_PVM_1:
<> 144:ef7eb2e8f9f7 713 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
<> 144:ef7eb2e8f9f7 714 __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();
<> 144:ef7eb2e8f9f7 715 __HAL_PWR_PVM1_EXTI_DISABLE_IT();
<> 144:ef7eb2e8f9f7 716 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 717 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 /* Configure interrupt mode */
<> 144:ef7eb2e8f9f7 720 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
<> 144:ef7eb2e8f9f7 721 {
<> 144:ef7eb2e8f9f7 722 __HAL_PWR_PVM1_EXTI_ENABLE_IT();
<> 144:ef7eb2e8f9f7 723 }
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 /* Configure event mode */
<> 144:ef7eb2e8f9f7 726 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
<> 144:ef7eb2e8f9f7 727 {
<> 144:ef7eb2e8f9f7 728 __HAL_PWR_PVM1_EXTI_ENABLE_EVENT();
<> 144:ef7eb2e8f9f7 729 }
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 /* Configure the edge */
<> 144:ef7eb2e8f9f7 732 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
<> 144:ef7eb2e8f9f7 733 {
<> 144:ef7eb2e8f9f7 734 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();
<> 144:ef7eb2e8f9f7 735 }
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
<> 144:ef7eb2e8f9f7 738 {
<> 144:ef7eb2e8f9f7 739 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 740 }
<> 144:ef7eb2e8f9f7 741 break;
<> 144:ef7eb2e8f9f7 742 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
<> 144:ef7eb2e8f9f7 743
<> 144:ef7eb2e8f9f7 744 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
<> 144:ef7eb2e8f9f7 745 case PWR_PVM_2:
<> 144:ef7eb2e8f9f7 746 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
<> 144:ef7eb2e8f9f7 747 __HAL_PWR_PVM2_EXTI_DISABLE_EVENT();
<> 144:ef7eb2e8f9f7 748 __HAL_PWR_PVM2_EXTI_DISABLE_IT();
<> 144:ef7eb2e8f9f7 749 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 750 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 /* Configure interrupt mode */
<> 144:ef7eb2e8f9f7 753 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
<> 144:ef7eb2e8f9f7 754 {
<> 144:ef7eb2e8f9f7 755 __HAL_PWR_PVM2_EXTI_ENABLE_IT();
<> 144:ef7eb2e8f9f7 756 }
<> 144:ef7eb2e8f9f7 757
<> 144:ef7eb2e8f9f7 758 /* Configure event mode */
<> 144:ef7eb2e8f9f7 759 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
<> 144:ef7eb2e8f9f7 760 {
<> 144:ef7eb2e8f9f7 761 __HAL_PWR_PVM2_EXTI_ENABLE_EVENT();
<> 144:ef7eb2e8f9f7 762 }
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 /* Configure the edge */
<> 144:ef7eb2e8f9f7 765 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
<> 144:ef7eb2e8f9f7 766 {
<> 144:ef7eb2e8f9f7 767 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();
<> 144:ef7eb2e8f9f7 768 }
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
<> 144:ef7eb2e8f9f7 771 {
<> 144:ef7eb2e8f9f7 772 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 773 }
<> 144:ef7eb2e8f9f7 774 break;
<> 144:ef7eb2e8f9f7 775 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
<> 144:ef7eb2e8f9f7 776
<> 144:ef7eb2e8f9f7 777 case PWR_PVM_3:
<> 144:ef7eb2e8f9f7 778 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
<> 144:ef7eb2e8f9f7 779 __HAL_PWR_PVM3_EXTI_DISABLE_EVENT();
<> 144:ef7eb2e8f9f7 780 __HAL_PWR_PVM3_EXTI_DISABLE_IT();
<> 144:ef7eb2e8f9f7 781 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 782 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 /* Configure interrupt mode */
<> 144:ef7eb2e8f9f7 785 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
<> 144:ef7eb2e8f9f7 786 {
<> 144:ef7eb2e8f9f7 787 __HAL_PWR_PVM3_EXTI_ENABLE_IT();
<> 144:ef7eb2e8f9f7 788 }
<> 144:ef7eb2e8f9f7 789
<> 144:ef7eb2e8f9f7 790 /* Configure event mode */
<> 144:ef7eb2e8f9f7 791 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
<> 144:ef7eb2e8f9f7 792 {
<> 144:ef7eb2e8f9f7 793 __HAL_PWR_PVM3_EXTI_ENABLE_EVENT();
<> 144:ef7eb2e8f9f7 794 }
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 /* Configure the edge */
<> 144:ef7eb2e8f9f7 797 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
<> 144:ef7eb2e8f9f7 798 {
<> 144:ef7eb2e8f9f7 799 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();
<> 144:ef7eb2e8f9f7 800 }
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
<> 144:ef7eb2e8f9f7 803 {
<> 144:ef7eb2e8f9f7 804 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 805 }
<> 144:ef7eb2e8f9f7 806 break;
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808 case PWR_PVM_4:
<> 144:ef7eb2e8f9f7 809 /* Clear any previous config. Keep it clear if no event or IT mode is selected */
<> 144:ef7eb2e8f9f7 810 __HAL_PWR_PVM4_EXTI_DISABLE_EVENT();
<> 144:ef7eb2e8f9f7 811 __HAL_PWR_PVM4_EXTI_DISABLE_IT();
<> 144:ef7eb2e8f9f7 812 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 813 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 /* Configure interrupt mode */
<> 144:ef7eb2e8f9f7 816 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT)
<> 144:ef7eb2e8f9f7 817 {
<> 144:ef7eb2e8f9f7 818 __HAL_PWR_PVM4_EXTI_ENABLE_IT();
<> 144:ef7eb2e8f9f7 819 }
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 /* Configure event mode */
<> 144:ef7eb2e8f9f7 822 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT)
<> 144:ef7eb2e8f9f7 823 {
<> 144:ef7eb2e8f9f7 824 __HAL_PWR_PVM4_EXTI_ENABLE_EVENT();
<> 144:ef7eb2e8f9f7 825 }
<> 144:ef7eb2e8f9f7 826
<> 144:ef7eb2e8f9f7 827 /* Configure the edge */
<> 144:ef7eb2e8f9f7 828 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE)
<> 144:ef7eb2e8f9f7 829 {
<> 144:ef7eb2e8f9f7 830 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();
<> 144:ef7eb2e8f9f7 831 }
<> 144:ef7eb2e8f9f7 832
<> 144:ef7eb2e8f9f7 833 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE)
<> 144:ef7eb2e8f9f7 834 {
<> 144:ef7eb2e8f9f7 835 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();
<> 144:ef7eb2e8f9f7 836 }
<> 144:ef7eb2e8f9f7 837 break;
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 default:
<> 144:ef7eb2e8f9f7 840 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 }
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 return HAL_OK;
<> 144:ef7eb2e8f9f7 846 }
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 /**
<> 144:ef7eb2e8f9f7 851 * @brief Enter Low-power Run mode
<> 144:ef7eb2e8f9f7 852 * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode.
<> 144:ef7eb2e8f9f7 853 * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the
<> 144:ef7eb2e8f9f7 854 * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register.
<> 144:ef7eb2e8f9f7 855 * Additionally, the clock frequency must be reduced below 2 MHz.
<> 144:ef7eb2e8f9f7 856 * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must
<> 144:ef7eb2e8f9f7 857 * be done before calling HAL_PWREx_EnableLowPowerRunMode() API.
<> 144:ef7eb2e8f9f7 858 * @retval None
<> 144:ef7eb2e8f9f7 859 */
<> 144:ef7eb2e8f9f7 860 void HAL_PWREx_EnableLowPowerRunMode(void)
<> 144:ef7eb2e8f9f7 861 {
<> 144:ef7eb2e8f9f7 862 /* Set Regulator parameter */
<> 144:ef7eb2e8f9f7 863 SET_BIT(PWR->CR1, PWR_CR1_LPR);
<> 144:ef7eb2e8f9f7 864 }
<> 144:ef7eb2e8f9f7 865
<> 144:ef7eb2e8f9f7 866
<> 144:ef7eb2e8f9f7 867 /**
<> 144:ef7eb2e8f9f7 868 * @brief Exit Low-power Run mode.
<> 144:ef7eb2e8f9f7 869 * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that
<> 144:ef7eb2e8f9f7 870 * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode
<> 144:ef7eb2e8f9f7 871 * returns HAL_TIMEOUT status). The system clock frequency can then be
<> 144:ef7eb2e8f9f7 872 * increased above 2 MHz.
<> 144:ef7eb2e8f9f7 873 * @retval HAL Status
<> 144:ef7eb2e8f9f7 874 */
<> 144:ef7eb2e8f9f7 875 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
<> 144:ef7eb2e8f9f7 876 {
<> 144:ef7eb2e8f9f7 877 uint32_t wait_loop_index = 0;
<> 144:ef7eb2e8f9f7 878
<> 144:ef7eb2e8f9f7 879 /* Clear LPR bit */
<> 144:ef7eb2e8f9f7 880 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
<> 144:ef7eb2e8f9f7 881
<> 144:ef7eb2e8f9f7 882 /* Wait until REGLPF is reset */
<> 144:ef7eb2e8f9f7 883 wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000));
<> 144:ef7eb2e8f9f7 884 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)))
<> 144:ef7eb2e8f9f7 885 {
<> 144:ef7eb2e8f9f7 886 wait_loop_index--;
<> 144:ef7eb2e8f9f7 887 }
<> 144:ef7eb2e8f9f7 888 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
<> 144:ef7eb2e8f9f7 889 {
<> 144:ef7eb2e8f9f7 890 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 891 }
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 return HAL_OK;
<> 144:ef7eb2e8f9f7 894 }
<> 144:ef7eb2e8f9f7 895
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /**
<> 144:ef7eb2e8f9f7 898 * @brief Enter Stop 0 mode.
<> 144:ef7eb2e8f9f7 899 * @note In Stop 0 mode, main and low voltage regulators are ON.
<> 144:ef7eb2e8f9f7 900 * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode.
<> 144:ef7eb2e8f9f7 901 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
<> 144:ef7eb2e8f9f7 902 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
<> 144:ef7eb2e8f9f7 903 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
<> 144:ef7eb2e8f9f7 904 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
<> 144:ef7eb2e8f9f7 905 * only to the peripheral requesting it.
<> 144:ef7eb2e8f9f7 906 * SRAM1, SRAM2 and register contents are preserved.
<> 144:ef7eb2e8f9f7 907 * The BOR is available.
<> 144:ef7eb2e8f9f7 908 * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event,
<> 144:ef7eb2e8f9f7 909 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
<> 144:ef7eb2e8f9f7 910 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
<> 144:ef7eb2e8f9f7 911 * @note By keeping the internal regulator ON during Stop 0 mode, the consumption
<> 144:ef7eb2e8f9f7 912 * is higher although the startup time is reduced.
<> 144:ef7eb2e8f9f7 913 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
<> 144:ef7eb2e8f9f7 914 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 915 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
<> 144:ef7eb2e8f9f7 916 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
<> 144:ef7eb2e8f9f7 917 * @retval None
<> 144:ef7eb2e8f9f7 918 */
<> 144:ef7eb2e8f9f7 919 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry)
<> 144:ef7eb2e8f9f7 920 {
<> 144:ef7eb2e8f9f7 921 /* Check the parameters */
<> 144:ef7eb2e8f9f7 922 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
<> 144:ef7eb2e8f9f7 923
<> 144:ef7eb2e8f9f7 924 /* Stop 0 mode with Main Regulator */
<> 144:ef7eb2e8f9f7 925 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0);
<> 144:ef7eb2e8f9f7 926
<> 144:ef7eb2e8f9f7 927 /* Set SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 928 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 144:ef7eb2e8f9f7 929
<> 144:ef7eb2e8f9f7 930 /* Select Stop mode entry --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 931 if(STOPEntry == PWR_STOPENTRY_WFI)
<> 144:ef7eb2e8f9f7 932 {
<> 144:ef7eb2e8f9f7 933 /* Request Wait For Interrupt */
<> 144:ef7eb2e8f9f7 934 __WFI();
<> 144:ef7eb2e8f9f7 935 }
<> 144:ef7eb2e8f9f7 936 else
<> 144:ef7eb2e8f9f7 937 {
<> 144:ef7eb2e8f9f7 938 /* Request Wait For Event */
<> 144:ef7eb2e8f9f7 939 __SEV();
<> 144:ef7eb2e8f9f7 940 __WFE();
<> 144:ef7eb2e8f9f7 941 __WFE();
<> 144:ef7eb2e8f9f7 942 }
<> 144:ef7eb2e8f9f7 943
<> 144:ef7eb2e8f9f7 944 /* Reset SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 945 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 144:ef7eb2e8f9f7 946 }
<> 144:ef7eb2e8f9f7 947
<> 144:ef7eb2e8f9f7 948
<> 144:ef7eb2e8f9f7 949 /**
<> 144:ef7eb2e8f9f7 950 * @brief Enter Stop 1 mode.
<> 144:ef7eb2e8f9f7 951 * @note In Stop 1 mode, only low power voltage regulator is ON.
<> 144:ef7eb2e8f9f7 952 * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode.
<> 144:ef7eb2e8f9f7 953 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI,
<> 144:ef7eb2e8f9f7 954 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability
<> 144:ef7eb2e8f9f7 955 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI
<> 144:ef7eb2e8f9f7 956 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated
<> 144:ef7eb2e8f9f7 957 * only to the peripheral requesting it.
<> 144:ef7eb2e8f9f7 958 * SRAM1, SRAM2 and register contents are preserved.
<> 144:ef7eb2e8f9f7 959 * The BOR is available.
<> 144:ef7eb2e8f9f7 960 * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event,
<> 144:ef7eb2e8f9f7 961 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
<> 144:ef7eb2e8f9f7 962 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
<> 144:ef7eb2e8f9f7 963 * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode.
<> 144:ef7eb2e8f9f7 964 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
<> 144:ef7eb2e8f9f7 965 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 966 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
<> 144:ef7eb2e8f9f7 967 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
<> 144:ef7eb2e8f9f7 968 * @retval None
<> 144:ef7eb2e8f9f7 969 */
<> 144:ef7eb2e8f9f7 970 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
<> 144:ef7eb2e8f9f7 971 {
<> 144:ef7eb2e8f9f7 972 /* Check the parameters */
<> 144:ef7eb2e8f9f7 973 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
<> 144:ef7eb2e8f9f7 974
<> 144:ef7eb2e8f9f7 975 /* Stop 1 mode with Low-Power Regulator */
<> 144:ef7eb2e8f9f7 976 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1);
<> 144:ef7eb2e8f9f7 977
<> 144:ef7eb2e8f9f7 978 /* Set SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 979 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 /* Select Stop mode entry --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 982 if(STOPEntry == PWR_STOPENTRY_WFI)
<> 144:ef7eb2e8f9f7 983 {
<> 144:ef7eb2e8f9f7 984 /* Request Wait For Interrupt */
<> 144:ef7eb2e8f9f7 985 __WFI();
<> 144:ef7eb2e8f9f7 986 }
<> 144:ef7eb2e8f9f7 987 else
<> 144:ef7eb2e8f9f7 988 {
<> 144:ef7eb2e8f9f7 989 /* Request Wait For Event */
<> 144:ef7eb2e8f9f7 990 __SEV();
<> 144:ef7eb2e8f9f7 991 __WFE();
<> 144:ef7eb2e8f9f7 992 __WFE();
<> 144:ef7eb2e8f9f7 993 }
<> 144:ef7eb2e8f9f7 994
<> 144:ef7eb2e8f9f7 995 /* Reset SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 996 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 144:ef7eb2e8f9f7 997 }
<> 144:ef7eb2e8f9f7 998
<> 144:ef7eb2e8f9f7 999
<> 144:ef7eb2e8f9f7 1000 /**
<> 144:ef7eb2e8f9f7 1001 * @brief Enter Stop 2 mode.
<> 144:ef7eb2e8f9f7 1002 * @note In Stop 2 mode, only low power voltage regulator is ON.
<> 144:ef7eb2e8f9f7 1003 * @note In Stop 2 mode, all I/O pins keep the same state as in Run mode.
<> 144:ef7eb2e8f9f7 1004 * @note All clocks in the VCORE domain are stopped, the PLL, the MSI,
<> 144:ef7eb2e8f9f7 1005 * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability
<> 144:ef7eb2e8f9f7 1006 * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after
<> 144:ef7eb2e8f9f7 1007 * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only
<> 144:ef7eb2e8f9f7 1008 * to the peripheral requesting it.
<> 144:ef7eb2e8f9f7 1009 * SRAM1, SRAM2 and register contents are preserved.
<> 144:ef7eb2e8f9f7 1010 * The BOR is available.
<> 144:ef7eb2e8f9f7 1011 * The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode.
<> 144:ef7eb2e8f9f7 1012 * Otherwise, Stop 1 mode is entered.
<> 144:ef7eb2e8f9f7 1013 * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event,
<> 144:ef7eb2e8f9f7 1014 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
<> 144:ef7eb2e8f9f7 1015 * is set; the MSI oscillator is selected if STOPWUCK is cleared.
<> 144:ef7eb2e8f9f7 1016 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
<> 144:ef7eb2e8f9f7 1017 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1018 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction
<> 144:ef7eb2e8f9f7 1019 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction
<> 144:ef7eb2e8f9f7 1020 * @retval None
<> 144:ef7eb2e8f9f7 1021 */
<> 144:ef7eb2e8f9f7 1022 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry)
<> 144:ef7eb2e8f9f7 1023 {
<> 144:ef7eb2e8f9f7 1024 /* Check the parameter */
<> 144:ef7eb2e8f9f7 1025 assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
<> 144:ef7eb2e8f9f7 1026
<> 144:ef7eb2e8f9f7 1027 /* Set Stop mode 2 */
<> 144:ef7eb2e8f9f7 1028 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP2);
<> 144:ef7eb2e8f9f7 1029
<> 144:ef7eb2e8f9f7 1030 /* Set SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 1031 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 144:ef7eb2e8f9f7 1032
<> 144:ef7eb2e8f9f7 1033 /* Select Stop mode entry --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1034 if(STOPEntry == PWR_STOPENTRY_WFI)
<> 144:ef7eb2e8f9f7 1035 {
<> 144:ef7eb2e8f9f7 1036 /* Request Wait For Interrupt */
<> 144:ef7eb2e8f9f7 1037 __WFI();
<> 144:ef7eb2e8f9f7 1038 }
<> 144:ef7eb2e8f9f7 1039 else
<> 144:ef7eb2e8f9f7 1040 {
<> 144:ef7eb2e8f9f7 1041 /* Request Wait For Event */
<> 144:ef7eb2e8f9f7 1042 __SEV();
<> 144:ef7eb2e8f9f7 1043 __WFE();
<> 144:ef7eb2e8f9f7 1044 __WFE();
<> 144:ef7eb2e8f9f7 1045 }
<> 144:ef7eb2e8f9f7 1046
<> 144:ef7eb2e8f9f7 1047 /* Reset SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 1048 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 144:ef7eb2e8f9f7 1049 }
<> 144:ef7eb2e8f9f7 1050
<> 144:ef7eb2e8f9f7 1051
<> 144:ef7eb2e8f9f7 1052
<> 144:ef7eb2e8f9f7 1053
<> 144:ef7eb2e8f9f7 1054
<> 144:ef7eb2e8f9f7 1055 /**
<> 144:ef7eb2e8f9f7 1056 * @brief Enter Shutdown mode.
<> 144:ef7eb2e8f9f7 1057 * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched
<> 144:ef7eb2e8f9f7 1058 * off. The voltage regulator is disabled and Vcore domain is powered off.
<> 144:ef7eb2e8f9f7 1059 * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain.
<> 144:ef7eb2e8f9f7 1060 * The BOR is not available.
<> 144:ef7eb2e8f9f7 1061 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
<> 144:ef7eb2e8f9f7 1062 * @retval None
<> 144:ef7eb2e8f9f7 1063 */
<> 144:ef7eb2e8f9f7 1064 void HAL_PWREx_EnterSHUTDOWNMode(void)
<> 144:ef7eb2e8f9f7 1065 {
<> 144:ef7eb2e8f9f7 1066
<> 144:ef7eb2e8f9f7 1067 /* Set Shutdown mode */
<> 144:ef7eb2e8f9f7 1068 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN);
<> 144:ef7eb2e8f9f7 1069
<> 144:ef7eb2e8f9f7 1070 /* Set SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 1071 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 144:ef7eb2e8f9f7 1072
<> 144:ef7eb2e8f9f7 1073 /* This option is used to ensure that store operations are completed */
<> 144:ef7eb2e8f9f7 1074 #if defined ( __CC_ARM)
<> 144:ef7eb2e8f9f7 1075 __force_stores();
<> 144:ef7eb2e8f9f7 1076 #endif
<> 144:ef7eb2e8f9f7 1077 /* Request Wait For Interrupt */
<> 144:ef7eb2e8f9f7 1078 __WFI();
<> 144:ef7eb2e8f9f7 1079 }
<> 144:ef7eb2e8f9f7 1080
<> 144:ef7eb2e8f9f7 1081
<> 144:ef7eb2e8f9f7 1082
<> 144:ef7eb2e8f9f7 1083
<> 144:ef7eb2e8f9f7 1084 /**
<> 144:ef7eb2e8f9f7 1085 * @brief This function handles the PWR PVD/PVMx interrupt request.
<> 144:ef7eb2e8f9f7 1086 * @note This API should be called under the PVD_PVM_IRQHandler().
<> 144:ef7eb2e8f9f7 1087 * @retval None
<> 144:ef7eb2e8f9f7 1088 */
<> 144:ef7eb2e8f9f7 1089 void HAL_PWREx_PVD_PVM_IRQHandler(void)
<> 144:ef7eb2e8f9f7 1090 {
<> 144:ef7eb2e8f9f7 1091 /* Check PWR exti flag */
<> 144:ef7eb2e8f9f7 1092 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
<> 144:ef7eb2e8f9f7 1093 {
<> 144:ef7eb2e8f9f7 1094 /* PWR PVD interrupt user callback */
<> 144:ef7eb2e8f9f7 1095 HAL_PWR_PVDCallback();
<> 144:ef7eb2e8f9f7 1096
<> 144:ef7eb2e8f9f7 1097 /* Clear PVD exti pending bit */
<> 144:ef7eb2e8f9f7 1098 __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
<> 144:ef7eb2e8f9f7 1099 }
<> 144:ef7eb2e8f9f7 1100 /* Next, successively check PVMx exti flags */
<> 144:ef7eb2e8f9f7 1101 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
<> 144:ef7eb2e8f9f7 1102 if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != RESET)
<> 144:ef7eb2e8f9f7 1103 {
<> 144:ef7eb2e8f9f7 1104 /* PWR PVM1 interrupt user callback */
<> 144:ef7eb2e8f9f7 1105 HAL_PWREx_PVM1Callback();
<> 144:ef7eb2e8f9f7 1106
<> 144:ef7eb2e8f9f7 1107 /* Clear PVM1 exti pending bit */
<> 144:ef7eb2e8f9f7 1108 __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();
<> 144:ef7eb2e8f9f7 1109 }
<> 144:ef7eb2e8f9f7 1110 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
<> 144:ef7eb2e8f9f7 1111 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
<> 144:ef7eb2e8f9f7 1112 if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != RESET)
<> 144:ef7eb2e8f9f7 1113 {
<> 144:ef7eb2e8f9f7 1114 /* PWR PVM2 interrupt user callback */
<> 144:ef7eb2e8f9f7 1115 HAL_PWREx_PVM2Callback();
<> 144:ef7eb2e8f9f7 1116
<> 144:ef7eb2e8f9f7 1117 /* Clear PVM2 exti pending bit */
<> 144:ef7eb2e8f9f7 1118 __HAL_PWR_PVM2_EXTI_CLEAR_FLAG();
<> 144:ef7eb2e8f9f7 1119 }
<> 144:ef7eb2e8f9f7 1120 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
<> 144:ef7eb2e8f9f7 1121 if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != RESET)
<> 144:ef7eb2e8f9f7 1122 {
<> 144:ef7eb2e8f9f7 1123 /* PWR PVM3 interrupt user callback */
<> 144:ef7eb2e8f9f7 1124 HAL_PWREx_PVM3Callback();
<> 144:ef7eb2e8f9f7 1125
<> 144:ef7eb2e8f9f7 1126 /* Clear PVM3 exti pending bit */
<> 144:ef7eb2e8f9f7 1127 __HAL_PWR_PVM3_EXTI_CLEAR_FLAG();
<> 144:ef7eb2e8f9f7 1128 }
<> 144:ef7eb2e8f9f7 1129 if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != RESET)
<> 144:ef7eb2e8f9f7 1130 {
<> 144:ef7eb2e8f9f7 1131 /* PWR PVM4 interrupt user callback */
<> 144:ef7eb2e8f9f7 1132 HAL_PWREx_PVM4Callback();
<> 144:ef7eb2e8f9f7 1133
<> 144:ef7eb2e8f9f7 1134 /* Clear PVM4 exti pending bit */
<> 144:ef7eb2e8f9f7 1135 __HAL_PWR_PVM4_EXTI_CLEAR_FLAG();
<> 144:ef7eb2e8f9f7 1136 }
<> 144:ef7eb2e8f9f7 1137 }
<> 144:ef7eb2e8f9f7 1138
<> 144:ef7eb2e8f9f7 1139
<> 144:ef7eb2e8f9f7 1140 #if defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
<> 144:ef7eb2e8f9f7 1141 /**
<> 144:ef7eb2e8f9f7 1142 * @brief PWR PVM1 interrupt callback
<> 144:ef7eb2e8f9f7 1143 * @retval None
<> 144:ef7eb2e8f9f7 1144 */
<> 144:ef7eb2e8f9f7 1145 __weak void HAL_PWREx_PVM1Callback(void)
<> 144:ef7eb2e8f9f7 1146 {
<> 144:ef7eb2e8f9f7 1147 /* NOTE : This function should not be modified; when the callback is needed,
<> 144:ef7eb2e8f9f7 1148 HAL_PWREx_PVM1Callback() API can be implemented in the user file
<> 144:ef7eb2e8f9f7 1149 */
<> 144:ef7eb2e8f9f7 1150 }
<> 144:ef7eb2e8f9f7 1151 #endif /* defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
<> 144:ef7eb2e8f9f7 1152
<> 144:ef7eb2e8f9f7 1153 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
<> 144:ef7eb2e8f9f7 1154 /**
<> 144:ef7eb2e8f9f7 1155 * @brief PWR PVM2 interrupt callback
<> 144:ef7eb2e8f9f7 1156 * @retval None
<> 144:ef7eb2e8f9f7 1157 */
<> 144:ef7eb2e8f9f7 1158 __weak void HAL_PWREx_PVM2Callback(void)
<> 144:ef7eb2e8f9f7 1159 {
<> 144:ef7eb2e8f9f7 1160 /* NOTE : This function should not be modified; when the callback is needed,
<> 144:ef7eb2e8f9f7 1161 HAL_PWREx_PVM2Callback() API can be implemented in the user file
<> 144:ef7eb2e8f9f7 1162 */
<> 144:ef7eb2e8f9f7 1163 }
<> 144:ef7eb2e8f9f7 1164 #endif /* defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
<> 144:ef7eb2e8f9f7 1165
<> 144:ef7eb2e8f9f7 1166 /**
<> 144:ef7eb2e8f9f7 1167 * @brief PWR PVM3 interrupt callback
<> 144:ef7eb2e8f9f7 1168 * @retval None
<> 144:ef7eb2e8f9f7 1169 */
<> 144:ef7eb2e8f9f7 1170 __weak void HAL_PWREx_PVM3Callback(void)
<> 144:ef7eb2e8f9f7 1171 {
<> 144:ef7eb2e8f9f7 1172 /* NOTE : This function should not be modified; when the callback is needed,
<> 144:ef7eb2e8f9f7 1173 HAL_PWREx_PVM3Callback() API can be implemented in the user file
<> 144:ef7eb2e8f9f7 1174 */
<> 144:ef7eb2e8f9f7 1175 }
<> 144:ef7eb2e8f9f7 1176
<> 144:ef7eb2e8f9f7 1177 /**
<> 144:ef7eb2e8f9f7 1178 * @brief PWR PVM4 interrupt callback
<> 144:ef7eb2e8f9f7 1179 * @retval None
<> 144:ef7eb2e8f9f7 1180 */
<> 144:ef7eb2e8f9f7 1181 __weak void HAL_PWREx_PVM4Callback(void)
<> 144:ef7eb2e8f9f7 1182 {
<> 144:ef7eb2e8f9f7 1183 /* NOTE : This function should not be modified; when the callback is needed,
<> 144:ef7eb2e8f9f7 1184 HAL_PWREx_PVM4Callback() API can be implemented in the user file
<> 144:ef7eb2e8f9f7 1185 */
<> 144:ef7eb2e8f9f7 1186 }
<> 144:ef7eb2e8f9f7 1187
<> 144:ef7eb2e8f9f7 1188
<> 144:ef7eb2e8f9f7 1189 /**
<> 144:ef7eb2e8f9f7 1190 * @}
<> 144:ef7eb2e8f9f7 1191 */
<> 144:ef7eb2e8f9f7 1192
<> 144:ef7eb2e8f9f7 1193 /**
<> 144:ef7eb2e8f9f7 1194 * @}
<> 144:ef7eb2e8f9f7 1195 */
<> 144:ef7eb2e8f9f7 1196
<> 144:ef7eb2e8f9f7 1197 #endif /* HAL_PWR_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1198 /**
<> 144:ef7eb2e8f9f7 1199 * @}
<> 144:ef7eb2e8f9f7 1200 */
<> 144:ef7eb2e8f9f7 1201
<> 144:ef7eb2e8f9f7 1202 /**
<> 144:ef7eb2e8f9f7 1203 * @}
<> 144:ef7eb2e8f9f7 1204 */
<> 144:ef7eb2e8f9f7 1205
<> 144:ef7eb2e8f9f7 1206 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/