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targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_adc_ex.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:: <>
Date:: Fri Sep 02 15:07:44 2016 +0100
Revision:: 144:ef7eb2e8f9f7
Parent:: 0:9b334a45a8ff

This updates the lib to the mbed lib v125

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32l4xx_hal_adc_ex.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.5.1
<>	144:ef7eb2e8f9f7	6	* @date 31-May-2016
<>	144:ef7eb2e8f9f7	7	* @brief Header file of ADC HAL extended module.
<>	144:ef7eb2e8f9f7	8	******************************************************************************
<>	144:ef7eb2e8f9f7	9	* @attention
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	12	*
<>	144:ef7eb2e8f9f7	13	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	14	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	18	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	19	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	21	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	22	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	23	*
<>	144:ef7eb2e8f9f7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	34	*
<>	144:ef7eb2e8f9f7	35	******************************************************************************
<>	144:ef7eb2e8f9f7	36	*/
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	39	#ifndef __STM32L4xx_ADC_EX_H
<>	144:ef7eb2e8f9f7	40	#define __STM32L4xx_ADC_EX_H
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	43	extern "C" {
<>	144:ef7eb2e8f9f7	44	#endif
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	47	#include "stm32l4xx_hal_def.h"
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	/** @addtogroup STM32L4xx_HAL_Driver
<>	144:ef7eb2e8f9f7	50	* @{
<>	144:ef7eb2e8f9f7	51	*/
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	/** @addtogroup ADCEx ADCEx
<>	144:ef7eb2e8f9f7	54	* @{
<>	144:ef7eb2e8f9f7	55	*/
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	58	/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
<>	144:ef7eb2e8f9f7	59	* @{
<>	144:ef7eb2e8f9f7	60	*/
<>	144:ef7eb2e8f9f7	61
<>	144:ef7eb2e8f9f7	62	/**
<>	144:ef7eb2e8f9f7	63	* @brief Structure definition of ADC initialization and regular group
<>	144:ef7eb2e8f9f7	64	* @note Parameters of this structure are shared within 2 scopes:
<>	144:ef7eb2e8f9f7	65	* - Scope entire ADC (affects regular and injected groups): ClockPrescaler and ClockDivider, Resolution, DataAlign,
<>	144:ef7eb2e8f9f7	66	* ScanConvMode, EOCSelection, LowPowerAutoWait.
<>	144:ef7eb2e8f9f7	67	* - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge,
<>	144:ef7eb2e8f9f7	68	* ExternalTrigConv, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
<>	144:ef7eb2e8f9f7	69	* @note The setting of these parameters by function HAL_ADC_Init() is conditioned by ADC state.
<>	144:ef7eb2e8f9f7	70	* ADC state can be either:
<>	144:ef7eb2e8f9f7	71	* - For all parameters: ADC disabled
<>	144:ef7eb2e8f9f7	72	* - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on regular group.
<>	144:ef7eb2e8f9f7	73	* - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on regular and injected groups.
<>	144:ef7eb2e8f9f7	74	* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
<>	144:ef7eb2e8f9f7	75	* without error reporting (as it can be the expected behaviour in case of intended action to update another parameter
<>	144:ef7eb2e8f9f7	76	* (which fulfills the ADC state condition) on the fly).
<>	144:ef7eb2e8f9f7	77	*/
<>	144:ef7eb2e8f9f7	78	typedef struct
<>	144:ef7eb2e8f9f7	79	{
<>	144:ef7eb2e8f9f7	80	uint32_t ClockPrescaler; /*!< Selects ADC clock source (asynchronous System/PLLSAI1/PLLSAI2 clocks or synchronous AHB clock) as well as
<>	144:ef7eb2e8f9f7	81	the division factor applied to the clock.
<>	144:ef7eb2e8f9f7	82	This parameter can be a value of @ref ADC_ClockPrescaler.
<>	144:ef7eb2e8f9f7	83	Note: The clock is common for all the ADCs.
<>	144:ef7eb2e8f9f7	84	Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
<>	144:ef7eb2e8f9f7	85	AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
<>	144:ef7eb2e8f9f7	86	Note: In case of usage of the ADC dedicated PLL clock, this clock must be preliminarily enabled and prescaler set at RCC top level.
<>	144:ef7eb2e8f9f7	87	Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only if the AHB clock prescaler is set to 1
<>	144:ef7eb2e8f9f7	88	and if the system clock has a 50% duty cycle.
<>	144:ef7eb2e8f9f7	89	Note: This parameter can be modified only if all ADCs are disabled. */
<>	144:ef7eb2e8f9f7	90
<>	144:ef7eb2e8f9f7	91	uint32_t Resolution; /*!< Configures the ADC resolution.
<>	144:ef7eb2e8f9f7	92	This parameter can be a value of @ref ADC_Resolution */
<>	144:ef7eb2e8f9f7	93
<>	144:ef7eb2e8f9f7	94	uint32_t DataAlign; /*!< Specifies ADC data alignment (right or left).
<>	144:ef7eb2e8f9f7	95	See reference manual for alignments formats versus resolutions.
<>	144:ef7eb2e8f9f7	96	This parameter can be a value of @ref ADC_Data_align */
<>	144:ef7eb2e8f9f7	97
<>	144:ef7eb2e8f9f7	98	uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
<>	144:ef7eb2e8f9f7	99	This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
<>	144:ef7eb2e8f9f7	100	If disabled: Conversion is performed in single mode (one channel converted, that defined in rank 1).
<>	144:ef7eb2e8f9f7	101	Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
<>	144:ef7eb2e8f9f7	102	If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or'InjectedNbrOfConversion').
<>	144:ef7eb2e8f9f7	103	Scan direction is upward: from rank 1 to rank 'n'.
<>	144:ef7eb2e8f9f7	104	This parameter can be a value of @ref ADC_Scan_mode */
<>	144:ef7eb2e8f9f7	105
<>	144:ef7eb2e8f9f7	106	uint32_t EOCSelection; /*!< Specifies which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
<>	144:ef7eb2e8f9f7	107	This parameter can be a value of @ref ADC_EOCSelection. */
<>	144:ef7eb2e8f9f7	108
<>	144:ef7eb2e8f9f7	109	uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous
<>	144:ef7eb2e8f9f7	110	conversion (for regular group) or previous sequence (for injected group) has been processed by user software
<>	144:ef7eb2e8f9f7	111	(EOC bit cleared or DR read for regular conversions, JEOS cleared for injected conversions).
<>	144:ef7eb2e8f9f7	112	This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun
<>	144:ef7eb2e8f9f7	113	for low frequency applications.
<>	144:ef7eb2e8f9f7	114	This parameter can be set to ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	115	Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA(), HAL_ADCEx_InjectedStart_IT()) when it is necessary
<>	144:ef7eb2e8f9f7	116	to clear immediately the EOC flag to free the IRQ vector sequencer.
<>	144:ef7eb2e8f9f7	117	Do use with polling: 1. Start conversion with HAL_ADC_Start() or HAL_ADCEx_InjectedStart(), 2. When conversion data is available: use
<>	144:ef7eb2e8f9f7	118	HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another
<>	144:ef7eb2e8f9f7	119	conversion. For injected conversion, resort to HAL_ADCEx_InjectedPollForConversion() then HAL_ADCEx_InjectedGetValue() */
<>	144:ef7eb2e8f9f7	120
<>	144:ef7eb2e8f9f7	121	uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
<>	144:ef7eb2e8f9f7	122	after software start or external trigger occurred.
<>	144:ef7eb2e8f9f7	123	This parameter can be set to ENABLE or DISABLE. */
<>	144:ef7eb2e8f9f7	124
<>	144:ef7eb2e8f9f7	125	uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
<>	144:ef7eb2e8f9f7	126	To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
<>	144:ef7eb2e8f9f7	127	This parameter must be a number between Min_Data = 1 and Max_Data = 16.
<>	144:ef7eb2e8f9f7	128	Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without
<>	144:ef7eb2e8f9f7	129	continuous mode or external trigger that could launch a conversion). */
<>	144:ef7eb2e8f9f7	130
<>	144:ef7eb2e8f9f7	131	uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence
<>	144:ef7eb2e8f9f7	132	subdivided in successive parts).
<>	144:ef7eb2e8f9f7	133	Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
<>	144:ef7eb2e8f9f7	134	Discontinuous mode can be enabled only if continuous mode is disabled.
<>	144:ef7eb2e8f9f7	135	This parameter can be set to ENABLE or DISABLE. */
<>	144:ef7eb2e8f9f7	136
<>	144:ef7eb2e8f9f7	137	uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
<>	144:ef7eb2e8f9f7	138	If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
<>	144:ef7eb2e8f9f7	139	This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
<>	144:ef7eb2e8f9f7	140
<>	144:ef7eb2e8f9f7	141	uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
<>	144:ef7eb2e8f9f7	142	If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
<>	144:ef7eb2e8f9f7	143	This parameter can be a value of @ref ADC_Regular_External_Trigger_Source.
<>	144:ef7eb2e8f9f7	144	Caution: external trigger source is common to ADCs. */
<>	144:ef7eb2e8f9f7	145
<>	144:ef7eb2e8f9f7	146	uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
<>	144:ef7eb2e8f9f7	147	If set to ADC_EXTERNALTRIGCONVEDGE_NONE, external triggers are disabled and software trigger is used instead.
<>	144:ef7eb2e8f9f7	148	This parameter can be a value of @ref ADC_Regular_External_Trigger_Source_Edge */
<>	144:ef7eb2e8f9f7	149
<>	144:ef7eb2e8f9f7	150	uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
<>	144:ef7eb2e8f9f7	151	or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
<>	144:ef7eb2e8f9f7	152	Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
<>	144:ef7eb2e8f9f7	153	This parameter can be set to ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	154	Note: This parameter must be modified when no conversion is on going on both regular and injected groups
<>	144:ef7eb2e8f9f7	155	(ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
<>	144:ef7eb2e8f9f7	156
<>	144:ef7eb2e8f9f7	157	uint32_t Overrun; /*!< Select the behaviour in case of overrun: data overwritten or preserved (default).
<>	144:ef7eb2e8f9f7	158	This parameter applies to regular group only.
<>	144:ef7eb2e8f9f7	159	This parameter can be a value of @ref ADC_Overrun.
<>	144:ef7eb2e8f9f7	160	Note: Case of overrun set to data preserved and usage with end on conversion interruption (HAL_Start_IT()): ADC IRQ handler has to clear
<>	144:ef7eb2e8f9f7	161	end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved by user-developped function
<>	144:ef7eb2e8f9f7	162	HAL_ADC_ConvCpltCallback() (called before end of conversion flags clear).
<>	144:ef7eb2e8f9f7	163	Note: Error reporting with respect to the conversion mode:
<>	144:ef7eb2e8f9f7	164	- Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
<>	144:ef7eb2e8f9f7	165	overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
<>	144:ef7eb2e8f9f7	166	- Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
<>	144:ef7eb2e8f9f7	167
<>	144:ef7eb2e8f9f7	168	uint32_t OversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled.
<>	144:ef7eb2e8f9f7	169	This parameter can be set to ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	170	Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
<>	144:ef7eb2e8f9f7	171
<>	144:ef7eb2e8f9f7	172	ADC_OversamplingTypeDef Oversampling; /*!< Specifies the Oversampling parameters.
<>	144:ef7eb2e8f9f7	173	Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.
<>	144:ef7eb2e8f9f7	174	Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
<>	144:ef7eb2e8f9f7	175	}ADC_InitTypeDef;
<>	144:ef7eb2e8f9f7	176
<>	144:ef7eb2e8f9f7	177
<>	144:ef7eb2e8f9f7	178	/**
<>	144:ef7eb2e8f9f7	179	* @brief ADC handle Structure definition
<>	144:ef7eb2e8f9f7	180	*/
<>	144:ef7eb2e8f9f7	181	typedef struct
<>	144:ef7eb2e8f9f7	182	{
<>	144:ef7eb2e8f9f7	183	ADC_TypeDef Instance; /!< Register base address */
<>	144:ef7eb2e8f9f7	184
<>	144:ef7eb2e8f9f7	185	ADC_InitTypeDef Init; /!< ADC initialization parameters and regular conversions setting /
<>	144:ef7eb2e8f9f7	186
<>	144:ef7eb2e8f9f7	187	DMA_HandleTypeDef DMA_Handle; /!< Pointer DMA Handler */
<>	144:ef7eb2e8f9f7	188
<>	144:ef7eb2e8f9f7	189	HAL_LockTypeDef Lock; /!< ADC locking object /
<>	144:ef7eb2e8f9f7	190
<>	144:ef7eb2e8f9f7	191	__IO uint32_t State; /!< ADC communication state (bit-map of ADC states) /
<>	144:ef7eb2e8f9f7	192
<>	144:ef7eb2e8f9f7	193	__IO uint32_t ErrorCode; /!< ADC Error code /
<>	144:ef7eb2e8f9f7	194
<>	144:ef7eb2e8f9f7	195	ADC_InjectionConfigTypeDef InjectionConfig ; /!< ADC injected channel configuration build-up structure /
<>	144:ef7eb2e8f9f7	196	}ADC_HandleTypeDef;
<>	144:ef7eb2e8f9f7	197
<>	144:ef7eb2e8f9f7	198
<>	144:ef7eb2e8f9f7	199	/**
<>	144:ef7eb2e8f9f7	200	* @brief ADC Injected Conversion Oversampling structure definition
<>	144:ef7eb2e8f9f7	201	*/
<>	144:ef7eb2e8f9f7	202	typedef struct
<>	144:ef7eb2e8f9f7	203	{
<>	144:ef7eb2e8f9f7	204	uint32_t Ratio; /*!< Configures the oversampling ratio.
<>	144:ef7eb2e8f9f7	205	This parameter can be a value of @ref ADCEx_Oversampling_Ratio */
<>	144:ef7eb2e8f9f7	206
<>	144:ef7eb2e8f9f7	207	uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
<>	144:ef7eb2e8f9f7	208	This parameter can be a value of @ref ADCEx_Right_Bit_Shift */
<>	144:ef7eb2e8f9f7	209	}ADC_InjOversamplingTypeDef;
<>	144:ef7eb2e8f9f7	210
<>	144:ef7eb2e8f9f7	211
<>	144:ef7eb2e8f9f7	212
<>	144:ef7eb2e8f9f7	213	/**
<>	144:ef7eb2e8f9f7	214	* @brief Structure definition of ADC injected group and ADC channel for injected group
<>	144:ef7eb2e8f9f7	215	* @note Parameters of this structure are shared within 2 scopes:
<>	144:ef7eb2e8f9f7	216	* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
<>	144:ef7eb2e8f9f7	217	* - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
<>	144:ef7eb2e8f9f7	218	* AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConvEdge, ExternalTrigInjecConv, InjecOversamplingMode, InjecOversampling.
<>	144:ef7eb2e8f9f7	219	* @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned by ADC state.
<>	144:ef7eb2e8f9f7	220	* ADC state can be either:
<>	144:ef7eb2e8f9f7	221	* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
<>	144:ef7eb2e8f9f7	222	* - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
<>	144:ef7eb2e8f9f7	223	* - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
<>	144:ef7eb2e8f9f7	224	* - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going
<>	144:ef7eb2e8f9f7	225	* on regular and injected groups.
<>	144:ef7eb2e8f9f7	226	* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
<>	144:ef7eb2e8f9f7	227	* without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
<>	144:ef7eb2e8f9f7	228	*/
<>	144:ef7eb2e8f9f7	229	typedef struct
<>	144:ef7eb2e8f9f7	230	{
<>	144:ef7eb2e8f9f7	231	uint32_t InjectedChannel; /*!< Configure the ADC injected channel.
<>	144:ef7eb2e8f9f7	232	This parameter can be a value of @ref ADC_channels
<>	144:ef7eb2e8f9f7	233	Note: Depending on devices and ADC instances, some channels may not be available. Refer to device DataSheet for channels availability. */
<>	144:ef7eb2e8f9f7	234	uint32_t InjectedRank; /*!< The rank in the injected group sequencer.
<>	144:ef7eb2e8f9f7	235	This parameter must be a value of @ref ADCEx_injected_rank.
<>	144:ef7eb2e8f9f7	236	Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
<>	144:ef7eb2e8f9f7	237	the new channel setting (or parameter number of conversions adjusted). */
<>	144:ef7eb2e8f9f7	238	uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
<>	144:ef7eb2e8f9f7	239	Unit: ADC clock cycles.
<>	144:ef7eb2e8f9f7	240	Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits,
<>	144:ef7eb2e8f9f7	241	8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
<>	144:ef7eb2e8f9f7	242	This parameter can be a value of @ref ADC_sampling_times.
<>	144:ef7eb2e8f9f7	243	Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
<>	144:ef7eb2e8f9f7	244	It overwrites the last setting.
<>	144:ef7eb2e8f9f7	245	Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
<>	144:ef7eb2e8f9f7	246	sampling time constraints must be respected (sampling time can be adjusted with respect to the ADC clock frequency and sampling time
<>	144:ef7eb2e8f9f7	247	setting). Refer to device DataSheet for timings values. */
<>	144:ef7eb2e8f9f7	248	uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input.
<>	144:ef7eb2e8f9f7	249	In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
<>	144:ef7eb2e8f9f7	250	Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
<>	144:ef7eb2e8f9f7	251	This parameter must be a value of @ref ADCEx_SingleDifferential.
<>	144:ef7eb2e8f9f7	252	Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
<>	144:ef7eb2e8f9f7	253	It overwrites the last setting.
<>	144:ef7eb2e8f9f7	254	Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
<>	144:ef7eb2e8f9f7	255	Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
<>	144:ef7eb2e8f9f7	256	Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
<>	144:ef7eb2e8f9f7	257	If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case
<>	144:ef7eb2e8f9f7	258	of another parameter update on the fly) */
<>	144:ef7eb2e8f9f7	259	uint32_t InjectedOffsetNumber; /*!< Selects the offset number.
<>	144:ef7eb2e8f9f7	260	This parameter can be a value of @ref ADCEx_OffsetNumber.
<>	144:ef7eb2e8f9f7	261	Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
<>	144:ef7eb2e8f9f7	262	uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data.
<>	144:ef7eb2e8f9f7	263	Offset value must be a positive number.
<>	144:ef7eb2e8f9f7	264	Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
<>	144:ef7eb2e8f9f7	265	0x3FF, 0xFF or 0x3F respectively.
<>	144:ef7eb2e8f9f7	266	Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
<>	144:ef7eb2e8f9f7	267	without continuous mode or external trigger that could launch a conversion). */
<>	144:ef7eb2e8f9f7	268	uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
<>	144:ef7eb2e8f9f7	269	To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
<>	144:ef7eb2e8f9f7	270	This parameter must be a number between Min_Data = 1 and Max_Data = 4.
<>	144:ef7eb2e8f9f7	271	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<>	144:ef7eb2e8f9f7	272	configure a channel on injected group can impact the configuration of other channels previously set. */
<>	144:ef7eb2e8f9f7	273	uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence
<>	144:ef7eb2e8f9f7	274	subdivided in successive parts).
<>	144:ef7eb2e8f9f7	275	Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
<>	144:ef7eb2e8f9f7	276	Discontinuous mode can be enabled only if continuous mode is disabled.
<>	144:ef7eb2e8f9f7	277	This parameter can be set to ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	278	Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
<>	144:ef7eb2e8f9f7	279	Note: For injected group, discontinuous mode converts the sequence channel by channel (only one channel at a time).
<>	144:ef7eb2e8f9f7	280	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<>	144:ef7eb2e8f9f7	281	configure a channel on injected group can impact the configuration of other channels previously set. */
<>	144:ef7eb2e8f9f7	282	uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
<>	144:ef7eb2e8f9f7	283	This parameter can be set to ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	284	Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
<>	144:ef7eb2e8f9f7	285	Note: To use Automatic injected conversion, injected group external triggers must be disabled.
<>	144:ef7eb2e8f9f7	286	Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
<>	144:ef7eb2e8f9f7	287	To maintain JAUTO always enabled, DMA must be configured in circular mode.
<>	144:ef7eb2e8f9f7	288	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<>	144:ef7eb2e8f9f7	289	configure a channel on injected group can impact the configuration of other channels previously set. */
<>	144:ef7eb2e8f9f7	290	uint32_t QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled.
<>	144:ef7eb2e8f9f7	291	This parameter can be set to ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	292	If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
<>	144:ef7eb2e8f9f7	293	new injected context is set when queue is full, error is triggered by interruption and through function
<>	144:ef7eb2e8f9f7	294	'HAL_ADCEx_InjectedQueueOverflowCallback'.
<>	144:ef7eb2e8f9f7	295	Caution: This feature request that the sequence is fully configured before injected conversion start.
<>	144:ef7eb2e8f9f7	296	Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter.
<>	144:ef7eb2e8f9f7	297	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<>	144:ef7eb2e8f9f7	298	configure a channel on injected group can impact the configuration of other channels previously set.
<>	144:ef7eb2e8f9f7	299	Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
<>	144:ef7eb2e8f9f7	300	uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
<>	144:ef7eb2e8f9f7	301	If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
<>	144:ef7eb2e8f9f7	302	This parameter can be a value of @ref ADCEx_Injected_External_Trigger_Source.
<>	144:ef7eb2e8f9f7	303	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<>	144:ef7eb2e8f9f7	304	configure a channel on injected group can impact the configuration of other channels previously set. */
<>	144:ef7eb2e8f9f7	305	uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
<>	144:ef7eb2e8f9f7	306	This parameter can be a value of @ref ADCEx_Injected_External_Trigger_Source_Edge.
<>	144:ef7eb2e8f9f7	307	If trigger edge is set to ADC_EXTERNALTRIGINJECCONV_EDGE_NONE, external triggers are disabled and software trigger is used instead.
<>	144:ef7eb2e8f9f7	308	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
<>	144:ef7eb2e8f9f7	309	configure a channel on injected group can impact the configuration of other channels previously set. */
<>	144:ef7eb2e8f9f7	310
<>	144:ef7eb2e8f9f7	311	uint32_t InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled.
<>	144:ef7eb2e8f9f7	312	This parameter can be set to ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	313	Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
<>	144:ef7eb2e8f9f7	314
<>	144:ef7eb2e8f9f7	315	ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters.
<>	144:ef7eb2e8f9f7	316	Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.
<>	144:ef7eb2e8f9f7	317	Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
<>	144:ef7eb2e8f9f7	318	}ADC_InjectionConfTypeDef;
<>	144:ef7eb2e8f9f7	319
<>	144:ef7eb2e8f9f7	320
<>	144:ef7eb2e8f9f7	321	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx)
<>	144:ef7eb2e8f9f7	322	/**
<>	144:ef7eb2e8f9f7	323	* @brief Structure definition of ADC multimode
<>	144:ef7eb2e8f9f7	324	* @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs).
<>	144:ef7eb2e8f9f7	325	* Both Master and Slave ADCs must be disabled.
<>	144:ef7eb2e8f9f7	326	*/
<>	144:ef7eb2e8f9f7	327	typedef struct
<>	144:ef7eb2e8f9f7	328	{
<>	144:ef7eb2e8f9f7	329	uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode.
<>	144:ef7eb2e8f9f7	330	This parameter can be a value of @ref ADCEx_Common_mode. */
<>	144:ef7eb2e8f9f7	331	uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC:
<>	144:ef7eb2e8f9f7	332	selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master)
<>	144:ef7eb2e8f9f7	333	This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multimode. */
<>	144:ef7eb2e8f9f7	334	uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
<>	144:ef7eb2e8f9f7	335	This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases.
<>	144:ef7eb2e8f9f7	336	Delay range depends on selected resolution:
<>	144:ef7eb2e8f9f7	337	from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits,
<>	144:ef7eb2e8f9f7	338	from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */
<>	144:ef7eb2e8f9f7	339	}ADC_MultiModeTypeDef;
<>	144:ef7eb2e8f9f7	340	#endif /* defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) */
<>	144:ef7eb2e8f9f7	341
<>	144:ef7eb2e8f9f7	342	/**
<>	144:ef7eb2e8f9f7	343	* @}
<>	144:ef7eb2e8f9f7	344	*/
<>	144:ef7eb2e8f9f7	345
<>	144:ef7eb2e8f9f7	346	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	347
<>	144:ef7eb2e8f9f7	348	/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
<>	144:ef7eb2e8f9f7	349	* @{
<>	144:ef7eb2e8f9f7	350	*/
<>	144:ef7eb2e8f9f7	351
<>	144:ef7eb2e8f9f7	352	/** @defgroup ADCEx_SingleDifferential ADC Extended Single-ended/Differential input mode
<>	144:ef7eb2e8f9f7	353	* @{
<>	144:ef7eb2e8f9f7	354	*/
<>	144:ef7eb2e8f9f7	355	#define ADC_SINGLE_ENDED ((uint32_t)0x00000000) /!< ADC channel set in single-ended input mode /
<>	144:ef7eb2e8f9f7	356	#define ADC_DIFFERENTIAL_ENDED ((uint32_t)ADC_CR_ADCALDIF) /!< ADC channel set in differential mode /
<>	144:ef7eb2e8f9f7	357	/**
<>	144:ef7eb2e8f9f7	358	* @}
<>	144:ef7eb2e8f9f7	359	*/
<>	144:ef7eb2e8f9f7	360
<>	144:ef7eb2e8f9f7	361	/** @defgroup ADCEx_OffsetNumber ADC Extended Offset Number
<>	144:ef7eb2e8f9f7	362	* @{
<>	144:ef7eb2e8f9f7	363	*/
<>	144:ef7eb2e8f9f7	364	#define ADC_OFFSET_NONE ((uint32_t)0x00) /!< No offset correction /
<>	144:ef7eb2e8f9f7	365	#define ADC_OFFSET_1 ((uint32_t)0x01) /!< Offset correction to apply to a first channel /
<>	144:ef7eb2e8f9f7	366	#define ADC_OFFSET_2 ((uint32_t)0x02) /!< Offset correction to apply to a second channel /
<>	144:ef7eb2e8f9f7	367	#define ADC_OFFSET_3 ((uint32_t)0x03) /!< Offset correction to apply to a third channel /
<>	144:ef7eb2e8f9f7	368	#define ADC_OFFSET_4 ((uint32_t)0x04) /!< Offset correction to apply to a fourth channel /
<>	144:ef7eb2e8f9f7	369	/**
<>	144:ef7eb2e8f9f7	370	* @}
<>	144:ef7eb2e8f9f7	371	*/
<>	144:ef7eb2e8f9f7	372
<>	144:ef7eb2e8f9f7	373	/** @defgroup ADCEx_regular_rank ADC Extended Regular Channel Rank
<>	144:ef7eb2e8f9f7	374	* @{
<>	144:ef7eb2e8f9f7	375	*/
<>	144:ef7eb2e8f9f7	376	#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) /!< ADC regular conversion rank 1 /
<>	144:ef7eb2e8f9f7	377	#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) /!< ADC regular conversion rank 2 /
<>	144:ef7eb2e8f9f7	378	#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) /!< ADC regular conversion rank 3 /
<>	144:ef7eb2e8f9f7	379	#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) /!< ADC regular conversion rank 4 /
<>	144:ef7eb2e8f9f7	380	#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) /!< ADC regular conversion rank 5 /
<>	144:ef7eb2e8f9f7	381	#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) /!< ADC regular conversion rank 6 /
<>	144:ef7eb2e8f9f7	382	#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) /!< ADC regular conversion rank 7 /
<>	144:ef7eb2e8f9f7	383	#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) /!< ADC regular conversion rank 8 /
<>	144:ef7eb2e8f9f7	384	#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) /!< ADC regular conversion rank 9 /
<>	144:ef7eb2e8f9f7	385	#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) /!< ADC regular conversion rank 10 /
<>	144:ef7eb2e8f9f7	386	#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) /!< ADC regular conversion rank 11 /
<>	144:ef7eb2e8f9f7	387	#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) /!< ADC regular conversion rank 12 /
<>	144:ef7eb2e8f9f7	388	#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) /!< ADC regular conversion rank 13 /
<>	144:ef7eb2e8f9f7	389	#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) /!< ADC regular conversion rank 14 /
<>	144:ef7eb2e8f9f7	390	#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) /!< ADC regular conversion rank 15 /
<>	144:ef7eb2e8f9f7	391	#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) /!< ADC regular conversion rank 16 /
<>	144:ef7eb2e8f9f7	392	/**
<>	144:ef7eb2e8f9f7	393	* @}
<>	144:ef7eb2e8f9f7	394	*/
<>	144:ef7eb2e8f9f7	395
<>	144:ef7eb2e8f9f7	396	/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
<>	144:ef7eb2e8f9f7	397	* @{
<>	144:ef7eb2e8f9f7	398	*/
<>	144:ef7eb2e8f9f7	399	#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) /!< ADC injected conversion rank 1 /
<>	144:ef7eb2e8f9f7	400	#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) /!< ADC injected conversion rank 2 /
<>	144:ef7eb2e8f9f7	401	#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) /!< ADC injected conversion rank 3 /
<>	144:ef7eb2e8f9f7	402	#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) /!< ADC injected conversion rank 4 /
<>	144:ef7eb2e8f9f7	403	/**injected
<>	144:ef7eb2e8f9f7	404	* @}
<>	144:ef7eb2e8f9f7	405	*/
<>	144:ef7eb2e8f9f7	406
<>	144:ef7eb2e8f9f7	407	/** @defgroup ADCEx_Injected_External_Trigger_Source_Edge ADC External Trigger Source Edge for Injected Group
<>	144:ef7eb2e8f9f7	408	* @{
<>	144:ef7eb2e8f9f7	409	*/
<>	144:ef7eb2e8f9f7	410	#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE ((uint32_t)0x00000000) /!< Injected conversions hardware trigger detection disabled /
<>	144:ef7eb2e8f9f7	411	#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING ((uint32_t)ADC_JSQR_JEXTEN_0) /!< Injected conversions hardware trigger detection on the rising edge /
<>	144:ef7eb2e8f9f7	412	#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING ((uint32_t)ADC_JSQR_JEXTEN_1) /!< Injected conversions hardware trigger detection on the falling edge /
<>	144:ef7eb2e8f9f7	413	#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING ((uint32_t)ADC_JSQR_JEXTEN) /!< Injected conversions hardware trigger detection on both the rising and falling edges /
<>	144:ef7eb2e8f9f7	414	/**
<>	144:ef7eb2e8f9f7	415	* @}
<>	144:ef7eb2e8f9f7	416	*/
<>	144:ef7eb2e8f9f7	417
<>	144:ef7eb2e8f9f7	418	/** @defgroup ADCEx_Injected_External_Trigger_Source ADC Extended External Trigger Source for Injected Group
<>	144:ef7eb2e8f9f7	419	* @{
<>	144:ef7eb2e8f9f7	420	*/
<>	144:ef7eb2e8f9f7	421	#define ADC_EXTERNALTRIGINJEC_T1_TRGO ((uint32_t)0x00000000) /!< Event 0 triggers injected group conversion start /
<>	144:ef7eb2e8f9f7	422	#define ADC_EXTERNALTRIGINJEC_T1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) /!< Event 1 triggers injected group conversion start /
<>	144:ef7eb2e8f9f7	423	#define ADC_EXTERNALTRIGINJEC_T2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) /!< Event 2 triggers injected group conversion start /
<>	144:ef7eb2e8f9f7	424	#define ADC_EXTERNALTRIGINJEC_T2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0)) /!< Event 3 triggers injected group conversion start /
<>	144:ef7eb2e8f9f7	425	#define ADC_EXTERNALTRIGINJEC_T3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2) /!< Event 4 triggers injected group conversion start /
<>	144:ef7eb2e8f9f7	426	#define ADC_EXTERNALTRIGINJEC_T4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_0)) /!< Event 5 triggers injected group conversion start /
<>	144:ef7eb2e8f9f7	427	#define ADC_EXTERNALTRIGINJEC_EXT_IT15 ((uint32_t)(ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1)) /!< Event 6 triggers injected group conversion start /
<>	144:ef7eb2e8f9f7	428	#define ADC_EXTERNALTRIGINJEC_T8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0)) /!< Event 7 triggers injected group conversion start /
<>	144:ef7eb2e8f9f7	429	#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3) /!< Event 8 triggers injected group conversion start /
<>	144:ef7eb2e8f9f7	430	#define ADC_EXTERNALTRIGINJEC_T8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_0)) /!< Event 9 triggers injected group conversion start /
<>	144:ef7eb2e8f9f7	431	#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_1)) /!< Event 10 triggers injected group conversion start /
<>	144:ef7eb2e8f9f7	432	#define ADC_EXTERNALTRIGINJEC_T3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_1 \| ADC_JSQR_JEXTSEL_0)) /!< Event 11 triggers injected group conversion start /
<>	144:ef7eb2e8f9f7	433	#define ADC_EXTERNALTRIGINJEC_T3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2)) /!< Event 12 triggers injected group conversion start /
<>	144:ef7eb2e8f9f7	434	#define ADC_EXTERNALTRIGINJEC_T3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_0)) /!< Event 13 triggers injected group conversion start /
<>	144:ef7eb2e8f9f7	435	#define ADC_EXTERNALTRIGINJEC_T6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_3 \| ADC_JSQR_JEXTSEL_2 \| ADC_JSQR_JEXTSEL_1)) /!< Event 14 triggers injected group conversion start /
<>	144:ef7eb2e8f9f7	436	#define ADC_EXTERNALTRIGINJEC_T15_TRGO ((uint32_t)ADC_JSQR_JEXTSEL) /!< Event 15 triggers injected group conversion start /
<>	144:ef7eb2e8f9f7	437
<>	144:ef7eb2e8f9f7	438	#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000001) /!< Software triggers injected group conversion start /
<>	144:ef7eb2e8f9f7	439	/**
<>	144:ef7eb2e8f9f7	440	* @}
<>	144:ef7eb2e8f9f7	441	*/
<>	144:ef7eb2e8f9f7	442
<>	144:ef7eb2e8f9f7	443	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx)
<>	144:ef7eb2e8f9f7	444	/** @defgroup ADCEx_Common_mode ADC Extended Dual ADC Mode
<>	144:ef7eb2e8f9f7	445	* @{
<>	144:ef7eb2e8f9f7	446	*/
<>	144:ef7eb2e8f9f7	447	#define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000)) /!< Independent ADC conversions mode /
<>	144:ef7eb2e8f9f7	448	#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_0)) /!< Combined regular simultaneous + injected simultaneous mode /
<>	144:ef7eb2e8f9f7	449	#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_1)) /!< Combined regular simultaneous + alternate trigger mode /
<>	144:ef7eb2e8f9f7	450	#define ADC_DUALMODE_REGINTERL_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_1 \| ADC_CCR_DUAL_0)) /!< Combined Interleaved mode + injected simultaneous mode /
<>	144:ef7eb2e8f9f7	451	#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_DUAL_2 \| ADC_CCR_DUAL_0)) /!< Injected simultaneous mode only /
<>	144:ef7eb2e8f9f7	452	#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_DUAL_2 \| ADC_CCR_DUAL_1)) /!< Regular simultaneous mode only /
<>	144:ef7eb2e8f9f7	453	#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_DUAL_2 \| ADC_CCR_DUAL_1 \| ADC_CCR_DUAL_0)) /!< Interleaved mode only /
<>	144:ef7eb2e8f9f7	454	#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_DUAL_3 \| ADC_CCR_DUAL_0)) /!< Alternate trigger mode only /
<>	144:ef7eb2e8f9f7	455	/**
<>	144:ef7eb2e8f9f7	456	* @}
<>	144:ef7eb2e8f9f7	457	*/
<>	144:ef7eb2e8f9f7	458
<>	144:ef7eb2e8f9f7	459	/** @defgroup ADCEx_Direct_memory_access_mode_for_multimode ADC Extended DMA Mode for Dual ADC Mode
<>	144:ef7eb2e8f9f7	460	* @{
<>	144:ef7eb2e8f9f7	461	*/
<>	144:ef7eb2e8f9f7	462	#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000) /!< DMA multimode disabled: each ADC uses its own DMA channel /
<>	144:ef7eb2e8f9f7	463	#define ADC_DMAACCESSMODE_12_10_BITS ((uint32_t)ADC_CCR_MDMA_1) /!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution /
<>	144:ef7eb2e8f9f7	464	#define ADC_DMAACCESSMODE_8_6_BITS ((uint32_t)ADC_CCR_MDMA) /!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution /
<>	144:ef7eb2e8f9f7	465	/**
<>	144:ef7eb2e8f9f7	466	* @}
<>	144:ef7eb2e8f9f7	467	*/
<>	144:ef7eb2e8f9f7	468
<>	144:ef7eb2e8f9f7	469	/** @defgroup ADCEx_delay_between_2_sampling_phases ADC Extended Delay Between 2 Sampling Phases
<>	144:ef7eb2e8f9f7	470	* @{
<>	144:ef7eb2e8f9f7	471	*/
<>	144:ef7eb2e8f9f7	472	#define ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)(0x00000000)) /!< 1 ADC clock cycle delay /
<>	144:ef7eb2e8f9f7	473	#define ADC_TWOSAMPLINGDELAY_2CYCLES ((uint32_t)(ADC_CCR_DELAY_0)) /!< 2 ADC clock cycles delay /
<>	144:ef7eb2e8f9f7	474	#define ADC_TWOSAMPLINGDELAY_3CYCLES ((uint32_t)(ADC_CCR_DELAY_1)) /!< 3 ADC clock cycles delay /
<>	144:ef7eb2e8f9f7	475	#define ADC_TWOSAMPLINGDELAY_4CYCLES ((uint32_t)(ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0)) /!< 4 ADC clock cycles delay /
<>	144:ef7eb2e8f9f7	476	#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)(ADC_CCR_DELAY_2)) /!< 5 ADC clock cycles delay /
<>	144:ef7eb2e8f9f7	477	#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)(ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_0)) /!< 6 ADC clock cycles delay /
<>	144:ef7eb2e8f9f7	478	#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)(ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1)) /!< 7 ADC clock cycles delay (lower for non 12-bit resolution) /
<>	144:ef7eb2e8f9f7	479	#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_2 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0)) /!< 8 ADC clock cycles delay (lower for non 12-bit resolution) /
<>	144:ef7eb2e8f9f7	480	#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)(ADC_CCR_DELAY_3)) /!< 9 ADC clock cycles delay (lower for non 12-bit resolution) /
<>	144:ef7eb2e8f9f7	481	#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_0)) /!< 10 ADC clock cycles delay (lower for non 12-bit resolution) /
<>	144:ef7eb2e8f9f7	482	#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_1)) /!< 11 ADC clock cycles delay (lower for non 12-bit resolution) /
<>	144:ef7eb2e8f9f7	483	#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_3 \| ADC_CCR_DELAY_1 \| ADC_CCR_DELAY_0)) /!< 12 ADC clock cycles delay (lower for non 12-bit resolution) /
<>	144:ef7eb2e8f9f7	484	/**
<>	144:ef7eb2e8f9f7	485	* @}
<>	144:ef7eb2e8f9f7	486	*/
<>	144:ef7eb2e8f9f7	487	#elif defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx)
<>	144:ef7eb2e8f9f7	488	/** @defgroup ADCEx_Common_mode ADC Extended Independent ADC Mode
<>	144:ef7eb2e8f9f7	489	* @{
<>	144:ef7eb2e8f9f7	490	*/
<>	144:ef7eb2e8f9f7	491	#define ADC_MODE_INDEPENDENT ((uint32_t)(0x00000000)) /!< Independent ADC conversions mode /
<>	144:ef7eb2e8f9f7	492	/**
<>	144:ef7eb2e8f9f7	493	* @}
<>	144:ef7eb2e8f9f7	494	*/
<>	144:ef7eb2e8f9f7	495
<>	144:ef7eb2e8f9f7	496	#endif /* defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) */
<>	144:ef7eb2e8f9f7	497
<>	144:ef7eb2e8f9f7	498	/** @defgroup ADCEx_analog_watchdog_number ADC Extended Analog Watchdog Selection
<>	144:ef7eb2e8f9f7	499	* @{
<>	144:ef7eb2e8f9f7	500	*/
<>	144:ef7eb2e8f9f7	501	#define ADC_ANALOGWATCHDOG_1 ((uint32_t)0x00000001) /!< Analog watchdog 1 selection /
<>	144:ef7eb2e8f9f7	502	#define ADC_ANALOGWATCHDOG_2 ((uint32_t)0x00000002) /!< Analog watchdog 2 selection /
<>	144:ef7eb2e8f9f7	503	#define ADC_ANALOGWATCHDOG_3 ((uint32_t)0x00000003) /!< Analog watchdog 3 selection /
<>	144:ef7eb2e8f9f7	504	/**
<>	144:ef7eb2e8f9f7	505	* @}
<>	144:ef7eb2e8f9f7	506	*/
<>	144:ef7eb2e8f9f7	507
<>	144:ef7eb2e8f9f7	508	/** @defgroup ADCEx_analog_watchdog_mode ADC Extended Analog Watchdog Mode
<>	144:ef7eb2e8f9f7	509	* @{
<>	144:ef7eb2e8f9f7	510	*/
<>	144:ef7eb2e8f9f7	511	#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000) /!< No analog watchdog selected /
<>	144:ef7eb2e8f9f7	512	#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR_AWD1SGL \| ADC_CFGR_AWD1EN)) /!< Analog watchdog applied to a regular group single channel /
<>	144:ef7eb2e8f9f7	513	#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CFGR_AWD1SGL \| ADC_CFGR_JAWD1EN)) /!< Analog watchdog applied to an injected group single channel /
<>	144:ef7eb2e8f9f7	514	#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CFGR_AWD1SGL \| ADC_CFGR_AWD1EN \| ADC_CFGR_JAWD1EN)) /!< Analog watchdog applied to a regular and injected groups single channel /
<>	144:ef7eb2e8f9f7	515	#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR_AWD1EN) /!< Analog watchdog applied to regular group all channels /
<>	144:ef7eb2e8f9f7	516	#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CFGR_JAWD1EN) /!< Analog watchdog applied to injected group all channels /
<>	144:ef7eb2e8f9f7	517	#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CFGR_AWD1EN \| ADC_CFGR_JAWD1EN)) /!< Analog watchdog applied to regular and injected groups all channels /
<>	144:ef7eb2e8f9f7	518	/**
<>	144:ef7eb2e8f9f7	519	* @}
<>	144:ef7eb2e8f9f7	520	*/
<>	144:ef7eb2e8f9f7	521
<>	144:ef7eb2e8f9f7	522	/** @defgroup ADCEx_conversion_group ADC Extended Conversion Group
<>	144:ef7eb2e8f9f7	523	* @{
<>	144:ef7eb2e8f9f7	524	*/
<>	144:ef7eb2e8f9f7	525	#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC \| ADC_FLAG_EOS)) /!< ADC regular group selection /
<>	144:ef7eb2e8f9f7	526	#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC \| ADC_FLAG_JEOS)) /!< ADC injected group selection /
<>	144:ef7eb2e8f9f7	527	#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_JEOC \| ADC_FLAG_JEOS)) /!< ADC regular and injected groups selection /
<>	144:ef7eb2e8f9f7	528	/**
<>	144:ef7eb2e8f9f7	529	* @}
<>	144:ef7eb2e8f9f7	530	*/
<>	144:ef7eb2e8f9f7	531
<>	144:ef7eb2e8f9f7	532	/** @defgroup ADCEx_Event_type ADC Extended Event Type
<>	144:ef7eb2e8f9f7	533	* @{
<>	144:ef7eb2e8f9f7	534	*/
<>	144:ef7eb2e8f9f7	535	#define ADC_EOSMP_EVENT ((uint32_t)ADC_FLAG_EOSMP) /!< ADC End of Sampling event /
<>	144:ef7eb2e8f9f7	536	#define ADC_AWD1_EVENT ((uint32_t)ADC_FLAG_AWD1) /!< ADC Analog watchdog 1 event (main analog watchdog) /
<>	144:ef7eb2e8f9f7	537	#define ADC_AWD2_EVENT ((uint32_t)ADC_FLAG_AWD2) /!< ADC Analog watchdog 2 event (additional analog watchdog) /
<>	144:ef7eb2e8f9f7	538	#define ADC_AWD3_EVENT ((uint32_t)ADC_FLAG_AWD3) /!< ADC Analog watchdog 3 event (additional analog watchdog) /
<>	144:ef7eb2e8f9f7	539	#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /!< ADC overrun event /
<>	144:ef7eb2e8f9f7	540	#define ADC_JQOVF_EVENT ((uint32_t)ADC_FLAG_JQOVF) /!< ADC Injected Context Queue Overflow event /
<>	144:ef7eb2e8f9f7	541
<>	144:ef7eb2e8f9f7	542	#define ADC_AWD_EVENT ADC_AWD1_EVENT /!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog /
<>	144:ef7eb2e8f9f7	543	/**
<>	144:ef7eb2e8f9f7	544	* @}
<>	144:ef7eb2e8f9f7	545	*/
<>	144:ef7eb2e8f9f7	546
<>	144:ef7eb2e8f9f7	547	/** @defgroup ADCEx_interrupts_definition ADC Extended Interrupts Definition
<>	144:ef7eb2e8f9f7	548	* @{
<>	144:ef7eb2e8f9f7	549	*/
<>	144:ef7eb2e8f9f7	550	#define ADC_IT_RDY ADC_IER_ADRDY /!< ADC Ready (ADRDY) interrupt source /
<>	144:ef7eb2e8f9f7	551	#define ADC_IT_EOSMP ADC_IER_EOSMP /!< ADC End of sampling interrupt source /
<>	144:ef7eb2e8f9f7	552	#define ADC_IT_EOC ADC_IER_EOC /!< ADC End of regular conversion interrupt source /
<>	144:ef7eb2e8f9f7	553	#define ADC_IT_EOS ADC_IER_EOS /!< ADC End of regular sequence of conversions interrupt source /
<>	144:ef7eb2e8f9f7	554	#define ADC_IT_OVR ADC_IER_OVR /!< ADC overrun interrupt source /
<>	144:ef7eb2e8f9f7	555	#define ADC_IT_JEOC ADC_IER_JEOC /!< ADC End of injected conversion interrupt source /
<>	144:ef7eb2e8f9f7	556	#define ADC_IT_JEOS ADC_IER_JEOS /!< ADC End of injected sequence of conversions interrupt source /
<>	144:ef7eb2e8f9f7	557	#define ADC_IT_AWD1 ADC_IER_AWD1 /!< ADC Analog watchdog 1 interrupt source (main analog watchdog) /
<>	144:ef7eb2e8f9f7	558	#define ADC_IT_AWD2 ADC_IER_AWD2 /!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) /
<>	144:ef7eb2e8f9f7	559	#define ADC_IT_AWD3 ADC_IER_AWD3 /!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) /
<>	144:ef7eb2e8f9f7	560	#define ADC_IT_JQOVF ADC_IER_JQOVF /!< ADC Injected Context Queue Overflow interrupt source /
<>	144:ef7eb2e8f9f7	561
<>	144:ef7eb2e8f9f7	562	#define ADC_IT_AWD ADC_IT_AWD1 /!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog /
<>	144:ef7eb2e8f9f7	563
<>	144:ef7eb2e8f9f7	564	/**
<>	144:ef7eb2e8f9f7	565	* @}
<>	144:ef7eb2e8f9f7	566	*/
<>	144:ef7eb2e8f9f7	567
<>	144:ef7eb2e8f9f7	568	/** @defgroup ADCEx_flags_definition ADC Extended Flags Definition
<>	144:ef7eb2e8f9f7	569	* @{
<>	144:ef7eb2e8f9f7	570	*/
<>	144:ef7eb2e8f9f7	571	#define ADC_FLAG_RDY ADC_ISR_ADRDY /!< ADC Ready (ADRDY) flag /
<>	144:ef7eb2e8f9f7	572	#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /!< ADC End of Sampling flag /
<>	144:ef7eb2e8f9f7	573	#define ADC_FLAG_EOC ADC_ISR_EOC /!< ADC End of Regular Conversion flag /
<>	144:ef7eb2e8f9f7	574	#define ADC_FLAG_EOS ADC_ISR_EOS /!< ADC End of Regular sequence of Conversions flag /
<>	144:ef7eb2e8f9f7	575	#define ADC_FLAG_OVR ADC_ISR_OVR /!< ADC overrun flag /
<>	144:ef7eb2e8f9f7	576	#define ADC_FLAG_JEOC ADC_ISR_JEOC /!< ADC End of Injected Conversion flag /
<>	144:ef7eb2e8f9f7	577	#define ADC_FLAG_JEOS ADC_ISR_JEOS /!< ADC End of Injected sequence of Conversions flag /
<>	144:ef7eb2e8f9f7	578	#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /!< ADC Analog watchdog 1 flag (main analog watchdog) /
<>	144:ef7eb2e8f9f7	579	#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /!< ADC Analog watchdog 2 flag (additional analog watchdog) /
<>	144:ef7eb2e8f9f7	580	#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /!< ADC Analog watchdog 3 flag (additional analog watchdog) /
<>	144:ef7eb2e8f9f7	581	#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /!< ADC Injected Context Queue Overflow flag /
<>	144:ef7eb2e8f9f7	582
<>	144:ef7eb2e8f9f7	583	#define ADC_FLAG_AWD ADC_FLAG_AWD1 /!< ADC Analog watchdog 1 flag: Naming for compatibility with other STM32 devices having only one analog watchdog /
<>	144:ef7eb2e8f9f7	584
<>	144:ef7eb2e8f9f7	585	#define ADC_FLAG_ALL (ADC_FLAG_RDY \| ADC_FLAG_EOSMP \| ADC_FLAG_EOC \| ADC_FLAG_EOS \| \
<>	144:ef7eb2e8f9f7	586	ADC_FLAG_JEOC \| ADC_FLAG_JEOS \| ADC_FLAG_OVR \| ADC_FLAG_AWD1 \| \
<>	144:ef7eb2e8f9f7	587	ADC_FLAG_AWD2 \| ADC_FLAG_AWD3 \| ADC_FLAG_JQOVF) /!< ADC all flags /
<>	144:ef7eb2e8f9f7	588
<>	144:ef7eb2e8f9f7	589	/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx, JQOVF */
<>	144:ef7eb2e8f9f7	590	#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC \| ADC_FLAG_EOS \| ADC_FLAG_JEOC \| ADC_FLAG_JEOS \| \
<>	144:ef7eb2e8f9f7	591	ADC_FLAG_OVR \| ADC_FLAG_AWD1 \| ADC_FLAG_AWD2 \| ADC_FLAG_AWD3 \| \
<>	144:ef7eb2e8f9f7	592	ADC_FLAG_JQOVF) /!< ADC post-conversion all flags /
<>	144:ef7eb2e8f9f7	593
<>	144:ef7eb2e8f9f7	594	/**
<>	144:ef7eb2e8f9f7	595	* @}
<>	144:ef7eb2e8f9f7	596	*/
<>	144:ef7eb2e8f9f7	597
<>	144:ef7eb2e8f9f7	598
<>	144:ef7eb2e8f9f7	599	/** @defgroup ADCEx_injected_rank ADC Extended Injected Channel Rank
<>	144:ef7eb2e8f9f7	600	* @{
<>	144:ef7eb2e8f9f7	601	*/
<>	144:ef7eb2e8f9f7	602	#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001) /!< ADC injected conversion rank 1 /
<>	144:ef7eb2e8f9f7	603	#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002) /!< ADC injected conversion rank 2 /
<>	144:ef7eb2e8f9f7	604	#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003) /!< ADC injected conversion rank 3 /
<>	144:ef7eb2e8f9f7	605	#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004) /!< ADC injected conversion rank 4 /
<>	144:ef7eb2e8f9f7	606	/**
<>	144:ef7eb2e8f9f7	607	* @}
<>	144:ef7eb2e8f9f7	608	*/
<>	144:ef7eb2e8f9f7	609
<>	144:ef7eb2e8f9f7	610
<>	144:ef7eb2e8f9f7	611
<>	144:ef7eb2e8f9f7	612	/** @defgroup ADCEx_Oversampling_Ratio ADC Extended Oversampling Ratio
<>	144:ef7eb2e8f9f7	613	* @{
<>	144:ef7eb2e8f9f7	614	*/
<>	144:ef7eb2e8f9f7	615
<>	144:ef7eb2e8f9f7	616	#define ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000) /!< ADC Oversampling ratio 2x /
<>	144:ef7eb2e8f9f7	617	#define ADC_OVERSAMPLING_RATIO_4 ((uint32_t)ADC_CFGR2_OVSR_0) /!< ADC Oversampling ratio 4x /
<>	144:ef7eb2e8f9f7	618	#define ADC_OVERSAMPLING_RATIO_8 ((uint32_t)ADC_CFGR2_OVSR_1) /!< ADC Oversampling ratio 8x /
<>	144:ef7eb2e8f9f7	619	#define ADC_OVERSAMPLING_RATIO_16 ((uint32_t)(ADC_CFGR2_OVSR_1 \| ADC_CFGR2_OVSR_0)) /!< ADC Oversampling ratio 16x /
<>	144:ef7eb2e8f9f7	620	#define ADC_OVERSAMPLING_RATIO_32 ((uint32_t)ADC_CFGR2_OVSR_2) /!< ADC Oversampling ratio 32x /
<>	144:ef7eb2e8f9f7	621	#define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)(ADC_CFGR2_OVSR_2 \| ADC_CFGR2_OVSR_0)) /!< ADC Oversampling ratio 64x /
<>	144:ef7eb2e8f9f7	622	#define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)(ADC_CFGR2_OVSR_2 \| ADC_CFGR2_OVSR_1)) /!< ADC Oversampling ratio 128x /
<>	144:ef7eb2e8f9f7	623	#define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)(ADC_CFGR2_OVSR)) /!< ADC Oversampling ratio 256x /
<>	144:ef7eb2e8f9f7	624	/**
<>	144:ef7eb2e8f9f7	625	* @}
<>	144:ef7eb2e8f9f7	626	*/
<>	144:ef7eb2e8f9f7	627
<>	144:ef7eb2e8f9f7	628	/** @defgroup ADCEx_Right_Bit_Shift ADC Extended Oversampling Right Shift
<>	144:ef7eb2e8f9f7	629	* @{
<>	144:ef7eb2e8f9f7	630	*/
<>	144:ef7eb2e8f9f7	631	#define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000) /!< ADC No bit shift for oversampling /
<>	144:ef7eb2e8f9f7	632	#define ADC_RIGHTBITSHIFT_1 ((uint32_t)ADC_CFGR2_OVSS_0) /!< ADC 1 bit shift for oversampling /
<>	144:ef7eb2e8f9f7	633	#define ADC_RIGHTBITSHIFT_2 ((uint32_t)ADC_CFGR2_OVSS_1) /!< ADC 2 bits shift for oversampling /
<>	144:ef7eb2e8f9f7	634	#define ADC_RIGHTBITSHIFT_3 ((uint32_t)(ADC_CFGR2_OVSS_1 \| ADC_CFGR2_OVSS_0)) /!< ADC 3 bits shift for oversampling /
<>	144:ef7eb2e8f9f7	635	#define ADC_RIGHTBITSHIFT_4 ((uint32_t)ADC_CFGR2_OVSS_2) /!< ADC 4 bits shift for oversampling /
<>	144:ef7eb2e8f9f7	636	#define ADC_RIGHTBITSHIFT_5 ((uint32_t)(ADC_CFGR2_OVSS_2 \| ADC_CFGR2_OVSS_0)) /!< ADC 5 bits shift for oversampling /
<>	144:ef7eb2e8f9f7	637	#define ADC_RIGHTBITSHIFT_6 ((uint32_t)(ADC_CFGR2_OVSS_2 \| ADC_CFGR2_OVSS_1)) /!< ADC 6 bits shift for oversampling /
<>	144:ef7eb2e8f9f7	638	#define ADC_RIGHTBITSHIFT_7 ((uint32_t)(ADC_CFGR2_OVSS_2 \| ADC_CFGR2_OVSS_1 \| ADC_CFGR2_OVSS_0)) /!< ADC 7 bits shift for oversampling /
<>	144:ef7eb2e8f9f7	639	#define ADC_RIGHTBITSHIFT_8 ((uint32_t)ADC_CFGR2_OVSS_3) /!< ADC 8 bits shift for oversampling /
<>	144:ef7eb2e8f9f7	640	/**
<>	144:ef7eb2e8f9f7	641	* @}
<>	144:ef7eb2e8f9f7	642	*/
<>	144:ef7eb2e8f9f7	643
<>	144:ef7eb2e8f9f7	644	/** @defgroup ADCEx_Triggered_Oversampling_Mode ADC Extended Triggered Regular Oversampling
<>	144:ef7eb2e8f9f7	645	* @{
<>	144:ef7eb2e8f9f7	646	*/
<>	144:ef7eb2e8f9f7	647	#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000) /!< A single trigger for all channel oversampled conversions /
<>	144:ef7eb2e8f9f7	648	#define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)ADC_CFGR2_TROVS) /!< A trigger for each oversampled conversion /
<>	144:ef7eb2e8f9f7	649	/**
<>	144:ef7eb2e8f9f7	650	* @}
<>	144:ef7eb2e8f9f7	651	*/
<>	144:ef7eb2e8f9f7	652
<>	144:ef7eb2e8f9f7	653	/** @defgroup ADCEx_Regular_Oversampling_Mode ADC Extended Regular Oversampling Continued or Resumed Mode
<>	144:ef7eb2e8f9f7	654	* @{
<>	144:ef7eb2e8f9f7	655	*/
<>	144:ef7eb2e8f9f7	656	#define ADC_REGOVERSAMPLING_CONTINUED_MODE ((uint32_t)0x00000000) /!< Oversampling buffer maintained during injection sequence /
<>	144:ef7eb2e8f9f7	657	#define ADC_REGOVERSAMPLING_RESUMED_MODE ((uint32_t)ADC_CFGR2_ROVSM) /!< Oversampling buffer zeroed during injection sequence /
<>	144:ef7eb2e8f9f7	658	/**
<>	144:ef7eb2e8f9f7	659	* @}
<>	144:ef7eb2e8f9f7	660	*/
<>	144:ef7eb2e8f9f7	661
<>	144:ef7eb2e8f9f7	662	/** @defgroup ADC_sampling_times ADC Sampling Times
<>	144:ef7eb2e8f9f7	663	* @{
<>	144:ef7eb2e8f9f7	664	*/
<>	144:ef7eb2e8f9f7	665	#define ADC_SAMPLETIME_2CYCLES_5 ((uint32_t)0x00000000) /!< Sampling time 2.5 ADC clock cycle /
<>	144:ef7eb2e8f9f7	666	#define ADC_SAMPLETIME_6CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_0) /!< Sampling time 6.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	667	#define ADC_SAMPLETIME_12CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_1) /!< Sampling time 12.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	668	#define ADC_SAMPLETIME_24CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_1 \| ADC_SMPR2_SMP10_0)) /!< Sampling time 24.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	669	#define ADC_SAMPLETIME_47CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10_2) /!< Sampling time 47.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	670	#define ADC_SAMPLETIME_92CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 \| ADC_SMPR2_SMP10_0)) /!< Sampling time 92.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	671	#define ADC_SAMPLETIME_247CYCLES_5 ((uint32_t)(ADC_SMPR2_SMP10_2 \| ADC_SMPR2_SMP10_1)) /!< Sampling time 247.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	672	#define ADC_SAMPLETIME_640CYCLES_5 ((uint32_t)ADC_SMPR2_SMP10) /!< Sampling time 640.5 ADC clock cycles /
<>	144:ef7eb2e8f9f7	673	/**
<>	144:ef7eb2e8f9f7	674	* @}
<>	144:ef7eb2e8f9f7	675	*/
<>	144:ef7eb2e8f9f7	676
<>	144:ef7eb2e8f9f7	677	/** @defgroup ADC_CFGR_fields ADCx CFGR fields
<>	144:ef7eb2e8f9f7	678	* @{
<>	144:ef7eb2e8f9f7	679	*/
<>	144:ef7eb2e8f9f7	680	#define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH \| ADC_CFGR_JAUTO \| ADC_CFGR_JAWD1EN \|\
<>	144:ef7eb2e8f9f7	681	ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL \| ADC_CFGR_JQM \|\
<>	144:ef7eb2e8f9f7	682	ADC_CFGR_JDISCEN \| ADC_CFGR_DISCNUM \| ADC_CFGR_DISCEN \|\
<>	144:ef7eb2e8f9f7	683	ADC_CFGR_AUTDLY \| ADC_CFGR_CONT \| ADC_CFGR_OVRMOD \|\
<>	144:ef7eb2e8f9f7	684	ADC_CFGR_EXTEN \| ADC_CFGR_EXTSEL \| ADC_CFGR_ALIGN \|\
<>	144:ef7eb2e8f9f7	685	ADC_CFGR_RES \| ADC_CFGR_DMACFG \| ADC_CFGR_DMAEN )
<>	144:ef7eb2e8f9f7	686	/**
<>	144:ef7eb2e8f9f7	687	* @}
<>	144:ef7eb2e8f9f7	688	*/
<>	144:ef7eb2e8f9f7	689
<>	144:ef7eb2e8f9f7	690	/** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields
<>	144:ef7eb2e8f9f7	691	* @{
<>	144:ef7eb2e8f9f7	692	*/
<>	144:ef7eb2e8f9f7	693	#define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 \| ADC_SMPR1_SMP8 \| ADC_SMPR1_SMP7 \|\
<>	144:ef7eb2e8f9f7	694	ADC_SMPR1_SMP6 \| ADC_SMPR1_SMP5 \| ADC_SMPR1_SMP4 \|\
<>	144:ef7eb2e8f9f7	695	ADC_SMPR1_SMP3 \| ADC_SMPR1_SMP2 \| ADC_SMPR1_SMP1 \|\
<>	144:ef7eb2e8f9f7	696	ADC_SMPR1_SMP0)
<>	144:ef7eb2e8f9f7	697	/**
<>	144:ef7eb2e8f9f7	698	* @}
<>	144:ef7eb2e8f9f7	699	*/
<>	144:ef7eb2e8f9f7	700
<>	144:ef7eb2e8f9f7	701	/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields
<>	144:ef7eb2e8f9f7	702	* @{
<>	144:ef7eb2e8f9f7	703	*/
<>	144:ef7eb2e8f9f7	704	/* ADC_CFGR fields of parameters that can be updated when no conversion
<>	144:ef7eb2e8f9f7	705	(neither regular nor injected) is on-going */
<>	144:ef7eb2e8f9f7	706	#define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMACFG \| ADC_CFGR_AUTDLY))
<>	144:ef7eb2e8f9f7	707	/**
<>	144:ef7eb2e8f9f7	708	* @}
<>	144:ef7eb2e8f9f7	709	*/
<>	144:ef7eb2e8f9f7	710
<>	144:ef7eb2e8f9f7	711	/**
<>	144:ef7eb2e8f9f7	712	* @}
<>	144:ef7eb2e8f9f7	713	*/
<>	144:ef7eb2e8f9f7	714
<>	144:ef7eb2e8f9f7	715
<>	144:ef7eb2e8f9f7	716
<>	144:ef7eb2e8f9f7	717	/* Private macros -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	718
<>	144:ef7eb2e8f9f7	719	/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
<>	144:ef7eb2e8f9f7	720	* @{
<>	144:ef7eb2e8f9f7	721	*/
<>	144:ef7eb2e8f9f7	722
<>	144:ef7eb2e8f9f7	723	/**
<>	144:ef7eb2e8f9f7	724	* @brief Test if conversion trigger of injected group is software start
<>	144:ef7eb2e8f9f7	725	* or external trigger.
<>	144:ef7eb2e8f9f7	726	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	727	* @retval SET (software start) or RESET (external trigger).
<>	144:ef7eb2e8f9f7	728	*/
<>	144:ef7eb2e8f9f7	729	#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
<>	144:ef7eb2e8f9f7	730	(((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET)
<>	144:ef7eb2e8f9f7	731
<>	144:ef7eb2e8f9f7	732	/**
<>	144:ef7eb2e8f9f7	733	* @brief Check if conversion is on going on regular or injected groups.
<>	144:ef7eb2e8f9f7	734	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	735	* @retval SET (conversion is on going) or RESET (no conversion is on going).
<>	144:ef7eb2e8f9f7	736	*/
<>	144:ef7eb2e8f9f7	737	#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \
<>	144:ef7eb2e8f9f7	738	(( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART \| ADC_CR_JADSTART)) == RESET \
<>	144:ef7eb2e8f9f7	739	) ? RESET : SET)
<>	144:ef7eb2e8f9f7	740
<>	144:ef7eb2e8f9f7	741
<>	144:ef7eb2e8f9f7	742	/**
<>	144:ef7eb2e8f9f7	743	* @brief Check if conversion is on going on injected group.
<>	144:ef7eb2e8f9f7	744	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	745	* @retval SET (conversion is on going) or RESET (no conversion is on going).
<>	144:ef7eb2e8f9f7	746	*/
<>	144:ef7eb2e8f9f7	747	#define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \
<>	144:ef7eb2e8f9f7	748	(( (((__HANDLE__)->Instance->CR) & ADC_CR_JADSTART) == RESET \
<>	144:ef7eb2e8f9f7	749	) ? RESET : SET)
<>	144:ef7eb2e8f9f7	750
<>	144:ef7eb2e8f9f7	751
<>	144:ef7eb2e8f9f7	752
<>	144:ef7eb2e8f9f7	753	/**
<>	144:ef7eb2e8f9f7	754	* @brief Check whether or not ADC is independent.
<>	144:ef7eb2e8f9f7	755	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	756	* @note When multimode feature is not available, the macro always returns SET.
<>	144:ef7eb2e8f9f7	757	* @retval SET (ADC is independent) or RESET (ADC is not).
<>	144:ef7eb2e8f9f7	758	*/
<>	144:ef7eb2e8f9f7	759	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx)
<>	144:ef7eb2e8f9f7	760	#define ADC_IS_INDEPENDENT(__HANDLE__) \
<>	144:ef7eb2e8f9f7	761	( ( ( ((__HANDLE__)->Instance) == ADC3) \
<>	144:ef7eb2e8f9f7	762	)? \
<>	144:ef7eb2e8f9f7	763	SET \
<>	144:ef7eb2e8f9f7	764	: \
<>	144:ef7eb2e8f9f7	765	RESET \
<>	144:ef7eb2e8f9f7	766	)
<>	144:ef7eb2e8f9f7	767	#elif defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx)
<>	144:ef7eb2e8f9f7	768	#define ADC_IS_INDEPENDENT(__HANDLE__) (SET)
<>	144:ef7eb2e8f9f7	769	#endif
<>	144:ef7eb2e8f9f7	770
<>	144:ef7eb2e8f9f7	771
<>	144:ef7eb2e8f9f7	772	/**
<>	144:ef7eb2e8f9f7	773	* @brief Set the sample time for Channels numbers between 0 and 9.
<>	144:ef7eb2e8f9f7	774	* @param __SAMPLETIME__: Sample time parameter.
<>	144:ef7eb2e8f9f7	775	* @param __CHANNELNB__: Channel number.
<>	144:ef7eb2e8f9f7	776	* @retval None
<>	144:ef7eb2e8f9f7	777	*/
<>	144:ef7eb2e8f9f7	778	#define ADC_SMPR1(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << (POSITION_VAL(ADC_SMPR1_SMP1) * (__CHANNELNB__)))
<>	144:ef7eb2e8f9f7	779
<>	144:ef7eb2e8f9f7	780	/**
<>	144:ef7eb2e8f9f7	781	* @brief Set the sample time for Channels numbers between 10 and 18.
<>	144:ef7eb2e8f9f7	782	* @param __SAMPLETIME__: Sample time parameter.
<>	144:ef7eb2e8f9f7	783	* @param __CHANNELNB__: Channel number.
<>	144:ef7eb2e8f9f7	784	* @retval None
<>	144:ef7eb2e8f9f7	785	*/
<>	144:ef7eb2e8f9f7	786	#define ADC_SMPR2(__SAMPLETIME__, __CHANNELNB__) ((__SAMPLETIME__) << ((POSITION_VAL(ADC_SMPR2_SMP11) * ((__CHANNELNB__) - 10))))
<>	144:ef7eb2e8f9f7	787
<>	144:ef7eb2e8f9f7	788	/**
<>	144:ef7eb2e8f9f7	789	* @brief Write SMPR1 register.
<>	144:ef7eb2e8f9f7	790	* @param __HANDLE__ : ADC handle.
<>	144:ef7eb2e8f9f7	791	* @param __SAMPLETIME__: Sample time parameter.
<>	144:ef7eb2e8f9f7	792	* @param __CHANNELNB__ : Channel number.
<>	144:ef7eb2e8f9f7	793	* @retval None
<>	144:ef7eb2e8f9f7	794	*/
<>	144:ef7eb2e8f9f7	795	#define ADC_SMPR1_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__) \
<>	144:ef7eb2e8f9f7	796	MODIFY_REG((__HANDLE__)->Instance->SMPR1, \
<>	144:ef7eb2e8f9f7	797	ADC_SMPR1(ADC_SMPR1_SMP0, (__CHANNELNB__)), \
<>	144:ef7eb2e8f9f7	798	ADC_SMPR1((__SAMPLETIME__), (__CHANNELNB__)))
<>	144:ef7eb2e8f9f7	799
<>	144:ef7eb2e8f9f7	800	/**
<>	144:ef7eb2e8f9f7	801	* @brief Write SMPR2 register.
<>	144:ef7eb2e8f9f7	802	* @param __HANDLE__ : ADC handle.
<>	144:ef7eb2e8f9f7	803	* @param __SAMPLETIME__: Sample time parameter.
<>	144:ef7eb2e8f9f7	804	* @param __CHANNELNB__ : Channel number.
<>	144:ef7eb2e8f9f7	805	* @retval None
<>	144:ef7eb2e8f9f7	806	*/
<>	144:ef7eb2e8f9f7	807	#define ADC_SMPR2_SETTING(__HANDLE__, __SAMPLETIME__, __CHANNELNB__) \
<>	144:ef7eb2e8f9f7	808	MODIFY_REG((__HANDLE__)->Instance->SMPR2, \
<>	144:ef7eb2e8f9f7	809	ADC_SMPR2(ADC_SMPR2_SMP10, (__CHANNELNB__)), \
<>	144:ef7eb2e8f9f7	810	ADC_SMPR2((__SAMPLETIME__), (__CHANNELNB__)))
<>	144:ef7eb2e8f9f7	811
<>	144:ef7eb2e8f9f7	812
<>	144:ef7eb2e8f9f7	813	/**
<>	144:ef7eb2e8f9f7	814	* @brief Set the selected regular Channel rank for rank between 1 and 4.
<>	144:ef7eb2e8f9f7	815	* @param __CHANNELNB__: Channel number.
<>	144:ef7eb2e8f9f7	816	* @param __RANKNB__: Rank number.
<>	144:ef7eb2e8f9f7	817	* @retval None
<>	144:ef7eb2e8f9f7	818	*/
<>	144:ef7eb2e8f9f7	819	#define ADC_SQR1_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR1_SQ1) * (__RANKNB__)))
<>	144:ef7eb2e8f9f7	820
<>	144:ef7eb2e8f9f7	821	/**
<>	144:ef7eb2e8f9f7	822	* @brief Set the selected regular Channel rank for rank between 5 and 9.
<>	144:ef7eb2e8f9f7	823	* @param __CHANNELNB__: Channel number.
<>	144:ef7eb2e8f9f7	824	* @param __RANKNB__: Rank number.
<>	144:ef7eb2e8f9f7	825	* @retval None
<>	144:ef7eb2e8f9f7	826	*/
<>	144:ef7eb2e8f9f7	827	#define ADC_SQR2_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR2_SQ6) * ((__RANKNB__) - 5)))
<>	144:ef7eb2e8f9f7	828
<>	144:ef7eb2e8f9f7	829	/**
<>	144:ef7eb2e8f9f7	830	* @brief Set the selected regular Channel rank for rank between 10 and 14.
<>	144:ef7eb2e8f9f7	831	* @param __CHANNELNB__: Channel number.
<>	144:ef7eb2e8f9f7	832	* @param __RANKNB__: Rank number.
<>	144:ef7eb2e8f9f7	833	* @retval None
<>	144:ef7eb2e8f9f7	834	*/
<>	144:ef7eb2e8f9f7	835	#define ADC_SQR3_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR3_SQ11) * ((__RANKNB__) - 10)))
<>	144:ef7eb2e8f9f7	836
<>	144:ef7eb2e8f9f7	837	/**
<>	144:ef7eb2e8f9f7	838	* @brief Set the selected regular Channel rank for rank between 15 and 16.
<>	144:ef7eb2e8f9f7	839	* @param __CHANNELNB__: Channel number.
<>	144:ef7eb2e8f9f7	840	* @param __RANKNB__: Rank number.
<>	144:ef7eb2e8f9f7	841	* @retval None
<>	144:ef7eb2e8f9f7	842	*/
<>	144:ef7eb2e8f9f7	843	#define ADC_SQR4_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << (POSITION_VAL(ADC_SQR4_SQ16) * ((__RANKNB__) - 15)))
<>	144:ef7eb2e8f9f7	844
<>	144:ef7eb2e8f9f7	845	/**
<>	144:ef7eb2e8f9f7	846	* @brief Set the selected injected Channel rank.
<>	144:ef7eb2e8f9f7	847	* @param __CHANNELNB__: Channel number.
<>	144:ef7eb2e8f9f7	848	* @param __RANKNB__: Rank number.
<>	144:ef7eb2e8f9f7	849	* @retval None
<>	144:ef7eb2e8f9f7	850	*/
<>	144:ef7eb2e8f9f7	851	#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((__CHANNELNB__) << ((POSITION_VAL(ADC_JSQR_JSQ1)-2) * (__RANKNB__) +2))
<>	144:ef7eb2e8f9f7	852
<>	144:ef7eb2e8f9f7	853
<>	144:ef7eb2e8f9f7	854	/**
<>	144:ef7eb2e8f9f7	855	* @brief Set the Analog Watchdog 1 channel.
<>	144:ef7eb2e8f9f7	856	* @param __CHANNEL__: channel to be monitored by Analog Watchdog 1.
<>	144:ef7eb2e8f9f7	857	* @retval None
<>	144:ef7eb2e8f9f7	858	*/
<>	144:ef7eb2e8f9f7	859	#define ADC_CFGR_SET_AWD1CH(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_CFGR_AWD1CH))
<>	144:ef7eb2e8f9f7	860
<>	144:ef7eb2e8f9f7	861	/**
<>	144:ef7eb2e8f9f7	862	* @brief Configure the channel number in Analog Watchdog 2 or 3.
<>	144:ef7eb2e8f9f7	863	* @param __CHANNEL__: ADC Channel
<>	144:ef7eb2e8f9f7	864	* @retval None
<>	144:ef7eb2e8f9f7	865	*/
<>	144:ef7eb2e8f9f7	866	#define ADC_CFGR_SET_AWD23CR(__CHANNEL__) (1U << (__CHANNEL__))
<>	144:ef7eb2e8f9f7	867
<>	144:ef7eb2e8f9f7	868	/**
<>	144:ef7eb2e8f9f7	869	* @brief Configure ADC injected context queue
<>	144:ef7eb2e8f9f7	870	* @param __INJECT_CONTEXT_QUEUE_MODE__: Injected context queue mode.
<>	144:ef7eb2e8f9f7	871	* @retval None
<>	144:ef7eb2e8f9f7	872	*/
<>	144:ef7eb2e8f9f7	873	#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << POSITION_VAL(ADC_CFGR_JQM))
<>	144:ef7eb2e8f9f7	874
<>	144:ef7eb2e8f9f7	875	/**
<>	144:ef7eb2e8f9f7	876	* @brief Configure ADC discontinuous conversion mode for injected group
<>	144:ef7eb2e8f9f7	877	* @param __INJECT_DISCONTINUOUS_MODE__: Injected discontinuous mode.
<>	144:ef7eb2e8f9f7	878	* @retval None
<>	144:ef7eb2e8f9f7	879	*/
<>	144:ef7eb2e8f9f7	880	#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_JDISCEN))
<>	144:ef7eb2e8f9f7	881
<>	144:ef7eb2e8f9f7	882	/**
<>	144:ef7eb2e8f9f7	883	* @brief Configure ADC discontinuous conversion mode for regular group
<>	144:ef7eb2e8f9f7	884	* @param __REG_DISCONTINUOUS_MODE__: Regular discontinuous mode.
<>	144:ef7eb2e8f9f7	885	* @retval None
<>	144:ef7eb2e8f9f7	886	*/
<>	144:ef7eb2e8f9f7	887	#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_DISCEN))
<>	144:ef7eb2e8f9f7	888	/**
<>	144:ef7eb2e8f9f7	889	* @brief Configure the number of discontinuous conversions for regular group.
<>	144:ef7eb2e8f9f7	890	* @param __NBR_DISCONTINUOUS_CONV__: Number of discontinuous conversions.
<>	144:ef7eb2e8f9f7	891	* @retval None
<>	144:ef7eb2e8f9f7	892	*/
<>	144:ef7eb2e8f9f7	893	#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1) << POSITION_VAL(ADC_CFGR_DISCNUM))
<>	144:ef7eb2e8f9f7	894
<>	144:ef7eb2e8f9f7	895	/**
<>	144:ef7eb2e8f9f7	896	* @brief Configure the ADC auto delay mode.
<>	144:ef7eb2e8f9f7	897	* @param __AUTOWAIT__: Auto delay bit enable or disable.
<>	144:ef7eb2e8f9f7	898	* @retval None
<>	144:ef7eb2e8f9f7	899	*/
<>	144:ef7eb2e8f9f7	900	#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << POSITION_VAL(ADC_CFGR_AUTDLY))
<>	144:ef7eb2e8f9f7	901
<>	144:ef7eb2e8f9f7	902	/**
<>	144:ef7eb2e8f9f7	903	* @brief Configure ADC continuous conversion mode.
<>	144:ef7eb2e8f9f7	904	* @param __CONTINUOUS_MODE__: Continuous mode.
<>	144:ef7eb2e8f9f7	905	* @retval None
<>	144:ef7eb2e8f9f7	906	*/
<>	144:ef7eb2e8f9f7	907	#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << POSITION_VAL(ADC_CFGR_CONT))
<>	144:ef7eb2e8f9f7	908
<>	144:ef7eb2e8f9f7	909	/**
<>	144:ef7eb2e8f9f7	910	* @brief Configure the ADC DMA continuous request.
<>	144:ef7eb2e8f9f7	911	* @param __DMACONTREQ_MODE__: DMA continuous request mode.
<>	144:ef7eb2e8f9f7	912	* @retval None
<>	144:ef7eb2e8f9f7	913	*/
<>	144:ef7eb2e8f9f7	914	#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CFGR_DMACFG))
<>	144:ef7eb2e8f9f7	915
<>	144:ef7eb2e8f9f7	916
<>	144:ef7eb2e8f9f7	917	/**
<>	144:ef7eb2e8f9f7	918	* @brief Configure the channel number into offset OFRx register.
<>	144:ef7eb2e8f9f7	919	* @param __CHANNEL__: ADC Channel.
<>	144:ef7eb2e8f9f7	920	* @retval None
<>	144:ef7eb2e8f9f7	921	*/
<>	144:ef7eb2e8f9f7	922	#define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << POSITION_VAL(ADC_OFR1_OFFSET1_CH))
<>	144:ef7eb2e8f9f7	923
<>	144:ef7eb2e8f9f7	924	/**
<>	144:ef7eb2e8f9f7	925	* @brief Configure the channel number into differential mode selection register.
<>	144:ef7eb2e8f9f7	926	* @param __CHANNEL__: ADC Channel.
<>	144:ef7eb2e8f9f7	927	* @retval None
<>	144:ef7eb2e8f9f7	928	*/
<>	144:ef7eb2e8f9f7	929	#define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1U << (__CHANNEL__))
<>	144:ef7eb2e8f9f7	930
<>	144:ef7eb2e8f9f7	931	/**
<>	144:ef7eb2e8f9f7	932	* @brief Configure calibration factor in differential mode to be set into calibration register.
<>	144:ef7eb2e8f9f7	933	* @param __CALIBRATION_FACTOR__: Calibration factor value.
<>	144:ef7eb2e8f9f7	934	* @retval None
<>	144:ef7eb2e8f9f7	935	*/
<>	144:ef7eb2e8f9f7	936	#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D >> POSITION_VAL(ADC_CALFACT_CALFACT_D)) ) << POSITION_VAL(ADC_CALFACT_CALFACT_D))
<>	144:ef7eb2e8f9f7	937	/**
<>	144:ef7eb2e8f9f7	938	* @brief Calibration factor in differential mode to be retrieved from calibration register.
<>	144:ef7eb2e8f9f7	939	* @param __CALIBRATION_FACTOR__: Calibration factor value.
<>	144:ef7eb2e8f9f7	940	* @retval None
<>	144:ef7eb2e8f9f7	941	*/
<>	144:ef7eb2e8f9f7	942	#define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> POSITION_VAL(ADC_CALFACT_CALFACT_D))
<>	144:ef7eb2e8f9f7	943
<>	144:ef7eb2e8f9f7	944	/**
<>	144:ef7eb2e8f9f7	945	* @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
<>	144:ef7eb2e8f9f7	946	* @param __THRESHOLD__: Threshold value.
<>	144:ef7eb2e8f9f7	947	* @retval None
<>	144:ef7eb2e8f9f7	948	*/
<>	144:ef7eb2e8f9f7	949	#define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16)
<>	144:ef7eb2e8f9f7	950
<>	144:ef7eb2e8f9f7	951	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx)
<>	144:ef7eb2e8f9f7	952	/**
<>	144:ef7eb2e8f9f7	953	* @brief Configure the ADC DMA continuous request for ADC multimode.
<>	144:ef7eb2e8f9f7	954	* @param __DMACONTREQ_MODE__: DMA continuous request mode.
<>	144:ef7eb2e8f9f7	955	* @retval None
<>	144:ef7eb2e8f9f7	956	*/
<>	144:ef7eb2e8f9f7	957	#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << POSITION_VAL(ADC_CCR_DMACFG))
<>	144:ef7eb2e8f9f7	958	#endif /* defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) */
<>	144:ef7eb2e8f9f7	959
<>	144:ef7eb2e8f9f7	960	/**
<>	144:ef7eb2e8f9f7	961	* @brief Enable the ADC peripheral.
<>	144:ef7eb2e8f9f7	962	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	963	* @retval None
<>	144:ef7eb2e8f9f7	964	*/
<>	144:ef7eb2e8f9f7	965	#define ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR \|= ADC_CR_ADEN)
<>	144:ef7eb2e8f9f7	966
<>	144:ef7eb2e8f9f7	967	/**
<>	144:ef7eb2e8f9f7	968	* @brief Verification of hardware constraints before ADC can be enabled.
<>	144:ef7eb2e8f9f7	969	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	970	* @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
<>	144:ef7eb2e8f9f7	971	*/
<>	144:ef7eb2e8f9f7	972	#define ADC_ENABLING_CONDITIONS(__HANDLE__) \
<>	144:ef7eb2e8f9f7	973	(( ( ((__HANDLE__)->Instance->CR) & \
<>	144:ef7eb2e8f9f7	974	(ADC_CR_ADCAL \| ADC_CR_JADSTP \| ADC_CR_ADSTP \| ADC_CR_JADSTART \| \
<>	144:ef7eb2e8f9f7	975	ADC_CR_ADSTART \| ADC_CR_ADDIS \| ADC_CR_ADEN ) \
<>	144:ef7eb2e8f9f7	976	) == RESET \
<>	144:ef7eb2e8f9f7	977	) ? SET : RESET)
<>	144:ef7eb2e8f9f7	978
<>	144:ef7eb2e8f9f7	979	/**
<>	144:ef7eb2e8f9f7	980	* @brief Disable the ADC peripheral.
<>	144:ef7eb2e8f9f7	981	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	982	* @retval None
<>	144:ef7eb2e8f9f7	983	*/
<>	144:ef7eb2e8f9f7	984	#define ADC_DISABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	985	do{ \
<>	144:ef7eb2e8f9f7	986	(__HANDLE__)->Instance->CR \|= ADC_CR_ADDIS; \
<>	144:ef7eb2e8f9f7	987	__HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP \| ADC_FLAG_RDY)); \
<>	144:ef7eb2e8f9f7	988	} while(0)
<>	144:ef7eb2e8f9f7	989
<>	144:ef7eb2e8f9f7	990	/**
<>	144:ef7eb2e8f9f7	991	* @brief Verification of hardware constraints before ADC can be disabled.
<>	144:ef7eb2e8f9f7	992	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	993	* @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
<>	144:ef7eb2e8f9f7	994	*/
<>	144:ef7eb2e8f9f7	995	#define ADC_DISABLING_CONDITIONS(__HANDLE__) \
<>	144:ef7eb2e8f9f7	996	(( ( ((__HANDLE__)->Instance->CR) & \
<>	144:ef7eb2e8f9f7	997	(ADC_CR_JADSTART \| ADC_CR_ADSTART \| ADC_CR_ADEN)) == ADC_CR_ADEN \
<>	144:ef7eb2e8f9f7	998	) ? SET : RESET)
<>	144:ef7eb2e8f9f7	999
<>	144:ef7eb2e8f9f7	1000
<>	144:ef7eb2e8f9f7	1001	/**
<>	144:ef7eb2e8f9f7	1002	* @brief Shift the offset with respect to the selected ADC resolution.
<>	144:ef7eb2e8f9f7	1003	* @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
<>	144:ef7eb2e8f9f7	1004	* If resolution 12 bits, no shift.
<>	144:ef7eb2e8f9f7	1005	* If resolution 10 bits, shift of 2 ranks on the left.
<>	144:ef7eb2e8f9f7	1006	* If resolution 8 bits, shift of 4 ranks on the left.
<>	144:ef7eb2e8f9f7	1007	* If resolution 6 bits, shift of 6 ranks on the left.
<>	144:ef7eb2e8f9f7	1008	* Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
<>	144:ef7eb2e8f9f7	1009	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	1010	* @param __OFFSET__: Value to be shifted
<>	144:ef7eb2e8f9f7	1011	* @retval None
<>	144:ef7eb2e8f9f7	1012	*/
<>	144:ef7eb2e8f9f7	1013	#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
<>	144:ef7eb2e8f9f7	1014	((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
<>	144:ef7eb2e8f9f7	1015
<>	144:ef7eb2e8f9f7	1016
<>	144:ef7eb2e8f9f7	1017	/**
<>	144:ef7eb2e8f9f7	1018	* @brief Shift the AWD1 threshold with respect to the selected ADC resolution.
<>	144:ef7eb2e8f9f7	1019	* @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
<>	144:ef7eb2e8f9f7	1020	* If resolution 12 bits, no shift.
<>	144:ef7eb2e8f9f7	1021	* If resolution 10 bits, shift of 2 ranks on the left.
<>	144:ef7eb2e8f9f7	1022	* If resolution 8 bits, shift of 4 ranks on the left.
<>	144:ef7eb2e8f9f7	1023	* If resolution 6 bits, shift of 6 ranks on the left.
<>	144:ef7eb2e8f9f7	1024	* Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
<>	144:ef7eb2e8f9f7	1025	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	1026	* @param __THRESHOLD__: Value to be shifted
<>	144:ef7eb2e8f9f7	1027	* @retval None
<>	144:ef7eb2e8f9f7	1028	*/
<>	144:ef7eb2e8f9f7	1029	#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
<>	144:ef7eb2e8f9f7	1030	((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
<>	144:ef7eb2e8f9f7	1031
<>	144:ef7eb2e8f9f7	1032	/**
<>	144:ef7eb2e8f9f7	1033	* @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
<>	144:ef7eb2e8f9f7	1034	* @note Thresholds have to be left-aligned on bit 7.
<>	144:ef7eb2e8f9f7	1035	* If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded).
<>	144:ef7eb2e8f9f7	1036	* If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded).
<>	144:ef7eb2e8f9f7	1037	* If resolution 8 bits, no shift.
<>	144:ef7eb2e8f9f7	1038	* If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0).
<>	144:ef7eb2e8f9f7	1039	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	1040	* @param __THRESHOLD__: Value to be shifted
<>	144:ef7eb2e8f9f7	1041	* @retval None
<>	144:ef7eb2e8f9f7	1042	*/
<>	144:ef7eb2e8f9f7	1043	#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
<>	144:ef7eb2e8f9f7	1044	( ((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 \| ADC_CFGR_RES_0) ? \
<>	144:ef7eb2e8f9f7	1045	((__THRESHOLD__) >> (4- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))) : \
<>	144:ef7eb2e8f9f7	1046	(__THRESHOLD__) << 2 )
<>	144:ef7eb2e8f9f7	1047
<>	144:ef7eb2e8f9f7	1048
<>	144:ef7eb2e8f9f7	1049	/**
<>	144:ef7eb2e8f9f7	1050	* @brief Report ADC common register.
<>	144:ef7eb2e8f9f7	1051	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	1052	* @retval Common control register
<>	144:ef7eb2e8f9f7	1053	*/
<>	144:ef7eb2e8f9f7	1054	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx)
<>	144:ef7eb2e8f9f7	1055	#define ADC_COMMON_REGISTER(__HANDLE__) (ADC123_COMMON)
<>	144:ef7eb2e8f9f7	1056	#elif defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx)
<>	144:ef7eb2e8f9f7	1057	#define ADC_COMMON_REGISTER(__HANDLE__) (ADC1_COMMON)
<>	144:ef7eb2e8f9f7	1058	#endif
<>	144:ef7eb2e8f9f7	1059
<>	144:ef7eb2e8f9f7	1060	/**
<>	144:ef7eb2e8f9f7	1061	* @brief Report Master Instance.
<>	144:ef7eb2e8f9f7	1062	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	1063	* @note Return same instance if ADC of input handle is independent ADC or if
<>	144:ef7eb2e8f9f7	1064	* multimode feature is not available.
<>	144:ef7eb2e8f9f7	1065	* @retval Master Instance
<>	144:ef7eb2e8f9f7	1066	*/
<>	144:ef7eb2e8f9f7	1067	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx)
<>	144:ef7eb2e8f9f7	1068	#define ADC_MASTER_REGISTER(__HANDLE__) \
<>	144:ef7eb2e8f9f7	1069	( ( ((((__HANDLE__)->Instance) == ADC1) \|\| (((__HANDLE__)->Instance) == ADC3)) \
<>	144:ef7eb2e8f9f7	1070	)? \
<>	144:ef7eb2e8f9f7	1071	((__HANDLE__)->Instance) \
<>	144:ef7eb2e8f9f7	1072	: \
<>	144:ef7eb2e8f9f7	1073	(ADC1) \
<>	144:ef7eb2e8f9f7	1074	)
<>	144:ef7eb2e8f9f7	1075	#elif defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx)
<>	144:ef7eb2e8f9f7	1076	#define ADC_MASTER_REGISTER(__HANDLE__) ((__HANDLE__)->Instance)
<>	144:ef7eb2e8f9f7	1077	#endif
<>	144:ef7eb2e8f9f7	1078
<>	144:ef7eb2e8f9f7	1079
<>	144:ef7eb2e8f9f7	1080	/**
<>	144:ef7eb2e8f9f7	1081	* @brief Clear Common Control Register.
<>	144:ef7eb2e8f9f7	1082	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	1083	* @retval None
<>	144:ef7eb2e8f9f7	1084	*/
<>	144:ef7eb2e8f9f7	1085	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx)
<>	144:ef7eb2e8f9f7	1086	#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(ADC_COMMON_REGISTER(__HANDLE__)->CCR, ADC_CCR_CKMODE \| \
<>	144:ef7eb2e8f9f7	1087	ADC_CCR_PRESC \| \
<>	144:ef7eb2e8f9f7	1088	ADC_CCR_VBATEN \| \
<>	144:ef7eb2e8f9f7	1089	ADC_CCR_TSEN \| \
<>	144:ef7eb2e8f9f7	1090	ADC_CCR_VREFEN \| \
<>	144:ef7eb2e8f9f7	1091	ADC_CCR_MDMA \| \
<>	144:ef7eb2e8f9f7	1092	ADC_CCR_DMACFG \| \
<>	144:ef7eb2e8f9f7	1093	ADC_CCR_DELAY \| \
<>	144:ef7eb2e8f9f7	1094	ADC_CCR_DUAL )
<>	144:ef7eb2e8f9f7	1095	#elif defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx)
<>	144:ef7eb2e8f9f7	1096	#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(ADC_COMMON_REGISTER(__HANDLE__)->CCR, ADC_CCR_CKMODE \| \
<>	144:ef7eb2e8f9f7	1097	ADC_CCR_PRESC \| \
<>	144:ef7eb2e8f9f7	1098	ADC_CCR_VBATEN \| \
<>	144:ef7eb2e8f9f7	1099	ADC_CCR_TSEN \| \
<>	144:ef7eb2e8f9f7	1100	ADC_CCR_VREFEN )
<>	144:ef7eb2e8f9f7	1101	#endif
<>	144:ef7eb2e8f9f7	1102
<>	144:ef7eb2e8f9f7	1103
<>	144:ef7eb2e8f9f7	1104	/**
<>	144:ef7eb2e8f9f7	1105	* @brief Check whether or not dual conversions are enabled.
<>	144:ef7eb2e8f9f7	1106	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	1107	* @note Return RESET if ADC of input handle is independent ADC or if multimode feature is not available.
<>	144:ef7eb2e8f9f7	1108	* @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)
<>	144:ef7eb2e8f9f7	1109	*/
<>	144:ef7eb2e8f9f7	1110	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx)
<>	144:ef7eb2e8f9f7	1111	#define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	1112	( ( ((((__HANDLE__)->Instance) == ADC1) \|\| (((__HANDLE__)->Instance) == ADC2)) \
<>	144:ef7eb2e8f9f7	1113	)? \
<>	144:ef7eb2e8f9f7	1114	( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) ) \
<>	144:ef7eb2e8f9f7	1115	: \
<>	144:ef7eb2e8f9f7	1116	RESET \
<>	144:ef7eb2e8f9f7	1117	)
<>	144:ef7eb2e8f9f7	1118	#elif defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx)
<>	144:ef7eb2e8f9f7	1119	#define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__) (RESET)
<>	144:ef7eb2e8f9f7	1120	#endif
<>	144:ef7eb2e8f9f7	1121
<>	144:ef7eb2e8f9f7	1122	/**
<>	144:ef7eb2e8f9f7	1123	* @brief Check whether or not dual regular conversions are enabled.
<>	144:ef7eb2e8f9f7	1124	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	1125	* @note Return RESET if ADC of input handle is independent ADC or if multimode feature is not available.
<>	144:ef7eb2e8f9f7	1126	* @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)
<>	144:ef7eb2e8f9f7	1127	*/
<>	144:ef7eb2e8f9f7	1128	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx)
<>	144:ef7eb2e8f9f7	1129	#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	1130	( ( ((((__HANDLE__)->Instance) == ADC1) \|\| (((__HANDLE__)->Instance) == ADC2)) \
<>	144:ef7eb2e8f9f7	1131	)? \
<>	144:ef7eb2e8f9f7	1132	( (((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \
<>	144:ef7eb2e8f9f7	1133	(((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \
<>	144:ef7eb2e8f9f7	1134	(((ADC_COMMON_REGISTER(__HANDLE__))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \
<>	144:ef7eb2e8f9f7	1135	: \
<>	144:ef7eb2e8f9f7	1136	RESET \
<>	144:ef7eb2e8f9f7	1137	)
<>	144:ef7eb2e8f9f7	1138	#elif defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx)
<>	144:ef7eb2e8f9f7	1139	#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) (RESET)
<>	144:ef7eb2e8f9f7	1140	#endif
<>	144:ef7eb2e8f9f7	1141
<>	144:ef7eb2e8f9f7	1142
<>	144:ef7eb2e8f9f7	1143	/**
<>	144:ef7eb2e8f9f7	1144	* @brief Verification of condition for ADC start conversion: ADC must be in non-multimode or multimode with handle of ADC master.
<>	144:ef7eb2e8f9f7	1145	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	1146	* @note Return SET if multimode feature is not available.
<>	144:ef7eb2e8f9f7	1147	* @retval SET (non-multimode or Master handle) or RESET (handle of Slave ADC in multimode)
<>	144:ef7eb2e8f9f7	1148	*/
<>	144:ef7eb2e8f9f7	1149	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx)
<>	144:ef7eb2e8f9f7	1150	#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
<>	144:ef7eb2e8f9f7	1151	( ( ((__HANDLE__)->Instance == ADC1) \|\| ((__HANDLE__)->Instance == ADC3) \
<>	144:ef7eb2e8f9f7	1152	)? \
<>	144:ef7eb2e8f9f7	1153	SET \
<>	144:ef7eb2e8f9f7	1154	: \
<>	144:ef7eb2e8f9f7	1155	((ADC123_COMMON->CCR & ADC_CCR_DUAL) == RESET) \
<>	144:ef7eb2e8f9f7	1156	)
<>	144:ef7eb2e8f9f7	1157	#elif defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx)
<>	144:ef7eb2e8f9f7	1158	#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (SET)
<>	144:ef7eb2e8f9f7	1159	#endif
<>	144:ef7eb2e8f9f7	1160
<>	144:ef7eb2e8f9f7	1161	/**
<>	144:ef7eb2e8f9f7	1162	* @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled.
<>	144:ef7eb2e8f9f7	1163	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	1164	* @note Return SET if multimode feature is not available.
<>	144:ef7eb2e8f9f7	1165	* @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled)
<>	144:ef7eb2e8f9f7	1166	*/
<>	144:ef7eb2e8f9f7	1167	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx)
<>	144:ef7eb2e8f9f7	1168	#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	1169	( ( ((__HANDLE__)->Instance == ADC1) \|\| ((__HANDLE__)->Instance == ADC3) \
<>	144:ef7eb2e8f9f7	1170	)? \
<>	144:ef7eb2e8f9f7	1171	SET \
<>	144:ef7eb2e8f9f7	1172	: \
<>	144:ef7eb2e8f9f7	1173	( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) \|\| \
<>	144:ef7eb2e8f9f7	1174	((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) \|\| \
<>	144:ef7eb2e8f9f7	1175	((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))
<>	144:ef7eb2e8f9f7	1176	#elif defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx)
<>	144:ef7eb2e8f9f7	1177	#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) (SET)
<>	144:ef7eb2e8f9f7	1178	#endif
<>	144:ef7eb2e8f9f7	1179
<>	144:ef7eb2e8f9f7	1180	/**
<>	144:ef7eb2e8f9f7	1181	* @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled.
<>	144:ef7eb2e8f9f7	1182	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	1183	* @note Return SET if multimode feature is not available.
<>	144:ef7eb2e8f9f7	1184	* @retval SET (non-multimode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled)
<>	144:ef7eb2e8f9f7	1185	*/
<>	144:ef7eb2e8f9f7	1186	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx)
<>	144:ef7eb2e8f9f7	1187	#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	1188	( ( ((__HANDLE__)->Instance == ADC1) \|\| ((__HANDLE__)->Instance == ADC3) \
<>	144:ef7eb2e8f9f7	1189	)? \
<>	144:ef7eb2e8f9f7	1190	SET \
<>	144:ef7eb2e8f9f7	1191	: \
<>	144:ef7eb2e8f9f7	1192	( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) \|\| \
<>	144:ef7eb2e8f9f7	1193	((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) \|\| \
<>	144:ef7eb2e8f9f7	1194	((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
<>	144:ef7eb2e8f9f7	1195	#elif defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx)
<>	144:ef7eb2e8f9f7	1196	#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) (SET)
<>	144:ef7eb2e8f9f7	1197	#endif
<>	144:ef7eb2e8f9f7	1198
<>	144:ef7eb2e8f9f7	1199	/**
<>	144:ef7eb2e8f9f7	1200	* @brief Verification of ADC state: enabled or disabled, directly checked on instance as input parameter.
<>	144:ef7eb2e8f9f7	1201	* @param __INSTANCE__: ADC instance.
<>	144:ef7eb2e8f9f7	1202	* @retval SET (ADC enabled) or RESET (ADC disabled)
<>	144:ef7eb2e8f9f7	1203	*/
<>	144:ef7eb2e8f9f7	1204	#define ADC_INSTANCE_IS_ENABLED(__INSTANCE__) \
<>	144:ef7eb2e8f9f7	1205	(( ((((__INSTANCE__)->CR) & (ADC_CR_ADEN \| ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
<>	144:ef7eb2e8f9f7	1206	((((__INSTANCE__)->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
<>	144:ef7eb2e8f9f7	1207	) ? SET : RESET)
<>	144:ef7eb2e8f9f7	1208
<>	144:ef7eb2e8f9f7	1209	/**
<>	144:ef7eb2e8f9f7	1210	* @brief Verification of enabled/disabled status of ADCs other than that associated to the input parameter handle.
<>	144:ef7eb2e8f9f7	1211	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	1212	* @retval SET (at least one other ADC is enabled) or RESET (no other ADC is enabled, all other ADCs are disabled)
<>	144:ef7eb2e8f9f7	1213	*/
<>	144:ef7eb2e8f9f7	1214	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx)
<>	144:ef7eb2e8f9f7	1215	#define ADC_ANY_OTHER_ENABLED(__HANDLE__) \
<>	144:ef7eb2e8f9f7	1216	( ( ((__HANDLE__)->Instance == ADC1) \
<>	144:ef7eb2e8f9f7	1217	)? \
<>	144:ef7eb2e8f9f7	1218	(ADC_INSTANCE_IS_ENABLED(ADC2)) \|\| (ADC_INSTANCE_IS_ENABLED(ADC3)) \
<>	144:ef7eb2e8f9f7	1219	: \
<>	144:ef7eb2e8f9f7	1220	( ( ((__HANDLE__)->Instance == ADC2) \
<>	144:ef7eb2e8f9f7	1221	)? \
<>	144:ef7eb2e8f9f7	1222	(ADC_INSTANCE_IS_ENABLED(ADC1)) \|\| (ADC_INSTANCE_IS_ENABLED(ADC3)) \
<>	144:ef7eb2e8f9f7	1223	: \
<>	144:ef7eb2e8f9f7	1224	ADC_INSTANCE_IS_ENABLED(ADC1)) \|\| (ADC_INSTANCE_IS_ENABLED(ADC2)) \
<>	144:ef7eb2e8f9f7	1225	)
<>	144:ef7eb2e8f9f7	1226	#elif defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx)
<>	144:ef7eb2e8f9f7	1227	#define ADC_ANY_OTHER_ENABLED(__HANDLE__) (RESET)
<>	144:ef7eb2e8f9f7	1228	#endif
<>	144:ef7eb2e8f9f7	1229
<>	144:ef7eb2e8f9f7	1230
<>	144:ef7eb2e8f9f7	1231	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx)
<>	144:ef7eb2e8f9f7	1232	/**
<>	144:ef7eb2e8f9f7	1233	* @brief Set handle instance of the ADC slave associated to the ADC master.
<>	144:ef7eb2e8f9f7	1234	* @param __HANDLE_MASTER__: ADC master handle.
<>	144:ef7eb2e8f9f7	1235	* @param __HANDLE_SLAVE__: ADC slave handle.
<>	144:ef7eb2e8f9f7	1236	* @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC (ADC3), __HANDLE_SLAVE__ instance is set to NULL.
<>	144:ef7eb2e8f9f7	1237	* @retval None
<>	144:ef7eb2e8f9f7	1238	*/
<>	144:ef7eb2e8f9f7	1239	#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
<>	144:ef7eb2e8f9f7	1240	( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )
<>	144:ef7eb2e8f9f7	1241	#endif /* defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) */
<>	144:ef7eb2e8f9f7	1242
<>	144:ef7eb2e8f9f7	1243
<>	144:ef7eb2e8f9f7	1244	/**
<>	144:ef7eb2e8f9f7	1245	* @brief Check whether or not multimode is configured in DMA mode.
<>	144:ef7eb2e8f9f7	1246	* @note Return RESET if multimode feature is not available.
<>	144:ef7eb2e8f9f7	1247	* @retval SET (multimode is configured in DMA mode) or RESET (DMA multimode is disabled)
<>	144:ef7eb2e8f9f7	1248	*/
<>	144:ef7eb2e8f9f7	1249	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx)
<>	144:ef7eb2e8f9f7	1250	#define ADC_MULTIMODE_DMA_ENABLED() \
<>	144:ef7eb2e8f9f7	1251	((READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_12_10_BITS) \
<>	144:ef7eb2e8f9f7	1252	\|\| (READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_8_6_BITS))
<>	144:ef7eb2e8f9f7	1253	#elif defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx)
<>	144:ef7eb2e8f9f7	1254	#define ADC_MULTIMODE_DMA_ENABLED() (RESET)
<>	144:ef7eb2e8f9f7	1255	#endif
<>	144:ef7eb2e8f9f7	1256
<>	144:ef7eb2e8f9f7	1257
<>	144:ef7eb2e8f9f7	1258	/**
<>	144:ef7eb2e8f9f7	1259	* @brief Verify the ADC instance connected to the temperature sensor.
<>	144:ef7eb2e8f9f7	1260	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	1261	* @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
<>	144:ef7eb2e8f9f7	1262	*/
<>	144:ef7eb2e8f9f7	1263	#if defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx)
<>	144:ef7eb2e8f9f7	1264	/* The temperature sensor measurement path (channel 17) is available on ADC1 */
<>	144:ef7eb2e8f9f7	1265	#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
<>	144:ef7eb2e8f9f7	1266	#elif defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx)
<>	144:ef7eb2e8f9f7	1267	/* The temperature sensor measurement path (channel 17) is available on ADC1 and ADC3 */
<>	144:ef7eb2e8f9f7	1268	#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) \|\| (((__HANDLE__)->Instance) == ADC3))
<>	144:ef7eb2e8f9f7	1269	#endif
<>	144:ef7eb2e8f9f7	1270
<>	144:ef7eb2e8f9f7	1271	/**
<>	144:ef7eb2e8f9f7	1272	* @brief Verify the ADC instance connected to the battery voltage VBAT.
<>	144:ef7eb2e8f9f7	1273	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	1274	* @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
<>	144:ef7eb2e8f9f7	1275	*/
<>	144:ef7eb2e8f9f7	1276	#if defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx)
<>	144:ef7eb2e8f9f7	1277	/* The battery voltage measurement path (channel 18) is available on ADC1 */
<>	144:ef7eb2e8f9f7	1278	#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
<>	144:ef7eb2e8f9f7	1279	#elif defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx)
<>	144:ef7eb2e8f9f7	1280	/* The battery voltage measurement path (channel 18) is available on ADC1 and ADC3 */
<>	144:ef7eb2e8f9f7	1281	#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) \|\| (((__HANDLE__)->Instance) == ADC3))
<>	144:ef7eb2e8f9f7	1282	#endif
<>	144:ef7eb2e8f9f7	1283
<>	144:ef7eb2e8f9f7	1284	/**
<>	144:ef7eb2e8f9f7	1285	* @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
<>	144:ef7eb2e8f9f7	1286	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	1287	* @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
<>	144:ef7eb2e8f9f7	1288	*/
<>	144:ef7eb2e8f9f7	1289	/* The internal voltage reference VREFINT measurement path (channel 0) is available on ADC1 */
<>	144:ef7eb2e8f9f7	1290	#define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
<>	144:ef7eb2e8f9f7	1291
<>	144:ef7eb2e8f9f7	1292
<>	144:ef7eb2e8f9f7	1293	/**
<>	144:ef7eb2e8f9f7	1294	* @brief Verify the length of scheduled injected conversions group.
<>	144:ef7eb2e8f9f7	1295	* @param __LENGTH__: number of programmed conversions.
<>	144:ef7eb2e8f9f7	1296	* @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)
<>	144:ef7eb2e8f9f7	1297	*/
<>	144:ef7eb2e8f9f7	1298	#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4)))
<>	144:ef7eb2e8f9f7	1299
<>	144:ef7eb2e8f9f7	1300
<>	144:ef7eb2e8f9f7	1301	/**
<>	144:ef7eb2e8f9f7	1302	* @brief Calibration factor size verification (7 bits maximum).
<>	144:ef7eb2e8f9f7	1303	* @param __CALIBRATION_FACTOR__: Calibration factor value.
<>	144:ef7eb2e8f9f7	1304	* @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
<>	144:ef7eb2e8f9f7	1305	*/
<>	144:ef7eb2e8f9f7	1306	#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= ((uint32_t)0x7F))
<>	144:ef7eb2e8f9f7	1307
<>	144:ef7eb2e8f9f7	1308
<>	144:ef7eb2e8f9f7	1309	/**
<>	144:ef7eb2e8f9f7	1310	* @brief Verify the ADC channel setting.
<>	144:ef7eb2e8f9f7	1311	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	1312	* @param __CHANNEL__: programmed ADC channel.
<>	144:ef7eb2e8f9f7	1313	* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
<>	144:ef7eb2e8f9f7	1314	*/
<>	144:ef7eb2e8f9f7	1315	#if defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx)
<>	144:ef7eb2e8f9f7	1316	#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) && \
<>	144:ef7eb2e8f9f7	1317	(((__CHANNEL__) == ADC_CHANNEL_VREFINT) \|\| \
<>	144:ef7eb2e8f9f7	1318	((__CHANNEL__) == ADC_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	1319	((__CHANNEL__) == ADC_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	1320	((__CHANNEL__) == ADC_CHANNEL_3) \|\| \
<>	144:ef7eb2e8f9f7	1321	((__CHANNEL__) == ADC_CHANNEL_4) \|\| \
<>	144:ef7eb2e8f9f7	1322	((__CHANNEL__) == ADC_CHANNEL_5) \|\| \
<>	144:ef7eb2e8f9f7	1323	((__CHANNEL__) == ADC_CHANNEL_6) \|\| \
<>	144:ef7eb2e8f9f7	1324	((__CHANNEL__) == ADC_CHANNEL_7) \|\| \
<>	144:ef7eb2e8f9f7	1325	((__CHANNEL__) == ADC_CHANNEL_8) \|\| \
<>	144:ef7eb2e8f9f7	1326	((__CHANNEL__) == ADC_CHANNEL_9) \|\| \
<>	144:ef7eb2e8f9f7	1327	((__CHANNEL__) == ADC_CHANNEL_10) \|\| \
<>	144:ef7eb2e8f9f7	1328	((__CHANNEL__) == ADC_CHANNEL_11) \|\| \
<>	144:ef7eb2e8f9f7	1329	((__CHANNEL__) == ADC_CHANNEL_12) \|\| \
<>	144:ef7eb2e8f9f7	1330	((__CHANNEL__) == ADC_CHANNEL_13) \|\| \
<>	144:ef7eb2e8f9f7	1331	((__CHANNEL__) == ADC_CHANNEL_14) \|\| \
<>	144:ef7eb2e8f9f7	1332	((__CHANNEL__) == ADC_CHANNEL_15) \|\| \
<>	144:ef7eb2e8f9f7	1333	((__CHANNEL__) == ADC_CHANNEL_16) \|\| \
<>	144:ef7eb2e8f9f7	1334	((__CHANNEL__) == ADC_CHANNEL_17) \|\| \
<>	144:ef7eb2e8f9f7	1335	((__CHANNEL__) == ADC_CHANNEL_18) \|\| \
<>	144:ef7eb2e8f9f7	1336	((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) \|\| \
<>	144:ef7eb2e8f9f7	1337	((__CHANNEL__) == ADC_CHANNEL_VBAT)))
<>	144:ef7eb2e8f9f7	1338	#elif defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx)
<>	144:ef7eb2e8f9f7	1339	#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \
<>	144:ef7eb2e8f9f7	1340	(((__CHANNEL__) == ADC_CHANNEL_VREFINT) \|\| \
<>	144:ef7eb2e8f9f7	1341	((__CHANNEL__) == ADC_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	1342	((__CHANNEL__) == ADC_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	1343	((__CHANNEL__) == ADC_CHANNEL_3) \|\| \
<>	144:ef7eb2e8f9f7	1344	((__CHANNEL__) == ADC_CHANNEL_4) \|\| \
<>	144:ef7eb2e8f9f7	1345	((__CHANNEL__) == ADC_CHANNEL_5) \|\| \
<>	144:ef7eb2e8f9f7	1346	((__CHANNEL__) == ADC_CHANNEL_6) \|\| \
<>	144:ef7eb2e8f9f7	1347	((__CHANNEL__) == ADC_CHANNEL_7) \|\| \
<>	144:ef7eb2e8f9f7	1348	((__CHANNEL__) == ADC_CHANNEL_8) \|\| \
<>	144:ef7eb2e8f9f7	1349	((__CHANNEL__) == ADC_CHANNEL_9) \|\| \
<>	144:ef7eb2e8f9f7	1350	((__CHANNEL__) == ADC_CHANNEL_10) \|\| \
<>	144:ef7eb2e8f9f7	1351	((__CHANNEL__) == ADC_CHANNEL_11) \|\| \
<>	144:ef7eb2e8f9f7	1352	((__CHANNEL__) == ADC_CHANNEL_12) \|\| \
<>	144:ef7eb2e8f9f7	1353	((__CHANNEL__) == ADC_CHANNEL_13) \|\| \
<>	144:ef7eb2e8f9f7	1354	((__CHANNEL__) == ADC_CHANNEL_14) \|\| \
<>	144:ef7eb2e8f9f7	1355	((__CHANNEL__) == ADC_CHANNEL_15) \|\| \
<>	144:ef7eb2e8f9f7	1356	((__CHANNEL__) == ADC_CHANNEL_16) \|\| \
<>	144:ef7eb2e8f9f7	1357	((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) \|\| \
<>	144:ef7eb2e8f9f7	1358	((__CHANNEL__) == ADC_CHANNEL_VBAT))) \|\| \
<>	144:ef7eb2e8f9f7	1359	((((__HANDLE__)->Instance) == ADC2) && \
<>	144:ef7eb2e8f9f7	1360	(((__CHANNEL__) == ADC_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	1361	((__CHANNEL__) == ADC_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	1362	((__CHANNEL__) == ADC_CHANNEL_3) \|\| \
<>	144:ef7eb2e8f9f7	1363	((__CHANNEL__) == ADC_CHANNEL_4) \|\| \
<>	144:ef7eb2e8f9f7	1364	((__CHANNEL__) == ADC_CHANNEL_5) \|\| \
<>	144:ef7eb2e8f9f7	1365	((__CHANNEL__) == ADC_CHANNEL_6) \|\| \
<>	144:ef7eb2e8f9f7	1366	((__CHANNEL__) == ADC_CHANNEL_7) \|\| \
<>	144:ef7eb2e8f9f7	1367	((__CHANNEL__) == ADC_CHANNEL_8) \|\| \
<>	144:ef7eb2e8f9f7	1368	((__CHANNEL__) == ADC_CHANNEL_9) \|\| \
<>	144:ef7eb2e8f9f7	1369	((__CHANNEL__) == ADC_CHANNEL_10) \|\| \
<>	144:ef7eb2e8f9f7	1370	((__CHANNEL__) == ADC_CHANNEL_11) \|\| \
<>	144:ef7eb2e8f9f7	1371	((__CHANNEL__) == ADC_CHANNEL_12) \|\| \
<>	144:ef7eb2e8f9f7	1372	((__CHANNEL__) == ADC_CHANNEL_13) \|\| \
<>	144:ef7eb2e8f9f7	1373	((__CHANNEL__) == ADC_CHANNEL_14) \|\| \
<>	144:ef7eb2e8f9f7	1374	((__CHANNEL__) == ADC_CHANNEL_15) \|\| \
<>	144:ef7eb2e8f9f7	1375	((__CHANNEL__) == ADC_CHANNEL_16) \|\| \
<>	144:ef7eb2e8f9f7	1376	((__CHANNEL__) == ADC_CHANNEL_17) \|\| \
<>	144:ef7eb2e8f9f7	1377	((__CHANNEL__) == ADC_CHANNEL_18))) \|\| \
<>	144:ef7eb2e8f9f7	1378	((((__HANDLE__)->Instance) == ADC3) && \
<>	144:ef7eb2e8f9f7	1379	(((__CHANNEL__) == ADC_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	1380	((__CHANNEL__) == ADC_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	1381	((__CHANNEL__) == ADC_CHANNEL_3) \|\| \
<>	144:ef7eb2e8f9f7	1382	((__CHANNEL__) == ADC_CHANNEL_4) \|\| \
<>	144:ef7eb2e8f9f7	1383	((__CHANNEL__) == ADC_CHANNEL_6) \|\| \
<>	144:ef7eb2e8f9f7	1384	((__CHANNEL__) == ADC_CHANNEL_7) \|\| \
<>	144:ef7eb2e8f9f7	1385	((__CHANNEL__) == ADC_CHANNEL_8) \|\| \
<>	144:ef7eb2e8f9f7	1386	((__CHANNEL__) == ADC_CHANNEL_9) \|\| \
<>	144:ef7eb2e8f9f7	1387	((__CHANNEL__) == ADC_CHANNEL_10) \|\| \
<>	144:ef7eb2e8f9f7	1388	((__CHANNEL__) == ADC_CHANNEL_11) \|\| \
<>	144:ef7eb2e8f9f7	1389	((__CHANNEL__) == ADC_CHANNEL_12) \|\| \
<>	144:ef7eb2e8f9f7	1390	((__CHANNEL__) == ADC_CHANNEL_13) \|\| \
<>	144:ef7eb2e8f9f7	1391	((__CHANNEL__) == ADC_CHANNEL_14) \|\| \
<>	144:ef7eb2e8f9f7	1392	((__CHANNEL__) == ADC_CHANNEL_15) \|\| \
<>	144:ef7eb2e8f9f7	1393	((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) \|\| \
<>	144:ef7eb2e8f9f7	1394	((__CHANNEL__) == ADC_CHANNEL_VBAT) )))
<>	144:ef7eb2e8f9f7	1395	#endif
<>	144:ef7eb2e8f9f7	1396
<>	144:ef7eb2e8f9f7	1397	/**
<>	144:ef7eb2e8f9f7	1398	* @brief Verify the ADC channel setting in differential mode.
<>	144:ef7eb2e8f9f7	1399	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	1400	* @param __CHANNEL__: programmed ADC channel.
<>	144:ef7eb2e8f9f7	1401	* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
<>	144:ef7eb2e8f9f7	1402	*/
<>	144:ef7eb2e8f9f7	1403	#if defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx)
<>	144:ef7eb2e8f9f7	1404	#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	1405	((__CHANNEL__) == ADC_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	1406	((__CHANNEL__) == ADC_CHANNEL_3) \|\| \
<>	144:ef7eb2e8f9f7	1407	((__CHANNEL__) == ADC_CHANNEL_4) \|\| \
<>	144:ef7eb2e8f9f7	1408	((__CHANNEL__) == ADC_CHANNEL_5) \|\| \
<>	144:ef7eb2e8f9f7	1409	((__CHANNEL__) == ADC_CHANNEL_6) \|\| \
<>	144:ef7eb2e8f9f7	1410	((__CHANNEL__) == ADC_CHANNEL_7) \|\| \
<>	144:ef7eb2e8f9f7	1411	((__CHANNEL__) == ADC_CHANNEL_8) \|\| \
<>	144:ef7eb2e8f9f7	1412	((__CHANNEL__) == ADC_CHANNEL_9) \|\| \
<>	144:ef7eb2e8f9f7	1413	((__CHANNEL__) == ADC_CHANNEL_10) \|\| \
<>	144:ef7eb2e8f9f7	1414	((__CHANNEL__) == ADC_CHANNEL_11) \|\| \
<>	144:ef7eb2e8f9f7	1415	((__CHANNEL__) == ADC_CHANNEL_12) \|\| \
<>	144:ef7eb2e8f9f7	1416	((__CHANNEL__) == ADC_CHANNEL_13) \|\| \
<>	144:ef7eb2e8f9f7	1417	((__CHANNEL__) == ADC_CHANNEL_14) \|\| \
<>	144:ef7eb2e8f9f7	1418	((__CHANNEL__) == ADC_CHANNEL_15) )
<>	144:ef7eb2e8f9f7	1419	#elif defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx)
<>	144:ef7eb2e8f9f7	1420	/* For ADC1 and ADC2, channels 1 to 15 are available in differential mode,
<>	144:ef7eb2e8f9f7	1421	channels 0, 16 to 18 can be only used in single-ended mode.
<>	144:ef7eb2e8f9f7	1422	For ADC3, channels 1 to 3 and 6 to 12 are available in differential mode,
<>	144:ef7eb2e8f9f7	1423	channels 4, 5 and 13 to 18 can only be used in single-ended mode. */
<>	144:ef7eb2e8f9f7	1424	#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ((((((__HANDLE__)->Instance) == ADC1) \|\| \
<>	144:ef7eb2e8f9f7	1425	(((__HANDLE__)->Instance) == ADC2)) && \
<>	144:ef7eb2e8f9f7	1426	(((__CHANNEL__) == ADC_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	1427	((__CHANNEL__) == ADC_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	1428	((__CHANNEL__) == ADC_CHANNEL_3) \|\| \
<>	144:ef7eb2e8f9f7	1429	((__CHANNEL__) == ADC_CHANNEL_4) \|\| \
<>	144:ef7eb2e8f9f7	1430	((__CHANNEL__) == ADC_CHANNEL_5) \|\| \
<>	144:ef7eb2e8f9f7	1431	((__CHANNEL__) == ADC_CHANNEL_6) \|\| \
<>	144:ef7eb2e8f9f7	1432	((__CHANNEL__) == ADC_CHANNEL_7) \|\| \
<>	144:ef7eb2e8f9f7	1433	((__CHANNEL__) == ADC_CHANNEL_8) \|\| \
<>	144:ef7eb2e8f9f7	1434	((__CHANNEL__) == ADC_CHANNEL_9) \|\| \
<>	144:ef7eb2e8f9f7	1435	((__CHANNEL__) == ADC_CHANNEL_10) \|\| \
<>	144:ef7eb2e8f9f7	1436	((__CHANNEL__) == ADC_CHANNEL_11) \|\| \
<>	144:ef7eb2e8f9f7	1437	((__CHANNEL__) == ADC_CHANNEL_12) \|\| \
<>	144:ef7eb2e8f9f7	1438	((__CHANNEL__) == ADC_CHANNEL_13) \|\| \
<>	144:ef7eb2e8f9f7	1439	((__CHANNEL__) == ADC_CHANNEL_14) \|\| \
<>	144:ef7eb2e8f9f7	1440	((__CHANNEL__) == ADC_CHANNEL_15))) \|\| \
<>	144:ef7eb2e8f9f7	1441	((((__HANDLE__)->Instance) == ADC3) && \
<>	144:ef7eb2e8f9f7	1442	(((__CHANNEL__) == ADC_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	1443	((__CHANNEL__) == ADC_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	1444	((__CHANNEL__) == ADC_CHANNEL_3) \|\| \
<>	144:ef7eb2e8f9f7	1445	((__CHANNEL__) == ADC_CHANNEL_6) \|\| \
<>	144:ef7eb2e8f9f7	1446	((__CHANNEL__) == ADC_CHANNEL_7) \|\| \
<>	144:ef7eb2e8f9f7	1447	((__CHANNEL__) == ADC_CHANNEL_8) \|\| \
<>	144:ef7eb2e8f9f7	1448	((__CHANNEL__) == ADC_CHANNEL_9) \|\| \
<>	144:ef7eb2e8f9f7	1449	((__CHANNEL__) == ADC_CHANNEL_10) \|\| \
<>	144:ef7eb2e8f9f7	1450	((__CHANNEL__) == ADC_CHANNEL_11) \|\| \
<>	144:ef7eb2e8f9f7	1451	((__CHANNEL__) == ADC_CHANNEL_12) )))
<>	144:ef7eb2e8f9f7	1452	#endif
<>	144:ef7eb2e8f9f7	1453
<>	144:ef7eb2e8f9f7	1454	/**
<>	144:ef7eb2e8f9f7	1455	* @brief Verify the ADC single-ended input or differential mode setting.
<>	144:ef7eb2e8f9f7	1456	* @param __SING_DIFF__: programmed channel setting.
<>	144:ef7eb2e8f9f7	1457	* @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
<>	144:ef7eb2e8f9f7	1458	*/
<>	144:ef7eb2e8f9f7	1459	#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) \|\| \
<>	144:ef7eb2e8f9f7	1460	((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) )
<>	144:ef7eb2e8f9f7	1461
<>	144:ef7eb2e8f9f7	1462	/**
<>	144:ef7eb2e8f9f7	1463	* @brief Verify the ADC offset management setting.
<>	144:ef7eb2e8f9f7	1464	* @param __OFFSET_NUMBER__: ADC offset management.
<>	144:ef7eb2e8f9f7	1465	* @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)
<>	144:ef7eb2e8f9f7	1466	*/
<>	144:ef7eb2e8f9f7	1467	#define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) \|\| \
<>	144:ef7eb2e8f9f7	1468	((__OFFSET_NUMBER__) == ADC_OFFSET_1) \|\| \
<>	144:ef7eb2e8f9f7	1469	((__OFFSET_NUMBER__) == ADC_OFFSET_2) \|\| \
<>	144:ef7eb2e8f9f7	1470	((__OFFSET_NUMBER__) == ADC_OFFSET_3) \|\| \
<>	144:ef7eb2e8f9f7	1471	((__OFFSET_NUMBER__) == ADC_OFFSET_4) )
<>	144:ef7eb2e8f9f7	1472
<>	144:ef7eb2e8f9f7	1473	/**
<>	144:ef7eb2e8f9f7	1474	* @brief Verify the ADC regular channel setting.
<>	144:ef7eb2e8f9f7	1475	* @param __CHANNEL__: programmed ADC regular channel.
<>	144:ef7eb2e8f9f7	1476	* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
<>	144:ef7eb2e8f9f7	1477	*/
<>	144:ef7eb2e8f9f7	1478	#define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) \|\| \
<>	144:ef7eb2e8f9f7	1479	((__CHANNEL__) == ADC_REGULAR_RANK_2 ) \|\| \
<>	144:ef7eb2e8f9f7	1480	((__CHANNEL__) == ADC_REGULAR_RANK_3 ) \|\| \
<>	144:ef7eb2e8f9f7	1481	((__CHANNEL__) == ADC_REGULAR_RANK_4 ) \|\| \
<>	144:ef7eb2e8f9f7	1482	((__CHANNEL__) == ADC_REGULAR_RANK_5 ) \|\| \
<>	144:ef7eb2e8f9f7	1483	((__CHANNEL__) == ADC_REGULAR_RANK_6 ) \|\| \
<>	144:ef7eb2e8f9f7	1484	((__CHANNEL__) == ADC_REGULAR_RANK_7 ) \|\| \
<>	144:ef7eb2e8f9f7	1485	((__CHANNEL__) == ADC_REGULAR_RANK_8 ) \|\| \
<>	144:ef7eb2e8f9f7	1486	((__CHANNEL__) == ADC_REGULAR_RANK_9 ) \|\| \
<>	144:ef7eb2e8f9f7	1487	((__CHANNEL__) == ADC_REGULAR_RANK_10) \|\| \
<>	144:ef7eb2e8f9f7	1488	((__CHANNEL__) == ADC_REGULAR_RANK_11) \|\| \
<>	144:ef7eb2e8f9f7	1489	((__CHANNEL__) == ADC_REGULAR_RANK_12) \|\| \
<>	144:ef7eb2e8f9f7	1490	((__CHANNEL__) == ADC_REGULAR_RANK_13) \|\| \
<>	144:ef7eb2e8f9f7	1491	((__CHANNEL__) == ADC_REGULAR_RANK_14) \|\| \
<>	144:ef7eb2e8f9f7	1492	((__CHANNEL__) == ADC_REGULAR_RANK_15) \|\| \
<>	144:ef7eb2e8f9f7	1493	((__CHANNEL__) == ADC_REGULAR_RANK_16) )
<>	144:ef7eb2e8f9f7	1494
<>	144:ef7eb2e8f9f7	1495
<>	144:ef7eb2e8f9f7	1496	/**
<>	144:ef7eb2e8f9f7	1497	* @brief Verify the ADC injected channel setting.
<>	144:ef7eb2e8f9f7	1498	* @param __CHANNEL__: programmed ADC injected channel.
<>	144:ef7eb2e8f9f7	1499	* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
<>	144:ef7eb2e8f9f7	1500	*/
<>	144:ef7eb2e8f9f7	1501	#define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) \|\| \
<>	144:ef7eb2e8f9f7	1502	((__CHANNEL__) == ADC_INJECTED_RANK_2) \|\| \
<>	144:ef7eb2e8f9f7	1503	((__CHANNEL__) == ADC_INJECTED_RANK_3) \|\| \
<>	144:ef7eb2e8f9f7	1504	((__CHANNEL__) == ADC_INJECTED_RANK_4) )
<>	144:ef7eb2e8f9f7	1505
<>	144:ef7eb2e8f9f7	1506	/**
<>	144:ef7eb2e8f9f7	1507	* @brief Verify the ADC edge trigger setting for injected group.
<>	144:ef7eb2e8f9f7	1508	* @param __EDGE__: programmed ADC edge trigger setting.
<>	144:ef7eb2e8f9f7	1509	* @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
<>	144:ef7eb2e8f9f7	1510	*/
<>	144:ef7eb2e8f9f7	1511	#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) \|\| \
<>	144:ef7eb2e8f9f7	1512	((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) \|\| \
<>	144:ef7eb2e8f9f7	1513	((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) \|\| \
<>	144:ef7eb2e8f9f7	1514	((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
<>	144:ef7eb2e8f9f7	1515
<>	144:ef7eb2e8f9f7	1516
<>	144:ef7eb2e8f9f7	1517	/**
<>	144:ef7eb2e8f9f7	1518	* @brief Verify the ADC injected conversions external trigger.
<>	144:ef7eb2e8f9f7	1519	* @param __INJTRIG__: programmed ADC injected conversions external trigger.
<>	144:ef7eb2e8f9f7	1520	* @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
<>	144:ef7eb2e8f9f7	1521	*/
<>	144:ef7eb2e8f9f7	1522	#define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	1523	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) \|\| \
<>	144:ef7eb2e8f9f7	1524	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	1525	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) \|\| \
<>	144:ef7eb2e8f9f7	1526	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) \|\| \
<>	144:ef7eb2e8f9f7	1527	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	1528	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) \|\| \
<>	144:ef7eb2e8f9f7	1529	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) \|\| \
<>	144:ef7eb2e8f9f7	1530	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	1531	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	1532	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) \|\| \
<>	144:ef7eb2e8f9f7	1533	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) \|\| \
<>	144:ef7eb2e8f9f7	1534	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	1535	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) \|\| \
<>	144:ef7eb2e8f9f7	1536	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	1537	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) \|\| \
<>	144:ef7eb2e8f9f7	1538	\
<>	144:ef7eb2e8f9f7	1539	((__INJTRIG__) == ADC_SOFTWARE_START) )
<>	144:ef7eb2e8f9f7	1540
<>	144:ef7eb2e8f9f7	1541
<>	144:ef7eb2e8f9f7	1542	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx)
<>	144:ef7eb2e8f9f7	1543	/**
<>	144:ef7eb2e8f9f7	1544	* @brief Verify the ADC multimode setting.
<>	144:ef7eb2e8f9f7	1545	* @param __MODE__: programmed ADC multimode setting.
<>	144:ef7eb2e8f9f7	1546	* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
<>	144:ef7eb2e8f9f7	1547	*/
<>	144:ef7eb2e8f9f7	1548	#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) \|\| \
<>	144:ef7eb2e8f9f7	1549	((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) \|\| \
<>	144:ef7eb2e8f9f7	1550	((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) \|\| \
<>	144:ef7eb2e8f9f7	1551	((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) \|\| \
<>	144:ef7eb2e8f9f7	1552	((__MODE__) == ADC_DUALMODE_INJECSIMULT) \|\| \
<>	144:ef7eb2e8f9f7	1553	((__MODE__) == ADC_DUALMODE_REGSIMULT) \|\| \
<>	144:ef7eb2e8f9f7	1554	((__MODE__) == ADC_DUALMODE_INTERL) \|\| \
<>	144:ef7eb2e8f9f7	1555	((__MODE__) == ADC_DUALMODE_ALTERTRIG) )
<>	144:ef7eb2e8f9f7	1556
<>	144:ef7eb2e8f9f7	1557	/**
<>	144:ef7eb2e8f9f7	1558	* @brief Verify the ADC multimode DMA access setting.
<>	144:ef7eb2e8f9f7	1559	* @param __MODE__: programmed ADC multimode DMA access setting.
<>	144:ef7eb2e8f9f7	1560	* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
<>	144:ef7eb2e8f9f7	1561	*/
<>	144:ef7eb2e8f9f7	1562	#define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) \|\| \
<>	144:ef7eb2e8f9f7	1563	((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) \|\| \
<>	144:ef7eb2e8f9f7	1564	((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS) )
<>	144:ef7eb2e8f9f7	1565
<>	144:ef7eb2e8f9f7	1566	/**
<>	144:ef7eb2e8f9f7	1567	* @brief Verify the ADC multimode delay setting.
<>	144:ef7eb2e8f9f7	1568	* @param __DELAY__: programmed ADC multimode delay setting.
<>	144:ef7eb2e8f9f7	1569	* @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)
<>	144:ef7eb2e8f9f7	1570	*/
<>	144:ef7eb2e8f9f7	1571	#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) \|\| \
<>	144:ef7eb2e8f9f7	1572	((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	1573	((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	1574	((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	1575	((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	1576	((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	1577	((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	1578	((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	1579	((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	1580	((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	1581	((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) \|\| \
<>	144:ef7eb2e8f9f7	1582	((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) )
<>	144:ef7eb2e8f9f7	1583	#endif /* defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) */
<>	144:ef7eb2e8f9f7	1584
<>	144:ef7eb2e8f9f7	1585	/**
<>	144:ef7eb2e8f9f7	1586	* @brief Verify the ADC analog watchdog setting.
<>	144:ef7eb2e8f9f7	1587	* @param __WATCHDOG__: programmed ADC analog watchdog setting.
<>	144:ef7eb2e8f9f7	1588	* @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
<>	144:ef7eb2e8f9f7	1589	*/
<>	144:ef7eb2e8f9f7	1590	#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) \|\| \
<>	144:ef7eb2e8f9f7	1591	((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) \|\| \
<>	144:ef7eb2e8f9f7	1592	((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) )
<>	144:ef7eb2e8f9f7	1593
<>	144:ef7eb2e8f9f7	1594	/**
<>	144:ef7eb2e8f9f7	1595	* @brief Verify the ADC analog watchdog mode setting.
<>	144:ef7eb2e8f9f7	1596	* @param __WATCHDOG_MODE__: programmed ADC analog watchdog mode setting.
<>	144:ef7eb2e8f9f7	1597	* @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
<>	144:ef7eb2e8f9f7	1598	*/
<>	144:ef7eb2e8f9f7	1599	#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) \|\| \
<>	144:ef7eb2e8f9f7	1600	((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\| \
<>	144:ef7eb2e8f9f7	1601	((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) \|\| \
<>	144:ef7eb2e8f9f7	1602	((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) \|\| \
<>	144:ef7eb2e8f9f7	1603	((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) \|\| \
<>	144:ef7eb2e8f9f7	1604	((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) \|\| \
<>	144:ef7eb2e8f9f7	1605	((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
<>	144:ef7eb2e8f9f7	1606
<>	144:ef7eb2e8f9f7	1607	/**
<>	144:ef7eb2e8f9f7	1608	* @brief Verify the ADC conversion (regular or injected or both).
<>	144:ef7eb2e8f9f7	1609	* @param __CONVERSION__: ADC conversion group.
<>	144:ef7eb2e8f9f7	1610	* @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
<>	144:ef7eb2e8f9f7	1611	*/
<>	144:ef7eb2e8f9f7	1612	#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) \|\| \
<>	144:ef7eb2e8f9f7	1613	((__CONVERSION__) == ADC_INJECTED_GROUP) \|\| \
<>	144:ef7eb2e8f9f7	1614	((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) )
<>	144:ef7eb2e8f9f7	1615
<>	144:ef7eb2e8f9f7	1616	/**
<>	144:ef7eb2e8f9f7	1617	* @brief Verify the ADC event type.
<>	144:ef7eb2e8f9f7	1618	* @param __EVENT__: ADC event.
<>	144:ef7eb2e8f9f7	1619	* @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
<>	144:ef7eb2e8f9f7	1620	*/
<>	144:ef7eb2e8f9f7	1621	#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) \|\| \
<>	144:ef7eb2e8f9f7	1622	((__EVENT__) == ADC_AWD_EVENT) \|\| \
<>	144:ef7eb2e8f9f7	1623	((__EVENT__) == ADC_AWD2_EVENT) \|\| \
<>	144:ef7eb2e8f9f7	1624	((__EVENT__) == ADC_AWD3_EVENT) \|\| \
<>	144:ef7eb2e8f9f7	1625	((__EVENT__) == ADC_OVR_EVENT) \|\| \
<>	144:ef7eb2e8f9f7	1626	((__EVENT__) == ADC_JQOVF_EVENT) )
<>	144:ef7eb2e8f9f7	1627
<>	144:ef7eb2e8f9f7	1628	/**
<>	144:ef7eb2e8f9f7	1629	* @brief Verify the ADC oversampling ratio.
<>	144:ef7eb2e8f9f7	1630	* @param __RATIO__: programmed ADC oversampling ratio.
<>	144:ef7eb2e8f9f7	1631	* @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
<>	144:ef7eb2e8f9f7	1632	*/
<>	144:ef7eb2e8f9f7	1633	#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) \|\| \
<>	144:ef7eb2e8f9f7	1634	((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) \|\| \
<>	144:ef7eb2e8f9f7	1635	((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) \|\| \
<>	144:ef7eb2e8f9f7	1636	((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) \|\| \
<>	144:ef7eb2e8f9f7	1637	((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) \|\| \
<>	144:ef7eb2e8f9f7	1638	((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) \|\| \
<>	144:ef7eb2e8f9f7	1639	((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) \|\| \
<>	144:ef7eb2e8f9f7	1640	((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
<>	144:ef7eb2e8f9f7	1641
<>	144:ef7eb2e8f9f7	1642	/**
<>	144:ef7eb2e8f9f7	1643	* @brief Verify the ADC oversampling shift.
<>	144:ef7eb2e8f9f7	1644	* @param __SHIFT__: programmed ADC oversampling shift.
<>	144:ef7eb2e8f9f7	1645	* @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
<>	144:ef7eb2e8f9f7	1646	*/
<>	144:ef7eb2e8f9f7	1647	#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) \|\| \
<>	144:ef7eb2e8f9f7	1648	((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) \|\| \
<>	144:ef7eb2e8f9f7	1649	((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) \|\| \
<>	144:ef7eb2e8f9f7	1650	((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) \|\| \
<>	144:ef7eb2e8f9f7	1651	((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) \|\| \
<>	144:ef7eb2e8f9f7	1652	((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) \|\| \
<>	144:ef7eb2e8f9f7	1653	((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) \|\| \
<>	144:ef7eb2e8f9f7	1654	((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) \|\| \
<>	144:ef7eb2e8f9f7	1655	((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ))
<>	144:ef7eb2e8f9f7	1656
<>	144:ef7eb2e8f9f7	1657	/**
<>	144:ef7eb2e8f9f7	1658	* @brief Verify the ADC oversampling triggered mode.
<>	144:ef7eb2e8f9f7	1659	* @param __MODE__: programmed ADC oversampling triggered mode.
<>	144:ef7eb2e8f9f7	1660	* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
<>	144:ef7eb2e8f9f7	1661	*/
<>	144:ef7eb2e8f9f7	1662	#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) \|\| \
<>	144:ef7eb2e8f9f7	1663	((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
<>	144:ef7eb2e8f9f7	1664
<>	144:ef7eb2e8f9f7	1665	/**
<>	144:ef7eb2e8f9f7	1666	* @brief Verify the ADC oversampling regular conversion resumed or continued mode.
<>	144:ef7eb2e8f9f7	1667	* @param __MODE__: programmed ADC oversampling regular conversion resumed or continued mode.
<>	144:ef7eb2e8f9f7	1668	* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
<>	144:ef7eb2e8f9f7	1669	*/
<>	144:ef7eb2e8f9f7	1670	#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) \|\| \
<>	144:ef7eb2e8f9f7	1671	((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
<>	144:ef7eb2e8f9f7	1672
<>	144:ef7eb2e8f9f7	1673
<>	144:ef7eb2e8f9f7	1674	/**
<>	144:ef7eb2e8f9f7	1675	* @brief Verify the DFSDM mode configuration.
<>	144:ef7eb2e8f9f7	1676	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	1677	* @note When DMSDFM configuration is not supported, the macro systematically reports SET. For
<>	144:ef7eb2e8f9f7	1678	* this reason, the input parameter is the ADC handle and not the configuration parameter
<>	144:ef7eb2e8f9f7	1679	* directly.
<>	144:ef7eb2e8f9f7	1680	* @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)
<>	144:ef7eb2e8f9f7	1681	*/
<>	144:ef7eb2e8f9f7	1682	#define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
<>	144:ef7eb2e8f9f7	1683
<>	144:ef7eb2e8f9f7	1684	/**
<>	144:ef7eb2e8f9f7	1685	* @brief Return the DFSDM configuration mode.
<>	144:ef7eb2e8f9f7	1686	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	1687	* @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled).
<>	144:ef7eb2e8f9f7	1688	* For this reason, the input parameter is the ADC handle and not the configuration parameter
<>	144:ef7eb2e8f9f7	1689	* directly.
<>	144:ef7eb2e8f9f7	1690	* @retval DFSDM configuration mode
<>	144:ef7eb2e8f9f7	1691	*/
<>	144:ef7eb2e8f9f7	1692	#define ADC_CFGR_DFSDM(__HANDLE__) (0x0)
<>	144:ef7eb2e8f9f7	1693
<>	144:ef7eb2e8f9f7	1694
<>	144:ef7eb2e8f9f7	1695	/**
<>	144:ef7eb2e8f9f7	1696	* @}
<>	144:ef7eb2e8f9f7	1697	*/
<>	144:ef7eb2e8f9f7	1698
<>	144:ef7eb2e8f9f7	1699
<>	144:ef7eb2e8f9f7	1700	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1701	/** @addtogroup ADCEx_Exported_Functions ADC Extended Exported Functions
<>	144:ef7eb2e8f9f7	1702	* @{
<>	144:ef7eb2e8f9f7	1703	*/
<>	144:ef7eb2e8f9f7	1704
<>	144:ef7eb2e8f9f7	1705	/* Initialization/de-initialization functions *********************************/
<>	144:ef7eb2e8f9f7	1706
<>	144:ef7eb2e8f9f7	1707	/** @addtogroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
<>	144:ef7eb2e8f9f7	1708	* @brief Extended IO operation functions
<>	144:ef7eb2e8f9f7	1709	* @{
<>	144:ef7eb2e8f9f7	1710	*/
<>	144:ef7eb2e8f9f7	1711	/* I/O operation functions ****************************************************/
<>	144:ef7eb2e8f9f7	1712
<>	144:ef7eb2e8f9f7	1713	/* ADC calibration */
<>	144:ef7eb2e8f9f7	1714
<>	144:ef7eb2e8f9f7	1715	HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
<>	144:ef7eb2e8f9f7	1716	uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
<>	144:ef7eb2e8f9f7	1717	HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
<>	144:ef7eb2e8f9f7	1718
<>	144:ef7eb2e8f9f7	1719
<>	144:ef7eb2e8f9f7	1720
<>	144:ef7eb2e8f9f7	1721	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1722	HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1723	HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1724	HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	1725
<>	144:ef7eb2e8f9f7	1726	/* Non-blocking mode: Interruption */
<>	144:ef7eb2e8f9f7	1727	HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1728	HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1729
<>	144:ef7eb2e8f9f7	1730
<>	144:ef7eb2e8f9f7	1731	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx)
<>	144:ef7eb2e8f9f7	1732	/* ADC multimode */
<>	144:ef7eb2e8f9f7	1733	HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef hadc, uint32_t pData, uint32_t Length);
<>	144:ef7eb2e8f9f7	1734	HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
<>	144:ef7eb2e8f9f7	1735	uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
<>	144:ef7eb2e8f9f7	1736	#endif /* defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) */
<>	144:ef7eb2e8f9f7	1737
<>	144:ef7eb2e8f9f7	1738	/* ADC retrieve conversion value intended to be used with polling or interruption */
<>	144:ef7eb2e8f9f7	1739	uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
<>	144:ef7eb2e8f9f7	1740
<>	144:ef7eb2e8f9f7	1741	/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
<>	144:ef7eb2e8f9f7	1742	void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1743	void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1744	void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1745	void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1746	void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1747
<>	144:ef7eb2e8f9f7	1748
<>	144:ef7eb2e8f9f7	1749	/* ADC Regular conversions stop */
<>	144:ef7eb2e8f9f7	1750	HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1751	HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1752	HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1753	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx)
<>	144:ef7eb2e8f9f7	1754	HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1755	#endif /* defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) */
<>	144:ef7eb2e8f9f7	1756
<>	144:ef7eb2e8f9f7	1757	/**
<>	144:ef7eb2e8f9f7	1758	* @}
<>	144:ef7eb2e8f9f7	1759	*/
<>	144:ef7eb2e8f9f7	1760
<>	144:ef7eb2e8f9f7	1761	/** @addtogroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions
<>	144:ef7eb2e8f9f7	1762	* @brief Extended Peripheral Control functions
<>	144:ef7eb2e8f9f7	1763	* @{
<>	144:ef7eb2e8f9f7	1764	*/
<>	144:ef7eb2e8f9f7	1765	/* Peripheral Control functions ***********************************************/
<>	144:ef7eb2e8f9f7	1766	HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
<>	144:ef7eb2e8f9f7	1767	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx)
<>	144:ef7eb2e8f9f7	1768	HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef hadc, ADC_MultiModeTypeDef multimode);
<>	144:ef7eb2e8f9f7	1769	#endif /* defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) */
<>	144:ef7eb2e8f9f7	1770	HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1771	HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1772	HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1773	HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1774
<>	144:ef7eb2e8f9f7	1775	/**
<>	144:ef7eb2e8f9f7	1776	* @}
<>	144:ef7eb2e8f9f7	1777	*/
<>	144:ef7eb2e8f9f7	1778
<>	144:ef7eb2e8f9f7	1779	/**
<>	144:ef7eb2e8f9f7	1780	* @}
<>	144:ef7eb2e8f9f7	1781	*/
<>	144:ef7eb2e8f9f7	1782
<>	144:ef7eb2e8f9f7	1783	/**
<>	144:ef7eb2e8f9f7	1784	* @}
<>	144:ef7eb2e8f9f7	1785	*/
<>	144:ef7eb2e8f9f7	1786
<>	144:ef7eb2e8f9f7	1787	/**
<>	144:ef7eb2e8f9f7	1788	* @}
<>	144:ef7eb2e8f9f7	1789	*/
<>	144:ef7eb2e8f9f7	1790
<>	144:ef7eb2e8f9f7	1791	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	1792	}
<>	144:ef7eb2e8f9f7	1793	#endif
<>	144:ef7eb2e8f9f7	1794
<>	144:ef7eb2e8f9f7	1795	#endif /__STM32L4xx_ADC_EX_H /
<>	144:ef7eb2e8f9f7	1796
<>	144:ef7eb2e8f9f7	1797
<>	144:ef7eb2e8f9f7	1798	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Created:	25 Nov 2016
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