mbed library sources. Supersedes mbed-src.
Fork of mbed-dev by
targets/hal/TARGET_Freescale/TARGET_KLXX/sleep.c@0:9b334a45a8ff, 2015-10-01 (annotated)
- Committer:
- bogdanm
- Date:
- Thu Oct 01 15:25:22 2015 +0300
- Revision:
- 0:9b334a45a8ff
- Child:
- 144:ef7eb2e8f9f7
Initial commit on mbed-dev
Replaces mbed-src (now inactive)
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 0:9b334a45a8ff | 1 | /* mbed Microcontroller Library |
bogdanm | 0:9b334a45a8ff | 2 | * Copyright (c) 2006-2013 ARM Limited |
bogdanm | 0:9b334a45a8ff | 3 | * |
bogdanm | 0:9b334a45a8ff | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
bogdanm | 0:9b334a45a8ff | 5 | * you may not use this file except in compliance with the License. |
bogdanm | 0:9b334a45a8ff | 6 | * You may obtain a copy of the License at |
bogdanm | 0:9b334a45a8ff | 7 | * |
bogdanm | 0:9b334a45a8ff | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
bogdanm | 0:9b334a45a8ff | 9 | * |
bogdanm | 0:9b334a45a8ff | 10 | * Unless required by applicable law or agreed to in writing, software |
bogdanm | 0:9b334a45a8ff | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
bogdanm | 0:9b334a45a8ff | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
bogdanm | 0:9b334a45a8ff | 13 | * See the License for the specific language governing permissions and |
bogdanm | 0:9b334a45a8ff | 14 | * limitations under the License. |
bogdanm | 0:9b334a45a8ff | 15 | */ |
bogdanm | 0:9b334a45a8ff | 16 | #include "sleep_api.h" |
bogdanm | 0:9b334a45a8ff | 17 | #include "cmsis.h" |
bogdanm | 0:9b334a45a8ff | 18 | #include "PeripheralPins.h" |
bogdanm | 0:9b334a45a8ff | 19 | |
bogdanm | 0:9b334a45a8ff | 20 | //Normal wait mode |
bogdanm | 0:9b334a45a8ff | 21 | void sleep(void) |
bogdanm | 0:9b334a45a8ff | 22 | { |
bogdanm | 0:9b334a45a8ff | 23 | SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK; |
bogdanm | 0:9b334a45a8ff | 24 | |
bogdanm | 0:9b334a45a8ff | 25 | //Normal sleep mode for ARM core: |
bogdanm | 0:9b334a45a8ff | 26 | SCB->SCR = 0; |
bogdanm | 0:9b334a45a8ff | 27 | __WFI(); |
bogdanm | 0:9b334a45a8ff | 28 | } |
bogdanm | 0:9b334a45a8ff | 29 | |
bogdanm | 0:9b334a45a8ff | 30 | //Very low-power stop mode |
bogdanm | 0:9b334a45a8ff | 31 | void deepsleep(void) |
bogdanm | 0:9b334a45a8ff | 32 | { |
bogdanm | 0:9b334a45a8ff | 33 | //Check if ADC is enabled and HS mode is set, if yes disable it (lowers power consumption by 60uA) |
bogdanm | 0:9b334a45a8ff | 34 | uint8_t ADC_HSC = 0; |
bogdanm | 0:9b334a45a8ff | 35 | if (SIM->SCGC6 & SIM_SCGC6_ADC0_MASK) { |
bogdanm | 0:9b334a45a8ff | 36 | if (ADC0->CFG2 & ADC_CFG2_ADHSC_MASK) { |
bogdanm | 0:9b334a45a8ff | 37 | ADC_HSC = 1; |
bogdanm | 0:9b334a45a8ff | 38 | ADC0->CFG2 &= ~(ADC_CFG2_ADHSC_MASK); |
bogdanm | 0:9b334a45a8ff | 39 | } |
bogdanm | 0:9b334a45a8ff | 40 | } |
bogdanm | 0:9b334a45a8ff | 41 | |
bogdanm | 0:9b334a45a8ff | 42 | #if ! defined(TARGET_KL43Z) |
bogdanm | 0:9b334a45a8ff | 43 | //Check if PLL/FLL is enabled: |
bogdanm | 0:9b334a45a8ff | 44 | uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0); |
bogdanm | 0:9b334a45a8ff | 45 | #endif |
bogdanm | 0:9b334a45a8ff | 46 | |
bogdanm | 0:9b334a45a8ff | 47 | SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK; |
bogdanm | 0:9b334a45a8ff | 48 | SMC->PMCTRL = SMC_PMCTRL_STOPM(2); |
bogdanm | 0:9b334a45a8ff | 49 | |
bogdanm | 0:9b334a45a8ff | 50 | //Deep sleep for ARM core: |
bogdanm | 0:9b334a45a8ff | 51 | SCB->SCR = 1<<SCB_SCR_SLEEPDEEP_Pos; |
bogdanm | 0:9b334a45a8ff | 52 | |
bogdanm | 0:9b334a45a8ff | 53 | __WFI(); |
bogdanm | 0:9b334a45a8ff | 54 | |
bogdanm | 0:9b334a45a8ff | 55 | #if ! defined(TARGET_KL43Z) |
bogdanm | 0:9b334a45a8ff | 56 | //Switch back to PLL as clock source if needed |
bogdanm | 0:9b334a45a8ff | 57 | //The interrupt that woke up the device will run at reduced speed |
bogdanm | 0:9b334a45a8ff | 58 | if (PLL_FLL_en) { |
bogdanm | 0:9b334a45a8ff | 59 | #ifdef MCG_C5_PLLCLKEN0_MASK //PLL available |
bogdanm | 0:9b334a45a8ff | 60 | if (MCG->C6 & (1<<MCG_C6_PLLS_SHIFT) != 0) /* If PLL */ |
bogdanm | 0:9b334a45a8ff | 61 | while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */ |
bogdanm | 0:9b334a45a8ff | 62 | #endif |
bogdanm | 0:9b334a45a8ff | 63 | MCG->C1 &= ~MCG_C1_CLKS_MASK; |
bogdanm | 0:9b334a45a8ff | 64 | } |
bogdanm | 0:9b334a45a8ff | 65 | #endif |
bogdanm | 0:9b334a45a8ff | 66 | |
bogdanm | 0:9b334a45a8ff | 67 | if (ADC_HSC) { |
bogdanm | 0:9b334a45a8ff | 68 | ADC0->CFG2 |= (ADC_CFG2_ADHSC_MASK); |
bogdanm | 0:9b334a45a8ff | 69 | } |
bogdanm | 0:9b334a45a8ff | 70 | } |