Sippakorn Saeng-aroon / Mbed 2 deprecated InventorStudio_LCP2

v1.1

Dependencies:   mbed QEI

RF/MFRC522.cpp@4:4b28e4aa1742, 2019-05-05 (annotated)

Committer:
sippasaeng
Date:
Sun May 05 18:17:07 2019 +0000
Revision:
4:4b28e4aa1742
v1.1 update char-->int type

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sippasaeng 4:4b28e4aa1742 1 /*
sippasaeng 4:4b28e4aa1742 2 * MFRC522.cpp - Library to use ARDUINO RFID MODULE KIT 13.56 MHZ WITH TAGS SPI W AND R BY COOQROBOT.
sippasaeng 4:4b28e4aa1742 3 * _Please_ see the comments in MFRC522.h - they give useful hints and background.
sippasaeng 4:4b28e4aa1742 4 * Released into the public domain.
sippasaeng 4:4b28e4aa1742 5 */
sippasaeng 4:4b28e4aa1742 6
sippasaeng 4:4b28e4aa1742 7 #include "MFRC522.h"
sippasaeng 4:4b28e4aa1742 8
sippasaeng 4:4b28e4aa1742 9 static const char* const _TypeNamePICC[] =
sippasaeng 4:4b28e4aa1742 10 {
sippasaeng 4:4b28e4aa1742 11 "Unknown type",
sippasaeng 4:4b28e4aa1742 12 "PICC compliant with ISO/IEC 14443-4",
sippasaeng 4:4b28e4aa1742 13 "PICC compliant with ISO/IEC 18092 (NFC)",
sippasaeng 4:4b28e4aa1742 14 "MIFARE Mini, 320 bytes",
sippasaeng 4:4b28e4aa1742 15 "MIFARE 1KB",
sippasaeng 4:4b28e4aa1742 16 "MIFARE 4KB",
sippasaeng 4:4b28e4aa1742 17 "MIFARE Ultralight or Ultralight C",
sippasaeng 4:4b28e4aa1742 18 "MIFARE Plus",
sippasaeng 4:4b28e4aa1742 19 "MIFARE TNP3XXX",
sippasaeng 4:4b28e4aa1742 20
sippasaeng 4:4b28e4aa1742 21 /* not complete UID */
sippasaeng 4:4b28e4aa1742 22 "SAK indicates UID is not complete"
sippasaeng 4:4b28e4aa1742 23 };
sippasaeng 4:4b28e4aa1742 24
sippasaeng 4:4b28e4aa1742 25 static const char* const _ErrorMessage[] =
sippasaeng 4:4b28e4aa1742 26 {
sippasaeng 4:4b28e4aa1742 27 "Unknown error",
sippasaeng 4:4b28e4aa1742 28 "Success",
sippasaeng 4:4b28e4aa1742 29 "Error in communication",
sippasaeng 4:4b28e4aa1742 30 "Collision detected",
sippasaeng 4:4b28e4aa1742 31 "Timeout in communication",
sippasaeng 4:4b28e4aa1742 32 "A buffer is not big enough",
sippasaeng 4:4b28e4aa1742 33 "Internal error in the code, should not happen",
sippasaeng 4:4b28e4aa1742 34 "Invalid argument",
sippasaeng 4:4b28e4aa1742 35 "The CRC_A does not match",
sippasaeng 4:4b28e4aa1742 36 "A MIFARE PICC responded with NAK"
sippasaeng 4:4b28e4aa1742 37 };
sippasaeng 4:4b28e4aa1742 38
sippasaeng 4:4b28e4aa1742 39 #define MFRC522_MaxPICCs (sizeof(_TypeNamePICC)/sizeof(_TypeNamePICC[0]))
sippasaeng 4:4b28e4aa1742 40 #define MFRC522_MaxError (sizeof(_ErrorMessage)/sizeof(_ErrorMessage[0]))
sippasaeng 4:4b28e4aa1742 41
sippasaeng 4:4b28e4aa1742 42 /////////////////////////////////////////////////////////////////////////////////////
sippasaeng 4:4b28e4aa1742 43 // Functions for setting up the driver
sippasaeng 4:4b28e4aa1742 44 /////////////////////////////////////////////////////////////////////////////////////
sippasaeng 4:4b28e4aa1742 45
sippasaeng 4:4b28e4aa1742 46 /**
sippasaeng 4:4b28e4aa1742 47 * Constructor.
sippasaeng 4:4b28e4aa1742 48 * Prepares the output pins.
sippasaeng 4:4b28e4aa1742 49 */
sippasaeng 4:4b28e4aa1742 50 MFRC522::MFRC522(PinName mosi,
sippasaeng 4:4b28e4aa1742 51 PinName miso,
sippasaeng 4:4b28e4aa1742 52 PinName sclk,
sippasaeng 4:4b28e4aa1742 53 PinName cs,
sippasaeng 4:4b28e4aa1742 54 PinName reset) : m_SPI(mosi, miso, sclk), m_CS(cs), m_RESET(reset)
sippasaeng 4:4b28e4aa1742 55 {
sippasaeng 4:4b28e4aa1742 56 /* Configure SPI bus */
sippasaeng 4:4b28e4aa1742 57 m_SPI.format(8, 0);
sippasaeng 4:4b28e4aa1742 58 m_SPI.frequency(8000000);
sippasaeng 4:4b28e4aa1742 59
sippasaeng 4:4b28e4aa1742 60 /* Release SPI-CS pin */
sippasaeng 4:4b28e4aa1742 61 m_CS = 1;
sippasaeng 4:4b28e4aa1742 62
sippasaeng 4:4b28e4aa1742 63 /* Release RESET pin */
sippasaeng 4:4b28e4aa1742 64 m_RESET = 1;
sippasaeng 4:4b28e4aa1742 65 } // End constructor
sippasaeng 4:4b28e4aa1742 66
sippasaeng 4:4b28e4aa1742 67
sippasaeng 4:4b28e4aa1742 68 /**
sippasaeng 4:4b28e4aa1742 69 * Destructor.
sippasaeng 4:4b28e4aa1742 70 */
sippasaeng 4:4b28e4aa1742 71 MFRC522::~MFRC522()
sippasaeng 4:4b28e4aa1742 72 {
sippasaeng 4:4b28e4aa1742 73
sippasaeng 4:4b28e4aa1742 74 }
sippasaeng 4:4b28e4aa1742 75
sippasaeng 4:4b28e4aa1742 76
sippasaeng 4:4b28e4aa1742 77 /////////////////////////////////////////////////////////////////////////////////////
sippasaeng 4:4b28e4aa1742 78 // Basic interface functions for communicating with the MFRC522
sippasaeng 4:4b28e4aa1742 79 /////////////////////////////////////////////////////////////////////////////////////
sippasaeng 4:4b28e4aa1742 80
sippasaeng 4:4b28e4aa1742 81 /**
sippasaeng 4:4b28e4aa1742 82 * Writes a byte to the specified register in the MFRC522 chip.
sippasaeng 4:4b28e4aa1742 83 * The interface is described in the datasheet section 8.1.2.
sippasaeng 4:4b28e4aa1742 84 */
sippasaeng 4:4b28e4aa1742 85 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t value)
sippasaeng 4:4b28e4aa1742 86 {
sippasaeng 4:4b28e4aa1742 87 m_CS = 0; /* Select SPI Chip MFRC522 */
sippasaeng 4:4b28e4aa1742 88
sippasaeng 4:4b28e4aa1742 89 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
sippasaeng 4:4b28e4aa1742 90 (void) m_SPI.write(reg & 0x7E);
sippasaeng 4:4b28e4aa1742 91 (void) m_SPI.write(value);
sippasaeng 4:4b28e4aa1742 92
sippasaeng 4:4b28e4aa1742 93 m_CS = 1; /* Release SPI Chip MFRC522 */
sippasaeng 4:4b28e4aa1742 94 } // End PCD_WriteRegister()
sippasaeng 4:4b28e4aa1742 95
sippasaeng 4:4b28e4aa1742 96 /**
sippasaeng 4:4b28e4aa1742 97 * Writes a number of bytes to the specified register in the MFRC522 chip.
sippasaeng 4:4b28e4aa1742 98 * The interface is described in the datasheet section 8.1.2.
sippasaeng 4:4b28e4aa1742 99 */
sippasaeng 4:4b28e4aa1742 100 void MFRC522::PCD_WriteRegister(uint8_t reg, uint8_t count, uint8_t *values)
sippasaeng 4:4b28e4aa1742 101 {
sippasaeng 4:4b28e4aa1742 102 m_CS = 0; /* Select SPI Chip MFRC522 */
sippasaeng 4:4b28e4aa1742 103
sippasaeng 4:4b28e4aa1742 104 // MSB == 0 is for writing. LSB is not used in address. Datasheet section 8.1.2.3.
sippasaeng 4:4b28e4aa1742 105 (void) m_SPI.write(reg & 0x7E);
sippasaeng 4:4b28e4aa1742 106 for (uint8_t index = 0; index < count; index++)
sippasaeng 4:4b28e4aa1742 107 {
sippasaeng 4:4b28e4aa1742 108 (void) m_SPI.write(values[index]);
sippasaeng 4:4b28e4aa1742 109 }
sippasaeng 4:4b28e4aa1742 110
sippasaeng 4:4b28e4aa1742 111 m_CS = 1; /* Release SPI Chip MFRC522 */
sippasaeng 4:4b28e4aa1742 112 } // End PCD_WriteRegister()
sippasaeng 4:4b28e4aa1742 113
sippasaeng 4:4b28e4aa1742 114 /**
sippasaeng 4:4b28e4aa1742 115 * Reads a byte from the specified register in the MFRC522 chip.
sippasaeng 4:4b28e4aa1742 116 * The interface is described in the datasheet section 8.1.2.
sippasaeng 4:4b28e4aa1742 117 */
sippasaeng 4:4b28e4aa1742 118 uint8_t MFRC522::PCD_ReadRegister(uint8_t reg)
sippasaeng 4:4b28e4aa1742 119 {
sippasaeng 4:4b28e4aa1742 120 uint8_t value;
sippasaeng 4:4b28e4aa1742 121 m_CS = 0; /* Select SPI Chip MFRC522 */
sippasaeng 4:4b28e4aa1742 122
sippasaeng 4:4b28e4aa1742 123 // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
sippasaeng 4:4b28e4aa1742 124 (void) m_SPI.write(0x80 | reg);
sippasaeng 4:4b28e4aa1742 125
sippasaeng 4:4b28e4aa1742 126 // Read the value back. Send 0 to stop reading.
sippasaeng 4:4b28e4aa1742 127 value = m_SPI.write(0);
sippasaeng 4:4b28e4aa1742 128
sippasaeng 4:4b28e4aa1742 129 m_CS = 1; /* Release SPI Chip MFRC522 */
sippasaeng 4:4b28e4aa1742 130
sippasaeng 4:4b28e4aa1742 131 return value;
sippasaeng 4:4b28e4aa1742 132 } // End PCD_ReadRegister()
sippasaeng 4:4b28e4aa1742 133
sippasaeng 4:4b28e4aa1742 134 /**
sippasaeng 4:4b28e4aa1742 135 * Reads a number of bytes from the specified register in the MFRC522 chip.
sippasaeng 4:4b28e4aa1742 136 * The interface is described in the datasheet section 8.1.2.
sippasaeng 4:4b28e4aa1742 137 */
sippasaeng 4:4b28e4aa1742 138 void MFRC522::PCD_ReadRegister(uint8_t reg, uint8_t count, uint8_t *values, uint8_t rxAlign)
sippasaeng 4:4b28e4aa1742 139 {
sippasaeng 4:4b28e4aa1742 140 if (count == 0) { return; }
sippasaeng 4:4b28e4aa1742 141
sippasaeng 4:4b28e4aa1742 142 uint8_t address = 0x80 | reg; // MSB == 1 is for reading. LSB is not used in address. Datasheet section 8.1.2.3.
sippasaeng 4:4b28e4aa1742 143 uint8_t index = 0; // Index in values array.
sippasaeng 4:4b28e4aa1742 144
sippasaeng 4:4b28e4aa1742 145 m_CS = 0; /* Select SPI Chip MFRC522 */
sippasaeng 4:4b28e4aa1742 146 count--; // One read is performed outside of the loop
sippasaeng 4:4b28e4aa1742 147 (void) m_SPI.write(address); // Tell MFRC522 which address we want to read
sippasaeng 4:4b28e4aa1742 148
sippasaeng 4:4b28e4aa1742 149 while (index < count)
sippasaeng 4:4b28e4aa1742 150 {
sippasaeng 4:4b28e4aa1742 151 if ((index == 0) && rxAlign) // Only update bit positions rxAlign..7 in values[0]
sippasaeng 4:4b28e4aa1742 152 {
sippasaeng 4:4b28e4aa1742 153 // Create bit mask for bit positions rxAlign..7
sippasaeng 4:4b28e4aa1742 154 uint8_t mask = 0;
sippasaeng 4:4b28e4aa1742 155 for (uint8_t i = rxAlign; i <= 7; i++)
sippasaeng 4:4b28e4aa1742 156 {
sippasaeng 4:4b28e4aa1742 157 mask |= (1 << i);
sippasaeng 4:4b28e4aa1742 158 }
sippasaeng 4:4b28e4aa1742 159
sippasaeng 4:4b28e4aa1742 160 // Read value and tell that we want to read the same address again.
sippasaeng 4:4b28e4aa1742 161 uint8_t value = m_SPI.write(address);
sippasaeng 4:4b28e4aa1742 162
sippasaeng 4:4b28e4aa1742 163 // Apply mask to both current value of values[0] and the new data in value.
sippasaeng 4:4b28e4aa1742 164 values[0] = (values[index] & ~mask) | (value & mask);
sippasaeng 4:4b28e4aa1742 165 }
sippasaeng 4:4b28e4aa1742 166 else
sippasaeng 4:4b28e4aa1742 167 {
sippasaeng 4:4b28e4aa1742 168 // Read value and tell that we want to read the same address again.
sippasaeng 4:4b28e4aa1742 169 values[index] = m_SPI.write(address);
sippasaeng 4:4b28e4aa1742 170 }
sippasaeng 4:4b28e4aa1742 171
sippasaeng 4:4b28e4aa1742 172 index++;
sippasaeng 4:4b28e4aa1742 173 }
sippasaeng 4:4b28e4aa1742 174
sippasaeng 4:4b28e4aa1742 175 values[index] = m_SPI.write(0); // Read the final byte. Send 0 to stop reading.
sippasaeng 4:4b28e4aa1742 176
sippasaeng 4:4b28e4aa1742 177 m_CS = 1; /* Release SPI Chip MFRC522 */
sippasaeng 4:4b28e4aa1742 178 } // End PCD_ReadRegister()
sippasaeng 4:4b28e4aa1742 179
sippasaeng 4:4b28e4aa1742 180 /**
sippasaeng 4:4b28e4aa1742 181 * Sets the bits given in mask in register reg.
sippasaeng 4:4b28e4aa1742 182 */
sippasaeng 4:4b28e4aa1742 183 void MFRC522::PCD_SetRegisterBits(uint8_t reg, uint8_t mask)
sippasaeng 4:4b28e4aa1742 184 {
sippasaeng 4:4b28e4aa1742 185 uint8_t tmp = PCD_ReadRegister(reg);
sippasaeng 4:4b28e4aa1742 186 PCD_WriteRegister(reg, tmp | mask); // set bit mask
sippasaeng 4:4b28e4aa1742 187 } // End PCD_SetRegisterBitMask()
sippasaeng 4:4b28e4aa1742 188
sippasaeng 4:4b28e4aa1742 189 /**
sippasaeng 4:4b28e4aa1742 190 * Clears the bits given in mask from register reg.
sippasaeng 4:4b28e4aa1742 191 */
sippasaeng 4:4b28e4aa1742 192 void MFRC522::PCD_ClrRegisterBits(uint8_t reg, uint8_t mask)
sippasaeng 4:4b28e4aa1742 193 {
sippasaeng 4:4b28e4aa1742 194 uint8_t tmp = PCD_ReadRegister(reg);
sippasaeng 4:4b28e4aa1742 195 PCD_WriteRegister(reg, tmp & (~mask)); // clear bit mask
sippasaeng 4:4b28e4aa1742 196 } // End PCD_ClearRegisterBitMask()
sippasaeng 4:4b28e4aa1742 197
sippasaeng 4:4b28e4aa1742 198
sippasaeng 4:4b28e4aa1742 199 /**
sippasaeng 4:4b28e4aa1742 200 * Use the CRC coprocessor in the MFRC522 to calculate a CRC_A.
sippasaeng 4:4b28e4aa1742 201 */
sippasaeng 4:4b28e4aa1742 202 uint8_t MFRC522::PCD_CalculateCRC(uint8_t *data, uint8_t length, uint8_t *result)
sippasaeng 4:4b28e4aa1742 203 {
sippasaeng 4:4b28e4aa1742 204 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
sippasaeng 4:4b28e4aa1742 205 PCD_WriteRegister(DivIrqReg, 0x04); // Clear the CRCIRq interrupt request bit
sippasaeng 4:4b28e4aa1742 206 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
sippasaeng 4:4b28e4aa1742 207 PCD_WriteRegister(FIFODataReg, length, data); // Write data to the FIFO
sippasaeng 4:4b28e4aa1742 208 PCD_WriteRegister(CommandReg, PCD_CalcCRC); // Start the calculation
sippasaeng 4:4b28e4aa1742 209
sippasaeng 4:4b28e4aa1742 210 // Wait for the CRC calculation to complete. Each iteration of the while-loop takes 17.73us.
sippasaeng 4:4b28e4aa1742 211 uint16_t i = 5000;
sippasaeng 4:4b28e4aa1742 212 uint8_t n;
sippasaeng 4:4b28e4aa1742 213 while (1)
sippasaeng 4:4b28e4aa1742 214 {
sippasaeng 4:4b28e4aa1742 215 n = PCD_ReadRegister(DivIrqReg); // DivIrqReg[7..0] bits are: Set2 reserved reserved MfinActIRq reserved CRCIRq reserved reserved
sippasaeng 4:4b28e4aa1742 216 if (n & 0x04)
sippasaeng 4:4b28e4aa1742 217 {
sippasaeng 4:4b28e4aa1742 218 // CRCIRq bit set - calculation done
sippasaeng 4:4b28e4aa1742 219 break;
sippasaeng 4:4b28e4aa1742 220 }
sippasaeng 4:4b28e4aa1742 221
sippasaeng 4:4b28e4aa1742 222 if (--i == 0)
sippasaeng 4:4b28e4aa1742 223 {
sippasaeng 4:4b28e4aa1742 224 // The emergency break. We will eventually terminate on this one after 89ms.
sippasaeng 4:4b28e4aa1742 225 // Communication with the MFRC522 might be down.
sippasaeng 4:4b28e4aa1742 226 return STATUS_TIMEOUT;
sippasaeng 4:4b28e4aa1742 227 }
sippasaeng 4:4b28e4aa1742 228 }
sippasaeng 4:4b28e4aa1742 229
sippasaeng 4:4b28e4aa1742 230 // Stop calculating CRC for new content in the FIFO.
sippasaeng 4:4b28e4aa1742 231 PCD_WriteRegister(CommandReg, PCD_Idle);
sippasaeng 4:4b28e4aa1742 232
sippasaeng 4:4b28e4aa1742 233 // Transfer the result from the registers to the result buffer
sippasaeng 4:4b28e4aa1742 234 result[0] = PCD_ReadRegister(CRCResultRegL);
sippasaeng 4:4b28e4aa1742 235 result[1] = PCD_ReadRegister(CRCResultRegH);
sippasaeng 4:4b28e4aa1742 236 return STATUS_OK;
sippasaeng 4:4b28e4aa1742 237 } // End PCD_CalculateCRC()
sippasaeng 4:4b28e4aa1742 238
sippasaeng 4:4b28e4aa1742 239
sippasaeng 4:4b28e4aa1742 240 /////////////////////////////////////////////////////////////////////////////////////
sippasaeng 4:4b28e4aa1742 241 // Functions for manipulating the MFRC522
sippasaeng 4:4b28e4aa1742 242 /////////////////////////////////////////////////////////////////////////////////////
sippasaeng 4:4b28e4aa1742 243
sippasaeng 4:4b28e4aa1742 244 /**
sippasaeng 4:4b28e4aa1742 245 * Initializes the MFRC522 chip.
sippasaeng 4:4b28e4aa1742 246 */
sippasaeng 4:4b28e4aa1742 247 void MFRC522::PCD_Init()
sippasaeng 4:4b28e4aa1742 248 {
sippasaeng 4:4b28e4aa1742 249 /* Reset MFRC522 */
sippasaeng 4:4b28e4aa1742 250 m_RESET = 0;
sippasaeng 4:4b28e4aa1742 251 wait_ms(10);
sippasaeng 4:4b28e4aa1742 252 m_RESET = 1;
sippasaeng 4:4b28e4aa1742 253
sippasaeng 4:4b28e4aa1742 254 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
sippasaeng 4:4b28e4aa1742 255 wait_ms(50);
sippasaeng 4:4b28e4aa1742 256
sippasaeng 4:4b28e4aa1742 257 // When communicating with a PICC we need a timeout if something goes wrong.
sippasaeng 4:4b28e4aa1742 258 // f_timer = 13.56 MHz / (2*TPreScaler+1) where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo].
sippasaeng 4:4b28e4aa1742 259 // TPrescaler_Hi are the four low bits in TModeReg. TPrescaler_Lo is TPrescalerReg.
sippasaeng 4:4b28e4aa1742 260 PCD_WriteRegister(TModeReg, 0x80); // TAuto=1; timer starts automatically at the end of the transmission in all communication modes at all speeds
sippasaeng 4:4b28e4aa1742 261 PCD_WriteRegister(TPrescalerReg, 0xA9); // TPreScaler = TModeReg[3..0]:TPrescalerReg, ie 0x0A9 = 169 => f_timer=40kHz, ie a timer period of 25us.
sippasaeng 4:4b28e4aa1742 262 PCD_WriteRegister(TReloadRegH, 0x03); // Reload timer with 0x3E8 = 1000, ie 25ms before timeout.
sippasaeng 4:4b28e4aa1742 263 PCD_WriteRegister(TReloadRegL, 0xE8);
sippasaeng 4:4b28e4aa1742 264
sippasaeng 4:4b28e4aa1742 265 PCD_WriteRegister(TxASKReg, 0x40); // Default 0x00. Force a 100 % ASK modulation independent of the ModGsPReg register setting
sippasaeng 4:4b28e4aa1742 266 PCD_WriteRegister(ModeReg, 0x3D); // Default 0x3F. Set the preset value for the CRC coprocessor for the CalcCRC command to 0x6363 (ISO 14443-3 part 6.2.4)
sippasaeng 4:4b28e4aa1742 267
sippasaeng 4:4b28e4aa1742 268 PCD_WriteRegister(RFCfgReg, (0x07<<4)); // Set Rx Gain to max
sippasaeng 4:4b28e4aa1742 269
sippasaeng 4:4b28e4aa1742 270 PCD_AntennaOn(); // Enable the antenna driver pins TX1 and TX2 (they were disabled by the reset)
sippasaeng 4:4b28e4aa1742 271 } // End PCD_Init()
sippasaeng 4:4b28e4aa1742 272
sippasaeng 4:4b28e4aa1742 273 /**
sippasaeng 4:4b28e4aa1742 274 * Performs a soft reset on the MFRC522 chip and waits for it to be ready again.
sippasaeng 4:4b28e4aa1742 275 */
sippasaeng 4:4b28e4aa1742 276 void MFRC522::PCD_Reset()
sippasaeng 4:4b28e4aa1742 277 {
sippasaeng 4:4b28e4aa1742 278 PCD_WriteRegister(CommandReg, PCD_SoftReset); // Issue the SoftReset command.
sippasaeng 4:4b28e4aa1742 279 // The datasheet does not mention how long the SoftRest command takes to complete.
sippasaeng 4:4b28e4aa1742 280 // But the MFRC522 might have been in soft power-down mode (triggered by bit 4 of CommandReg)
sippasaeng 4:4b28e4aa1742 281 // Section 8.8.2 in the datasheet says the oscillator start-up time is the start up time of the crystal + 37,74us. Let us be generous: 50ms.
sippasaeng 4:4b28e4aa1742 282 wait_ms(50);
sippasaeng 4:4b28e4aa1742 283
sippasaeng 4:4b28e4aa1742 284 // Wait for the PowerDown bit in CommandReg to be cleared
sippasaeng 4:4b28e4aa1742 285 while (PCD_ReadRegister(CommandReg) & (1<<4))
sippasaeng 4:4b28e4aa1742 286 {
sippasaeng 4:4b28e4aa1742 287 // PCD still restarting - unlikely after waiting 50ms, but better safe than sorry.
sippasaeng 4:4b28e4aa1742 288 }
sippasaeng 4:4b28e4aa1742 289 } // End PCD_Reset()
sippasaeng 4:4b28e4aa1742 290
sippasaeng 4:4b28e4aa1742 291 /**
sippasaeng 4:4b28e4aa1742 292 * Turns the antenna on by enabling pins TX1 and TX2.
sippasaeng 4:4b28e4aa1742 293 * After a reset these pins disabled.
sippasaeng 4:4b28e4aa1742 294 */
sippasaeng 4:4b28e4aa1742 295 void MFRC522::PCD_AntennaOn()
sippasaeng 4:4b28e4aa1742 296 {
sippasaeng 4:4b28e4aa1742 297 uint8_t value = PCD_ReadRegister(TxControlReg);
sippasaeng 4:4b28e4aa1742 298 if ((value & 0x03) != 0x03)
sippasaeng 4:4b28e4aa1742 299 {
sippasaeng 4:4b28e4aa1742 300 PCD_WriteRegister(TxControlReg, value | 0x03);
sippasaeng 4:4b28e4aa1742 301 }
sippasaeng 4:4b28e4aa1742 302 } // End PCD_AntennaOn()
sippasaeng 4:4b28e4aa1742 303
sippasaeng 4:4b28e4aa1742 304 /////////////////////////////////////////////////////////////////////////////////////
sippasaeng 4:4b28e4aa1742 305 // Functions for communicating with PICCs
sippasaeng 4:4b28e4aa1742 306 /////////////////////////////////////////////////////////////////////////////////////
sippasaeng 4:4b28e4aa1742 307
sippasaeng 4:4b28e4aa1742 308 /**
sippasaeng 4:4b28e4aa1742 309 * Executes the Transceive command.
sippasaeng 4:4b28e4aa1742 310 * CRC validation can only be done if backData and backLen are specified.
sippasaeng 4:4b28e4aa1742 311 */
sippasaeng 4:4b28e4aa1742 312 uint8_t MFRC522::PCD_TransceiveData(uint8_t *sendData,
sippasaeng 4:4b28e4aa1742 313 uint8_t sendLen,
sippasaeng 4:4b28e4aa1742 314 uint8_t *backData,
sippasaeng 4:4b28e4aa1742 315 uint8_t *backLen,
sippasaeng 4:4b28e4aa1742 316 uint8_t *validBits,
sippasaeng 4:4b28e4aa1742 317 uint8_t rxAlign,
sippasaeng 4:4b28e4aa1742 318 bool checkCRC)
sippasaeng 4:4b28e4aa1742 319 {
sippasaeng 4:4b28e4aa1742 320 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
sippasaeng 4:4b28e4aa1742 321 return PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, sendData, sendLen, backData, backLen, validBits, rxAlign, checkCRC);
sippasaeng 4:4b28e4aa1742 322 } // End PCD_TransceiveData()
sippasaeng 4:4b28e4aa1742 323
sippasaeng 4:4b28e4aa1742 324 /**
sippasaeng 4:4b28e4aa1742 325 * Transfers data to the MFRC522 FIFO, executes a commend, waits for completion and transfers data back from the FIFO.
sippasaeng 4:4b28e4aa1742 326 * CRC validation can only be done if backData and backLen are specified.
sippasaeng 4:4b28e4aa1742 327 */
sippasaeng 4:4b28e4aa1742 328 uint8_t MFRC522::PCD_CommunicateWithPICC(uint8_t command,
sippasaeng 4:4b28e4aa1742 329 uint8_t waitIRq,
sippasaeng 4:4b28e4aa1742 330 uint8_t *sendData,
sippasaeng 4:4b28e4aa1742 331 uint8_t sendLen,
sippasaeng 4:4b28e4aa1742 332 uint8_t *backData,
sippasaeng 4:4b28e4aa1742 333 uint8_t *backLen,
sippasaeng 4:4b28e4aa1742 334 uint8_t *validBits,
sippasaeng 4:4b28e4aa1742 335 uint8_t rxAlign,
sippasaeng 4:4b28e4aa1742 336 bool checkCRC)
sippasaeng 4:4b28e4aa1742 337 {
sippasaeng 4:4b28e4aa1742 338 uint8_t n, _validBits = 0;
sippasaeng 4:4b28e4aa1742 339 uint32_t i;
sippasaeng 4:4b28e4aa1742 340
sippasaeng 4:4b28e4aa1742 341 // Prepare values for BitFramingReg
sippasaeng 4:4b28e4aa1742 342 uint8_t txLastBits = validBits ? *validBits : 0;
sippasaeng 4:4b28e4aa1742 343 uint8_t bitFraming = (rxAlign << 4) + txLastBits; // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
sippasaeng 4:4b28e4aa1742 344
sippasaeng 4:4b28e4aa1742 345 PCD_WriteRegister(CommandReg, PCD_Idle); // Stop any active command.
sippasaeng 4:4b28e4aa1742 346 PCD_WriteRegister(ComIrqReg, 0x7F); // Clear all seven interrupt request bits
sippasaeng 4:4b28e4aa1742 347 PCD_SetRegisterBits(FIFOLevelReg, 0x80); // FlushBuffer = 1, FIFO initialization
sippasaeng 4:4b28e4aa1742 348 PCD_WriteRegister(FIFODataReg, sendLen, sendData); // Write sendData to the FIFO
sippasaeng 4:4b28e4aa1742 349 PCD_WriteRegister(BitFramingReg, bitFraming); // Bit adjustments
sippasaeng 4:4b28e4aa1742 350 PCD_WriteRegister(CommandReg, command); // Execute the command
sippasaeng 4:4b28e4aa1742 351 if (command == PCD_Transceive)
sippasaeng 4:4b28e4aa1742 352 {
sippasaeng 4:4b28e4aa1742 353 PCD_SetRegisterBits(BitFramingReg, 0x80); // StartSend=1, transmission of data starts
sippasaeng 4:4b28e4aa1742 354 }
sippasaeng 4:4b28e4aa1742 355
sippasaeng 4:4b28e4aa1742 356 // Wait for the command to complete.
sippasaeng 4:4b28e4aa1742 357 // In PCD_Init() we set the TAuto flag in TModeReg. This means the timer automatically starts when the PCD stops transmitting.
sippasaeng 4:4b28e4aa1742 358 // Each iteration of the do-while-loop takes 17.86us.
sippasaeng 4:4b28e4aa1742 359 i = 2000;
sippasaeng 4:4b28e4aa1742 360 while (1)
sippasaeng 4:4b28e4aa1742 361 {
sippasaeng 4:4b28e4aa1742 362 n = PCD_ReadRegister(ComIrqReg); // ComIrqReg[7..0] bits are: Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq
sippasaeng 4:4b28e4aa1742 363 if (n & waitIRq)
sippasaeng 4:4b28e4aa1742 364 { // One of the interrupts that signal success has been set.
sippasaeng 4:4b28e4aa1742 365 break;
sippasaeng 4:4b28e4aa1742 366 }
sippasaeng 4:4b28e4aa1742 367
sippasaeng 4:4b28e4aa1742 368 if (n & 0x01)
sippasaeng 4:4b28e4aa1742 369 { // Timer interrupt - nothing received in 25ms
sippasaeng 4:4b28e4aa1742 370 return STATUS_TIMEOUT;
sippasaeng 4:4b28e4aa1742 371 }
sippasaeng 4:4b28e4aa1742 372
sippasaeng 4:4b28e4aa1742 373 if (--i == 0)
sippasaeng 4:4b28e4aa1742 374 { // The emergency break. If all other condions fail we will eventually terminate on this one after 35.7ms. Communication with the MFRC522 might be down.
sippasaeng 4:4b28e4aa1742 375 return STATUS_TIMEOUT;
sippasaeng 4:4b28e4aa1742 376 }
sippasaeng 4:4b28e4aa1742 377 }
sippasaeng 4:4b28e4aa1742 378
sippasaeng 4:4b28e4aa1742 379 // Stop now if any errors except collisions were detected.
sippasaeng 4:4b28e4aa1742 380 uint8_t errorRegValue = PCD_ReadRegister(ErrorReg); // ErrorReg[7..0] bits are: WrErr TempErr reserved BufferOvfl CollErr CRCErr ParityErr ProtocolErr
sippasaeng 4:4b28e4aa1742 381 if (errorRegValue & 0x13)
sippasaeng 4:4b28e4aa1742 382 { // BufferOvfl ParityErr ProtocolErr
sippasaeng 4:4b28e4aa1742 383 return STATUS_ERROR;
sippasaeng 4:4b28e4aa1742 384 }
sippasaeng 4:4b28e4aa1742 385
sippasaeng 4:4b28e4aa1742 386 // If the caller wants data back, get it from the MFRC522.
sippasaeng 4:4b28e4aa1742 387 if (backData && backLen)
sippasaeng 4:4b28e4aa1742 388 {
sippasaeng 4:4b28e4aa1742 389 n = PCD_ReadRegister(FIFOLevelReg); // Number of bytes in the FIFO
sippasaeng 4:4b28e4aa1742 390 if (n > *backLen)
sippasaeng 4:4b28e4aa1742 391 {
sippasaeng 4:4b28e4aa1742 392 return STATUS_NO_ROOM;
sippasaeng 4:4b28e4aa1742 393 }
sippasaeng 4:4b28e4aa1742 394
sippasaeng 4:4b28e4aa1742 395 *backLen = n; // Number of bytes returned
sippasaeng 4:4b28e4aa1742 396 PCD_ReadRegister(FIFODataReg, n, backData, rxAlign); // Get received data from FIFO
sippasaeng 4:4b28e4aa1742 397 _validBits = PCD_ReadRegister(ControlReg) & 0x07; // RxLastBits[2:0] indicates the number of valid bits in the last received byte. If this value is 000b, the whole byte is valid.
sippasaeng 4:4b28e4aa1742 398 if (validBits)
sippasaeng 4:4b28e4aa1742 399 {
sippasaeng 4:4b28e4aa1742 400 *validBits = _validBits;
sippasaeng 4:4b28e4aa1742 401 }
sippasaeng 4:4b28e4aa1742 402 }
sippasaeng 4:4b28e4aa1742 403
sippasaeng 4:4b28e4aa1742 404 // Tell about collisions
sippasaeng 4:4b28e4aa1742 405 if (errorRegValue & 0x08)
sippasaeng 4:4b28e4aa1742 406 { // CollErr
sippasaeng 4:4b28e4aa1742 407 return STATUS_COLLISION;
sippasaeng 4:4b28e4aa1742 408 }
sippasaeng 4:4b28e4aa1742 409
sippasaeng 4:4b28e4aa1742 410 // Perform CRC_A validation if requested.
sippasaeng 4:4b28e4aa1742 411 if (backData && backLen && checkCRC)
sippasaeng 4:4b28e4aa1742 412 {
sippasaeng 4:4b28e4aa1742 413 // In this case a MIFARE Classic NAK is not OK.
sippasaeng 4:4b28e4aa1742 414 if ((*backLen == 1) && (_validBits == 4))
sippasaeng 4:4b28e4aa1742 415 {
sippasaeng 4:4b28e4aa1742 416 return STATUS_MIFARE_NACK;
sippasaeng 4:4b28e4aa1742 417 }
sippasaeng 4:4b28e4aa1742 418
sippasaeng 4:4b28e4aa1742 419 // We need at least the CRC_A value and all 8 bits of the last byte must be received.
sippasaeng 4:4b28e4aa1742 420 if ((*backLen < 2) || (_validBits != 0))
sippasaeng 4:4b28e4aa1742 421 {
sippasaeng 4:4b28e4aa1742 422 return STATUS_CRC_WRONG;
sippasaeng 4:4b28e4aa1742 423 }
sippasaeng 4:4b28e4aa1742 424
sippasaeng 4:4b28e4aa1742 425 // Verify CRC_A - do our own calculation and store the control in controlBuffer.
sippasaeng 4:4b28e4aa1742 426 uint8_t controlBuffer[2];
sippasaeng 4:4b28e4aa1742 427 n = PCD_CalculateCRC(&backData[0], *backLen - 2, &controlBuffer[0]);
sippasaeng 4:4b28e4aa1742 428 if (n != STATUS_OK)
sippasaeng 4:4b28e4aa1742 429 {
sippasaeng 4:4b28e4aa1742 430 return n;
sippasaeng 4:4b28e4aa1742 431 }
sippasaeng 4:4b28e4aa1742 432
sippasaeng 4:4b28e4aa1742 433 if ((backData[*backLen - 2] != controlBuffer[0]) || (backData[*backLen - 1] != controlBuffer[1]))
sippasaeng 4:4b28e4aa1742 434 {
sippasaeng 4:4b28e4aa1742 435 return STATUS_CRC_WRONG;
sippasaeng 4:4b28e4aa1742 436 }
sippasaeng 4:4b28e4aa1742 437 }
sippasaeng 4:4b28e4aa1742 438
sippasaeng 4:4b28e4aa1742 439 return STATUS_OK;
sippasaeng 4:4b28e4aa1742 440 } // End PCD_CommunicateWithPICC()
sippasaeng 4:4b28e4aa1742 441
sippasaeng 4:4b28e4aa1742 442 /*
sippasaeng 4:4b28e4aa1742 443 * Transmits a REQuest command, Type A. Invites PICCs in state IDLE to go to READY and prepare for anticollision or selection. 7 bit frame.
sippasaeng 4:4b28e4aa1742 444 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
sippasaeng 4:4b28e4aa1742 445 */
sippasaeng 4:4b28e4aa1742 446 uint8_t MFRC522::PICC_RequestA(uint8_t *bufferATQA, uint8_t *bufferSize)
sippasaeng 4:4b28e4aa1742 447 {
sippasaeng 4:4b28e4aa1742 448 return PICC_REQA_or_WUPA(PICC_CMD_REQA, bufferATQA, bufferSize);
sippasaeng 4:4b28e4aa1742 449 } // End PICC_RequestA()
sippasaeng 4:4b28e4aa1742 450
sippasaeng 4:4b28e4aa1742 451 /**
sippasaeng 4:4b28e4aa1742 452 * Transmits a Wake-UP command, Type A. Invites PICCs in state IDLE and HALT to go to READY(*) and prepare for anticollision or selection. 7 bit frame.
sippasaeng 4:4b28e4aa1742 453 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
sippasaeng 4:4b28e4aa1742 454 */
sippasaeng 4:4b28e4aa1742 455 uint8_t MFRC522::PICC_WakeupA(uint8_t *bufferATQA, uint8_t *bufferSize)
sippasaeng 4:4b28e4aa1742 456 {
sippasaeng 4:4b28e4aa1742 457 return PICC_REQA_or_WUPA(PICC_CMD_WUPA, bufferATQA, bufferSize);
sippasaeng 4:4b28e4aa1742 458 } // End PICC_WakeupA()
sippasaeng 4:4b28e4aa1742 459
sippasaeng 4:4b28e4aa1742 460 /*
sippasaeng 4:4b28e4aa1742 461 * Transmits REQA or WUPA commands.
sippasaeng 4:4b28e4aa1742 462 * Beware: When two PICCs are in the field at the same time I often get STATUS_TIMEOUT - probably due do bad antenna design.
sippasaeng 4:4b28e4aa1742 463 */
sippasaeng 4:4b28e4aa1742 464 uint8_t MFRC522::PICC_REQA_or_WUPA(uint8_t command, uint8_t *bufferATQA, uint8_t *bufferSize)
sippasaeng 4:4b28e4aa1742 465 {
sippasaeng 4:4b28e4aa1742 466 uint8_t validBits;
sippasaeng 4:4b28e4aa1742 467 uint8_t status;
sippasaeng 4:4b28e4aa1742 468
sippasaeng 4:4b28e4aa1742 469 if (bufferATQA == NULL || *bufferSize < 2)
sippasaeng 4:4b28e4aa1742 470 { // The ATQA response is 2 bytes long.
sippasaeng 4:4b28e4aa1742 471 return STATUS_NO_ROOM;
sippasaeng 4:4b28e4aa1742 472 }
sippasaeng 4:4b28e4aa1742 473
sippasaeng 4:4b28e4aa1742 474 // ValuesAfterColl=1 => Bits received after collision are cleared.
sippasaeng 4:4b28e4aa1742 475 PCD_ClrRegisterBits(CollReg, 0x80);
sippasaeng 4:4b28e4aa1742 476
sippasaeng 4:4b28e4aa1742 477 // For REQA and WUPA we need the short frame format
sippasaeng 4:4b28e4aa1742 478 // - transmit only 7 bits of the last (and only) byte. TxLastBits = BitFramingReg[2..0]
sippasaeng 4:4b28e4aa1742 479 validBits = 7;
sippasaeng 4:4b28e4aa1742 480
sippasaeng 4:4b28e4aa1742 481 status = PCD_TransceiveData(&command, 1, bufferATQA, bufferSize, &validBits);
sippasaeng 4:4b28e4aa1742 482 if (status != STATUS_OK)
sippasaeng 4:4b28e4aa1742 483 {
sippasaeng 4:4b28e4aa1742 484 return status;
sippasaeng 4:4b28e4aa1742 485 }
sippasaeng 4:4b28e4aa1742 486
sippasaeng 4:4b28e4aa1742 487 if ((*bufferSize != 2) || (validBits != 0))
sippasaeng 4:4b28e4aa1742 488 { // ATQA must be exactly 16 bits.
sippasaeng 4:4b28e4aa1742 489 return STATUS_ERROR;
sippasaeng 4:4b28e4aa1742 490 }
sippasaeng 4:4b28e4aa1742 491
sippasaeng 4:4b28e4aa1742 492 return STATUS_OK;
sippasaeng 4:4b28e4aa1742 493 } // End PICC_REQA_or_WUPA()
sippasaeng 4:4b28e4aa1742 494
sippasaeng 4:4b28e4aa1742 495 /*
sippasaeng 4:4b28e4aa1742 496 * Transmits SELECT/ANTICOLLISION commands to select a single PICC.
sippasaeng 4:4b28e4aa1742 497 */
sippasaeng 4:4b28e4aa1742 498 uint8_t MFRC522::PICC_Select(Uid *uid, uint8_t validBits)
sippasaeng 4:4b28e4aa1742 499 {
sippasaeng 4:4b28e4aa1742 500 bool uidComplete;
sippasaeng 4:4b28e4aa1742 501 bool selectDone;
sippasaeng 4:4b28e4aa1742 502 bool useCascadeTag;
sippasaeng 4:4b28e4aa1742 503 uint8_t cascadeLevel = 1;
sippasaeng 4:4b28e4aa1742 504 uint8_t result;
sippasaeng 4:4b28e4aa1742 505 uint8_t count;
sippasaeng 4:4b28e4aa1742 506 uint8_t index;
sippasaeng 4:4b28e4aa1742 507 uint8_t uidIndex; // The first index in uid->uidByte[] that is used in the current Cascade Level.
sippasaeng 4:4b28e4aa1742 508 uint8_t currentLevelKnownBits; // The number of known UID bits in the current Cascade Level.
sippasaeng 4:4b28e4aa1742 509 uint8_t buffer[9]; // The SELECT/ANTICOLLISION commands uses a 7 byte standard frame + 2 bytes CRC_A
sippasaeng 4:4b28e4aa1742 510 uint8_t bufferUsed; // The number of bytes used in the buffer, ie the number of bytes to transfer to the FIFO.
sippasaeng 4:4b28e4aa1742 511 uint8_t rxAlign; // Used in BitFramingReg. Defines the bit position for the first bit received.
sippasaeng 4:4b28e4aa1742 512 uint8_t txLastBits; // Used in BitFramingReg. The number of valid bits in the last transmitted byte.
sippasaeng 4:4b28e4aa1742 513 uint8_t *responseBuffer;
sippasaeng 4:4b28e4aa1742 514 uint8_t responseLength;
sippasaeng 4:4b28e4aa1742 515
sippasaeng 4:4b28e4aa1742 516 // Description of buffer structure:
sippasaeng 4:4b28e4aa1742 517 // Byte 0: SEL Indicates the Cascade Level: PICC_CMD_SEL_CL1, PICC_CMD_SEL_CL2 or PICC_CMD_SEL_CL3
sippasaeng 4:4b28e4aa1742 518 // Byte 1: NVB Number of Valid Bits (in complete command, not just the UID): High nibble: complete bytes, Low nibble: Extra bits.
sippasaeng 4:4b28e4aa1742 519 // Byte 2: UID-data or CT See explanation below. CT means Cascade Tag.
sippasaeng 4:4b28e4aa1742 520 // Byte 3: UID-data
sippasaeng 4:4b28e4aa1742 521 // Byte 4: UID-data
sippasaeng 4:4b28e4aa1742 522 // Byte 5: UID-data
sippasaeng 4:4b28e4aa1742 523 // Byte 6: BCC Block Check Character - XOR of bytes 2-5
sippasaeng 4:4b28e4aa1742 524 // Byte 7: CRC_A
sippasaeng 4:4b28e4aa1742 525 // Byte 8: CRC_A
sippasaeng 4:4b28e4aa1742 526 // The BCC and CRC_A is only transmitted if we know all the UID bits of the current Cascade Level.
sippasaeng 4:4b28e4aa1742 527 //
sippasaeng 4:4b28e4aa1742 528 // Description of bytes 2-5: (Section 6.5.4 of the ISO/IEC 14443-3 draft: UID contents and cascade levels)
sippasaeng 4:4b28e4aa1742 529 // UID size Cascade level Byte2 Byte3 Byte4 Byte5
sippasaeng 4:4b28e4aa1742 530 // ======== ============= ===== ===== ===== =====
sippasaeng 4:4b28e4aa1742 531 // 4 bytes 1 uid0 uid1 uid2 uid3
sippasaeng 4:4b28e4aa1742 532 // 7 bytes 1 CT uid0 uid1 uid2
sippasaeng 4:4b28e4aa1742 533 // 2 uid3 uid4 uid5 uid6
sippasaeng 4:4b28e4aa1742 534 // 10 bytes 1 CT uid0 uid1 uid2
sippasaeng 4:4b28e4aa1742 535 // 2 CT uid3 uid4 uid5
sippasaeng 4:4b28e4aa1742 536 // 3 uid6 uid7 uid8 uid9
sippasaeng 4:4b28e4aa1742 537
sippasaeng 4:4b28e4aa1742 538 // Sanity checks
sippasaeng 4:4b28e4aa1742 539 if (validBits > 80)
sippasaeng 4:4b28e4aa1742 540 {
sippasaeng 4:4b28e4aa1742 541 return STATUS_INVALID;
sippasaeng 4:4b28e4aa1742 542 }
sippasaeng 4:4b28e4aa1742 543
sippasaeng 4:4b28e4aa1742 544 // Prepare MFRC522
sippasaeng 4:4b28e4aa1742 545 // ValuesAfterColl=1 => Bits received after collision are cleared.
sippasaeng 4:4b28e4aa1742 546 PCD_ClrRegisterBits(CollReg, 0x80);
sippasaeng 4:4b28e4aa1742 547
sippasaeng 4:4b28e4aa1742 548 // Repeat Cascade Level loop until we have a complete UID.
sippasaeng 4:4b28e4aa1742 549 uidComplete = false;
sippasaeng 4:4b28e4aa1742 550 while ( ! uidComplete)
sippasaeng 4:4b28e4aa1742 551 {
sippasaeng 4:4b28e4aa1742 552 // Set the Cascade Level in the SEL byte, find out if we need to use the Cascade Tag in byte 2.
sippasaeng 4:4b28e4aa1742 553 switch (cascadeLevel)
sippasaeng 4:4b28e4aa1742 554 {
sippasaeng 4:4b28e4aa1742 555 case 1:
sippasaeng 4:4b28e4aa1742 556 buffer[0] = PICC_CMD_SEL_CL1;
sippasaeng 4:4b28e4aa1742 557 uidIndex = 0;
sippasaeng 4:4b28e4aa1742 558 useCascadeTag = validBits && (uid->size > 4); // When we know that the UID has more than 4 bytes
sippasaeng 4:4b28e4aa1742 559 break;
sippasaeng 4:4b28e4aa1742 560
sippasaeng 4:4b28e4aa1742 561 case 2:
sippasaeng 4:4b28e4aa1742 562 buffer[0] = PICC_CMD_SEL_CL2;
sippasaeng 4:4b28e4aa1742 563 uidIndex = 3;
sippasaeng 4:4b28e4aa1742 564 useCascadeTag = validBits && (uid->size > 7); // When we know that the UID has more than 7 bytes
sippasaeng 4:4b28e4aa1742 565 break;
sippasaeng 4:4b28e4aa1742 566
sippasaeng 4:4b28e4aa1742 567 case 3:
sippasaeng 4:4b28e4aa1742 568 buffer[0] = PICC_CMD_SEL_CL3;
sippasaeng 4:4b28e4aa1742 569 uidIndex = 6;
sippasaeng 4:4b28e4aa1742 570 useCascadeTag = false; // Never used in CL3.
sippasaeng 4:4b28e4aa1742 571 break;
sippasaeng 4:4b28e4aa1742 572
sippasaeng 4:4b28e4aa1742 573 default:
sippasaeng 4:4b28e4aa1742 574 return STATUS_INTERNAL_ERROR;
sippasaeng 4:4b28e4aa1742 575 //break;
sippasaeng 4:4b28e4aa1742 576 }
sippasaeng 4:4b28e4aa1742 577
sippasaeng 4:4b28e4aa1742 578 // How many UID bits are known in this Cascade Level?
sippasaeng 4:4b28e4aa1742 579 if(validBits > (8 * uidIndex))
sippasaeng 4:4b28e4aa1742 580 {
sippasaeng 4:4b28e4aa1742 581 currentLevelKnownBits = validBits - (8 * uidIndex);
sippasaeng 4:4b28e4aa1742 582 }
sippasaeng 4:4b28e4aa1742 583 else
sippasaeng 4:4b28e4aa1742 584 {
sippasaeng 4:4b28e4aa1742 585 currentLevelKnownBits = 0;
sippasaeng 4:4b28e4aa1742 586 }
sippasaeng 4:4b28e4aa1742 587
sippasaeng 4:4b28e4aa1742 588 // Copy the known bits from uid->uidByte[] to buffer[]
sippasaeng 4:4b28e4aa1742 589 index = 2; // destination index in buffer[]
sippasaeng 4:4b28e4aa1742 590 if (useCascadeTag)
sippasaeng 4:4b28e4aa1742 591 {
sippasaeng 4:4b28e4aa1742 592 buffer[index++] = PICC_CMD_CT;
sippasaeng 4:4b28e4aa1742 593 }
sippasaeng 4:4b28e4aa1742 594
sippasaeng 4:4b28e4aa1742 595 uint8_t bytesToCopy = currentLevelKnownBits / 8 + (currentLevelKnownBits % 8 ? 1 : 0); // The number of bytes needed to represent the known bits for this level.
sippasaeng 4:4b28e4aa1742 596 if (bytesToCopy)
sippasaeng 4:4b28e4aa1742 597 {
sippasaeng 4:4b28e4aa1742 598 // Max 4 bytes in each Cascade Level. Only 3 left if we use the Cascade Tag
sippasaeng 4:4b28e4aa1742 599 uint8_t maxBytes = useCascadeTag ? 3 : 4;
sippasaeng 4:4b28e4aa1742 600 if (bytesToCopy > maxBytes)
sippasaeng 4:4b28e4aa1742 601 {
sippasaeng 4:4b28e4aa1742 602 bytesToCopy = maxBytes;
sippasaeng 4:4b28e4aa1742 603 }
sippasaeng 4:4b28e4aa1742 604
sippasaeng 4:4b28e4aa1742 605 for (count = 0; count < bytesToCopy; count++)
sippasaeng 4:4b28e4aa1742 606 {
sippasaeng 4:4b28e4aa1742 607 buffer[index++] = uid->uidByte[uidIndex + count];
sippasaeng 4:4b28e4aa1742 608 }
sippasaeng 4:4b28e4aa1742 609 }
sippasaeng 4:4b28e4aa1742 610
sippasaeng 4:4b28e4aa1742 611 // Now that the data has been copied we need to include the 8 bits in CT in currentLevelKnownBits
sippasaeng 4:4b28e4aa1742 612 if (useCascadeTag)
sippasaeng 4:4b28e4aa1742 613 {
sippasaeng 4:4b28e4aa1742 614 currentLevelKnownBits += 8;
sippasaeng 4:4b28e4aa1742 615 }
sippasaeng 4:4b28e4aa1742 616
sippasaeng 4:4b28e4aa1742 617 // Repeat anti collision loop until we can transmit all UID bits + BCC and receive a SAK - max 32 iterations.
sippasaeng 4:4b28e4aa1742 618 selectDone = false;
sippasaeng 4:4b28e4aa1742 619 while ( ! selectDone)
sippasaeng 4:4b28e4aa1742 620 {
sippasaeng 4:4b28e4aa1742 621 // Find out how many bits and bytes to send and receive.
sippasaeng 4:4b28e4aa1742 622 if (currentLevelKnownBits >= 32)
sippasaeng 4:4b28e4aa1742 623 { // All UID bits in this Cascade Level are known. This is a SELECT.
sippasaeng 4:4b28e4aa1742 624 //Serial.print("SELECT: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
sippasaeng 4:4b28e4aa1742 625 buffer[1] = 0x70; // NVB - Number of Valid Bits: Seven whole bytes
sippasaeng 4:4b28e4aa1742 626
sippasaeng 4:4b28e4aa1742 627 // Calulate BCC - Block Check Character
sippasaeng 4:4b28e4aa1742 628 buffer[6] = buffer[2] ^ buffer[3] ^ buffer[4] ^ buffer[5];
sippasaeng 4:4b28e4aa1742 629
sippasaeng 4:4b28e4aa1742 630 // Calculate CRC_A
sippasaeng 4:4b28e4aa1742 631 result = PCD_CalculateCRC(buffer, 7, &buffer[7]);
sippasaeng 4:4b28e4aa1742 632 if (result != STATUS_OK)
sippasaeng 4:4b28e4aa1742 633 {
sippasaeng 4:4b28e4aa1742 634 return result;
sippasaeng 4:4b28e4aa1742 635 }
sippasaeng 4:4b28e4aa1742 636
sippasaeng 4:4b28e4aa1742 637 txLastBits = 0; // 0 => All 8 bits are valid.
sippasaeng 4:4b28e4aa1742 638 bufferUsed = 9;
sippasaeng 4:4b28e4aa1742 639
sippasaeng 4:4b28e4aa1742 640 // Store response in the last 3 bytes of buffer (BCC and CRC_A - not needed after tx)
sippasaeng 4:4b28e4aa1742 641 responseBuffer = &buffer[6];
sippasaeng 4:4b28e4aa1742 642 responseLength = 3;
sippasaeng 4:4b28e4aa1742 643 }
sippasaeng 4:4b28e4aa1742 644 else
sippasaeng 4:4b28e4aa1742 645 { // This is an ANTICOLLISION.
sippasaeng 4:4b28e4aa1742 646 //Serial.print("ANTICOLLISION: currentLevelKnownBits="); Serial.println(currentLevelKnownBits, DEC);
sippasaeng 4:4b28e4aa1742 647 txLastBits = currentLevelKnownBits % 8;
sippasaeng 4:4b28e4aa1742 648 count = currentLevelKnownBits / 8; // Number of whole bytes in the UID part.
sippasaeng 4:4b28e4aa1742 649 index = 2 + count; // Number of whole bytes: SEL + NVB + UIDs
sippasaeng 4:4b28e4aa1742 650 buffer[1] = (index << 4) + txLastBits; // NVB - Number of Valid Bits
sippasaeng 4:4b28e4aa1742 651 bufferUsed = index + (txLastBits ? 1 : 0);
sippasaeng 4:4b28e4aa1742 652
sippasaeng 4:4b28e4aa1742 653 // Store response in the unused part of buffer
sippasaeng 4:4b28e4aa1742 654 responseBuffer = &buffer[index];
sippasaeng 4:4b28e4aa1742 655 responseLength = sizeof(buffer) - index;
sippasaeng 4:4b28e4aa1742 656 }
sippasaeng 4:4b28e4aa1742 657
sippasaeng 4:4b28e4aa1742 658 // Set bit adjustments
sippasaeng 4:4b28e4aa1742 659 rxAlign = txLastBits; // Having a seperate variable is overkill. But it makes the next line easier to read.
sippasaeng 4:4b28e4aa1742 660 PCD_WriteRegister(BitFramingReg, (rxAlign << 4) + txLastBits); // RxAlign = BitFramingReg[6..4]. TxLastBits = BitFramingReg[2..0]
sippasaeng 4:4b28e4aa1742 661
sippasaeng 4:4b28e4aa1742 662 // Transmit the buffer and receive the response.
sippasaeng 4:4b28e4aa1742 663 result = PCD_TransceiveData(buffer, bufferUsed, responseBuffer, &responseLength, &txLastBits, rxAlign);
sippasaeng 4:4b28e4aa1742 664 if (result == STATUS_COLLISION)
sippasaeng 4:4b28e4aa1742 665 { // More than one PICC in the field => collision.
sippasaeng 4:4b28e4aa1742 666 result = PCD_ReadRegister(CollReg); // CollReg[7..0] bits are: ValuesAfterColl reserved CollPosNotValid CollPos[4:0]
sippasaeng 4:4b28e4aa1742 667 if (result & 0x20)
sippasaeng 4:4b28e4aa1742 668 { // CollPosNotValid
sippasaeng 4:4b28e4aa1742 669 return STATUS_COLLISION; // Without a valid collision position we cannot continue
sippasaeng 4:4b28e4aa1742 670 }
sippasaeng 4:4b28e4aa1742 671
sippasaeng 4:4b28e4aa1742 672 uint8_t collisionPos = result & 0x1F; // Values 0-31, 0 means bit 32.
sippasaeng 4:4b28e4aa1742 673 if (collisionPos == 0)
sippasaeng 4:4b28e4aa1742 674 {
sippasaeng 4:4b28e4aa1742 675 collisionPos = 32;
sippasaeng 4:4b28e4aa1742 676 }
sippasaeng 4:4b28e4aa1742 677
sippasaeng 4:4b28e4aa1742 678 if (collisionPos <= currentLevelKnownBits)
sippasaeng 4:4b28e4aa1742 679 { // No progress - should not happen
sippasaeng 4:4b28e4aa1742 680 return STATUS_INTERNAL_ERROR;
sippasaeng 4:4b28e4aa1742 681 }
sippasaeng 4:4b28e4aa1742 682
sippasaeng 4:4b28e4aa1742 683 // Choose the PICC with the bit set.
sippasaeng 4:4b28e4aa1742 684 currentLevelKnownBits = collisionPos;
sippasaeng 4:4b28e4aa1742 685 count = (currentLevelKnownBits - 1) % 8; // The bit to modify
sippasaeng 4:4b28e4aa1742 686 index = 1 + (currentLevelKnownBits / 8) + (count ? 1 : 0); // First byte is index 0.
sippasaeng 4:4b28e4aa1742 687 buffer[index] |= (1 << count);
sippasaeng 4:4b28e4aa1742 688 }
sippasaeng 4:4b28e4aa1742 689 else if (result != STATUS_OK)
sippasaeng 4:4b28e4aa1742 690 {
sippasaeng 4:4b28e4aa1742 691 return result;
sippasaeng 4:4b28e4aa1742 692 }
sippasaeng 4:4b28e4aa1742 693 else
sippasaeng 4:4b28e4aa1742 694 { // STATUS_OK
sippasaeng 4:4b28e4aa1742 695 if (currentLevelKnownBits >= 32)
sippasaeng 4:4b28e4aa1742 696 { // This was a SELECT.
sippasaeng 4:4b28e4aa1742 697 selectDone = true; // No more anticollision
sippasaeng 4:4b28e4aa1742 698 // We continue below outside the while.
sippasaeng 4:4b28e4aa1742 699 }
sippasaeng 4:4b28e4aa1742 700 else
sippasaeng 4:4b28e4aa1742 701 { // This was an ANTICOLLISION.
sippasaeng 4:4b28e4aa1742 702 // We now have all 32 bits of the UID in this Cascade Level
sippasaeng 4:4b28e4aa1742 703 currentLevelKnownBits = 32;
sippasaeng 4:4b28e4aa1742 704 // Run loop again to do the SELECT.
sippasaeng 4:4b28e4aa1742 705 }
sippasaeng 4:4b28e4aa1742 706 }
sippasaeng 4:4b28e4aa1742 707 } // End of while ( ! selectDone)
sippasaeng 4:4b28e4aa1742 708
sippasaeng 4:4b28e4aa1742 709 // We do not check the CBB - it was constructed by us above.
sippasaeng 4:4b28e4aa1742 710
sippasaeng 4:4b28e4aa1742 711 // Copy the found UID bytes from buffer[] to uid->uidByte[]
sippasaeng 4:4b28e4aa1742 712 index = (buffer[2] == PICC_CMD_CT) ? 3 : 2; // source index in buffer[]
sippasaeng 4:4b28e4aa1742 713 bytesToCopy = (buffer[2] == PICC_CMD_CT) ? 3 : 4;
sippasaeng 4:4b28e4aa1742 714 for (count = 0; count < bytesToCopy; count++)
sippasaeng 4:4b28e4aa1742 715 {
sippasaeng 4:4b28e4aa1742 716 uid->uidByte[uidIndex + count] = buffer[index++];
sippasaeng 4:4b28e4aa1742 717 }
sippasaeng 4:4b28e4aa1742 718
sippasaeng 4:4b28e4aa1742 719 // Check response SAK (Select Acknowledge)
sippasaeng 4:4b28e4aa1742 720 if (responseLength != 3 || txLastBits != 0)
sippasaeng 4:4b28e4aa1742 721 { // SAK must be exactly 24 bits (1 byte + CRC_A).
sippasaeng 4:4b28e4aa1742 722 return STATUS_ERROR;
sippasaeng 4:4b28e4aa1742 723 }
sippasaeng 4:4b28e4aa1742 724
sippasaeng 4:4b28e4aa1742 725 // Verify CRC_A - do our own calculation and store the control in buffer[2..3] - those bytes are not needed anymore.
sippasaeng 4:4b28e4aa1742 726 result = PCD_CalculateCRC(responseBuffer, 1, &buffer[2]);
sippasaeng 4:4b28e4aa1742 727 if (result != STATUS_OK)
sippasaeng 4:4b28e4aa1742 728 {
sippasaeng 4:4b28e4aa1742 729 return result;
sippasaeng 4:4b28e4aa1742 730 }
sippasaeng 4:4b28e4aa1742 731
sippasaeng 4:4b28e4aa1742 732 if ((buffer[2] != responseBuffer[1]) || (buffer[3] != responseBuffer[2]))
sippasaeng 4:4b28e4aa1742 733 {
sippasaeng 4:4b28e4aa1742 734 return STATUS_CRC_WRONG;
sippasaeng 4:4b28e4aa1742 735 }
sippasaeng 4:4b28e4aa1742 736
sippasaeng 4:4b28e4aa1742 737 if (responseBuffer[0] & 0x04)
sippasaeng 4:4b28e4aa1742 738 { // Cascade bit set - UID not complete yes
sippasaeng 4:4b28e4aa1742 739 cascadeLevel++;
sippasaeng 4:4b28e4aa1742 740 }
sippasaeng 4:4b28e4aa1742 741 else
sippasaeng 4:4b28e4aa1742 742 {
sippasaeng 4:4b28e4aa1742 743 uidComplete = true;
sippasaeng 4:4b28e4aa1742 744 uid->sak = responseBuffer[0];
sippasaeng 4:4b28e4aa1742 745 }
sippasaeng 4:4b28e4aa1742 746 } // End of while ( ! uidComplete)
sippasaeng 4:4b28e4aa1742 747
sippasaeng 4:4b28e4aa1742 748 // Set correct uid->size
sippasaeng 4:4b28e4aa1742 749 uid->size = 3 * cascadeLevel + 1;
sippasaeng 4:4b28e4aa1742 750
sippasaeng 4:4b28e4aa1742 751 return STATUS_OK;
sippasaeng 4:4b28e4aa1742 752 } // End PICC_Select()
sippasaeng 4:4b28e4aa1742 753
sippasaeng 4:4b28e4aa1742 754 /*
sippasaeng 4:4b28e4aa1742 755 * Instructs a PICC in state ACTIVE(*) to go to state HALT.
sippasaeng 4:4b28e4aa1742 756 */
sippasaeng 4:4b28e4aa1742 757 uint8_t MFRC522::PICC_HaltA()
sippasaeng 4:4b28e4aa1742 758 {
sippasaeng 4:4b28e4aa1742 759 uint8_t result;
sippasaeng 4:4b28e4aa1742 760 uint8_t buffer[4];
sippasaeng 4:4b28e4aa1742 761
sippasaeng 4:4b28e4aa1742 762 // Build command buffer
sippasaeng 4:4b28e4aa1742 763 buffer[0] = PICC_CMD_HLTA;
sippasaeng 4:4b28e4aa1742 764 buffer[1] = 0;
sippasaeng 4:4b28e4aa1742 765
sippasaeng 4:4b28e4aa1742 766 // Calculate CRC_A
sippasaeng 4:4b28e4aa1742 767 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
sippasaeng 4:4b28e4aa1742 768 if (result == STATUS_OK)
sippasaeng 4:4b28e4aa1742 769 {
sippasaeng 4:4b28e4aa1742 770 // Send the command.
sippasaeng 4:4b28e4aa1742 771 // The standard says:
sippasaeng 4:4b28e4aa1742 772 // If the PICC responds with any modulation during a period of 1 ms after the end of the frame containing the
sippasaeng 4:4b28e4aa1742 773 // HLTA command, this response shall be interpreted as 'not acknowledge'.
sippasaeng 4:4b28e4aa1742 774 // We interpret that this way: Only STATUS_TIMEOUT is an success.
sippasaeng 4:4b28e4aa1742 775 result = PCD_TransceiveData(buffer, sizeof(buffer), NULL, 0);
sippasaeng 4:4b28e4aa1742 776 if (result == STATUS_TIMEOUT)
sippasaeng 4:4b28e4aa1742 777 {
sippasaeng 4:4b28e4aa1742 778 result = STATUS_OK;
sippasaeng 4:4b28e4aa1742 779 }
sippasaeng 4:4b28e4aa1742 780 else if (result == STATUS_OK)
sippasaeng 4:4b28e4aa1742 781 { // That is ironically NOT ok in this case ;-)
sippasaeng 4:4b28e4aa1742 782 result = STATUS_ERROR;
sippasaeng 4:4b28e4aa1742 783 }
sippasaeng 4:4b28e4aa1742 784 }
sippasaeng 4:4b28e4aa1742 785
sippasaeng 4:4b28e4aa1742 786 return result;
sippasaeng 4:4b28e4aa1742 787 } // End PICC_HaltA()
sippasaeng 4:4b28e4aa1742 788
sippasaeng 4:4b28e4aa1742 789
sippasaeng 4:4b28e4aa1742 790 /////////////////////////////////////////////////////////////////////////////////////
sippasaeng 4:4b28e4aa1742 791 // Functions for communicating with MIFARE PICCs
sippasaeng 4:4b28e4aa1742 792 /////////////////////////////////////////////////////////////////////////////////////
sippasaeng 4:4b28e4aa1742 793
sippasaeng 4:4b28e4aa1742 794 /*
sippasaeng 4:4b28e4aa1742 795 * Executes the MFRC522 MFAuthent command.
sippasaeng 4:4b28e4aa1742 796 */
sippasaeng 4:4b28e4aa1742 797 uint8_t MFRC522::PCD_Authenticate(uint8_t command, uint8_t blockAddr, MIFARE_Key *key, Uid *uid)
sippasaeng 4:4b28e4aa1742 798 {
sippasaeng 4:4b28e4aa1742 799 uint8_t i, waitIRq = 0x10; // IdleIRq
sippasaeng 4:4b28e4aa1742 800
sippasaeng 4:4b28e4aa1742 801 // Build command buffer
sippasaeng 4:4b28e4aa1742 802 uint8_t sendData[12];
sippasaeng 4:4b28e4aa1742 803 sendData[0] = command;
sippasaeng 4:4b28e4aa1742 804 sendData[1] = blockAddr;
sippasaeng 4:4b28e4aa1742 805
sippasaeng 4:4b28e4aa1742 806 for (i = 0; i < MF_KEY_SIZE; i++)
sippasaeng 4:4b28e4aa1742 807 { // 6 key bytes
sippasaeng 4:4b28e4aa1742 808 sendData[2+i] = key->keyByte[i];
sippasaeng 4:4b28e4aa1742 809 }
sippasaeng 4:4b28e4aa1742 810
sippasaeng 4:4b28e4aa1742 811 for (i = 0; i < 4; i++)
sippasaeng 4:4b28e4aa1742 812 { // The first 4 bytes of the UID
sippasaeng 4:4b28e4aa1742 813 sendData[8+i] = uid->uidByte[i];
sippasaeng 4:4b28e4aa1742 814 }
sippasaeng 4:4b28e4aa1742 815
sippasaeng 4:4b28e4aa1742 816 // Start the authentication.
sippasaeng 4:4b28e4aa1742 817 return PCD_CommunicateWithPICC(PCD_MFAuthent, waitIRq, &sendData[0], sizeof(sendData));
sippasaeng 4:4b28e4aa1742 818 } // End PCD_Authenticate()
sippasaeng 4:4b28e4aa1742 819
sippasaeng 4:4b28e4aa1742 820 /*
sippasaeng 4:4b28e4aa1742 821 * Used to exit the PCD from its authenticated state.
sippasaeng 4:4b28e4aa1742 822 * Remember to call this function after communicating with an authenticated PICC - otherwise no new communications can start.
sippasaeng 4:4b28e4aa1742 823 */
sippasaeng 4:4b28e4aa1742 824 void MFRC522::PCD_StopCrypto1()
sippasaeng 4:4b28e4aa1742 825 {
sippasaeng 4:4b28e4aa1742 826 // Clear MFCrypto1On bit
sippasaeng 4:4b28e4aa1742 827 PCD_ClrRegisterBits(Status2Reg, 0x08); // Status2Reg[7..0] bits are: TempSensClear I2CForceHS reserved reserved MFCrypto1On ModemState[2:0]
sippasaeng 4:4b28e4aa1742 828 } // End PCD_StopCrypto1()
sippasaeng 4:4b28e4aa1742 829
sippasaeng 4:4b28e4aa1742 830 /*
sippasaeng 4:4b28e4aa1742 831 * Reads 16 bytes (+ 2 bytes CRC_A) from the active PICC.
sippasaeng 4:4b28e4aa1742 832 */
sippasaeng 4:4b28e4aa1742 833 uint8_t MFRC522::MIFARE_Read(uint8_t blockAddr, uint8_t *buffer, uint8_t *bufferSize)
sippasaeng 4:4b28e4aa1742 834 {
sippasaeng 4:4b28e4aa1742 835 uint8_t result = STATUS_NO_ROOM;
sippasaeng 4:4b28e4aa1742 836
sippasaeng 4:4b28e4aa1742 837 // Sanity check
sippasaeng 4:4b28e4aa1742 838 if ((buffer == NULL) || (*bufferSize < 18))
sippasaeng 4:4b28e4aa1742 839 {
sippasaeng 4:4b28e4aa1742 840 return result;
sippasaeng 4:4b28e4aa1742 841 }
sippasaeng 4:4b28e4aa1742 842
sippasaeng 4:4b28e4aa1742 843 // Build command buffer
sippasaeng 4:4b28e4aa1742 844 buffer[0] = PICC_CMD_MF_READ;
sippasaeng 4:4b28e4aa1742 845 buffer[1] = blockAddr;
sippasaeng 4:4b28e4aa1742 846
sippasaeng 4:4b28e4aa1742 847 // Calculate CRC_A
sippasaeng 4:4b28e4aa1742 848 result = PCD_CalculateCRC(buffer, 2, &buffer[2]);
sippasaeng 4:4b28e4aa1742 849 if (result != STATUS_OK)
sippasaeng 4:4b28e4aa1742 850 {
sippasaeng 4:4b28e4aa1742 851 return result;
sippasaeng 4:4b28e4aa1742 852 }
sippasaeng 4:4b28e4aa1742 853
sippasaeng 4:4b28e4aa1742 854 // Transmit the buffer and receive the response, validate CRC_A.
sippasaeng 4:4b28e4aa1742 855 return PCD_TransceiveData(buffer, 4, buffer, bufferSize, NULL, 0, true);
sippasaeng 4:4b28e4aa1742 856 } // End MIFARE_Read()
sippasaeng 4:4b28e4aa1742 857
sippasaeng 4:4b28e4aa1742 858 /*
sippasaeng 4:4b28e4aa1742 859 * Writes 16 bytes to the active PICC.
sippasaeng 4:4b28e4aa1742 860 */
sippasaeng 4:4b28e4aa1742 861 uint8_t MFRC522::MIFARE_Write(uint8_t blockAddr, uint8_t *buffer, uint8_t bufferSize)
sippasaeng 4:4b28e4aa1742 862 {
sippasaeng 4:4b28e4aa1742 863 uint8_t result;
sippasaeng 4:4b28e4aa1742 864
sippasaeng 4:4b28e4aa1742 865 // Sanity check
sippasaeng 4:4b28e4aa1742 866 if (buffer == NULL || bufferSize < 16)
sippasaeng 4:4b28e4aa1742 867 {
sippasaeng 4:4b28e4aa1742 868 return STATUS_INVALID;
sippasaeng 4:4b28e4aa1742 869 }
sippasaeng 4:4b28e4aa1742 870
sippasaeng 4:4b28e4aa1742 871 // Mifare Classic protocol requires two communications to perform a write.
sippasaeng 4:4b28e4aa1742 872 // Step 1: Tell the PICC we want to write to block blockAddr.
sippasaeng 4:4b28e4aa1742 873 uint8_t cmdBuffer[2];
sippasaeng 4:4b28e4aa1742 874 cmdBuffer[0] = PICC_CMD_MF_WRITE;
sippasaeng 4:4b28e4aa1742 875 cmdBuffer[1] = blockAddr;
sippasaeng 4:4b28e4aa1742 876 // Adds CRC_A and checks that the response is MF_ACK.
sippasaeng 4:4b28e4aa1742 877 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
sippasaeng 4:4b28e4aa1742 878 if (result != STATUS_OK)
sippasaeng 4:4b28e4aa1742 879 {
sippasaeng 4:4b28e4aa1742 880 return result;
sippasaeng 4:4b28e4aa1742 881 }
sippasaeng 4:4b28e4aa1742 882
sippasaeng 4:4b28e4aa1742 883 // Step 2: Transfer the data
sippasaeng 4:4b28e4aa1742 884 // Adds CRC_A and checks that the response is MF_ACK.
sippasaeng 4:4b28e4aa1742 885 result = PCD_MIFARE_Transceive(buffer, bufferSize);
sippasaeng 4:4b28e4aa1742 886 if (result != STATUS_OK)
sippasaeng 4:4b28e4aa1742 887 {
sippasaeng 4:4b28e4aa1742 888 return result;
sippasaeng 4:4b28e4aa1742 889 }
sippasaeng 4:4b28e4aa1742 890
sippasaeng 4:4b28e4aa1742 891 return STATUS_OK;
sippasaeng 4:4b28e4aa1742 892 } // End MIFARE_Write()
sippasaeng 4:4b28e4aa1742 893
sippasaeng 4:4b28e4aa1742 894 /*
sippasaeng 4:4b28e4aa1742 895 * Writes a 4 byte page to the active MIFARE Ultralight PICC.
sippasaeng 4:4b28e4aa1742 896 */
sippasaeng 4:4b28e4aa1742 897 uint8_t MFRC522::MIFARE_UltralightWrite(uint8_t page, uint8_t *buffer, uint8_t bufferSize)
sippasaeng 4:4b28e4aa1742 898 {
sippasaeng 4:4b28e4aa1742 899 uint8_t result;
sippasaeng 4:4b28e4aa1742 900
sippasaeng 4:4b28e4aa1742 901 // Sanity check
sippasaeng 4:4b28e4aa1742 902 if (buffer == NULL || bufferSize < 4)
sippasaeng 4:4b28e4aa1742 903 {
sippasaeng 4:4b28e4aa1742 904 return STATUS_INVALID;
sippasaeng 4:4b28e4aa1742 905 }
sippasaeng 4:4b28e4aa1742 906
sippasaeng 4:4b28e4aa1742 907 // Build commmand buffer
sippasaeng 4:4b28e4aa1742 908 uint8_t cmdBuffer[6];
sippasaeng 4:4b28e4aa1742 909 cmdBuffer[0] = PICC_CMD_UL_WRITE;
sippasaeng 4:4b28e4aa1742 910 cmdBuffer[1] = page;
sippasaeng 4:4b28e4aa1742 911 memcpy(&cmdBuffer[2], buffer, 4);
sippasaeng 4:4b28e4aa1742 912
sippasaeng 4:4b28e4aa1742 913 // Perform the write
sippasaeng 4:4b28e4aa1742 914 result = PCD_MIFARE_Transceive(cmdBuffer, 6); // Adds CRC_A and checks that the response is MF_ACK.
sippasaeng 4:4b28e4aa1742 915 if (result != STATUS_OK)
sippasaeng 4:4b28e4aa1742 916 {
sippasaeng 4:4b28e4aa1742 917 return result;
sippasaeng 4:4b28e4aa1742 918 }
sippasaeng 4:4b28e4aa1742 919
sippasaeng 4:4b28e4aa1742 920 return STATUS_OK;
sippasaeng 4:4b28e4aa1742 921 } // End MIFARE_Ultralight_Write()
sippasaeng 4:4b28e4aa1742 922
sippasaeng 4:4b28e4aa1742 923 /*
sippasaeng 4:4b28e4aa1742 924 * MIFARE Decrement subtracts the delta from the value of the addressed block, and stores the result in a volatile memory.
sippasaeng 4:4b28e4aa1742 925 */
sippasaeng 4:4b28e4aa1742 926 uint8_t MFRC522::MIFARE_Decrement(uint8_t blockAddr, uint32_t delta)
sippasaeng 4:4b28e4aa1742 927 {
sippasaeng 4:4b28e4aa1742 928 return MIFARE_TwoStepHelper(PICC_CMD_MF_DECREMENT, blockAddr, delta);
sippasaeng 4:4b28e4aa1742 929 } // End MIFARE_Decrement()
sippasaeng 4:4b28e4aa1742 930
sippasaeng 4:4b28e4aa1742 931 /*
sippasaeng 4:4b28e4aa1742 932 * MIFARE Increment adds the delta to the value of the addressed block, and stores the result in a volatile memory.
sippasaeng 4:4b28e4aa1742 933 */
sippasaeng 4:4b28e4aa1742 934 uint8_t MFRC522::MIFARE_Increment(uint8_t blockAddr, uint32_t delta)
sippasaeng 4:4b28e4aa1742 935 {
sippasaeng 4:4b28e4aa1742 936 return MIFARE_TwoStepHelper(PICC_CMD_MF_INCREMENT, blockAddr, delta);
sippasaeng 4:4b28e4aa1742 937 } // End MIFARE_Increment()
sippasaeng 4:4b28e4aa1742 938
sippasaeng 4:4b28e4aa1742 939 /**
sippasaeng 4:4b28e4aa1742 940 * MIFARE Restore copies the value of the addressed block into a volatile memory.
sippasaeng 4:4b28e4aa1742 941 */
sippasaeng 4:4b28e4aa1742 942 uint8_t MFRC522::MIFARE_Restore(uint8_t blockAddr)
sippasaeng 4:4b28e4aa1742 943 {
sippasaeng 4:4b28e4aa1742 944 // The datasheet describes Restore as a two step operation, but does not explain what data to transfer in step 2.
sippasaeng 4:4b28e4aa1742 945 // Doing only a single step does not work, so I chose to transfer 0L in step two.
sippasaeng 4:4b28e4aa1742 946 return MIFARE_TwoStepHelper(PICC_CMD_MF_RESTORE, blockAddr, 0L);
sippasaeng 4:4b28e4aa1742 947 } // End MIFARE_Restore()
sippasaeng 4:4b28e4aa1742 948
sippasaeng 4:4b28e4aa1742 949 /*
sippasaeng 4:4b28e4aa1742 950 * Helper function for the two-step MIFARE Classic protocol operations Decrement, Increment and Restore.
sippasaeng 4:4b28e4aa1742 951 */
sippasaeng 4:4b28e4aa1742 952 uint8_t MFRC522::MIFARE_TwoStepHelper(uint8_t command, uint8_t blockAddr, uint32_t data)
sippasaeng 4:4b28e4aa1742 953 {
sippasaeng 4:4b28e4aa1742 954 uint8_t result;
sippasaeng 4:4b28e4aa1742 955 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
sippasaeng 4:4b28e4aa1742 956
sippasaeng 4:4b28e4aa1742 957 // Step 1: Tell the PICC the command and block address
sippasaeng 4:4b28e4aa1742 958 cmdBuffer[0] = command;
sippasaeng 4:4b28e4aa1742 959 cmdBuffer[1] = blockAddr;
sippasaeng 4:4b28e4aa1742 960
sippasaeng 4:4b28e4aa1742 961 // Adds CRC_A and checks that the response is MF_ACK.
sippasaeng 4:4b28e4aa1742 962 result = PCD_MIFARE_Transceive(cmdBuffer, 2);
sippasaeng 4:4b28e4aa1742 963 if (result != STATUS_OK)
sippasaeng 4:4b28e4aa1742 964 {
sippasaeng 4:4b28e4aa1742 965 return result;
sippasaeng 4:4b28e4aa1742 966 }
sippasaeng 4:4b28e4aa1742 967
sippasaeng 4:4b28e4aa1742 968 // Step 2: Transfer the data
sippasaeng 4:4b28e4aa1742 969 // Adds CRC_A and accept timeout as success.
sippasaeng 4:4b28e4aa1742 970 result = PCD_MIFARE_Transceive((uint8_t *) &data, 4, true);
sippasaeng 4:4b28e4aa1742 971 if (result != STATUS_OK)
sippasaeng 4:4b28e4aa1742 972 {
sippasaeng 4:4b28e4aa1742 973 return result;
sippasaeng 4:4b28e4aa1742 974 }
sippasaeng 4:4b28e4aa1742 975
sippasaeng 4:4b28e4aa1742 976 return STATUS_OK;
sippasaeng 4:4b28e4aa1742 977 } // End MIFARE_TwoStepHelper()
sippasaeng 4:4b28e4aa1742 978
sippasaeng 4:4b28e4aa1742 979 /*
sippasaeng 4:4b28e4aa1742 980 * MIFARE Transfer writes the value stored in the volatile memory into one MIFARE Classic block.
sippasaeng 4:4b28e4aa1742 981 */
sippasaeng 4:4b28e4aa1742 982 uint8_t MFRC522::MIFARE_Transfer(uint8_t blockAddr)
sippasaeng 4:4b28e4aa1742 983 {
sippasaeng 4:4b28e4aa1742 984 uint8_t cmdBuffer[2]; // We only need room for 2 bytes.
sippasaeng 4:4b28e4aa1742 985
sippasaeng 4:4b28e4aa1742 986 // Tell the PICC we want to transfer the result into block blockAddr.
sippasaeng 4:4b28e4aa1742 987 cmdBuffer[0] = PICC_CMD_MF_TRANSFER;
sippasaeng 4:4b28e4aa1742 988 cmdBuffer[1] = blockAddr;
sippasaeng 4:4b28e4aa1742 989
sippasaeng 4:4b28e4aa1742 990 // Adds CRC_A and checks that the response is MF_ACK.
sippasaeng 4:4b28e4aa1742 991 return PCD_MIFARE_Transceive(cmdBuffer, 2);
sippasaeng 4:4b28e4aa1742 992 } // End MIFARE_Transfer()
sippasaeng 4:4b28e4aa1742 993
sippasaeng 4:4b28e4aa1742 994
sippasaeng 4:4b28e4aa1742 995 /////////////////////////////////////////////////////////////////////////////////////
sippasaeng 4:4b28e4aa1742 996 // Support functions
sippasaeng 4:4b28e4aa1742 997 /////////////////////////////////////////////////////////////////////////////////////
sippasaeng 4:4b28e4aa1742 998
sippasaeng 4:4b28e4aa1742 999 /*
sippasaeng 4:4b28e4aa1742 1000 * Wrapper for MIFARE protocol communication.
sippasaeng 4:4b28e4aa1742 1001 * Adds CRC_A, executes the Transceive command and checks that the response is MF_ACK or a timeout.
sippasaeng 4:4b28e4aa1742 1002 */
sippasaeng 4:4b28e4aa1742 1003 uint8_t MFRC522::PCD_MIFARE_Transceive(uint8_t *sendData, uint8_t sendLen, bool acceptTimeout)
sippasaeng 4:4b28e4aa1742 1004 {
sippasaeng 4:4b28e4aa1742 1005 uint8_t result;
sippasaeng 4:4b28e4aa1742 1006 uint8_t cmdBuffer[18]; // We need room for 16 bytes data and 2 bytes CRC_A.
sippasaeng 4:4b28e4aa1742 1007
sippasaeng 4:4b28e4aa1742 1008 // Sanity check
sippasaeng 4:4b28e4aa1742 1009 if (sendData == NULL || sendLen > 16)
sippasaeng 4:4b28e4aa1742 1010 {
sippasaeng 4:4b28e4aa1742 1011 return STATUS_INVALID;
sippasaeng 4:4b28e4aa1742 1012 }
sippasaeng 4:4b28e4aa1742 1013
sippasaeng 4:4b28e4aa1742 1014 // Copy sendData[] to cmdBuffer[] and add CRC_A
sippasaeng 4:4b28e4aa1742 1015 memcpy(cmdBuffer, sendData, sendLen);
sippasaeng 4:4b28e4aa1742 1016 result = PCD_CalculateCRC(cmdBuffer, sendLen, &cmdBuffer[sendLen]);
sippasaeng 4:4b28e4aa1742 1017 if (result != STATUS_OK)
sippasaeng 4:4b28e4aa1742 1018 {
sippasaeng 4:4b28e4aa1742 1019 return result;
sippasaeng 4:4b28e4aa1742 1020 }
sippasaeng 4:4b28e4aa1742 1021
sippasaeng 4:4b28e4aa1742 1022 sendLen += 2;
sippasaeng 4:4b28e4aa1742 1023
sippasaeng 4:4b28e4aa1742 1024 // Transceive the data, store the reply in cmdBuffer[]
sippasaeng 4:4b28e4aa1742 1025 uint8_t waitIRq = 0x30; // RxIRq and IdleIRq
sippasaeng 4:4b28e4aa1742 1026 uint8_t cmdBufferSize = sizeof(cmdBuffer);
sippasaeng 4:4b28e4aa1742 1027 uint8_t validBits = 0;
sippasaeng 4:4b28e4aa1742 1028 result = PCD_CommunicateWithPICC(PCD_Transceive, waitIRq, cmdBuffer, sendLen, cmdBuffer, &cmdBufferSize, &validBits);
sippasaeng 4:4b28e4aa1742 1029 if (acceptTimeout && result == STATUS_TIMEOUT)
sippasaeng 4:4b28e4aa1742 1030 {
sippasaeng 4:4b28e4aa1742 1031 return STATUS_OK;
sippasaeng 4:4b28e4aa1742 1032 }
sippasaeng 4:4b28e4aa1742 1033
sippasaeng 4:4b28e4aa1742 1034 if (result != STATUS_OK)
sippasaeng 4:4b28e4aa1742 1035 {
sippasaeng 4:4b28e4aa1742 1036 return result;
sippasaeng 4:4b28e4aa1742 1037 }
sippasaeng 4:4b28e4aa1742 1038
sippasaeng 4:4b28e4aa1742 1039 // The PICC must reply with a 4 bit ACK
sippasaeng 4:4b28e4aa1742 1040 if (cmdBufferSize != 1 || validBits != 4)
sippasaeng 4:4b28e4aa1742 1041 {
sippasaeng 4:4b28e4aa1742 1042 return STATUS_ERROR;
sippasaeng 4:4b28e4aa1742 1043 }
sippasaeng 4:4b28e4aa1742 1044
sippasaeng 4:4b28e4aa1742 1045 if (cmdBuffer[0] != MF_ACK)
sippasaeng 4:4b28e4aa1742 1046 {
sippasaeng 4:4b28e4aa1742 1047 return STATUS_MIFARE_NACK;
sippasaeng 4:4b28e4aa1742 1048 }
sippasaeng 4:4b28e4aa1742 1049
sippasaeng 4:4b28e4aa1742 1050 return STATUS_OK;
sippasaeng 4:4b28e4aa1742 1051 } // End PCD_MIFARE_Transceive()
sippasaeng 4:4b28e4aa1742 1052
sippasaeng 4:4b28e4aa1742 1053
sippasaeng 4:4b28e4aa1742 1054 /*
sippasaeng 4:4b28e4aa1742 1055 * Translates the SAK (Select Acknowledge) to a PICC type.
sippasaeng 4:4b28e4aa1742 1056 */
sippasaeng 4:4b28e4aa1742 1057 uint8_t MFRC522::PICC_GetType(uint8_t sak)
sippasaeng 4:4b28e4aa1742 1058 {
sippasaeng 4:4b28e4aa1742 1059 uint8_t retType = PICC_TYPE_UNKNOWN;
sippasaeng 4:4b28e4aa1742 1060
sippasaeng 4:4b28e4aa1742 1061 if (sak & 0x04)
sippasaeng 4:4b28e4aa1742 1062 { // UID not complete
sippasaeng 4:4b28e4aa1742 1063 retType = PICC_TYPE_NOT_COMPLETE;
sippasaeng 4:4b28e4aa1742 1064 }
sippasaeng 4:4b28e4aa1742 1065 else
sippasaeng 4:4b28e4aa1742 1066 {
sippasaeng 4:4b28e4aa1742 1067 switch (sak)
sippasaeng 4:4b28e4aa1742 1068 {
sippasaeng 4:4b28e4aa1742 1069 case 0x09: retType = PICC_TYPE_MIFARE_MINI; break;
sippasaeng 4:4b28e4aa1742 1070 case 0x08: retType = PICC_TYPE_MIFARE_1K; break;
sippasaeng 4:4b28e4aa1742 1071 case 0x18: retType = PICC_TYPE_MIFARE_4K; break;
sippasaeng 4:4b28e4aa1742 1072 case 0x00: retType = PICC_TYPE_MIFARE_UL; break;
sippasaeng 4:4b28e4aa1742 1073 case 0x10:
sippasaeng 4:4b28e4aa1742 1074 case 0x11: retType = PICC_TYPE_MIFARE_PLUS; break;
sippasaeng 4:4b28e4aa1742 1075 case 0x01: retType = PICC_TYPE_TNP3XXX; break;
sippasaeng 4:4b28e4aa1742 1076 default:
sippasaeng 4:4b28e4aa1742 1077 if (sak & 0x20)
sippasaeng 4:4b28e4aa1742 1078 {
sippasaeng 4:4b28e4aa1742 1079 retType = PICC_TYPE_ISO_14443_4;
sippasaeng 4:4b28e4aa1742 1080 }
sippasaeng 4:4b28e4aa1742 1081 else if (sak & 0x40)
sippasaeng 4:4b28e4aa1742 1082 {
sippasaeng 4:4b28e4aa1742 1083 retType = PICC_TYPE_ISO_18092;
sippasaeng 4:4b28e4aa1742 1084 }
sippasaeng 4:4b28e4aa1742 1085 break;
sippasaeng 4:4b28e4aa1742 1086 }
sippasaeng 4:4b28e4aa1742 1087 }
sippasaeng 4:4b28e4aa1742 1088
sippasaeng 4:4b28e4aa1742 1089 return (retType);
sippasaeng 4:4b28e4aa1742 1090 } // End PICC_GetType()
sippasaeng 4:4b28e4aa1742 1091
sippasaeng 4:4b28e4aa1742 1092 /*
sippasaeng 4:4b28e4aa1742 1093 * Returns a string pointer to the PICC type name.
sippasaeng 4:4b28e4aa1742 1094 */
sippasaeng 4:4b28e4aa1742 1095 char* MFRC522::PICC_GetTypeName(uint8_t piccType)
sippasaeng 4:4b28e4aa1742 1096 {
sippasaeng 4:4b28e4aa1742 1097 if(piccType == PICC_TYPE_NOT_COMPLETE)
sippasaeng 4:4b28e4aa1742 1098 {
sippasaeng 4:4b28e4aa1742 1099 piccType = MFRC522_MaxPICCs - 1;
sippasaeng 4:4b28e4aa1742 1100 }
sippasaeng 4:4b28e4aa1742 1101
sippasaeng 4:4b28e4aa1742 1102 return((char *) _TypeNamePICC[piccType]);
sippasaeng 4:4b28e4aa1742 1103 } // End PICC_GetTypeName()
sippasaeng 4:4b28e4aa1742 1104
sippasaeng 4:4b28e4aa1742 1105 /*
sippasaeng 4:4b28e4aa1742 1106 * Returns a string pointer to a status code name.
sippasaeng 4:4b28e4aa1742 1107 */
sippasaeng 4:4b28e4aa1742 1108 char* MFRC522::GetStatusCodeName(uint8_t code)
sippasaeng 4:4b28e4aa1742 1109 {
sippasaeng 4:4b28e4aa1742 1110 return((char *) _ErrorMessage[code]);
sippasaeng 4:4b28e4aa1742 1111 } // End GetStatusCodeName()
sippasaeng 4:4b28e4aa1742 1112
sippasaeng 4:4b28e4aa1742 1113 /*
sippasaeng 4:4b28e4aa1742 1114 * Calculates the bit pattern needed for the specified access bits. In the [C1 C2 C3] tupples C1 is MSB (=4) and C3 is LSB (=1).
sippasaeng 4:4b28e4aa1742 1115 */
sippasaeng 4:4b28e4aa1742 1116 void MFRC522::MIFARE_SetAccessBits(uint8_t *accessBitBuffer,
sippasaeng 4:4b28e4aa1742 1117 uint8_t g0,
sippasaeng 4:4b28e4aa1742 1118 uint8_t g1,
sippasaeng 4:4b28e4aa1742 1119 uint8_t g2,
sippasaeng 4:4b28e4aa1742 1120 uint8_t g3)
sippasaeng 4:4b28e4aa1742 1121 {
sippasaeng 4:4b28e4aa1742 1122 uint8_t c1 = ((g3 & 4) << 1) | ((g2 & 4) << 0) | ((g1 & 4) >> 1) | ((g0 & 4) >> 2);
sippasaeng 4:4b28e4aa1742 1123 uint8_t c2 = ((g3 & 2) << 2) | ((g2 & 2) << 1) | ((g1 & 2) << 0) | ((g0 & 2) >> 1);
sippasaeng 4:4b28e4aa1742 1124 uint8_t c3 = ((g3 & 1) << 3) | ((g2 & 1) << 2) | ((g1 & 1) << 1) | ((g0 & 1) << 0);
sippasaeng 4:4b28e4aa1742 1125
sippasaeng 4:4b28e4aa1742 1126 accessBitBuffer[0] = (~c2 & 0xF) << 4 | (~c1 & 0xF);
sippasaeng 4:4b28e4aa1742 1127 accessBitBuffer[1] = c1 << 4 | (~c3 & 0xF);
sippasaeng 4:4b28e4aa1742 1128 accessBitBuffer[2] = c3 << 4 | c2;
sippasaeng 4:4b28e4aa1742 1129 } // End MIFARE_SetAccessBits()
sippasaeng 4:4b28e4aa1742 1130
sippasaeng 4:4b28e4aa1742 1131 /////////////////////////////////////////////////////////////////////////////////////
sippasaeng 4:4b28e4aa1742 1132 // Convenience functions - does not add extra functionality
sippasaeng 4:4b28e4aa1742 1133 /////////////////////////////////////////////////////////////////////////////////////
sippasaeng 4:4b28e4aa1742 1134
sippasaeng 4:4b28e4aa1742 1135 /*
sippasaeng 4:4b28e4aa1742 1136 * Returns true if a PICC responds to PICC_CMD_REQA.
sippasaeng 4:4b28e4aa1742 1137 * Only "new" cards in state IDLE are invited. Sleeping cards in state HALT are ignored.
sippasaeng 4:4b28e4aa1742 1138 */
sippasaeng 4:4b28e4aa1742 1139 bool MFRC522::PICC_IsNewCardPresent(void)
sippasaeng 4:4b28e4aa1742 1140 {
sippasaeng 4:4b28e4aa1742 1141 uint8_t bufferATQA[2];
sippasaeng 4:4b28e4aa1742 1142 uint8_t bufferSize = sizeof(bufferATQA);
sippasaeng 4:4b28e4aa1742 1143 uint8_t result = PICC_RequestA(bufferATQA, &bufferSize);
sippasaeng 4:4b28e4aa1742 1144 return ((result == STATUS_OK) || (result == STATUS_COLLISION));
sippasaeng 4:4b28e4aa1742 1145 } // End PICC_IsNewCardPresent()
sippasaeng 4:4b28e4aa1742 1146
sippasaeng 4:4b28e4aa1742 1147 /*
sippasaeng 4:4b28e4aa1742 1148 * Simple wrapper around PICC_Select.
sippasaeng 4:4b28e4aa1742 1149 */
sippasaeng 4:4b28e4aa1742 1150 bool MFRC522::PICC_ReadCardSerial(void)
sippasaeng 4:4b28e4aa1742 1151 {
sippasaeng 4:4b28e4aa1742 1152 uint8_t result = PICC_Select(&uid);
sippasaeng 4:4b28e4aa1742 1153 return (result == STATUS_OK);
sippasaeng 4:4b28e4aa1742 1154 } // End PICC_ReadCardSerial()