Sille Van Landschoot / SX1272Lib

SX1272Lib

Fork of SX1272Lib by Semtech

sx1272/sx1272-hal.cpp@7:91ad5308e1a2, 2016-06-14 (annotated)

Committer:
sillevl
Date:
Tue Jun 14 08:13:41 2016 +0000
Revision:
7:91ad5308e1a2
Parent:
6:3dbddff60dc9 
add support for lpc1768 and rfm95 WIP ! (part2)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mluis 0:45c4f0364ca4 1 /*
mluis 0:45c4f0364ca4 2 / _____) _ | |
mluis 0:45c4f0364ca4 3 ( (____ _____ ____ _| |_ _____ ____| |__
mluis 0:45c4f0364ca4 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
mluis 0:45c4f0364ca4 5 _____) ) ____| | | || |_| ____( (___| | | |
mluis 0:45c4f0364ca4 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 0:45c4f0364ca4 7 (C) 2015 Semtech
mluis 0:45c4f0364ca4 8
mluis 0:45c4f0364ca4 9 Description: -
mluis 0:45c4f0364ca4 10
mluis 0:45c4f0364ca4 11 License: Revised BSD License, see LICENSE.TXT file include in the project
mluis 0:45c4f0364ca4 12
mluis 0:45c4f0364ca4 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
mluis 0:45c4f0364ca4 14 */
mluis 0:45c4f0364ca4 15 #include "sx1272-hal.h"
mluis 0:45c4f0364ca4 16
GregCr 2:cd1093b6676f 17 const RadioRegisters_t SX1272MB2xAS::RadioRegsInit[] = RADIO_INIT_REGISTERS_VALUE;
mluis 0:45c4f0364ca4 18
GregCr 2:cd1093b6676f 19 SX1272MB2xAS::SX1272MB2xAS( RadioEvents_t *events,
mluis 0:45c4f0364ca4 20 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
sillevl 7:91ad5308e1a2 21 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5
mluis 0:45c4f0364ca4 22 #if defined ( TARGET_MOTE_L152RC )
sillevl 7:91ad5308e1a2 23 , PinName rfSwitchCntr1, PinName rfSwitchCntr2 )
dudmuck 1:b0372ef620d0 24 #elif defined ( TARGET_MTS_MDOT_F411RE )
sillevl 7:91ad5308e1a2 25 ,PinName txctl, PinName rxctl )
sillevl 7:91ad5308e1a2 26 #elif defined ( TARGET_MBED_LPC1768 )
sillevl 7:91ad5308e1a2 27 ) // nothing extra needed
mluis 0:45c4f0364ca4 28 #else
sillevl 7:91ad5308e1a2 29 ,PinName antSwitch )
mluis 0:45c4f0364ca4 30 #endif
sillevl 7:91ad5308e1a2 31 : SX1272( events, mosi, miso, sclk, nss, reset, dio0, dio1, dio2, dio3, dio4, dio5 )
mluis 0:45c4f0364ca4 32 #if defined ( TARGET_MOTE_L152RC )
sillevl 7:91ad5308e1a2 33 ,RfSwitchCntr1( rfSwitchCntr1 ),
mluis 0:45c4f0364ca4 34 RfSwitchCntr2( rfSwitchCntr2 ),
dudmuck 1:b0372ef620d0 35 PwrAmpCntr( PD_2 )
dudmuck 1:b0372ef620d0 36 #elif defined ( TARGET_MTS_MDOT_F411RE )
sillevl 7:91ad5308e1a2 37 ,TxCtl ( txctl ),
dudmuck 1:b0372ef620d0 38 RxCtl ( rxctl )
sillevl 7:91ad5308e1a2 39 #elif defined ( TARGET_MBED_LPC1768 )
sillevl 7:91ad5308e1a2 40 // nothing extra needed
mluis 0:45c4f0364ca4 41 #else
sillevl 7:91ad5308e1a2 42 ,AntSwitch( antSwitch ),
mluis 0:45c4f0364ca4 43 #if( defined ( TARGET_NUCLEO_L152RE ) )
dudmuck 1:b0372ef620d0 44 Fake( D8 )
mluis 0:45c4f0364ca4 45 #else
mluis 0:45c4f0364ca4 46 Fake( A3 )
mluis 0:45c4f0364ca4 47 #endif
mluis 0:45c4f0364ca4 48 #endif
mluis 0:45c4f0364ca4 49 {
mluis 0:45c4f0364ca4 50 this->RadioEvents = events;
mluis 0:45c4f0364ca4 51
mluis 0:45c4f0364ca4 52 Reset( );
mluis 4:90bd79f1b458 53
mluis 0:45c4f0364ca4 54 IoInit( );
mluis 4:90bd79f1b458 55
mluis 0:45c4f0364ca4 56 SetOpMode( RF_OPMODE_SLEEP );
mluis 4:90bd79f1b458 57
mluis 0:45c4f0364ca4 58 IoIrqInit( dioIrq );
mluis 4:90bd79f1b458 59
mluis 0:45c4f0364ca4 60 RadioRegistersInit( );
mluis 0:45c4f0364ca4 61
mluis 0:45c4f0364ca4 62 SetModem( MODEM_FSK );
mluis 0:45c4f0364ca4 63
mluis 0:45c4f0364ca4 64 this->settings.State = RF_IDLE ;
mluis 0:45c4f0364ca4 65 }
mluis 0:45c4f0364ca4 66
mluis 4:90bd79f1b458 67 SX1272MB2xAS::SX1272MB2xAS( RadioEvents_t *events )
mluis 0:45c4f0364ca4 68 #if defined ( TARGET_NUCLEO_L152RE )
mluis 0:45c4f0364ca4 69 : SX1272( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, A3, D9 ), // For NUCLEO L152RE dio4 is on port A3
mluis 0:45c4f0364ca4 70 AntSwitch( A4 ),
mluis 0:45c4f0364ca4 71 Fake( D8 )
mluis 0:45c4f0364ca4 72 #elif defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 73 : SX1272( events, PB_15, PB_14, PB_13, PB_12, PC_2, PC_6, PC_10, PC_11, PC_8, PC_9, PC_12 ),
mluis 0:45c4f0364ca4 74 RfSwitchCntr1( PC_4 ),
mluis 0:45c4f0364ca4 75 RfSwitchCntr2( PC_13 ),
mluis 0:45c4f0364ca4 76 PwrAmpCntr( PD_2 )
dudmuck 1:b0372ef620d0 77 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 78 : SX1272( events, LORA_MOSI, LORA_MISO, LORA_SCK, LORA_NSS, LORA_RESET, LORA_DIO0, LORA_DIO1, LORA_DIO2, LORA_DIO3, LORA_DIO4, LORA_DIO5 ),
dudmuck 1:b0372ef620d0 79 TxCtl( LORA_TXCTL ),
mluis 4:90bd79f1b458 80 RxCtl( LORA_RXCTL )
sillevl 6:3dbddff60dc9 81 #elif defined ( TARGET_MBED_LPC1768 )
sillevl 7:91ad5308e1a2 82 : SX1272( events, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15 )
mluis 0:45c4f0364ca4 83 #else
mluis 0:45c4f0364ca4 84 : SX1272( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
mluis 0:45c4f0364ca4 85 AntSwitch( A4 ),
mluis 0:45c4f0364ca4 86 Fake( A3 )
mluis 0:45c4f0364ca4 87 #endif
mluis 0:45c4f0364ca4 88 {
mluis 0:45c4f0364ca4 89 this->RadioEvents = events;
mluis 0:45c4f0364ca4 90
mluis 0:45c4f0364ca4 91 Reset( );
mluis 4:90bd79f1b458 92
mluis 0:45c4f0364ca4 93 boardConnected = UNKNOWN;
mluis 4:90bd79f1b458 94
mluis 0:45c4f0364ca4 95 DetectBoardType( );
mluis 4:90bd79f1b458 96
mluis 0:45c4f0364ca4 97 IoInit( );
mluis 4:90bd79f1b458 98
mluis 0:45c4f0364ca4 99 SetOpMode( RF_OPMODE_SLEEP );
mluis 0:45c4f0364ca4 100 IoIrqInit( dioIrq );
mluis 4:90bd79f1b458 101
mluis 0:45c4f0364ca4 102 RadioRegistersInit( );
mluis 0:45c4f0364ca4 103
mluis 0:45c4f0364ca4 104 SetModem( MODEM_FSK );
mluis 0:45c4f0364ca4 105
mluis 0:45c4f0364ca4 106 this->settings.State = RF_IDLE ;
mluis 0:45c4f0364ca4 107 }
mluis 0:45c4f0364ca4 108
mluis 0:45c4f0364ca4 109 //-------------------------------------------------------------------------
mluis 0:45c4f0364ca4 110 // Board relative functions
mluis 0:45c4f0364ca4 111 //-------------------------------------------------------------------------
GregCr 2:cd1093b6676f 112 uint8_t SX1272MB2xAS::DetectBoardType( void )
mluis 0:45c4f0364ca4 113 {
mluis 0:45c4f0364ca4 114 if( boardConnected == UNKNOWN )
mluis 0:45c4f0364ca4 115 {
mluis 0:45c4f0364ca4 116 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 117 boardConnected = NA_MOTE_72;
dudmuck 1:b0372ef620d0 118 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 119 boardConnected = MDOT_F411RE;
sillevl 6:3dbddff60dc9 120 #elif defined ( TARGET_MBED_LPC1768 )
sillevl 6:3dbddff60dc9 121 boardConnected = LPC1768_RFM95;
mluis 0:45c4f0364ca4 122 #else
mluis 0:45c4f0364ca4 123 this->AntSwitch.input( );
mluis 0:45c4f0364ca4 124 wait_ms( 1 );
mluis 0:45c4f0364ca4 125 if( this->AntSwitch == 1 )
mluis 0:45c4f0364ca4 126 {
mluis 0:45c4f0364ca4 127 boardConnected = SX1272MB1DCS;
mluis 0:45c4f0364ca4 128 }
mluis 0:45c4f0364ca4 129 else
mluis 0:45c4f0364ca4 130 {
GregCr 2:cd1093b6676f 131 boardConnected = SX1272MB2XAS;
mluis 0:45c4f0364ca4 132 }
mluis 0:45c4f0364ca4 133 this->AntSwitch.output( );
mluis 0:45c4f0364ca4 134 wait_ms( 1 );
mluis 0:45c4f0364ca4 135 #endif
mluis 0:45c4f0364ca4 136 }
mluis 0:45c4f0364ca4 137 return ( boardConnected );
mluis 0:45c4f0364ca4 138 }
mluis 0:45c4f0364ca4 139
GregCr 2:cd1093b6676f 140 void SX1272MB2xAS::IoInit( void )
mluis 0:45c4f0364ca4 141 {
mluis 0:45c4f0364ca4 142 AntSwInit( );
mluis 0:45c4f0364ca4 143 SpiInit( );
mluis 0:45c4f0364ca4 144 }
mluis 0:45c4f0364ca4 145
GregCr 2:cd1093b6676f 146 void SX1272MB2xAS::RadioRegistersInit( )
mluis 0:45c4f0364ca4 147 {
mluis 0:45c4f0364ca4 148 uint8_t i = 0;
mluis 0:45c4f0364ca4 149 for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ )
mluis 0:45c4f0364ca4 150 {
mluis 0:45c4f0364ca4 151 SetModem( RadioRegsInit[i].Modem );
mluis 0:45c4f0364ca4 152 Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
mluis 0:45c4f0364ca4 153 }
mluis 0:45c4f0364ca4 154 }
mluis 0:45c4f0364ca4 155
GregCr 2:cd1093b6676f 156 void SX1272MB2xAS::SpiInit( void )
mluis 0:45c4f0364ca4 157 {
mluis 0:45c4f0364ca4 158 nss = 1;
mluis 0:45c4f0364ca4 159 spi.format( 8,0 );
mluis 0:45c4f0364ca4 160 uint32_t frequencyToSet = 8000000;
sillevl 6:3dbddff60dc9 161 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_MOTE_L152RC ) || defined ( TARGET_LPC11U6X ) || defined ( TARGET_MTS_MDOT_F411RE ) || defined ( TARGET_MBED_LPC1768 ) )
mluis 0:45c4f0364ca4 162 spi.frequency( frequencyToSet );
mluis 0:45c4f0364ca4 163 #elif( defined ( TARGET_KL25Z ) ) //busclock frequency is halved -> double the spi frequency to compensate
mluis 0:45c4f0364ca4 164 spi.frequency( frequencyToSet * 2 );
mluis 0:45c4f0364ca4 165 #else
mluis 0:45c4f0364ca4 166 #warning "Check the board's SPI frequency"
mluis 0:45c4f0364ca4 167 #endif
mluis 0:45c4f0364ca4 168 wait(0.1);
mluis 0:45c4f0364ca4 169 }
mluis 0:45c4f0364ca4 170
GregCr 2:cd1093b6676f 171 void SX1272MB2xAS::IoIrqInit( DioIrqHandler *irqHandlers )
mluis 0:45c4f0364ca4 172 {
mluis 0:45c4f0364ca4 173 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_MOTE_L152RC ) || defined ( TARGET_LPC11U6X ) )
mluis 0:45c4f0364ca4 174 dio0.mode( PullDown );
mluis 0:45c4f0364ca4 175 dio1.mode( PullDown );
mluis 0:45c4f0364ca4 176 dio2.mode( PullDown );
mluis 0:45c4f0364ca4 177 dio3.mode( PullDown );
mluis 0:45c4f0364ca4 178 dio4.mode( PullDown );
mluis 0:45c4f0364ca4 179 #endif
GregCr 2:cd1093b6676f 180 dio0.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[0] ) );
GregCr 2:cd1093b6676f 181 dio1.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[1] ) );
GregCr 2:cd1093b6676f 182 dio2.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[2] ) );
GregCr 2:cd1093b6676f 183 dio3.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[3] ) );
GregCr 2:cd1093b6676f 184 dio4.rise( this, static_cast< TriggerMB2xAS > ( irqHandlers[4] ) );
mluis 0:45c4f0364ca4 185 }
mluis 0:45c4f0364ca4 186
GregCr 2:cd1093b6676f 187 void SX1272MB2xAS::IoDeInit( void )
mluis 0:45c4f0364ca4 188 {
mluis 0:45c4f0364ca4 189 //nothing
mluis 0:45c4f0364ca4 190 }
mluis 0:45c4f0364ca4 191
GregCr 2:cd1093b6676f 192 uint8_t SX1272MB2xAS::GetPaSelect( uint32_t channel )
mluis 0:45c4f0364ca4 193 {
sillevl 6:3dbddff60dc9 194 if( boardConnected == SX1272MB1DCS || boardConnected == MDOT_F411RE || boardConnected == LPC1768_RFM95 )
mluis 0:45c4f0364ca4 195 {
mluis 0:45c4f0364ca4 196 return RF_PACONFIG_PASELECT_PABOOST;
mluis 0:45c4f0364ca4 197 }
mluis 0:45c4f0364ca4 198 else
mluis 0:45c4f0364ca4 199 {
mluis 0:45c4f0364ca4 200 return RF_PACONFIG_PASELECT_RFO;
mluis 0:45c4f0364ca4 201 }
mluis 0:45c4f0364ca4 202 }
mluis 0:45c4f0364ca4 203
GregCr 2:cd1093b6676f 204 void SX1272MB2xAS::SetAntSwLowPower( bool status )
mluis 0:45c4f0364ca4 205 {
mluis 0:45c4f0364ca4 206 if( isRadioActive != status )
mluis 0:45c4f0364ca4 207 {
mluis 0:45c4f0364ca4 208 isRadioActive = status;
mluis 0:45c4f0364ca4 209
mluis 0:45c4f0364ca4 210 if( status == false )
mluis 0:45c4f0364ca4 211 {
mluis 0:45c4f0364ca4 212 AntSwInit( );
mluis 0:45c4f0364ca4 213 }
mluis 0:45c4f0364ca4 214 else
mluis 0:45c4f0364ca4 215 {
mluis 0:45c4f0364ca4 216 AntSwDeInit( );
mluis 0:45c4f0364ca4 217 }
mluis 0:45c4f0364ca4 218 }
mluis 0:45c4f0364ca4 219 }
mluis 0:45c4f0364ca4 220
GregCr 2:cd1093b6676f 221 void SX1272MB2xAS::AntSwInit( void )
mluis 0:45c4f0364ca4 222 {
mluis 0:45c4f0364ca4 223 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 224 this->RfSwitchCntr1 = 0;
mluis 0:45c4f0364ca4 225 this->RfSwitchCntr2 = 0;
mluis 0:45c4f0364ca4 226 this->PwrAmpCntr = 0;
dudmuck 1:b0372ef620d0 227 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 228 this->TxCtl = 0;
dudmuck 1:b0372ef620d0 229 this->RxCtl = 0;
sillevl 7:91ad5308e1a2 230 #elif defined ( TARGET_MBED_LPC1768 )
sillevl 7:91ad5308e1a2 231 // do nothing
mluis 0:45c4f0364ca4 232 #else
mluis 0:45c4f0364ca4 233 this->AntSwitch = 0;
mluis 0:45c4f0364ca4 234 #endif
mluis 0:45c4f0364ca4 235 }
mluis 0:45c4f0364ca4 236
GregCr 2:cd1093b6676f 237 void SX1272MB2xAS::AntSwDeInit( void )
mluis 0:45c4f0364ca4 238 {
mluis 0:45c4f0364ca4 239 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 240 this->RfSwitchCntr1 = 0;
mluis 0:45c4f0364ca4 241 this->RfSwitchCntr2 = 0;
mluis 0:45c4f0364ca4 242 this->PwrAmpCntr = 0;
dudmuck 1:b0372ef620d0 243 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 244 this->TxCtl = 0;
dudmuck 1:b0372ef620d0 245 this->RxCtl = 0;
sillevl 7:91ad5308e1a2 246 #elif defined ( TARGET_MBED_LPC1768 )
sillevl 7:91ad5308e1a2 247 // do nothing
mluis 0:45c4f0364ca4 248 #else
mluis 0:45c4f0364ca4 249 this->AntSwitch = 0;
mluis 0:45c4f0364ca4 250 #endif
mluis 0:45c4f0364ca4 251 }
mluis 0:45c4f0364ca4 252
GregCr 2:cd1093b6676f 253 void SX1272MB2xAS::SetAntSw( uint8_t rxTx )
mluis 0:45c4f0364ca4 254 {
mluis 0:45c4f0364ca4 255 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 256 switch( this->currentOpMode )
mluis 0:45c4f0364ca4 257 {
mluis 0:45c4f0364ca4 258 case RFLR_OPMODE_TRANSMITTER:
mluis 0:45c4f0364ca4 259 if( ( Read( REG_PACONFIG ) & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
mluis 0:45c4f0364ca4 260 {
mluis 0:45c4f0364ca4 261 this->RfSwitchCntr1 = 1;
mluis 0:45c4f0364ca4 262 this->RfSwitchCntr2 = 0;
mluis 0:45c4f0364ca4 263 }
mluis 0:45c4f0364ca4 264 else
mluis 0:45c4f0364ca4 265 {
mluis 0:45c4f0364ca4 266 this->RfSwitchCntr1 = 0;
mluis 0:45c4f0364ca4 267 this->RfSwitchCntr2 = 1;
mluis 0:45c4f0364ca4 268 }
mluis 0:45c4f0364ca4 269 break;
mluis 0:45c4f0364ca4 270 case RFLR_OPMODE_RECEIVER:
mluis 0:45c4f0364ca4 271 case RFLR_OPMODE_RECEIVER_SINGLE:
mluis 0:45c4f0364ca4 272 case RFLR_OPMODE_CAD:
mluis 0:45c4f0364ca4 273 this->RfSwitchCntr1 = 1;
mluis 0:45c4f0364ca4 274 this->RfSwitchCntr2 = 1;
mluis 0:45c4f0364ca4 275 break;
mluis 0:45c4f0364ca4 276 default:
mluis 0:45c4f0364ca4 277 this->RfSwitchCntr1 = 0;
mluis 0:45c4f0364ca4 278 this->RfSwitchCntr2 = 0;
mluis 0:45c4f0364ca4 279 this->PwrAmpCntr = 0;
mluis 0:45c4f0364ca4 280 break;
mluis 0:45c4f0364ca4 281 }
dudmuck 1:b0372ef620d0 282 #elif defined ( TARGET_MTS_MDOT_F411RE )
dudmuck 1:b0372ef620d0 283 /* SKY13350 */
dudmuck 1:b0372ef620d0 284 this->rxTx = rxTx;
dudmuck 1:b0372ef620d0 285
dudmuck 1:b0372ef620d0 286 // 1: Tx, 0: Rx
dudmuck 1:b0372ef620d0 287 if( rxTx != 0 )
dudmuck 1:b0372ef620d0 288 {
dudmuck 1:b0372ef620d0 289 this->TxCtl = 1;
dudmuck 1:b0372ef620d0 290 this->RxCtl = 0;
dudmuck 1:b0372ef620d0 291 }
dudmuck 1:b0372ef620d0 292 else
dudmuck 1:b0372ef620d0 293 {
dudmuck 1:b0372ef620d0 294 this->TxCtl = 0;
dudmuck 1:b0372ef620d0 295 this->RxCtl = 1;
dudmuck 1:b0372ef620d0 296 }
sillevl 7:91ad5308e1a2 297 #elif defined ( TARGET_MBED_LPC1768 )
sillevl 7:91ad5308e1a2 298 // do nothing
mluis 0:45c4f0364ca4 299 #else
mluis 0:45c4f0364ca4 300 this->rxTx = rxTx;
mluis 0:45c4f0364ca4 301
mluis 0:45c4f0364ca4 302 // 1: Tx, 0: Rx
mluis 0:45c4f0364ca4 303 if( rxTx != 0 )
mluis 0:45c4f0364ca4 304 {
mluis 0:45c4f0364ca4 305 this->AntSwitch = 1;
mluis 0:45c4f0364ca4 306 }
mluis 0:45c4f0364ca4 307 else
mluis 0:45c4f0364ca4 308 {
mluis 0:45c4f0364ca4 309 this->AntSwitch = 0;
mluis 0:45c4f0364ca4 310 }
mluis 0:45c4f0364ca4 311 #endif
mluis 0:45c4f0364ca4 312 }
mluis 0:45c4f0364ca4 313
GregCr 2:cd1093b6676f 314 bool SX1272MB2xAS::CheckRfFrequency( uint32_t frequency )
mluis 0:45c4f0364ca4 315 {
mluis 0:45c4f0364ca4 316 //TODO: Implement check, currently all frequencies are supported
mluis 0:45c4f0364ca4 317 return true;
mluis 0:45c4f0364ca4 318 }
mluis 0:45c4f0364ca4 319
mluis 0:45c4f0364ca4 320
GregCr 2:cd1093b6676f 321 void SX1272MB2xAS::Reset( void )
mluis 0:45c4f0364ca4 322 {
mluis 0:45c4f0364ca4 323 reset.output();
mluis 0:45c4f0364ca4 324 reset = 0;
mluis 0:45c4f0364ca4 325 wait_ms( 1 );
mluis 0:45c4f0364ca4 326 reset.input();
mluis 0:45c4f0364ca4 327 wait_ms( 6 );
mluis 0:45c4f0364ca4 328 }
mluis 0:45c4f0364ca4 329
GregCr 2:cd1093b6676f 330 void SX1272MB2xAS::Write( uint8_t addr, uint8_t data )
mluis 0:45c4f0364ca4 331 {
mluis 0:45c4f0364ca4 332 Write( addr, &data, 1 );
mluis 0:45c4f0364ca4 333 }
mluis 0:45c4f0364ca4 334
GregCr 2:cd1093b6676f 335 uint8_t SX1272MB2xAS::Read( uint8_t addr )
mluis 0:45c4f0364ca4 336 {
mluis 0:45c4f0364ca4 337 uint8_t data;
mluis 0:45c4f0364ca4 338 Read( addr, &data, 1 );
mluis 0:45c4f0364ca4 339 return data;
mluis 0:45c4f0364ca4 340 }
mluis 0:45c4f0364ca4 341
GregCr 2:cd1093b6676f 342 void SX1272MB2xAS::Write( uint8_t addr, uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 343 {
mluis 0:45c4f0364ca4 344 uint8_t i;
mluis 0:45c4f0364ca4 345
mluis 0:45c4f0364ca4 346 nss = 0;
mluis 0:45c4f0364ca4 347 spi.write( addr | 0x80 );
mluis 0:45c4f0364ca4 348 for( i = 0; i < size; i++ )
mluis 0:45c4f0364ca4 349 {
mluis 0:45c4f0364ca4 350 spi.write( buffer[i] );
mluis 0:45c4f0364ca4 351 }
mluis 0:45c4f0364ca4 352 nss = 1;
mluis 0:45c4f0364ca4 353 }
mluis 0:45c4f0364ca4 354
GregCr 2:cd1093b6676f 355 void SX1272MB2xAS::Read( uint8_t addr, uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 356 {
mluis 0:45c4f0364ca4 357 uint8_t i;
mluis 0:45c4f0364ca4 358
mluis 0:45c4f0364ca4 359 nss = 0;
mluis 0:45c4f0364ca4 360 spi.write( addr & 0x7F );
mluis 0:45c4f0364ca4 361 for( i = 0; i < size; i++ )
mluis 0:45c4f0364ca4 362 {
mluis 0:45c4f0364ca4 363 buffer[i] = spi.write( 0 );
mluis 0:45c4f0364ca4 364 }
mluis 0:45c4f0364ca4 365 nss = 1;
mluis 0:45c4f0364ca4 366 }
mluis 0:45c4f0364ca4 367
GregCr 2:cd1093b6676f 368 void SX1272MB2xAS::WriteFifo( uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 369 {
mluis 0:45c4f0364ca4 370 Write( 0, buffer, size );
mluis 0:45c4f0364ca4 371 }
mluis 0:45c4f0364ca4 372
GregCr 2:cd1093b6676f 373 void SX1272MB2xAS::ReadFifo( uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 374 {
mluis 0:45c4f0364ca4 375 Read( 0, buffer, size );
mluis 0:45c4f0364ca4 376 }